JP2584755B2 - Large-capacity memory and multiprocessor system having the large-capacity memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention has a data capacity that can be accessed by a large number of external devices (particularly processors) and can exceed the address capacity of each device. In particular, it relates to a large-capacity memory suitable for use in a multiprocessor system.

[Conventional technology]

Especially in applications involving complex real-time processing (eg, image processing, pattern and speech recognition, artificial intelligence, and general scientific computation), high computing power and the ability to handle large input / output data streams. The need to combine is generally accepted.

[Problems to be solved by the invention]

However, when a microprocessor system having a high computing capability is configured, problems arise such as the address capacity of a memory and high-speed data transfer between different memory groups.

An object of the present invention relates to a mass memory which can be advantageously used in a multiprocessor which is accessible by different devices (processors) at different ports, independently of the addresses generated by the devices. For each device, each word "segment" in which the memory is conceptually divided is assigned "visibility or invisibility" by the device and has access rights in the device address space (read only, read / write, Execution only) and random positioning (addressing). The purpose is as follows.

(1) By dynamically assigning the logical function of a "secondary memory" logically equivalent to a disk or the function of a direct access main memory to a part of a segment, the address limit of the device is exceeded. The assignment of these functions is logically equivalent to data transfer from main memory to secondary memory or vice versa, but since no physical transfer of data takes place, very high-speed data transfer regardless of segment size. Can be performed.

(2) Dynamically switch segments from one device to another so as to achieve an operation equivalent to very high-speed data transfer.

And (3) dynamically creating a common area for various devices, possibly with different access rights.

[Means for solving the problem]

In view of the above, according to the present invention, a multiprocessor system is connected to at least two buses, and the multiprocessor includes at least two processors connected to at least one of the two buses. One of which is accessible to the at least two processors in a mass memory connected to both of the two buses, for addressing the memory with addresses generated independently by each of the processors. Addressing means, wherein the addressing means includes matching coding means connected to each bus, and the matching coding means includes read / write memory means for each address data group of the processor. And the matching coding means converts each of the address data groups In order to change the address of the first portion of the address data, the first portion of the address data is converted, and further, the first portion obtained from the matching coding means and the address data group from each of the processors are converted. Means for combining the remaining second parts; the complete combined address data group is selected by a selection means for supplying to a main memory block of the mass memory, and the matching coding means comprises the two buses. And a main memory connected between the main memory block and the main memory block.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a block diagram of a multiprocessor system to which a memory according to the present invention is applied. Hereinafter, a main part of a multiprocessor system to which the memory according to the present invention is applied will be described in detail. The system itself is described in “Multiple-Hierarchical-Leve” filed on the same date as the present application.
It is described in an Italian patent application entitled "Multiprocessor", the contents of which are hereby incorporated solely by reference where necessary.

The multiprocessor system shows a common bus structure, which is divided into a number of areas 10, each of which is constituted by a family group 11. Each family has a common bus 12 (family bus)
And all the families 11 in one area 10 have a common bus.
Directly accessible via 13 (area bus). Within each region 10, the processors are tightly connected, i.e., allowing visibility of all memories in that region, while the individual regions 10 are loose, i.e., via units 14 connected by signal lines 15. Connected via exchanged messages. The monitoring and supervisory functions of the system are performed by a special area 10 'which is connected to all other areas 10 of the system via a unit 14 and to an external computer 16 via modules which will be described later. It is convenient. Each family 11 has a signal line 19
A monoprocessor module 17 (P1) connected to the family bus 12 and the area bus 13 via the buses 20 and 20, a large number of multiprocessor modules 18 (PN) connected only to the family bus 12 via the signal line 19 ', 8 according to the invention
Large-capacity memory block 22 convenient for megabytes
(HCSM), and an input / output block 23 (I / O) for inputting and outputting data to and from an environment to which the multiprocessor system is applied. The memory block 22 is a signal line 24
And 25 are connected to the family bus 12 and the area bus 13, respectively, and the block 23 is connected only to the family bus 12. The area bus 13 is also connected to an input / output block 24 (I / O) for communicating with peripheral devices. Thus, the monoprocessor module 17 (P1) connects two (family and region) hierarchy levels.

As shown in FIG. 1, the monitoring area 10 'includes a unit 14 (IR
CU) via a single or two parallel connected interface modules connected to an external computer 16
It is further connected to a TTL difference signal conversion unit 115 connected to the computer 16 via 116. This module 116
Is connected to the VAX11 / 750 external computer 16,
A standard DMA interface, for example DR11-W, may be used.

The various area buses 13 and family buses 12 exhibit nearly identical characteristics as follows: they support a main module, a subordinate module, and a master / slave module, and have five groups of signals (address and status, data, Control, error, and arbitration). Both are faster than 10MB / s in burst mode
Transfer 32-bit data. The capacity of the 32-bit bus allows the use of a 32-bit processor. However, 16
Even when using a bit processor, its properties are available to use the bus capacity described above for faster data transfer. Further, all memories accessible by the bus have a 32-bit parallel configuration. Therefore,
The multiprocessor system comprises a number of regions 10 interconnected by high-speed parallel connections. Since communication between the domains is based on the exchange of messages, a multiprocessor system can be defined at this higher level as a domain network and its geometry can be defined as optimal to meet the requirements of a given application environment. Further, by connecting the monitoring area 10 'to an external computer 16, the entire system benefits from programs and standard peripheral equipment available on the market. Therefore, each area 10 has many families.
11 and share a common memory address space and a common bus 13. More specifically, the 7 megabyte common area address space is divided into sub-spaces allocated to process modules connected to memory blocks or area blocks. These process units access the round-trip memory subspace via the area bus 13.

The configuration of each family 11 is very similar to that of the area 10, and is constituted by a group of process modules sharing the common memory address space and the common bus 12. region
Similarly, in the case of 10, the 8 MB family memory space is divided into local (not dedicated) sub-spaces for various processor modules, the local sub-space being the family bus 12.
Is accessible via a round-trip memory space.

The “local” functions of the various domain modules are accessible via the domain bus 13. In particular, coordination between the family level and the domain level is supported by module 17 (P1) and module 22 (HCSM). Module P1
Has address space for its own family (one PI per family) and multiple families (for example, 32 are convenient)
Gives visibility to both of the area address spaces to which it can connect. Furthermore, the module P1 can use the two large-capacity family buses 12 and the area buses 13 and the above-mentioned hardware characteristics by itself. Block 22 is designed to exchange large amounts of data between the two environments (family and domain) very efficiently. In fact, the block 22 has a very large storage capacity and has double ports connected to both the family bus 12 and the area bus 13, as will be explained in detail below with reference to FIG. In addition, the data available in one environment can be simultaneously used in the other environment by utilizing the great advantage that can be achieved without using the system bus. The memory block 22 (HCSM) shows a memory array 150 having a part 151 for exchanging control bits with a logic error detection and correction block 152. Read or write data in the memory 150 is supplied to a signal line 153 (preferably 32 bits), which is connected to two write data registers 154 and 155 connected to the family bus 12 and the area bus 13, respectively. Is also connected to two read data registers 156 and 157 connected to the family bus 12 and the area bus 13, respectively. Memory 15
The data exchanged with 0 is a logical block via the signal line 158.
It is also supplied to 152. The logic block 152 is connected to a signal line 153 via a read or write control signal line 159, requests arbitration via an error signal line 160, controls a dual (family area) port, and controls a control signal of the memory 150. It is connected to a block 161 which performs timing control. The block 161 supplies the address (RAS / CAS / ADRESS) to the memory 150 via the address signal line 163.

The family bus 12 has two signal lines 164 and 1 for supplying address bits 16 through 22 or another 7 bits, respectively.
It is connected to two input terminals of a multiplexer 166 via 65. The output of the multiplexer 166 is provided to a RAM memory block 168 for mapping the family address, which receives a (write) control signal 170 from the family bus 12 and the output of the block 168 is provided to a family address and status latch 171. Is done. The family bus 12 has a latch 171 via a direct signal line 173 supplying address bits 0 to 15, a control input block 174 of the family bus 12 supplying signals to the latch 171 and an input terminal of a family status and control register 176. Connected to output terminal. Further, the family bus 12 inputs a signal 177 from the data exchange acknowledgment and data exchange information logic block.

The area bus 13 is likewise connected to functionally equivalent blocks indicated by the same reference numerals with a prime.

The status output of latch 171 is available at blocks 178 and 16
The status decoding / cycle request generation block 180 connected to 1 is supplied. At the same time, the status output of latch 171 'is connected.

The outputs (bits 0 to 22) of the addresses of the latches 171 and 171 'are provided to the input terminals of a multiplexer 182 controlled by a block 161 and the output of the multiplexer 182 is directly (via only the AND or OR block 183). Or logic blocks 178 and 17 via pipeline 184
8 'is also supplied directly to the address input terminal of the controlling arbitration block 161.

As an example, assume that the maximum capacity of a memory block 22 divided into 128 segments of 64 kilobytes each is 8 megabytes. Because the memory block 22 is more visible to both the family bus 12 and the area bus 13 and the storage capacity is larger than the address space available for each bus, the present invention imposes a physical 8 megabyte limit on both buses. A mapping mechanism is provided.

The memory is organized in units of 32 bits word length (double word) and allows for 32 bit (double word), 16 bit (word) and 8 bit (byte) read and write access.

Two (family and region) memory access ports represent two identical and independent mapping systems. The logic of these systems divides a total of 8 megabytes into 128 segments of 64 kilobytes each, and each segment may be shifted to any point in the physical address space (within the 64K limit). A physical address is assigned to a segment by writing the number of the segment to the associated address mapping register. The mapping registers are categorized into 128 word RAM memory blocks 168 and 168 '. In a normal read and write cycle of memory array 150, addresses from the family bus and the area bus consist of two parts: Bits 0 through 15 of the first part are latches 171
Alternatively, it is supplied directly to the memory array 150 via a connection 173 or 173 'which is directly connected to 171'. Bits 16 to 22 of the second part are used to extract the (7 bit) segment number assigned to the address from mapping RAM 168 or 168 '. These seven bits are the most significant bits in the address of the memory array 150. As a result, 7 bits are mapped to PAM168 or 168 '.
(Via signal line 165 or 165 ')
Using the same address from the family bus or area bus, it is possible to access different segments and thus different areas of the memory array 150. The address bit 23 is set to zero on the area bus 13 and 1 on the family bus 12 and is not employed in the mapping logic.

The mapping register 168 or 168 'contains one bit defining a "read / write" or "read only" segment, one bit to determine if an HCSM memory segment exists at that particular address, and And one parity check bit generated and controlled directly by

The mapping mechanism in the present invention provides multiple memories 22 (HCSM) on the same area bus or family bus and also allows exclusive visibility of the memory by area or family. In addition, shifting the segment does not involve a data transfer, but merely involves changing the mapping registers on blocks 168 or 168 '.

The control program in memory 22 initializes and modifies the family and area mapping RAMs 168 and 168 'by gaining access to specific (selectable to switch) portions of the family and area I / O space. I do.

Control registers 176 and 176 'store memory 22 until the control program initializes mapping RAMs 168 and 168'.
It has a bit to block access to.

The memory block 22 (HCSM) is designed to interface the bus of the system according to the present invention, so that pipeline address generation, 8, 16, 32 bit data transfers, and non-contiguous or locked access Certain characteristics of the bus, such as possibilities, must be considered. In addition to this, it should be considered that the memory 22 is of a double port type, and the area bus 13 and the family bus 12
There is a need for provision to control the priority of completely asynchronous input request collisions from the Internet.

The problem of temporarily storing addresses is solved by storing addresses in latches 171 and 171 '. The status (eg, DOUBLE WORD) signal decoding provides information about the type of cycle requested in the dynamic control block.
161. This block 161 is for request synchronization or arbitration and is "locked"
Ensure data transfer. To improve the access time of the write cycle, two registers 15 containing the input data and terminating the bus cycle in the shortest possible time
4 and 155 (one for each bus) are provided. The random read cycle is burdened by the access time of the dynamic memory 150, which needs to add the delay introduced by the logic error detection and correction block 152, and requires a synchronization time.

In the case of sequential and locked accesses, the performance is significantly improved, it is possible to "predict" the address of the memory location to be requested in the next cycle, prefetch the data term and ensure it The pipeline logic operated for is available immediately upon request from the main module. Thus, in this case, the bus is only occupied for a minimum amount of time.

Such performance applies to any read operation in units such as double words, words and bytes.

In each case, the data items retrieved from memory 150 are contained in two independent registers 156 and 157 (one for each bus) to prevent possible interference between cycles operated by different buses. .

The memory array 150 has a 32-bit parallel configuration in order to fully utilize the transfer capacity of the memory according to the present invention.

Seven error check bits are added to the 32 data bits. Using 256 kilobytes of chips yields a total of eight 1 megabyte memory banks, each bank having a total of 312 memory chips.

According to the 32-bit parallel configuration, the 16-bit or 8-bit read performance of the system is not impaired at all.
The number of error checking chips can be reduced to some extent. Because the memory matrix 150 is formed by dynamic components that are susceptible to "soft" errors, the logic of the module 22 (HCSM) provides single-bit error correction and error detection for more than one bit. Also HCSM
The modules can be 6, 4, and 2 megabytes in configuration with or without error detection and correction via block 152.

In a more general form, the mass memory according to the invention is accessible by P different devices (especially processors) at P different ports, and 2 ^NK
Comprises a main memory array block 150 having 2 ^N words, each of which is conceptually divided into two segments, each having 2 ^K words. Thus, the physical address of any word on block 150 consists of N bits, where NK indicates a segment and K indicates a word within the segment.

Characteristics of the present invention to enable addressing of the memory in the address space of the various devices, addressable by similar and apparatus which is divided by the segment size 2 ^K for small mapping and second view of memory 168 and 168 ' This can be achieved simply and inexpensively by inserting a characteristic memory having the same number of words into the address path of each port. This word has NK bits (to physically address the segments on the memory array 150), plus visibility, access rights, and other property bits. Thus, the N address bits for the memory array are derived from the K least significant address bits supplied directly by the device and the (NK) segment address bits from the mapping memory. As previously described with reference to FIG. 2, the N device address bits are controlled by a logic control and arbitration block (similar to block 161 of FIG. 2) which scans the device address block (FIG. 2). (Similar to block 182).
The logic control and arbitration block inputs (among other things) visibility bits and device access control signals at the output terminals of the mapping and property memory.

 This will be explained more clearly with an example.

2 ^25- word memory array, ie, N = 25, K = 16 (2
Assuming a segment size of ¹⁶ words), and a device address range of 2 ²⁴ words, the device cannot see more than 256 of 512 (2 ^NK ) memory segments simultaneously, so a small 256 word mapping And via a characteristic memory (typically having a different word length than the memory array), it can be arbitrarily determined which segment is given visibility at any time for which address generated by the device. Of the 24 bits generated by the device, the 16 least significant bits are provided directly to the memory array, and the eight most significant bits are provided to a small mapping memory. If a memory array segment is assigned to a particular address, the mapping memory generates the corresponding nine segment address bits, as well as visibility bits and other segment characteristic bits.

More specifically, 2E0000 and 2EFF in the device address space
In FF (hexadecimal) address word 1A30000 to 1 on memory array to be given and located visibility
If a segment consisting of A3FFFF is required, the word at address 2E in the property memory need only contain 9 segment address bits and the visibility bit is 1
It is.

For example, switching the visibility from the memory segment IA3 to the segment OF5 in the same device address space segment is performed by changing the contents of the word 2E in the characteristic memory from 1A3 to OF5.
It can be easily done by changing to This is logically correspond to the 2 ¹⁶ words in the secondary memory and vice versa transfer from the primary memory, the time required to perform it can be measured within microseconds.

The advantages of the memory according to the invention will be clear from the above description. First, it is possible to exceed the addressing limits of each device. Second, it is possible to dynamically switch memory data from one device to another, thus achieving substantially equivalent data transfer at a very high speed. Finally, it is possible to create a common area for different devices, possibly with different access rights.
It will be apparent to those skilled in the art that modifications of the memory embodiments described and illustrated above may be made without departing from the spirit of the invention.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiprocessor system to which a memory according to the present invention is applied; FIG. 2 is a detailed block diagram of a memory according to the present invention. 12 Family bus; 13 Area bus; 17 Monoprocessor module; 18 Multiprocessor module; 22
…… Large capacity memory block; 150 …… Memory array; 154,155
…… Write data register; 156,157 …… Read data register; 161 …… Block; 165,165 ', 173,173' …… Signal line; 168 …… RAM memory block; 171 …… Latch; 180 ……
block.

Continuation of the front page (72) Inventor Fernando Pesche Italy, 16153 Genova-Sestri, Via Esse. Muskola, 60/20 (56) References JP-A-57-6481 (JP, A) JP-A-57-162162 (JP, A) JP-B-57-46099 (JP, B2)

Claims (6)

(57) [Claims] The multiprocessor system is connected to at least two buses (12, 13), and the multiprocessor system is connected to at least two processors (17, 16) connected to at least one of the two buses (12, 13). , 18), wherein one of the processors (17) is connected to both of the two buses (12, 13) and the two buses (12, 1).
3) In a large-capacity memory (22) having a storage capacity larger than the address space of (3), the large-capacity memory (22) is divided into segments composed of words, and the at least two processors (17,
Address means (168, 168 ', 171, 171') for addressing said memory (22) with an address independently generated by each of said processors (17, 18). , 161 and 182), the addressing means includes matching coding means (168, 168 ') connected to each bus, and the matching coding means (168, 168') includes the matching coding means (168, 168 '). , 18) is provided with read / write memory means, and a signal line (165, 1) connected from each of the processors (17, 18) to the two buses (12, 13) is provided.
65 ') to receive a first portion of the address data and change it to access a different segment, and further obtain and change the matched coding means (168, 168'). A signal line (17) connected from the first part (165, 165 ') of the address data and each of the processors (17, 18) to the two buses (12, 13).
3, 173 ') by recombining the remaining second part of the address data so that the address space of the two buses (12, 13) exceeds the limit of the mass memory (23); All the recombination address data from each of the processors (17, 18) are time-divisionally selected by selection means (161, 182) for supplying to the main memory array (150) of the mass memory (22); The matching coding means (168, 1
68 ') is a large capacity memory (22), which is connected between one of the two buses (12, 13) and the main memory array (150). 2. A large capacity memory according to claim 1, wherein said first part of said address data sent to said matching coding means is a most significant part. 3. The main memory array (150) comprises 2 ^N words of memory blocks conceptually divided into 2 ^NK segments each having 2 ^K words, provided that any one word Consists of N bits, of which NK indicates the segment, K indicates a word in the segment; the second part of the address data is the K
And the first part comprises (MK) bits, wherein the address data provided by the processor (17, 18) comprises M bits; 168 ') provides (NK) address bits for said segment. Wherein said aligning coding means (168, 168 ') is provided with a plurality of word equals addressable (2 ^M) by the processor (17, 18) divided by the size (2 ^K) of the segment 4. The mass memory of claim 3, wherein said word has (NK) bits to which additional codes and control bits are added. 5. The read or write data from said main memory array (150) is exchanged with said processor (17, 18) via registers (154, 156, 155, 157). The large-capacity memory according to claim 1. 6. The capacity of the memory (22) exceeds the address capacity of the processor (17, 18).
The large-capacity memory according to claim 1.