JP2580432B2 - Synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing method suitable for use in, for example, a helical scan type video tape recorder which converts an audio signal into a PCM during an overlap period and compresses the time axis.

[0002]

2. Description of the Related Art For example, in a helical scan type video tape recorder (VTR), an angle of winding of a tape around a rotary drum is made larger than an angle division of a head, and an overlap period in which a plurality of heads simultaneously contact the tape is provided. During this overlap period, for example, the audio signal is
It is proposed that the data be recorded after being compressed on a time axis.

FIG. 3 shows an example of such a recording / reproducing apparatus. In the figure, reference numeral 1 denotes an input terminal to which a video signal to be recorded is supplied. The video signal from the terminal 1 is supplied to the modulation processing circuit 2 to be a predetermined recording signal. This recording signal is supplied to one fixed contact v of the switches 4 and 5 through the amplifier 3.

Reference numeral 6 denotes an input terminal to which an audio signal to be recorded is supplied. The audio signal from this terminal 6 is
It is supplied to the time axis compression circuit 7.

Further, a vertical synchronizing signal of the input video signal from the processing circuit 2 is supplied to a timing signal forming circuit 9 through a fixed contact r on the recording side of the switch 8. In this circuit 9, for example, the last one of each vertical period as shown in FIG.
A signal corresponding to the period of / 5 is formed.

This signal is supplied to a circuit 7, and during this period, an audio signal corresponding to any one vertical period before that is converted into a PCM, compressed on a time axis, and extracted. This PC
The M signal is supplied to the other fixed contact a of the switches 4 and 5 through the amplifier 10.

Further, a signal which is inverted every vertical period as shown in FIG. 4C is formed by the circuit 9, and the switches 4 and 5 are switched to the opposite phases by this signal. As a result, the movable contacts of the switches 4 and 5 are connected to D and
As shown in E, the PCM signal (a) and the video signal (v) are extracted.

Signals obtained at the movable contacts of these switches 4 and 5 are supplied to the recording-side fixed contacts r of the switches 11 and 12, respectively. And these switches 11, 1
The signals obtained at the two movable contacts are respectively the heads 13, 1
4 and recorded on the tape T.

The heads 13 and 14 are provided on the rotating drum at an angle of 180 degrees. Further, the tape T is wound around a range of 220 degrees around the drum. Further, although not shown, the transfer of the tape T and the rotation servo of the drum are performed by a conventionally well-known method based on signals from the CTL, the pulse generator, and the forming circuit 9. By this servo, the heads 13 and 14 are brought into contact with the tape T during periods indicated by F and G in FIG.

Therefore, recording tracks are formed on the tape T, for example, as shown in FIG. In the figure, recording tracks are formed in order from the left side, and each track is recorded from the lower side to the upper side. Then, the PCM signal (a) is recorded in the hatched portions in the figure, and the video signal (v) is recorded in the non-hatched portions.

At the time of reproduction, the switches 8, 11, 1
2 is switched to the fixed contact p on the reproduction side. Then, a clock signal of, for example, 60 Hz from the oscillator 15 is generated by the forming circuit 9.
, And the same servo as in recording is performed by this signal.

Signals reproduced from the tape T by the heads 13 and 14 are supplied to the movable contacts of the switches 11 and 12, respectively, and taken out to the fixed contacts p. The reproduced signals from these switches 11 and 12 are respectively connected to switch 1
6 and 17 are supplied to the fixed contacts o and e. Further, the switches 16 and 17 are switched to mutually opposite phases by a signal equivalent to c from the circuit 9.

Accordingly, the video signal (v) is continuously taken out from the movable contact of the switch 16 as shown in FIG.
As shown in FIG.
The M signal (a) is intermittently extracted. The video signal (v) from the switch 16 is taken out to the video signal output terminal 20 through the amplifier 18 and the demodulation processing circuit 19.

The PCM signal (a) from the switch 17
PCM demodulation / time axis expansion circuit 22 through amplifier 21
Supplied to Further, the signal of FIG. 4B from the circuit 9 is supplied to the circuit 22, and the signal in this period is PCM-demodulated and time-base expanded. This signal is taken out to the audio signal output terminal 23.

In this manner, recording and reproduction of the video signal and the audio signal are performed.

By the way, in such an apparatus, PCM
When recording (transmitting) a signal, a series of signals is divided into blocks each having a predetermined bit, and signals are exchanged in a predetermined pattern between these blocks and transmitted, that is, so-called interleaving is performed.

On the other hand, on the reproducing side, deinterleaving is performed to undo the above-mentioned exchange. In this case, to perform deinterleaving, the position of each block of the reproduced PCM signal must be accurately determined.

However, in the above-mentioned apparatus, the reproduced PCM signal is intermittent as shown in FIG. Moreover, the tracks to be reproduced are different between them. For this reason, P which is reproduced due to tape jitter or the like
The time axis between the CM signals does not match. If the time axes do not match, the correct position of each block of the PCM signal cannot be determined, and deinterleaving cannot be performed.

Therefore, for example, a synchronization signal is provided for each block, and the position of each block is determined by detecting the synchronization signal. That is, the synchronization signal is detected and counted, and the position is determined based on the counted value.

However, in this case, a complicated structure for detecting the synchronization signal is required, and it is determined that the synchronization signal is lost due to dropout or the like, or that the synchronization signal is erroneously detected in the signal. An error may occur in the position, deinterleaving may be performed erroneously, and noise may occur.

[0021]

The problem to be solved is that in the method of detecting the synchronization signal and determining the position of each block, the synchronization signal is lost due to dropout or the like, or the synchronization signal is incorrect in the signal. If it is detected by mistake, the specified position will be wrong and deinterleaving will be performed erroneously,
That is, noise may be generated.

[0022]

SUMMARY OF THE INVENTION The present invention, code signal is divided every predetermined number of bits, the synchronization signal and the signal address signal is transmitted by being added consisting of patterns which are not used as a code signal for each the divided In the synchronization method of
The synchronous signal of the transmitted signal is detected and the address signal is read, and when the address signal cannot be read after the synchronous signal is detected, the detected synchronous signal is invalidated. And sync
Is the way .

[0023]

According to this, the position of each block can be accurately determined with a simple configuration.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a pattern (prohibited pattern) not used as a code signal is used as a synchronization signal in the present invention. This prohibition pattern is, for example, Tm in the MFM system.
When in = 1T and Tmax = 2T, a 2.5T signal is used.

An arbitrary address signal is provided after the synchronizing signal. Then, the synchronization signal and the address signal are inserted into the PCM signal at a cycle equal to or longer than the assumed maximum time axis fluctuation.

FIG. 1 shows a circuit for detecting the synchronization signal and the address signal inserted as described above. 3 in the figure
Reference numeral 1 denotes a terminal to which a reproduced PCM signal is supplied. The signal from the terminal 31 is supplied to the signal processing circuit 32. Further, a signal from the terminal 31 is used as a synchronization signal detection circuit 33.
Supplied to Here, by using the inhibition pattern as described above as the synchronization signal, the synchronization signal can be easily detected by a filter or a simple discrimination circuit.

This synchronization signal is supplied to the processing circuit 32 through the OR circuit 34. The signal from the OR circuit 34 is supplied to the interpolation circuit 35. Here, the interpolation circuit 35 is formed of, for example, a simple PLL, and is locked to a synchronization signal, and forms a signal at the same timing when the synchronization signal is lost. The signal from the interpolation circuit 35 is supplied to the OR circuit 34.

Further, a signal from the terminal 31 is supplied to the address reading circuit 36. Further, a signal from the OR circuit 34 is supplied to the circuit 36. The circuit 36 reads the address signal after the synchronization signal, and supplies the address signal to the processing circuit 32. Then, deinterleaving or the like is performed according to the address signal, and the result is output to the terminal 37.

In this circuit, when the signal is supplied to the terminal 31 as shown in FIG. 2A, the detection circuit 33 outputs a signal as shown in FIG. Here, if the synchronization signal at time point a is lost due to dropout or the like, the signal of this portion is interpolated by the interpolation circuit 35 and the OR circuit 34
Outputs a signal as shown in FIG.

Further, this signal is supplied to the reading circuit 36, and the address signal is read. Here, 2.
In the case of a 5T prohibition pattern, a part of the signal may be lost due to dropout or the like, and a signal equivalent to the synchronization signal may be generated. In that case, a signal is output from the detection circuit 33 as at time point b. However, since this signal does not include an address signal, the read circuit 36
Are not output from the processing circuit 32 and are ignored by the processing circuit 32.

The processing of the PCM signal is performed in this manner. According to the present invention, the synchronizing signal can be detected very easily because the inhibition pattern is used as the synchronizing signal. Further, since the address signal is provided after the synchronization signal, the position of the block can always be determined accurately, and even when the synchronization signal is erroneously detected, it can be reliably removed.

Accordingly, there is no need to provide a complicated synchronization detection circuit or synchronization protection circuit, and the position of each block can be accurately determined with a simple configuration.

The insertion of the synchronization signal and the address signal is P
This can be performed by the CM / time axis compression circuit 7.

The configuration for recording and reproducing the PCM signal in the present invention is not limited to the example shown in FIG.

[0035]

According to the present invention, the position of each block can be accurately determined with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of an apparatus for realizing a synchronization method according to the present invention.

FIG. 2 is a diagram for explaining this.

FIG. 3 is a diagram illustrating an example of a recording / reproducing device.

FIG. 4 is a timing chart for the explanation.

FIG. 5 is a diagram showing a tape pattern for the explanation.

[Explanation of symbols]

 22 PCM demodulation / time axis expansion circuit 31 Terminal to which reproduced PCM signal is supplied 32 Signal processing circuit 33 Synchronization signal detection circuit 34 OR circuit 35 Interpolation circuit 36 Address reading circuit 37 Output terminal

Claims (1)

(57) [Claims] 1. A code signal is divided into predetermined bits, in the method of synchronizing the synchronization signal and the address signal for each divided consisting pattern not used as the code signal is added to the transmitted signal is the transmission Detecting the synchronizing signal of the detected signal and reading the address signal. If the address signal cannot be read after the synchronizing signal is detected, the detected synchronizing signal is invalidated. How .