JP2580030B2 - Test / diagnosis interrupt processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] It has a central controller, a main storage device and a channel controller connected via an internal bus, and the central controller is connected to the central controller via a channel bus under the channel controller. Regarding test / diagnosis interrupt processing in a computer system having a plurality of input / output control devices that are tested / diagnosed by a control device, the purpose is to be able to identify whether a valid interrupt that responds to a test / diagnosis command is an interrupt, A coincidence detecting unit for transmitting and receiving information to and from the internal bus and the channel bus, wherein the coincidence detecting unit determines that an interrupt request is generated as a response to a test / diagnosis command from the central control unit. Activated when detected by the channel control device, the input / output control device targeted by the test / diagnosis command is The unique address assigned for the interrupt is fetched from the internal bus side, and the unique address used for the interrupt is fetched from the channel bus side, and when it is detected that the two unique addresses match, the unique address is used as a valid interrupt signal. It is configured to notify the central control unit.

[Industrial applications]

The present invention provides a central controller connected via an internal bus,
Test / diagnosis interrupt processing in a computer system having a main storage device and a channel control device, and having a plurality of input / output control devices which are tested / diagnosed by the central control device via a channel bus under the control of the channel control device Method and apparatus.

Testing and diagnosis are indispensable in computer systems with the core of computers to improve reliability. Therefore, tests and diagnoses are periodically performed also in, for example, an electronic exchange system having a computer as a core. The present invention describes, for example, interrupt processing in test and diagnosis in an electronic exchange. Interrupt processing is required for the following reasons.
The central control unit (CC) which forms the computer in the electronic exchange performs online processing such as circuit switching connection on the network, while a plurality of input / output control units and the like placed under the central control unit Execute test / diagnosis for. This is performed by sending a command for testing / diagnosis. However, it must be clearly distinguished from the execution of this command and the above-mentioned online processing. This is because if this distinction is not made, the original online processing will be affected by the effect of the command execution. So, in order not to cause such trouble,
Responses to test / diagnosis commands must always be made in the form of interrupts. Even if the online processing is momentarily interrupted, the test / diagnosis is executed without affecting the flow of the online processing at all. I have to. This is the significance of interrupts in testing and diagnosis.

[Conventional technology]

FIG. 4 is a diagram showing an example of a computer system to which the present invention is applied. The computer system 10 includes a central control device (hereinafter, also referred to as CC) 11, a main storage device (hereinafter, also referred to as MM) 15, and a channel control device (hereinafter, also referred to as CHC) 12, which are connected via an internal bus 16. Have, CHC12
Under the control of the CC11 via the channel bus 14
It has a plurality of input / output control devices (hereinafter, also referred to as IOCs) 13 to be diagnosed. In the figure, two IOCs (IOC1,
IOC2) 13 is shown. Various peripheral devices such as a display, a memory device, and a typewriter are connected to the IOC, but are not shown. Note that this computer system 10
If is in the electronic exchange, CC11 will give a speech bus
Network NW is connected via SB. In recent years, electronic exchanges have been performing so-called distributed processing in a multiprocessor format.
Via the ADP another central controller CC 'is connected, which acts, for example, as a management processor.

The central control unit (CC) 11
Sends test / diagnosis command CM to channel controller (CHC) 12
To one input / output control device (IOC) 13 to be tested / diagnosed, for example, IOC1. If a response to the command CM, that is, an interrupt as a command execution end notification is correctly returned from the IOC1, the IOC1 can be regarded as normally operating.

FIG. 5 is a flowchart showing a conventional example of a test / diagnosis interrupt procedure. The channel controller (CHC) 12 detects whether or not an interrupt request (REQ in FIG. 4) appears on the channel bus 14. (Step a) If there is a REQ (Yes), an interrupt signal INT from the CHC 12 to the central control unit (CC) 11
Is transmitted (step b).

[Problems to be solved by the invention]

As described above, since the central control unit (CC) 11 executes the processing while clearly distinguishing the online processing from the test / diagnosis processing, the CC 11 transmits the test / diagnosis command CM to the central control unit (CH).
C) All the responses after being thrown under 12 are interpreted as interrupts in response to the command CM.

Therefore, after the command CM is input, the channel bus 14
The signals appearing above are all interpreted as legitimate interrupts (responses), whether legitimate or illegal,
There is a problem that an incorrect test / diagnosis result may appear.

Actually, the above problem occurs, for example, I / O controller IO
If the key of the typewriter connected to C2 is erroneously operated by a maintenance person, and if a command CM for IOC1 was issued immediately before that, the signal resulting from this erroneous operation will be transmitted to the channel bus. Appearing on 14, CC11
IOC1 mistakenly recognizes that there is a valid interrupt signal. In addition, such an erroneous signal is transmitted to the central control unit CC 'described above.
May be given by the side. This is because CC11 and CC 'are generally operated independently.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide an interrupt processing method and apparatus capable of identifying whether or not a valid interrupt responds to a test / diagnosis command.

[Means for solving the problem]

The present invention relates to a device for generating an interrupt request REQ as a response to a test / diagnosis command CM.
A unique address (IOA) is pre-allocated to the target of the diagnostic command and sent out on the internal bus 16, while the specific address of the I / O control device IOC targeted by the test / diagnostic command CM together with the interrupt request REQ Of address IOA 'on the channel bus 14 to form a coincidence detecting means for detecting whether the unique address IOA' from the channel bus 14 coincides with the unique address IOA from the internal bus 16 side. I do.
This coincidence detecting means can be formed by hardware or software.

(Operation)

The coincidence detecting means constituted by hardware exchanges information with the internal bus 16 and the channel bus 14, and executes a test / diagnosis command CM from the central control unit (CC) 11.
Is activated when the channel controller (CHC) 12 detects that an interrupt request REQ has been generated as a response to the I / O controller (IOC) 13 which is the target of the test / diagnosis command CM. The assigned unique address IOA is fetched from the internal bus 16, while the corresponding interrupt R
The unique address IOA 'used for the EQ is assigned to the channel bus 14
Side, and when it is detected that the two unique addresses match, the central controller 1
1 shall be notified.

Further, if the method of the present invention is realized by software without using the coincidence detecting means, (I) the central control device 11 transmits the plurality of input / output control devices 13
(II) When the channel controller 12 detects that the interrupt request REQ has occurred in response to the test / diagnostic command CM, Generate a central controller 1
1 and write the unique address IOA 'used for the interrupt to the seed storage device 15; (III) The unique address IOA' written in (II) above.
The central control unit 11 detects whether or not the address matches the unique address IOA pre-assigned to the input / output control device 13 targeted by the test / diagnosis command CM. Is determined to be a legitimate interrupt, and if not, there is no relevant interrupt.

〔Example〕

FIG. 1 is a diagram showing a test / diagnosis interrupt device according to the present invention and its periphery. Note that the same components are denoted by the same reference numerals or symbols throughout the drawings. The difference from the computer system 10 of FIG. 4 described above is that a coincidence detecting means 21 is added. This coincidence detecting means 21
Is configured as a so-called comparator, a first register for taking in the unique address IOA from the internal bus 16 side, and the unique address IOA 'from the channel bus 14 side.
And a second register for taking in the data and comparing whether or not the contents of the two registers match. These IOA and IO
A 'is taken into the first and second registers when the channel controller (CHC) 12 detects the appearance of the interrupt request REQ. Then, the unique address IOA 'used for the interrupt is stored in the second register.

FIG. 2 is a flowchart used to explain the operation of the apparatus shown in FIG. However, it shows an example of the operation. Step b and step f in the steps of FIG.
Correspond to step a and step b in FIG. 5, respectively.

In step a of FIG. 2, the central control unit (CC) 11 that has issued the test / diagnosis command CM is assigned a unique address IOA assigned to one input / output control unit (IOC) 13 targeted by the command CM. Register This registration is preferably performed on the main storage device (MM) 15.

In step b, the channel controller (CHC) 12 monitors the presence or absence of the interrupt request REQ on the channel bus 14.

When there is an interrupt request REQ, the unique address IOA 'used for the interrupt is taken into the coincidence detecting means 21 in step c. At the same time, the unique address IOA registered in step a is fetched from the seed storage device (MM) 15 into the coincidence detecting means 21.

In step d, the two unique addresses IOA and IOA 'taken in step c are compared in the coincidence detecting means 21.
It is detected whether or not they match. If they match, the central control unit (C
C) Send to 11.

If the result of step d does not match, the interrupt is reset (discarded) in step e and the process returns to step b. Regardless of whether the interrupt request REQ is valid or not, the channel controller (CHC) 12 sets a flag in its own status register (not shown). If this flag remains set, acceptance of the next interrupt request REQ will be rejected. Then, when it is determined that the interrupt is invalid, the above-mentioned interrupt is reset (discarded). That is, the flag in the status register is reset. The CHC 12 has its own timer, and when the interrupt request REQ for the test / diagnosis command CM does not occur within a predetermined time, notifies the CC 11 that there is an abnormal situation.

FIG. 3 is a flowchart of a test / diagnosis interrupt method according to the present invention, which is performed without introducing the coincidence detecting means 21 in FIG. 1 (equivalent to FIG. 4). In this flowchart, a central controller (CC) 11 to a plurality of input / output controllers (IOCs) 13
Starts when a test / diagnosis command CM is sent to one of them. Step a in this figure is equivalent to step b described in FIG. In step b, when the interrupt request REQ is generated, the channel controller (CHC) 12 notifies the CC 11 of the request and writes the unique address IOA 'used for the interrupt into a predetermined area in the main memory (MM) 15. .

In step c, the unique address written to MM15
IOA 'is collected by CC11.

In step e after step d, the CC11 itself knows the unique address IOA assigned to the IOC that is the target of the test / diagnosis command CM currently performed by the CC11. The IOA 'collected by the CC 11 from a predetermined area is compared. If the comparison results in a match, it is recognized as a valid interrupt, and if they do not match, it is determined that there is no interrupt. As described above, since the CC 11 checks the validity of the interrupt by itself, the CC 11 does not transmit the interrupt signal INT shown in FIG.

The step d means that the flag set in the status register in the CHC 12 is unconditionally reset. As a result, the next interrupt request REQ can be immediately accepted. If REQ is not returned, it is the same as described above that the timer is timed out and the abnormality is detected.

〔The invention's effect〕

As described above, according to the present invention, a determination is made as to whether an interrupt that responds to a test / diagnosis command is a valid interrupt, and the reliability of the test / diagnosis can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a test / diagnosis interrupt device according to the present invention and its periphery, FIG. 2 is a flowchart used to explain the operation of the device shown in FIG. 1, and FIG. 3 is a test / diagnosis interrupt method according to the present invention. FIG. 4 is a diagram showing an example of a computer system to which the present invention is applied, and FIG. 5 is a flowchart showing a conventional example of a test / diagnosis interrupt procedure. In the figure, 11: central control device, 12: channel control device, 13: input / output control device, 14: channel bus, 15: main storage device, 16: internal bus, REQ: interrupt request, INT: Interrupt signal, CM: Test / diagnosis command.

Claims (2)

(57) [Claims] An information processing system includes a central control unit (11), a main storage unit (15), and a channel control unit (12) connected via an internal bus (16), under the control of the channel control unit (12). Is the central control unit (11) via the channel bus (14).
A test / diagnosis interrupt processing method in a computer system (10) having a plurality of input / output control devices (13) to be tested / diagnosed by the central control device (11); A first step of transmitting a test / diagnosis command (CM) to one of them; and an occurrence of an interrupt request (REQ) in response to the test / diagnosis command (CM) to the channel control device (12). A second step of notifying the occurrence of the interrupt request (REQ) to the central control device (11) and writing a unique address (IOA ') used for the interrupt to the main storage device (15). And the unique address (IO
A ′) is determined by the central control unit (1) to determine whether or not the address matches a unique address (IOA) previously assigned to the input / output control unit (13) targeted by the test / diagnosis command (CM).
Test / diagnostic interrupt processing, comprising a third step of detecting in 1), wherein when the comparisons in the third step match, a valid interrupt is determined, and when the comparisons do not match, there is no relevant interrupt. Method. 2. A communication system comprising a central control unit (11), a main storage unit (15) and a channel control unit (12) connected via an internal bus (16), under the control of the channel control unit (12). Is the central control unit (11) via the channel bus (14).
A test / diagnosis interrupt processing device in a computer system (10) having a plurality of input / output control devices (13) to be tested / diagnosed by the internal bus (16) and the channel bus (14). A coincidence detecting means (21) for performing transmission / reception, wherein the coincidence detecting means (21) generates an interrupt request (REQ) as a response to a test / diagnosis command (CM) from the central control device (11); Is activated when detected by the channel control device (12), and a unique address (IOA) previously assigned to the input / output control device (13) targeted by the test / diagnosis command (CM). ) Is taken in from the internal bus (16) side, while the unique address (IOA ') used for the interrupt is taken in from the channel bus (14) side, and both the unique addresses (IOA, IOA') are taken. There the central control unit (11) to the test and diagnosis interruption processing apparatus and notifies a valid interrupt signal when it is detected that the matched (INT).