JPS6314542B2 - - Google Patents

Info

Publication number
JPS6314542B2
JPS6314542B2 JP17072879A JP17072879A JPS6314542B2 JP S6314542 B2 JPS6314542 B2 JP S6314542B2 JP 17072879 A JP17072879 A JP 17072879A JP 17072879 A JP17072879 A JP 17072879A JP S6314542 B2 JPS6314542 B2 JP S6314542B2
Authority
JP
Japan
Prior art keywords
fault
processor
information
transmission path
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17072879A
Other languages
Japanese (ja)
Other versions
JPS5693496A (en
Inventor
Akihiro Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP17072879A priority Critical patent/JPS5693496A/en
Publication of JPS5693496A publication Critical patent/JPS5693496A/en
Publication of JPS6314542B2 publication Critical patent/JPS6314542B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575Software application
    • H04Q3/54591Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Description

【発明の詳細な説明】 本発明は、機能分散制御を行なうマルチプロセ
ツサ方式の電子交換機の障害検出方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure detection method for a multiprocessor type electronic exchange that performs function distributed control.

従来、この種の障害検出は被障害検出プロセツ
サの動作により自らが管理する機器の障害検出情
報を情報伝送路を通して障害管理プロセツサに報
告する方式が一般的であつた。したがつて、被障
害検出プロセツサで障害検出した障害情報が有効
であつたとしても、障害管理プロセツサと被障害
検出プロセツサ間の情報伝送路が異常であれば、
障害管理プロセツサには正しい障害情報が伝送さ
れず、被障害検出プロセツサの異常か情報伝送路
の異常かを、障害管理プロセツサは識別しにくい
欠点があつた。
Conventionally, this type of fault detection has generally been carried out by operating a fault detection processor to report fault detection information of the equipment it manages to a fault management processor through an information transmission path. Therefore, even if the fault information detected by the fault detection processor is valid, if the information transmission path between the fault management processor and the fault detection processor is abnormal,
Correct fault information is not transmitted to the fault management processor, and the fault management processor has the disadvantage that it is difficult to distinguish whether the fault is in the fault detection processor or in the information transmission path.

本発明は障害管理プロセツサからの要求により
被障害検出プロセツサ自らが管理するハードウエ
アの障害検出情報と、障害管理プロセツサからの
障害検出要求情報とを障害管理プロセツサに返送
する事により、障害管理プロセツサと被障害管理
プロセツサ間の情報伝送路と被障害検出プロセツ
サの障害とを、同時に検出する電子交換機の障害
検出方式を提供することにある。
The present invention enables a fault management processor to communicate with a fault management processor by sending back to the fault management processor fault detection information on hardware managed by the fault detection processor itself and fault detection request information from the fault management processor upon request from the fault management processor. An object of the present invention is to provide a fault detection method for an electronic exchange that simultaneously detects a fault in an information transmission path between faulty management processors and a fault in a faulty detection processor.

かかる、本発明の目的を達成するため、機能分
散制御を行なうマルチプロセツサ方式の電子交換
機において、障害管理プロセツサを設け、該プロ
セツサから情報伝送路を通して障害検出要求デー
タを被障害検出プロセツサに送出し、それを受信
した被障害検出プロセツサは自らが管理する機器
の障害検出を行ない障害管理プロセツサから受信
した障害検出要求情報と被障害検出プロセツサの
障害情報とを情報伝送路を通して障害管理プロセ
ツサに返送し、しかるのち障害管理プロセツサで
はこれらの情報を分析し情報伝送路と被障害検出
プロセツサの異常を同時に検出する事を特徴とし
ている。
In order to achieve the object of the present invention, a fault management processor is provided in a multiprocessor type electronic exchange that performs function distributed control, and fault detection request data is sent from the processor to the fault detection processor through an information transmission path. The fault detection processor that has received it performs fault detection on the equipment it manages, and returns the fault detection request information received from the fault management processor and the fault information of the fault detection processor to the fault management processor through the information transmission path. Then, the fault management processor analyzes this information and simultaneously detects abnormalities in the information transmission path and the fault detection processor.

以下、図面を参照して従来例および本発明の一
実施例を説明する。
Hereinafter, a conventional example and an embodiment of the present invention will be described with reference to the drawings.

第1図は、従来の障害情報転送方式図で、シス
テム全体の障害管理を行なう障害管理プロセツサ
SPの要求に基づく事なく、被障害検出プロセツ
サHPが一方的に該HPが制御する機器の障害情
報を管理プロセツサSPに送出している。このよ
うな方式では管理プロセツサSPの受信側の情報
伝送路(すなわちHPの送信側の情報伝送路)に
異常がなければHPで検出した障害情報はSPにお
いて有効となるが、仮りに、SPの受信側の情報
伝送路に異常がなかつたとしても、SPの送信側
の情報伝送路(すなわち、HPの受信側の情報伝
送路)に異常がないという保障はない。従つて
SPとHP間の送受信情報伝送路の障害検出とHP
が制御する機器の障害検出をSPが同時に行なう
事は困難であつた。
Figure 1 is a diagram of the conventional fault information transfer method, which uses a fault management processor that manages faults in the entire system.
The fault detection processor HP unilaterally sends fault information of the equipment controlled by the HP to the management processor SP without being based on a request from the SP. In such a method, if there is no abnormality in the information transmission path on the receiving side of the management processor SP (that is, the information transmission path on the sending side of the HP), the fault information detected by the HP will be valid at the SP. Even if there is no abnormality in the information transmission path on the receiving side, there is no guarantee that there is no abnormality in the information transmission path on the sending side of the SP (that is, the information transmission path on the receiving side of the HP). accordingly
Failure detection in the transmission/reception information transmission path between SP and HP and HP
It was difficult for the SP to simultaneously detect faults in equipment controlled by the SP.

第2図は本発明における障害情報転送方式図で
ある。第2図において、障害管理プロセツサSP
は被障害検出プロセツサHPに対してSPの送信側
情報伝送路(すなわち、HPの受信側の情報伝送
路)を通して障害検出要求情報を送出する。その
際管理プロセツサSPではSPとHP間の情報伝送
路が正常なら、HPにおいて機器の障害検出を行
い、該データをSPにて受信するのに充分な時間
をみた障害検出タイマーを設定しておく。HPで
はSPから障害検出要求情報を受信したときは該
情報の有効性を識別する。該情報が有効であれ
ば、SPとHP間の情報伝送路でSPの送信側の情
報伝送路(すなわち、HPの受信側の情報伝送
路)に異常がなかつた事が証明される。被障害検
出プロセツサHPでは該情報の要求に基づきHP
が管理する機器の障害検出を行ない、その障害情
報とともに、SPから受信した障害検出要求情報
をそのままSPに返送する。その後SPでは障害検
出タイマーのタイムアウト前にSPから該障害情
報を受信できれば、まずSP→HP→SPと転送さ
れたSPの障害検出要求情報の有効性を識別する
事によりSPとHP間の送受信用情報伝送路の正常
性が確認できる。次いで、情報伝送路に異常がな
い事が判明すれば、SPにて検出した障害情報は
有効となり、SPが管理する機器の障害状況を分
析できる。また、SPにて障害検出要求情報をHP
に送出する際設定した障害検出タイマーがタイム
アウトしてもHPからの返信情報を受信できなけ
れば、情報伝送路もしくはHP側のいずれかが異
常であるか、あるいは、その両者が異常であると
判断できる。このように本発明によればSPを中
心にしてブランチとなつているHPが、システム
として正常な処理が行なえるかどうか、また、
SPとHP間の情報伝送路が正常であるかどうかを
同時に検出する事ができる。
FIG. 2 is a diagram of a failure information transfer method according to the present invention. In Figure 2, the fault management processor SP
sends failure detection request information to the failure detection processor HP through the SP transmission side information transmission path (that is, the HP reception side information transmission path). At this time, if the information transmission path between the SP and the HP is normal, the management processor SP detects a failure in the equipment at the HP and sets a failure detection timer that is long enough for the SP to receive the data. . When the HP receives failure detection request information from the SP, it identifies the validity of the information. If the information is valid, it is proven that there is no abnormality in the information transmission path between the SP and the HP on the sending side of the SP (that is, the information transmission path on the receiving side of the HP). Based on the request for the information, the fault detection processor HP
Detects failures in devices managed by the SP, and sends the failure information as well as the failure detection request information received from the SP back to the SP. After that, if the SP can receive the fault information from the SP before the fault detection timer times out, it first identifies the validity of the fault detection request information of the SP transferred from SP → HP → SP, and then uses the information for transmission and reception between the SP and HP. The normality of the information transmission path can be confirmed. Next, if it is determined that there is no abnormality in the information transmission path, the fault information detected by the SP becomes valid, and the fault status of the equipment managed by the SP can be analyzed. In addition, the fault detection request information is available on the SP website.
If the response information from the HP cannot be received even after the failure detection timer set when sending the message to can. In this way, according to the present invention, it is possible to determine whether the HP, which is a branch centered on the SP, can perform normal processing as a system, and
It is possible to simultaneously detect whether the information transmission path between SP and HP is normal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の障害情報転送方式図、第2図は
本発明の情報転送方式図である。 SP……障害管理プロセツサ、HP……被障害検
出プロセツサ。
FIG. 1 is a diagram of a conventional failure information transfer system, and FIG. 2 is a diagram of an information transfer system of the present invention. SP...fault management processor, HP...fault detection processor.

Claims (1)

【特許請求の範囲】[Claims] 1 マルチプロセツサをもちいた機能分散制御形
電子交換機の障害検出方式において、障害管理プ
ロセツサと被障害プロセツサとを情報伝送路を介
して双方向に接続し、前記障害管理プロセツサか
ら情報伝送路を通して障害検出要求情報を被障害
検出プロセツサに送出し、該情報を受信した被障
害検出プロセツサは自らが管理する機器の障害検
出を行ないその結果得られた障害情報と障害管理
プロセツサから受信した障害検出要求情報とを情
報伝送路を通して障害管理プロセツサに返送し、
しかるのち障害管理プロセツサでは被障害検出プ
ロセツサの障害情報と障害管理プロセツサから被
障害検出プロセツサに送出され、再び障害管理プ
ロセツサに返送された障害検出要求情報とを分析
し障害管理プロセツサと被障害検出プロセツサ間
の情報伝送路と被障害検出プロセツサの障害状況
を同時に検出することを特徴とする電子交換機の
障害検出方式。
1. In a fault detection method for a functionally distributed control type electronic exchange using a multiprocessor, a fault management processor and a faulty processor are bidirectionally connected via an information transmission path, and a fault is detected from the fault management processor through the information transmission path. The detection request information is sent to the fault detection processor, and the fault detection processor that receives the information performs fault detection on the equipment it manages, and then sends the fault information obtained as a result and the fault detection request information received from the fault management processor. and is returned to the fault management processor through the information transmission path,
After that, the fault management processor analyzes the fault information of the fault detection processor and the fault detection request information sent from the fault management processor to the fault detection processor and returned to the fault management processor, and sends the fault information to the fault detection processor and the fault detection processor. A failure detection method for electronic exchanges characterized by simultaneously detecting the failure status of the information transmission path between them and the failure detection processor.
JP17072879A 1979-12-27 1979-12-27 Fault detection system of electronic exchange Granted JPS5693496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17072879A JPS5693496A (en) 1979-12-27 1979-12-27 Fault detection system of electronic exchange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17072879A JPS5693496A (en) 1979-12-27 1979-12-27 Fault detection system of electronic exchange

Publications (2)

Publication Number Publication Date
JPS5693496A JPS5693496A (en) 1981-07-29
JPS6314542B2 true JPS6314542B2 (en) 1988-03-31

Family

ID=15910286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17072879A Granted JPS5693496A (en) 1979-12-27 1979-12-27 Fault detection system of electronic exchange

Country Status (1)

Country Link
JP (1) JPS5693496A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4453213A (en) * 1981-07-30 1984-06-05 Harris Corporation Error reporting scheme
JPS61189756A (en) * 1985-02-19 1986-08-23 Fujitsu Ltd Trouble informing system
JPS6237093A (en) * 1985-08-07 1987-02-18 Hitachi Ltd Control method of number of revolution of air conditioner

Also Published As

Publication number Publication date
JPS5693496A (en) 1981-07-29

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