JP2576266B2 - FSK receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK receiver, and more particularly to an FSK receiver employing a quadrature detection reception system.

[Conventional technology]

In recent years, receivers have been miniaturized due to advances in integrated circuits. However, taking the wireless unit as an example, the integration is not possible because the basic scheme of the circuit is the same as before, or
At present, the limit of miniaturization is approaching due to the presence of elements that are difficult to integrate. For example, in a superheterodyne receiver, high-frequency and intermediate-frequency filters and the like require a large area for integration. Therefore,
To reduce the size and weight of the FSK receiver, a quadrature detection reception system as shown in FIG. 13 has been considered.

The quadrature detection reception system has two systems in which the carrier frequency of the received wave is equal to the local oscillation frequency, the beat of the reception frequency and the local oscillation frequency is extracted by the mixer circuit 102, and only the baseband signal is extracted by the low-pass filter 103. In this method, the baseband signals from these two systems are subjected to demodulation after limiting the amplitude by a limiter circuit 104 to obtain a demodulated signal.

In the quadrature detection reception method, the intermediate frequency becomes zero because the local oscillation frequency and the carrier frequency match, so that the image frequency does not exist. This means that the high-frequency amplifier 101 does not require any highly selective filter for attenuating the image frequency. In addition, the low-pass filter 103 acting as a channel filter for attenuating adjacent channel interference waves can be configured with a low-frequency active filter because the intermediate frequency is zero, and is realized on an integrated circuit. It becomes possible.

As described above, by using the quadrature detection reception method, the high frequency filter, the intermediate frequency filter, and the like can be eliminated, so that the FSK receiver can be reduced in size and weight.

[Problems to be solved by the invention]

However, the quadrature detection receiving system uses a mixer circuit 102, a low-pass filter 103, and a limiter circuit 104 as shown in FIG.
However, the conventional FSK receiver of the quadrature detection method has a drawback that the current consumption is larger than that of the FSK receiver of the single super heterodyne method.

[Means for solving the problem]

An FSK receiver according to the present invention is a FSK receiver for receiving a modulated wave frequency-modulated by a binary digital signal. In the FSK receiver, the frequency output by a voltage controlled oscillation circuit is substantially equal to the carrier frequency of the modulated wave. A first and second system for generating a baseband signal from the modulated wave by a mixer circuit using a signal, and a demodulation signal by performing signal processing on the baseband signal output from the first and second systems. A quadrature detection demodulation circuit for obtaining the following, and first means for frequency-detecting the baseband signal output from the first system,
A second means for outputting an average voltage of the signal output from the first means, a third means for generating a signal obtained by adding an offset voltage to the average voltage and a signal obtained by subtracting the signal,
Outputting a stop signal when the signal output from the first means is between two output signals of the third means;
Means for controlling an output frequency of the voltage-controlled oscillation circuit by an output voltage and holding the output voltage by the stop signal; and power supply control means for supplying power to the second system by the stop signal. Have.

The first and second systems may each include a mixer circuit, a low-pass filter, and a limiter circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

First, the demodulation operation of the embodiment shown in FIG. 1 will be described.

The received wave frequency-modulated by the binary digital signal of the mark or space is amplified by the high-frequency amplifier 101, and
The signals are divided and input to the mixer circuits 102, respectively. The local oscillation signal output from the voltage controlled oscillation circuit 109 is 9
The phase is input to the 0-degree phase shifter 108 and the phase is rotated by +45 degrees and −45 degrees, respectively, and then input to the mixer circuit 102.

By adopting such a circuit configuration, a signal whose phase is shifted by 90 degrees is frequency-converted from the mixer circuit 102 to the base bud and output. As described later, the voltage-controlled oscillation circuit 10
9 is controlled by the AFC circuit 110, and the carrier frequency matches the local oscillation frequency, so that the baseband signal becomes the beat frequency. The low-pass filter 103 extracts only the baseband signal and limits the band of noise. Each of the baseband signals is input to the limiter circuit 104 and binarized to be signals I and Q.

The waveforms of the signals I and Q are, for example, as shown in FIG.
Here, the data indicates data transmitted by the received wave. The signals I and Q are input to the demodulation circuit 105 to perform frequency detection. The demodulation circuit 105 is composed of a D flip-flop as shown in FIG. The clock input CL of the D flip-flop is signal I and the data input D is signal Q.
Then, when data is counted at the rising edge of the clock, the output becomes like the output L shown in FIG.
When the phases of I and Q change by 90 degrees, the output L also changes and data is demodulated.

The demodulated signal thus demodulated passes through a low-pass filter 106 for removing noise, is binarized by a comparator circuit 107, and output as a binary digital signal.

 Next, the AFC circuit 110 will be described.

 FIG. 4 is a block diagram of the AFC circuit 110.

In FIG. 4, 10 is a demodulation circuit, 11 is a low-pass filter, 12 is an average value circuit, 13 is an offset circuit, 14 and 15 are comparator circuits, 16 is an AND circuit, and 17 is a sawtooth wave generation circuit. FIG. 4 also shows the voltage controlled oscillation circuit 109 in FIG.

The AFC circuit 110 detects the offset frequency with respect to the carrier frequency by frequency-detecting the output signal Q of the limiter circuit 104, and when the offset frequency falls within a certain value, the self-running voltage control oscillation circuit 109 is fixed. It stops the frequency and causes the local oscillation frequency to follow the carrier frequency of the received wave.

FIG. 5 is a diagram showing signal waveforms at various parts of the AFC circuit 110.

The operation of the AFC circuit 110 will be described with reference to FIG.

It is assumed that the signal Q is an output of the limiter circuit 104 and has an offset frequency ΔF. That is, the frequency of the signal Q in the mark or space is ± FD-ΔF
(FD is frequency shift).

It is assumed that the demodulation circuit 10 is a delay detection circuit including a delay circuit 61 having a delay time T and an exclusive OR circuit 62 as shown in FIG. 6 as an example. The output of the demodulation circuit 10 is a pulse wave having a pulse width T indicated by D. By integrating the pulse wave D with the low-pass filter 11 shown in FIG.
A voltage output 0 proportional to the frequency of the signal Q is obtained.

The average value of the voltage output 0 is independent of the offset frequency ΔF, and becomes a voltage output corresponding to the frequency shift FD. This is because the frequency of the signal Q is FD−ΔF and | −FD−ΔF | = FD
Since it is + ΔF, the average value of the frequency is FD. Signal 0
The average value A is obtained by the average value circuit 12. The time constant is set sufficiently longer than 1 / BR (BR is the bit rate). The average value circuit 12 in this embodiment is a primary RC integration circuit as shown in FIG. The average value A is input to the offset circuit 13, and a voltage of ± ΔV is added, and VH =
A + ΔV and VL = A−ΔV are generated. 0 and VH, 0 and VL are input to the comparator circuits 14 and 15 so that the output VOH of the comparator circuit 14 is high when 0 <VH and the output VOL of the comparator circuit 15 is high when 0> VL. Is done. VOL and VOH are input to the AND circuit 16, and the output C of the AND circuit 16 becomes high only when both VOL and VOH are high. This indicates that the signal C becomes high when the signal 0 is within ΔV from the average value A.

 The above is shown with specific numerical values.

Assuming that the demodulation sensitivity in the demodulation circuit 10 is KD (V / kHz), the signal 0 becomes KD (FD ± ΔF), and the signal C becomes high when ΔV> KD · ΔF. KD = 10mV / kHz, ΔV = 10mV
In this case, the signal C becomes high when ΔF <1 kHz.

The offset circuit 13 is shown in FIG. The average value A generates an offset voltage ± ΔV by resistors 68, 69 and constant current circuits 66, 67 through a voltage follower 65. As shown in FIG. 10, the comparator circuits 14 and 15 each include a differential amplifier including transistors 77 and 78, resistors 75 and 76, and a constant current circuit 79, and a level shift circuit including transistors 80 and a resistor 81. doing.

 FIG. 11 is a block diagram of the sawtooth wave generation circuit 17.

The sawtooth wave generation circuit 17 includes an RS latch 91 and a comparator.
The constant current circuits 83 and 84 are controlled using 89 and 90, and the constant current circuits 83 and 84 are controlled.
When the voltage of the capacitor 82 becomes higher than the high voltage side set voltage VCH, the RS latch 91 is inverted and the capacitor 82 is rapidly discharged by the constant current circuit 84. Next, set the constant voltage side
When the voltage falls below VCL, the RS latch 91 reverses and the constant current circuit 8
This circuit generates a sawtooth wave by repeating the start of charging by step 3. Saw wave generator 17
Stops the self-running when the signal C is high, and the voltage VT at that time
To maintain. When signal C goes high, switch 92
Is closed, the constant current circuits 83 and 84 are turned off, and a high impedance state is established.

The output VT of the sawtooth wave generation circuit 17 is the voltage-controlled oscillation circuit 10
Entered in 9. For this purpose, the voltage controlled oscillation circuit 109 outputs the output VT as shown in FIG.
In a cycle of, it will be self-propelled. Here, since one cycle is within one bit, the cycle of the sawtooth wave needs to be shorter than one bit length.

Further, as shown in FIG. 12, the local oscillation frequency needs to change above and below the carrier frequency FC. This is the AFC circuit 110
It is not possible to determine whether the beat frequency input to the oscilloscope has a positive frequency offset or a negative frequency, so the local oscillation frequency FL changes above and below the carrier frequency FC. This is because it is necessary to detect a point where the offset is reduced.

When the local oscillation frequency changes periodically, the frequencies FI and FQ of the baseband signals I and Q also change. For this reason, since the error between the carrier frequency FC and the local oscillation frequency FL may be within a predetermined frequency at least once in one bit, the signal C also becomes high at least once in one bit. . The output of the sawtooth wave generation circuit 17 at this point
Since VT becomes a constant value, the local oscillation frequency FL falls within a predetermined frequency of the carrier frequency FC and AFC is applied.

Next, the power supply control circuit 111 will be described. AFC circuit 11
If the local oscillation frequency FL is not fixed by 0,
It can be considered that the intensity of the modulated wave of the carrier frequency FC is weak or when no signal is transmitted. for that reason,
It is sufficient that the power of the mixer circuit 102, the low-pass filter 103, and the limiter circuit 104 of the lower system 2 connected to the AFC circuit 110 be turned on, and the power of the system 1 is turned on except when the signal C is high. No need. When the signal C is high, that is, when the local oscillation frequency FL follows the carrier frequency FC and the AFC is applied, the power supply control circuit 111 controls the mixer circuit 102 of the upper system 1 shown in FIG. The power of the filter 103 and the limiter circuit 104 is turned on.

〔The invention's effect〕

As described above, according to the present invention, it is possible to stop one system of the mixer circuit which consumes a large amount of current when there is no signal, so that the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
3 is a waveform diagram for explaining the operation of the demodulation circuit 105, FIG. 3 is a block diagram of the demodulation circuit 105, and FIG.
FIG. 5 is a block diagram of the AFC circuit 110, and FIG.
Waveform diagrams of various signals in FIG. 10, and FIGS. 6, 7, 8, 9, 10, 11 show the demodulation circuit 10, low-pass filter 11, average value circuit 12, offset circuit 13, comparator circuits 14 and 15 in FIG. 12 is a block diagram showing the sawtooth wave generating circuit 17, FIG. 12 is a waveform diagram for explaining the operation of the AFC circuit 110 in FIG. 1, and FIG. 13 is a block diagram of an example of a conventional FSK receiver. 10 demodulation circuit, 11 low-pass filter, 12 average circuit, 13 offset circuit, 14, 15 comparator circuit, 16 AND circuit, 17 sawtooth wave generation circuit, 101 …… High frequency amplifier, 102 …… Mixer circuit, 103…
… Low-pass filter, 104… limiter circuit, 105… demodulation circuit, 106… low-pass filter, 107… comparator circuit, 108… 90-degree phase shifter, 109… voltage-controlled oscillation circuit, 110 …… AFC circuit, 111 …… Power supply control circuit.

Claims (2)

(57) [Claims] An FSK receiver for receiving a modulated wave frequency-modulated by a binary digital signal uses a local oscillation signal whose frequency output by a voltage controlled oscillator is substantially equal to the carrier frequency of the modulated wave. First and second systems for generating a baseband signal from the modulated wave by a mixer circuit;
A quadrature detection demodulation circuit that obtains a demodulated signal by performing signal processing on the baseband signal output by the first and second systems; and a quadrature detection demodulation circuit that performs frequency detection on the baseband signal output from the first system. (1) means, second means for outputting an average voltage of the signal output from the first means, and (iii) third means for generating a signal obtained by adding an offset voltage to the average voltage and a signal obtained by subtracting the signal. A fourth means for outputting a stop signal when a signal output from the first means is between two output signals of the third means; and an output frequency of the voltage-controlled oscillation circuit according to an output voltage. An FSK receiver comprising: an oscillation circuit that controls the power supply and holds an output voltage according to the stop signal; and a power supply control unit that supplies power to the second system according to the stop signal. 2. The FSK receiver according to claim 1, wherein said first and second systems each include a mixer circuit, a low-pass filter, and a limiter circuit.