JP2546198B2 - Speed control device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed control device suitable for use in, for example, an optical compact disc player.

[0002]

2. Description of the Related Art For example, in an optical compact disc, signals are spirally recorded from the inner circumference to the outer circumference of the disc at a constant linear velocity. Therefore, even when reproducing such a disc, it is necessary to apply a servo to the rotation of the disc so that the linear velocity is the same as that at the time of recording.

In this case, for example, it has been proposed to detect the distance between the reproduction position of the pickup and the center of the disk and calculate the rotational speed from this distance to perform servo, but in this method, an arithmetic circuit or the like is used. Had a complicated configuration, and the servo accuracy was not very high.

By the way, in recording on a compact disc, so-called run length limited coding is performed, and for example, the minimum and maximum of the number of consecutive "0" s are defined. Further, a pattern in which "0" continues for the maximum number (for example, 11) always exists as a frame synchronization signal every predetermined period.

Therefore, the inventor of the present application has previously proposed the following speed control device.

In FIG. 3, a signal taken out by a photodetector 1 from a disk (not shown) is supplied to a waveform converting circuit 2 and a differentiating circuit 3 to reproduce a signal corresponding to "0" or "1". And is supplied to the first contact A of the selector circuit 4. Further, the signal from the differentiating circuit 3 is supplied to the sync separation circuit 5. Here, the separation circuit 5 includes a PLL, and is locked to the clock signal in the reproduction signal to separate the frame synchronization signal. At the same time, the lock range of the PLL is narrowed so that the lock is not applied. Are taken out.

The separated synchronizing signal is the selector circuit 4.
Is supplied to the second contact B of the. Further, a reference clock generator 6 is provided, and from this generator 6, a reference clock signal having a frequency (for example, 2.16 MHz) equal to the clock signal in the reproduced signal when a predetermined servo is applied is formed. This reference clock signal is supplied to the frequency dividing circuit 7 to form a signal corresponding to four times (4 frames) of the frame synchronization signal, and this signal is supplied to the third contact C of the selector circuit 4.

The PLL lock display signal from the separation circuit 5 is supplied to the selector 4, and the selector 4 is connected to the contact A while the signal is "0". The selector 4 is normally connected to the contact B. The signal from the selector 4 is supplied to the reset terminal of the counter 8 and the clock signal from the generator 6 is supplied to the count terminal of the counter 8.

When the number of consecutive "0" s in the frame synchronization signal is 11, for example, an output indicating that the count number of the counter 8 is "8" is supplied to the NAND circuit 9 and the count number is " The output indicating "2" is the delay circuit 10
Is supplied to the NAND circuit 9 through. Therefore, the output of "1" is usually extracted from the NAND circuit 9 and
The output becomes "0" at the time corresponding to the time when the count value becomes "10" and the count value after a predetermined delay time becomes "11". This output signal is supplied to the enable terminal of the counter 8 so that the output of the counter 8 is fixed at "11" and is also supplied to the selector 4 so that this signal is "0".
During the period, the selector 4 is connected to the contact C.

Further, the output of the NAND circuit 9 is the inverter 1
1, the low-pass filter 12 and the resistor 13 are supplied to the inverter 14.

Further, the clock signal from the generator 6 is supplied to the frequency dividing circuit 15 to form a reference frame synchronizing signal,
This signal and the reproduction frame synchronization signal from the separation circuit 5 are supplied to the flip-flop circuit 16 and the phase difference between them is output. This output is supplied to the inverter 14 through the NAND circuit 17, the low pass filter 18, and the resistor 19.

As a result, the inverter 14 outputs an output corresponding to the length of the period in which the output of the counter 8 is "11" and the phase difference between the reference frame synchronization signal and the reproduction frame signal.

The output of the inverter 14 is the NAND circuit 2
The lock display output from the separation circuit 5 is supplied to the NAND circuit 20 while being supplied to 0. This NAND circuit 20
Is supplied to the bases of the npn transistor 21 and the pnp transistor 22. The output of the inverter 14 is supplied to the bases of the npn transistor 23 and the pnp transistor 24. The collectors of the transistors 21 and 23 are connected to the power supply terminal, and the transistors 22 and 24 are connected.
The collector of is grounded. Further transistors 21, 2
The two emitters are connected to each other and the transistors 23, 2
The four emitters are connected to each other, and the spindle motor 25 for rotating the disk is connected between the connection points.

In this circuit, "0" is supplied to the NAND circuit 20 until the PLL of the separation circuit 5 is locked, the output of the NAND circuit 20 is "1", the transistor 21 is turned on, and 22 is turned on. It has been turned off. At this time, the selector 4 is connected to the contact A, and the reproduction signal is directly supplied to the counter 8. Therefore, when the rotation of the disk is slow and the signal is extended, the counter 8 frequently becomes "11" and the output of the NAND circuit 9 becomes "0".

With this output, the counter 8 is stopped, the selector 4 is switched to the contact C, and the counter 8 is stopped for four frame periods. And the output of the NAND circuit 9 is "0".
As a result, the output of the inverter 14 becomes "0", the transistor 23 is turned off, and the transistor 24 is turned on so that a current flows in the direction of the arrow to the motor 25 and the rotation speed of the motor 25 is increased.

As a result, the rotation speed of the disk is increased until the maximum signal interval becomes about 11 clocks.

Further, at this time, the PLL of the separation circuit 5 is locked, the selector 4 is switched to the contact B, and "1" is supplied to the NAND circuit 20. Therefore, the separated frame synchronization signal is supplied to the counter 8. When the length of the synchronizing signal is 11 clocks or more, the output of the NAND circuit 9 becomes "0", the output of the inverter 14 becomes "0", and the output of the NAND circuit 20 becomes "1" as in the above. , The transistors 21 and 24 are turned on, 2
When the motors 2 and 23 are turned off, a current flows through the motor 25 in the direction of the arrow, and the rotation speed is increased.

On the other hand, when the length of the synchronizing signal becomes 11 clocks or less, the output of the NAND circuit 9 becomes "1",
The output of the inverter 14 is "1", the output of the NAND circuit 20 is "0", and the transistors 21 and 24 are off.
3 is turned on, a current is passed through the motor 25 in the direction opposite to the arrow, and the rotation speed is reduced.

Thus, the rotation speed servo is applied to the disk so that the length of the synchronizing signal becomes 11 clocks.

At this time, the flip-flop circuit 16 outputs "1" between the reproduction synchronizing signal and the reference synchronizing signal.
Then, a signal of "0" is taken out from the reference sync signal to the next reproduction sync signal. Therefore, when the reproduction sync signal is delayed from the position having a phase difference of 180 degrees from the reference sync signal, the period of the signal is "0" is long, and when it is advanced, the period of "1" is long. When the signal is "0", the output of the NAND circuit 17 is "1", the output of the inverter 14 is "0", the output of the NAND circuit 20 is "1", and the rotation speed of the motor 25 is increased. . On the contrary, when the signal is "1", the rotation speed is reduced.

As a result, the rotational phase servo is applied to the disk so that the synchronizing signal comes to a predetermined position.

In this way, the disk is subjected to the constant rotational speed servo and the rotational phase servo. In this case, since the counter 8 is also used to pull in the speed at the beginning of rotation, it is possible to favorably pull in the speed with a simple configuration.

However, in the case of this circuit, the rotation speed servo detects the length (11 clocks) of the synchronizing signal by the clock signal, and therefore the accuracy of this servo is 1/11 which is extremely coarse.

Here, for example, in a phase servo system, if the frame synchronization signal is multiplied and the phase servo is applied at a frequency higher than the original frame synchronization signal (for example, 7.35 kHz), it is necessary to improve the accuracy of the speed servo. is there. In such a case, the coarse servo as described above could not raise the frequency of the phase servo, so that good servo could not be performed.

[0025]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to enable a highly accurate speed servo with a simple structure.

[0026]

According to the present invention, a frame containing a predetermined number of encoded digital data and a boundary between the frames can be detected so that a predetermined bit is inserted at a predetermined position in each frame. Reading means (photodetector 1) for reading an information signal including a synchronizing signal having a pattern from a recording medium, and synchronizing signal detection for detecting the synchronizing signal from the reading signal obtained from the reading means to generate a reproduction synchronizing signal. In the information reading apparatus, the recording medium at the information detection point includes means (synchronization separation circuit 5) and clock signal generation means (clock generator 6) for generating a clock signal for processing the digital data at predetermined time intervals. A speed control device for controlling a relative moving speed in the track extension direction with respect to It counts the serial clock signal by a predetermined number
And a counting means (counter 39) for generating a speed control pulse having a pulse width over a period in which the clock signal is counted by a predetermined number.
It is a speed control device characterized by controlling the relative moving speed according to the life .

[0027]

According to this, extremely accurate speed servo can be performed with a simple structure.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, the signal from the differentiating circuit 3 is 1
This multi-vibrator 30 is supplied to the retriggerable monostable multi-vibrator 30 for one clock inversion period.
Is supplied to the retriggerable monostable multivibrator 31 in the inversion period of 4 frames. Further, the lock display signal from the sync separation circuit 5 is sent to the multivibrator 30,
31 is supplied to the inversion enable terminal.

In these circuits, the multivibrators 30 and 31 are in operation until the separation circuit 5 locks. During this period, if the interval of "1" in the reproduced signal is 11 clocks or more, the multivibrator 30 is inverted and the signal of "1" is taken out from the multivibrator 31 for four frame periods. When the interval of "1" is repeatedly 11 clocks or more, the output of the multivibrator 31 continuously becomes "1".

This signal is passed through the resistor 32 to the comparison circuit 3
3 is supplied.

An arbitrary potential from the voltage dividing circuit 34 is supplied to the comparison circuit 33. Here, if the input signal is "1", the output of the comparison circuit 33 is also "1". This comparison output is supplied to the NAND circuit 35 and also to the NAND circuit 37 through the inverter 36.
The outputs of 5 and 37 are supplied to the bases of the transistors 21, 22 and 23 and 24, respectively.

Therefore, when the output of the multivibrator 31 becomes "1" while the other input of the NAND circuits 35 and 37 is normally "1" in the period until the synchronization separation circuit 5 is locked, the motor 25 is indicated by an arrow. A current is applied in the direction, and the rotation of the disk is accelerated until it reaches a substantially predetermined speed, so-called retraction is performed.

Further, the sync signal from the sync separation circuit 5 is supplied to the reset terminal of the counter 39 through the NAND circuit 38. Further, the lock display signal from the separation circuit 5 is supplied to the NAND circuit 38. Further, the clock signal from the clock generator 6 is supplied to the count terminal of the counter 39 through the NAND circuit 40.

Then, for example, the clock frequency is 2.16M.
Hz and the frame frequency is 7.35 kHz,
The count value of the counter 39 is "1", "32",
The output indicating “256” is supplied to the NAND circuit 41, and when the count value reaches “289”, the output of the NAND circuit 41 becomes “0”. This output is supplied to the NAND circuit 40, after which the supply of the clock signal is stopped and the counter 3
The output of 9 is fixed to "289".

Further, the output of the NAND circuit 41 is supplied to the switching element 45 through the inverter 42, the integrating circuit 43, and the amplifier 44, the switching element 45 is turned on by the output of the NAND circuit 38, and the signal when this is turned on is generated. It is supplied to the capacitor 46.

In these circuits, when there is a frame sync signal as shown in A of FIG.
The output of 2 is as shown in B of FIG. Here, 2.16 (MHz) ÷ 7.35 (kHz) ≈294, and the period during which the output of the inverter 42 becomes “1” is 294-289 = 5 about 5 clock periods. This signal is supplied to the integrating circuit 43 to form a signal as shown in C of FIG. 2, and this signal is sampled and held at the output of the NAND circuit 38 and
A peak value is taken out as indicated by D in FIG. 1 and this peak value corresponds to the interval of the reproduction synchronizing signal, that is, the speed of the disc.

This signal is passed through the resistor 47 to the comparison circuit 3
3 is supplied.

Further, the sync signal from the sync separation circuit 5 is supplied to the reset terminal of the flip-flop circuit 49 through the differentiating circuit 48. Further, the reference synchronizing signal from the frequency dividing circuit 15 is supplied to the NAND circuit 50, and the NAND circuit 50
The lock display signal from the separation circuit 5 is supplied to the NAND circuit 50, and the output of the NAND circuit 50 is supplied to the set terminal of the flip-flop circuit 49 through the differentiating circuit 51. The output of the flip-flop circuit 49 is supplied to the integrating circuit 52.

In these circuits, when the reference synchronizing signal is as shown in E of FIG. 2, when the separation circuit 5 is locked, a signal as shown in F of FIG. 2 is taken out from the flip-flop circuit 49. Be done. This signal is integrated to form a signal corresponding to the phase difference between the reproduction sync signal and the reference sync signal, such as G in FIG.

This signal is a DC blocking capacitor 53,
It is supplied to the comparison circuit 33 through the resistor 54.

Therefore, the comparison circuit 33 includes a capacitor 46.
2 and the signal from the integration circuit 52 are resistance-added, and a signal as shown by H in FIG. 2 is supplied. This signal is compared at an arbitrary comparison level a, and a pulse width modulated signal corresponding to the disc speed and the phase difference of the synchronizing signal as shown in I of FIG. 2 is taken out.

Therefore, in the period after the synchronization separation circuit 5 is locked, when the other input of the NAND circuits 35 and 37 is normally "1", when the output of the comparison circuit 33 becomes low potential, the motor 25 is arrowed. The electric current is applied in the direction of, and when the electric potential becomes high, the opposite current is applied to perform the speed of rotation of the disk and the phase servo.

Further, the lock display signal from the sync separation circuit 5 is supplied to the retriggerable monostable multivibrator 55 during the inversion period of, for example, 3 frames, the output is supplied to the NAND circuit 56, and the display signal is supplied to the inverter 57.
Through the NAND circuit 56. The output of the NAND circuit 56 is supplied to the other inputs of the NAND circuits 35 and 37.

In these circuits, when the separation circuit 5 is normally locked, the multivibrator 55 is not inverted, the outputs of the multivibrator 55 and the inverter 57 are both "0", and the output of the NAND circuit 56 is "1". Is supplied to the other inputs of the NAND circuits 35 and 37. On the other hand, when the reproduced signal drops out due to scratches on the disk surface or the like and the lock display signal of the separation circuit 5 is no longer output, the multivibrator 55 is inverted at the fall of the display signal and the output becomes "1". Also, the output of the inverter 57 becomes "1" and the NAND circuit 56
Output becomes "0".

As a result, the outputs of the NAND circuits 35 and 37 are both fixed at "1", the transistors 21 and 23 are turned on, and the transistors 22 and 24 are turned off, so that no current flows through the motor 25 and the motor 25 has only inertia. Is rotated by. When the display signal is restored, the output of the inverter 57 becomes "0" and the output of the NAND circuit 56 becomes "1". Further, when the display signal is "0" continuously for 3 frames or more at the time of start-up or a long dropout, the output of the multivibrator 55 is returned to "0", and the output of the NAND circuit 56 becomes "1". The pull-in operation is performed by the circuits of the multivibrators 30 and 31.

Therefore, when a normal reproduction signal cannot be obtained due to dropout or the like, the current of the motor 25 is cut off to prevent the servo from running out of control due to an incorrect signal. When is greatly deviated, the pull-in operation is performed.

In this way, pull-in, speed servo,
Phase servo and dropout processing are performed, but according to this circuit, especially in the speed servo, 28
Since the deviation of the servo with respect to 9 clocks is detected,
The accuracy of the servo becomes extremely high, and even if the frequency of the phase servo is increased, it can be sufficiently dealt with. In addition, since it is a digital servo that uses a counter, the influence of temperature characteristics etc. is extremely small.

In FIG. 1, the reference synchronizing signal from the frequency dividing circuit 15 is supplied to the reset terminal of the counter 39, the clock signal obtained by multiplying the reproduction synchronizing signal is supplied to the counting terminal, and the phase of the comparing circuit 33 is reversed. However, the same operation can be obtained.

[0049]

According to the present invention, highly accurate speed servo can be performed with a simple structure.

[Brief description of drawings]

FIG. 1 is a system diagram of an example of a speed control device according to the present invention.

FIG. 2 is a waveform diagram for explaining that.

FIG. 3 is a system diagram of a conventional speed control device.

[Explanation of symbols]

5 Sync Separation Circuit 6 Clock Generator 15 Frequency Dividing Circuit 33 Comparing Circuit 39 Counter 43, 52 Integrating Circuit 45, 46 Switching Device and Capacitor for Sample and Hold 49 Flip-Flop Circuit for Phase Difference Detection

Claims (1)

(57) [Claims] 1. A frame including a predetermined number of encoded digital data and a sync signal having a predetermined bit pattern inserted at a predetermined position in each frame so that a boundary between the frames can be detected. A reading means for reading an information signal from a recording medium; a synchronizing signal detecting means for detecting the synchronizing signal from the reading signal obtained from the reading means to generate a reproduction synchronizing signal; and a clock signal for processing the digital data. A speed control device for controlling a relative moving speed of an information detection point in the track extending direction with respect to the recording medium in an information reading device including a clock signal generating means which generates at a predetermined time interval, The clock signal is counted by a predetermined number , and the clock signal is counted by a predetermined number. comprising a counting means for generating a speed control pulse having a pulse width over a <br/> period, speed control and controls the relative movement speed in response to occurrence of the speed control pulse apparatus.