JP2512945B2 - Image memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device for writing image data in a memory while synthesizing the image data.

[Conventional technology]

Conventionally, in such an apparatus, when synthesizing image data, a control circuit (hereinafter referred to as CPU) takes in the image data based on a control program, and shift-merges the data to be synthesized into a predetermined area of the taken-in image data ( (Shift composition) and write to the image memory.

[Problems to be solved by the invention]

However, in the above device, since the CPU shift-merges the image data based on the program, there is a drawback that it is difficult to obtain sufficient high speed and the shift operation of the CPU takes time. There is also a method of processing by using a CPU having a fast shift operation, but such a method has a problem that the cost becomes high because an expensive CPU must be used.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image memory device that can realize a shift merge function of image data at low cost and at high speed.

[Means and Actions for Solving Problems]

According to the present invention, in an image memory device in which additional data consisting of a predetermined bit is inserted at the beginning of image data input in a predetermined bit number unit and stored in an image memory, the image data is stored in the predetermined bit unit. A first shift register, a second shift register for storing the additional data, and the data stored in the first shift register are shifted bit by bit from the lower bit side to the first bit of the second shift register. And the second
Shift means for repeating the operation of shifting the data stored in the shift register from the lower bit side to the head bit of the first shift register bit by bit, and the shift means by the shift means ends the operation. Writing means for writing the data held in the first shift register in the image memory in units of the predetermined number of bits, and in response to storing the image data in the first shift register, The shift operation by the shift means and the write operation by the write means are repeated.

Therefore, according to the present invention, the image data can be written in the image memory at a high speed by having a shift merge function of the image data by hardware.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings of FIGS.

FIG. 1 is a schematic configuration diagram of an image memory device according to the present invention, FIG. 2 is image data when an input data width (1 word) is 8 bits, and (a) is sent from the CPU to the image memory device. FIG. 7B is a diagram showing image memory data in the case of being written, and FIG.
In this embodiment, it is assumed that 4-bit data "1111" is shift-merged at the beginning of the image data sent from the CPU.

In FIG. 1, the first shift register 11 holds image data (see FIG. 2 (a)) from a CPU (not shown), and the second shift register 13 is operated by the first shift register 11 described above. The preset data “1111 ***” to be merged at the beginning of the shifted image data is held. Of the above preset data, "*****"
Can be "0" or "1". The selector 14 constitutes a shift register control circuit 17 together with a shift load control circuit 16 which will be described later. Based on a select signal 18 from the shift load control circuit 16, the selector 14 outputs 8-bit input data 15 from the second shift register 13. Among them, a specific bit, in this example, the fourth bit from the left is selected. Image memory 20
Is a storage device for storing the shift-merged image data 21 (see second (b)). In addition to the control of the first and second shift registers 11 and 13 and the selector 14, the shift load control circuit 16 sends a write or read mode signal 22 to the image memory 20 to control writing and reading. ing.

 Next, the operation of the image memory device will be described.

First, the CPU activates the selection signal 23 and sends the control input data 24 to the shift load control circuit 16. The control input data 24 is stored in the first and second shift registers 11 and 13.
Data for defining the number of shifts, and in this example, the number of shifts is 4, which is the same as the number of bits of data to be combined, and is fetched and set in the shift load control circuit 16. The shift load control circuit 16 uses the control input data
Based on 24, the select signal 18 for controlling the select operation of the selector 14 is activated. As a result, the selector 14 can select the 4th bit data from the left of the input data 15 and send it as the shift-in data 25 to the first shift register 11.

Next, the CPU activates the load mode selection signal 26 to set and hold the preset data 27 “1111 ***” in the second shift register 13 described above. Then, the address signal 28 is sent to the image memory 20, the image data (see FIG. 2 (a)) is placed on the image input data 12, and the image memory access signal 29 is activated to set the write signal 30 to the shift load control circuit 16 described above. Send to. When the shift load control circuit 16 receives the write signal 30, it activates the load mode selection signal 31 and loads the image data on the image input data 12 into the first shift register 11 word by word.

Next, the shift load control circuit 16 activates the shift mode selection signal 32 by 4 bits in order to shift the data of the number of bits (4 bits) set by the selection signal 23. As a result, the first shift register 11
Is the first word "000100" of the loaded image data.
The right 4 bits "0010" of 10 "(see second (a)) are sequentially output from the right as out data 33. This out data 33 becomes shift-in data of the second shift register 13 and It is taken into the register 13.

By the way, the preset data “11” is stored in the second shift register 13 before the shift-in data is fetched.
11 *** ”is held, and this 8-bit preset data is input to the selector 14 as the input data 15.
The selector 14 selects the 4th bit data “1” from the left of the input data 15 “1111 ***” and outputs the above data “1”.
Is output to the first shift register 11 as shift-in data 25. When the shift-in data 25 is fetched from the selector 14 bit by bit, the first shift register 11 reads "00".
The shift operation of 10 "is performed bit by bit from the right. The data in the register 11 at this time becomes" 10001001 ".
Next, when the right side data “0” output from the first shift register 11 is taken into the second shift register 13, the data in the register 13 becomes “01111 ***”, and the data is real-time. Input to selector 14. As described above, the selector 14 selects the data “1” of the 4th bit from the left and outputs this data to the first shift register 11. The first shift register 11 fetches the above-mentioned data and shifts out the data of "1" on the right side at the same time.
Output as 33. As a result, the data in the register 11 becomes "11000100". Then, the first and second shift registers 11 and 13 and the selector 14 perform the above-mentioned shift and select operations for 4 bits, and the first shift register 1
When the data in the inside becomes "11110001" of the first word shown in FIG. 2 (b), the above operation is ended. Next, the shift load control circuit 16 outputs a write signal when the image memory 21 becomes stable due to the completion of the shift and select operations.
22 is sent to the image memory 20. When the write signal 22 is input, the image memory 20 takes in the image memory data 21 “11110001” from the first shift register 11 and writes it. After the above writing is completed, the shift load control circuit 16
The read mode signal 22 is sent to the image memory 20 to return the image memory 20 to the read mode. Next, the CPU again sends the address signal 28 to the image memory 20, puts the image data on the image input data 12, and sends the image memory access signal 29.
Is activated to send a write signal 30 to the shift load control circuit 16. When the shift load control circuit 16 receives the write signal 30, it activates the load mode selection 31 and sets the first word of the image data “00110100” (see FIG. 2A) of the second word on the image input data 12. The shift register 11 is loaded. Then, the first and second shift registers 11 and 13 and the selector 14 are caused to perform the same operation as described above to shift-merge the data. At this time, the last data "00101111" when the first word image data is shift-merged is stored in the first shift register 13.
Is held. The same operation control as described above may be performed for the image data of 3 words or more. Reference numeral 34 is a synchronous clock for synchronizing the first and second shift registers 11 and 13, and the shift operation of the shift registers 11 and 13 is performed in synchronization with the clock. Reference numeral 35 is output data read from the image memory 20 based on the address signal of the CPU.

Therefore, according to the present invention, the input image data shown in FIG. 2 (a) is shifted to the beginning by another 4 bits by the shift merge function by the shift register to shift the image memory data shown in FIG. 2 (b) by 4 bits. Since the data is generated, the shift operation time is shortened, and the above data can be written in the image memory at high speed.

Note that the present invention has been described with respect to image data that composes one word with 8 bits.
It can also be used for image data in which one word is composed of bits, 32 bits or more. Further, in the above case, when the number of bits forming one word is large, different shift registers may be connected to the first and second shift registers to deal with the number of bits.

〔The invention's effect〕

As described above, according to the present invention, the data stored in the first shift register is shifted bit by bit from the lower bit side to the head bit of the second shift register and stored in the second shift register. The operation of shifting the data one bit at a time from the lower bit side to the first bit of the first shift register is repeated for the number of bits of the additional data, and after the completion of this shift operation, the data held in the first shift register is written to the image memory. Since the operation is configured to be repeated, the soft merge function of image data can be configured at low cost, and the shift merge operation of image data can be realized at high speed.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment according to the present invention, and FIG. 2 is a diagram showing image data when an input data width is 8 bits. 11,13 …… Shift register, 12 …… Image input data, 14
...... Selector, 16 …… Shift load control circuit, 17 …… Shift register control circuit, 20 …… Image memory, 21 …… Image memory data, 27 …… Preset data

Claims (1)

(57) [Claims] 1. An image memory device in which additional data consisting of predetermined bits is inserted at the beginning of image data input in a predetermined bit number unit and stored in an image memory, wherein the image data is stored in the predetermined bit unit. First to do
Shift register, a second shift register for storing the additional data, and the data stored in the first shift register are shifted bit by bit from the lower bit side to the first bit of the second shift register. A shift means for repeating the operation of shifting the data stored in the second shift register bit by bit from the lower bit side to the head bit of the first shift register, the shift means repeating the number of bits of the additional data; After the end of the operation, the first
Writing means for writing the data held in the shift register in the image memory in units of the predetermined number of bits, and in response to the storage of the image data in the first shift register, the shift by the shift means is performed. An image memory device characterized by repeating an operation and a writing operation by the writing means.