JP2506811B2 - Data processing method in RDS receiver - Google Patents

Description

TECHNICAL FIELD The present invention relates to a receiver of a radio data system (hereinafter referred to as RDS).
A data processing method in a receiver).

BACKGROUND ART Broadcasting-related information such as information related to the program content is transmitted as data at the time of broadcasting from a broadcasting station by multiplex modulation, and the desired program content can be selected on the receiving side based on the demodulated data. In this way, a radio data system (RD that enables the service to be provided to radio listeners
S) there.

In this radio data system, 57KHz which is the third harmonic of the 19KHz stereo pilot signal outside the frequency band of the FM modulation wave is used as the subcarrier, and this subcarrier is filtered and biphase coded. A radio data signal is amplitude-modulated by a data signal indicating information related to broadcasting such as contents, and the amplitude-modulated subcarrier is frequency-modulated to a main carrier for broadcasting.

As is clear from FIG. 3 showing the baseband coding structure of the radio data signal, 104 bits correspond to 1 bit.
It is repeatedly multiplexed and transmitted as a group. One group consists of 4 blocks each having 26 bits, and each block consists of a 16-bit information word and a 10-bit check word. For example, as shown in FIG. 4, a block 1 is a program recognition (PI) code, a block 2 is an identification code such as a group type code, and a block 3 is a station frequency of a network station broadcasting the same program. (AF) data and program service name information (PS) data such as a broadcasting station name and a network name are arranged in block 4. In addition, each group is classified into 16 types of types 0 to 15 in 4 bits according to the contents, and two versions A and B are defined for each type (0 to 15). That is, the above-mentioned PI code is always arranged in each type in block 1, and blocks 2, 3, 4
Contents vary depending on group type and A, B version,
The data contents of blocks 3 and 4 which are data blocks can be known from the identification codes (codes such as group type code and version code B ₀ ) arranged in block 2 of the guide block.

Therefore, since the data is transmitted in the complicated format as described above, different types of data may be read as the desired type of data when the reception state deteriorates.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is capable of preventing the occurrence of reading different types of data.
It is an object to provide a data processing method in an S receiver.

The data processing method in the RDS receiver of the present invention receives a broadcast wave having a data signal including at least one data block and a guide block representing the type of data in the data block, and extracts the data signal from the broadcast wave. When the data signal is not read out for a predetermined time from the time when the data of the guide block is read, the data of the data block is ignored until the data of the next guide block is read.

Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an RD to which the data reading method according to the present invention is applied.
It is a block diagram which shows the outline of a basic structure of an S receiver. In this receiver, FM received by antenna 1
For the multiple broadcast wave, the desired station is selected in the front end 2,
After being converted to the intermediate frequency (IF),
It is supplied to the FM detector 4. The front end 2 adopts, for example, a PLL synthesizer method using a PLL circuit including a programmable frequency divider, and performs a channel selection operation by controlling the frequency division ratio of the programmable frequency divider by a controller 14 described later. Has become. The detection output of the FM detector 4 is supplied to an MPX (multiplex) demodulation circuit 5 and, in the case of stereo broadcasting, separated into L (left) and R (right) channel audio signals.

Further, the detection output of the FM detector 4 passes through the filter 6, so that the 57 KHz subcarrier amplitude-modulated by the biphase-coded data signal, that is, the radio data signal is extracted and demodulated by the PLL circuit 7. . This demodulated output is the digital (D) PLL circuit 8 and the decoder 9.
Is supplied to. The D-PLL circuit 8 generates a data demodulation clock based on the demodulation output of the PLL circuit 7. The generated clock is supplied to the gate circuit 10. The lock detection circuit 11 detects that the D-PLL circuit 8 is locked, generates a lock detection signal, supplies the lock detection signal to the gate circuit 10, and controls the circuit 10 to be in an open state. In the decoder 9, the bi-phase coded data signal which is the demodulated output of the PLL circuit 7 is decoded in synchronization with the clock generated in the D-PLL circuit 8.

As shown in FIG. 3, the output data of the decoder 9 is in units of 104 bits consisting of four blocks each having a 26-bit configuration, and is sequentially supplied to the group and block synchronization & error detection circuit 12. The data output from the decoder 9 is delayed one block time from the time of reception for the block synchronization, error detection and correction processing. In group, block synchronization & error detection circuit 12, each block is assigned a 10-bit check word
Block synchronization with groups based on a 10-bit offset word and checkword based
Error detection of the 16-bit information word is performed. Then, the error-detected data is sent to the error correction circuit 13 in the next stage.
Is supplied to the controller 14 after error correction.

The controller 14 is composed of a microcomputer and takes in the code information of each block in the radio data sequentially input in units of groups, that is, the radio data information related to the program content of the broadcasting station currently being received and stores it in the memory 15. The tuning operation is performed by controlling the frequency division ratio of the programmable frequency divider (not shown) of the PLL circuit forming a part of the front end 2 based on the tuning instruction from the operation unit 16. The selected reception frequency is written in the memory 15. Further, the controller 14 is also supplied with the detection output of the level detection circuit 20 that detects that the signal strength, that is, the electric field strength has dropped to a set level or less based on the IF signal level. When this detection output is supplied, it is assumed that the reception state of the broadcasting station currently being received has deteriorated, and the above-mentioned programmable to select another network station based on the AF data of the network station stored in advance in the memory 15. It also performs the operation of controlling the frequency division ratio of the frequency divider.

Data such as AF data is written in the memory 15.
It consists of RAM and ROM in which programs and data are written in advance.

Next, the operation of the processor of the controller 14 showing the procedure of the data processing method of the present invention will be described with reference to the flow chart shown in FIG.

The processor first inputs the data supplied from the error correction circuit 13 (step 51) and determines whether or not the data is the data of the block 2 (step 51).
Block identification is determined from the offset word. If it is the data of the block 2, a timer (not shown) for measuring a predetermined time is reset to a reference value to start the measurement (step 53), the input data is read, and the data processing is performed in accordance therewith (step 54). ). The predetermined time is set to be longer than the transmission time of 26 bits (for example, 21.9 ms) and shorter than the transmission time of 52 bits (for example, 43.8 ms). If the input data is not the data of block 2, it is determined whether or not it is the data of block 3 (step 5
Five). If the input data is not the data of block 3, it is determined whether or not it is the data of block 4 (step
56). When the input data is the data of block 3 or 4, it is determined whether the measured value of the timer has reached a predetermined time, that is, whether the timer has expired (step 57).
If the timer has not expired, the data in blocks 3 and 4 can be read and the process proceeds to steps 53 and 54. On the other hand, if the timer has expired, the data of blocks 3 and 4 could not be obtained for a predetermined time or longer after the data of block 2 was obtained, so that the data of blocks 3 and 4 cannot be processed correctly and the steps 53 and 54 are executed. Stop execution.

When the input data is not the data of the block 4 as well, it is determined whether or not it is the data of the block 1 (step 5
8). In the case of block 1 data, the PI code is read and written in a predetermined position in the memory 15 (step 5
9).

By repeating this operation, when the data of the block 3 or 4 is input before the predetermined time elapses from the time when the data of the block 2 is detected, the data is read and data processing is performed. However, if the data of block 3 or 4 is not input within a predetermined time from the time when the data of block 2 is detected, the block 3 or 4 is input until the data of block 2 is detected next.
Even if the data of 4 and 4 are input, they are ignored and the data processing is not performed.

As described above, in the data processing method in the RDS receiver of the present invention, when the data signal is not extracted for a predetermined time from the time when the data of the guide block is read, the data of the next guide block is read. Up to ignore the data in the data block. Therefore, it is possible to prevent different types of data from being read as desired types of data. Further, it is possible to prevent reading of data out of synchronization.

[Brief description of drawings]

FIG. 1 is a block diagram showing the outline of the basic configuration of an RDS receiver to which the data processing method of the present invention is applied, and FIG.
FIG. 4 is a flow chart showing the operation of the processor in the controller 14 in the receiver of the figure, FIG. 3 is a diagram showing the baseband coating structure of radio data, and FIG. 4 is a diagram showing the format of one group of radio data. . Explanation of symbols of main parts 2 ... Front end, 4 ... FM detector 5 ... Multiplex demodulation circuit 8 ... Digital PLL circuit 9 ... Decoder, 14 ... Controller 20 ... Level detection circuit

Claims (1)

(57) [Claims] 1. An RDS for receiving a broadcast wave having a data signal including at least one data block and a guide block representing the type of data in the data block, extracting the data signal from the broadcast wave, and reading the data.
A data processing method in a receiver, wherein when the data signal is not extracted for a predetermined time from the time when the data of the guide block is read, the data of the data block is ignored until the data of the next guide block is read. A data processing method characterized by.