JP2504512B2 - DMA controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a DMA controller that controls direct data transfer, and separates direct data transfer for the purpose of early notification of a cause of system failure to a central processing unit to prevent secondary failure. Have multiple channels to do
In the DMA controller, when the plurality of channels finish data transfer at the same time, the channel that has abnormally ended due to a system failure is given priority over the channel that has normally completed data transfer, and then the predetermined priority order of the plurality of channels. An interrupt channel determination circuit for selecting and determining a single channel for performing an interrupt in accordance with the above, and a vector storing an interrupt vector for each of the normal interrupt corresponding to the normal end and the abnormal interrupt corresponding to the abnormal end for each of the plurality of channels. A register, a channel determined by the interrupt channel determination circuit, and a read control circuit for reading an interrupt vector from the vector register according to normal termination or abnormal termination thereof, and central processing of the interrupt vector read from the vector register It is configured to supply to the device.

[Industrial applications]

The present invention relates to a DMA (Direct Memory Access) controller, and more particularly to a DMA controller that controls direct data transfer.

Conventionally, in order to reduce the data transfer time between the memory and the input / output (I / O) interface in a computer system, direct control is not performed via the central processing unit (CPU) as a peripheral device by the control of the DMA controller. DMA transfer is in progress to transfer data.

Some such DMA controllers have a plurality of channels, and each channel carries out separate data transfer. In this case, in general, each channel notifies the CPU of the end of data transfer by an interrupt when the data transfer is completed. This causes the CPU to execute an interrupt acknowledge cycle and
Executes the processing routine for the end of data transfer according to the interrupt vector returned from the MA controller.

Therefore, if there are interrupt requests on multiple channels, select one and set the interrupt vector for that interrupt request.
Need to supply to CPU.

[Conventional technology]

A conventional DMA controller assigns priorities to a plurality of channels in advance. If there are interrupt requests on multiple channels, select the channel with the highest priority and set the interrupt vector for this channel to the CPU.
Is being supplied to.

[Problems to be Solved by the Invention]

Here, if a low priority channel ends data transfer due to an exception factor such as a bus error, and at the same time as a high priority channel ends data transfer normally, the conventional DMA controller will use the priority of the normally completed channel according to the priority. The high channel interrupt vector is being supplied to the CPU.

Therefore, the factors related to system failure such as bus error
There was a problem that notification to the CPU would be delayed and a secondary failure might occur.

The present invention has been made in view of the above points, and can notify a CPU of a factor of a system failure early to prevent a secondary failure.
The purpose is to provide an MA controller.

[Means for solving the problem]

The DMA controller of the present invention has multiple channels for direct direct data transfer.
In the DMA controller, when multiple channels finish data transfer at the same time,
An interrupt channel determination circuit (111) that prioritizes a channel that has abnormally ended due to a system failure over a channel that has normally completed data transfer and then selects and determines a single channel for interrupting according to a predetermined priority order of a plurality of channels (111 ), And a vector register (115) storing the interrupt vector of each of the normal interrupt corresponding to the normal end and the abnormal interrupt corresponding to the abnormal end for each of a plurality of channels, and the interrupt channel determination circuit (111). A read control circuit (1 that reads an interrupt vector from a vector register (115) according to a channel and its normal termination or abnormal termination.
12) and have.

[Action]

In the present invention, the interrupt channel determination circuit (11
In 1), the channel that ended abnormally is given priority over the channel that ends normally, then the interrupt channel is determined according to the priority order of multiple channels, and the read control circuit (11
In 2), read the interrupt vector from the vector register (115) and supply it to the CPU.

Therefore, the abnormal interrupt vector is preferentially supplied to the CPU, and the cause of the system failure is preferentially and early notified to the CPU.

〔Example〕

FIG. 2 shows a system configuration diagram of an embodiment of a 2-bus system to which the DMA controller of the present invention is applied.

In the figure, a bus 30 is an address bus 30a, a data bus 30b,
It consists of a controller bus 30c, and the bus 30 has a C
The PU 31, the I / O interface 32, and the memory 33 are connected to each other. Similarly, the bus 40 is composed of an address bus 40a, a data bus 40b, and a controller bus 40c.
A CPU 41, an I / O interface 42, and a memory 43 are connected to the 40.

DMA controller 50 is a direct controller bus 30c, 40c
And address buses 30a and 40a via bidirectional buffers 51a and 51b, respectively, and data buses 30b and 40b via bidirectional buffers 52a and 52b, respectively.

The buffers 52a and 52b have a control signal DBEN for switching the buffer on / off from the DMA controller 50 to the terminal EN.
1, DBEN2 are respectively supplied, and control signals DIN1, DIN2 for switching the signal direction are supplied to the terminal T / R. Thereby, between the data bus 30b and the data input / output terminal of the DMA controller 50, or between the data bus 40b and the DMA controller.
It is possible to connect between 50 input / output terminals or between the data buses 30b and 40b.

Each of the buffers 51a and 51b has exactly the same configuration as the above-mentioned buffers 52a and 52b, and the terminal EN is supplied with control signals ABEN1 and ABEN2 for switching on / off from the DMA controller 50 and the signal direction is switched to the terminal T / R. Control signals AIN1 and AIN2 are supplied.

FIG. 1 shows a block diagram of an embodiment of the DMA controller 50.

In the figure, the transfer request control unit 70 includes an I / O interface 32,
42, transfer request signals REQO to REQ3 for four channels coming to the terminal 71 via the control buses 30c and 40c are supplied from the respective terminals. The transfer request control unit 70 selects a single transfer request signal according to the priority (priority) set in advance and set in the priority register 70a even if there are a plurality of transfer requests at the same time, and the central processing unit 72 and the operation determining unit 73 are selected. Report to. The operation determining unit 73 responds to this report. The contents of the priority register 70a are also supplied to the interrupt control unit 92 described later.

The slave control unit 74 is supplied with the chip select signals CS1 and CS2 and the interrupt request response signals IACK1 and IACK2 coming into the terminals 75 and 76 through the control buses 30c and 40c from the CPUs 31 and 41, respectively. The chip select signal is a signal for the CPU 31 and 41 to access the registers in the DMA controller 50, and the interrupt request response signal is the CPU 3 for the DMA controller 50.
This is a signal to which each of the CPUs 31 and 41 responds when an interrupt request is made to each of them. The slave controller 74 selects a single signal according to a predetermined priority and reports it to the operation determiner 73 even if these signals are present at the same time, and also generates a vector request signal when the interrupt request response signal is supplied. And supplies it to the interrupt control unit 92.

The operation determination unit 73 responds to this report and also transmits the report from the slave control unit 74 to the central processing unit 72.

The central processing unit 72 manages the operation state of the entire DMA controller 50 and the data transfer operation performed by each of the four channels, and this operation state and operation request are reported to the operation determining unit 73. A register 77 built in the central processing unit 72 stores a transfer source address, a destination address, the number of bytes of transfer data, and the like.

When the central processing unit 72 requests the bus right, the operation determining unit 73 gives an instruction to the bus right control unit 80. As a result, the bus control unit 80 sends the bus right request signal HREQ1,
Supply HREQ2. On the other hand, the bus right request response signals HACK1 and HACK2 output by the CPUs 31 and 41 respectively come in from the terminal 82, and the bus right control unit 80 reports the arrival of the signals HACK1 and HACK2 to the operation determining unit 73. This report is transmitted to the central processing unit 72.

Further, when the operation determining unit 73 is supplied with the bus error signals BERR1 and BERR2 from the controller buses 30c and 40c via the terminal 78, the operation determining unit 73 requests the central processing unit 72 to close the channel that is performing the data transfer. .

At the time of normal termination when the byte count, which is the number of remaining bytes of the transfer data of each channel, becomes zero, the central processing unit 72
Or, at the abnormal end when the close request is supplied due to the arrival of the bus error signals BERR1 and 2, the data transfer of the corresponding channel is ended and the interrupt request signal is generated and supplied to the interrupt control unit 92. An interrupt status indicating the transfer end status is sent to the internal data bus. Terminal control section
The terminal 84 is supplied with data complete signals DC1 and DC2 indicating the completion of writing / reading of data coming from the control buses 30c and 40c, respectively, to the terminal 84, and reports this to the operation deciding unit 73 and the operation deciding unit 73. The data complete signal DC is output from the terminal 84 in accordance with the instruction. Similarly, read / write signals R / W1 and R / W2 supplied from terminal 85
Each of them is reported to the operation determining unit 73, and the signal address strobe signals AS1 and AS2, the data strobe signals DS1 and DS2, and the read / write signal R / W1 are instructed by the operation determining unit 73.
Output each R / W2 from pin 85. Further, in accordance with an instruction from the operation determining unit 73, control signals AIN1, AIN2, ABEN1, ABEN2, DIN1, DIN2, DBEN1, DBE are supplied from the terminal 86 to the buffers 51a to 52b, respectively.
N2 is supplied and the data transfer acknowledge signals ACK0 to ACK3 are output from the terminal 94.

The input / output control unit 87 supplies the address coming from the buffers 51a and 51b to the terminal 88 to the register 77 and the communication register 91 of the central processing unit 72 via the internal address bus according to the instruction of the operation determining unit 73, and also performs the central processing. Part 72
From the terminal 88 to the buffers 51a and 51b, respectively. Further, the data coming from the buffers 52a and 52b to the terminal 89 is supplied to the register 77 and the communication register 91 via the internal data bus, and the data from the register 77 or the communication register 91 is supplied from the terminal 89 to the buffers 52a and 52b. To do. Further, the data holding register 90 built in the input / output control unit 87 stores transfer data at the time of dual transfer.

The communication register 91 stores communication messages between the CPUs 31 and 41.

 The interrupt controller 92 has the configuration shown in FIG.

In FIG. 3, the end status register 100 is divided corresponding to four channels (CHO to CH3), and when an interrupt request signal for each channel is supplied from the central processing unit 72 via the terminal 101, an interrupt is generated. The end status supplied from the central processing unit 72 via the internal data bus 102 is stored in the area of the channel designated by the request signal.

Further, when a predetermined address is supplied from the CPU 31 or 41 to the decoder 103 via the internal address bus 104, the end status register 100 is cleared in a channel unit by an output signal of the decoder 103.

The interrupt max register 105 is divided corresponding to the channels (CHO to CH3), and when the output signal of the decoder 106 for decoding the address is instructed, the value of the interrupt mask for each channel supplied from the CPU 31 or 41 is set. Store.

The end status and interrupt mask output by the end status register 100 and the interrupt mask register 105 are the interrupt mask and interrupt judgment circuit 11 for each channel.
It is supplied to 0. Here, the interrupt status is judged by comparing the end status and interrupt mask for each channel, and if the interrupt is enabled, the abnormal status due to the bus error etc. from the end status indicates the normal end due to the end of data transfer. Is determined and the determination result is supplied to the interrupt channel determination circuit 111 for each channel.

The priority of each channel is supplied to the interrupt channel determination circuit 111 from the priority register 70a via the terminal 109. First, if there is an abnormally terminated channel, the channel with the highest priority is selected, and there is no abnormal termination and the operation is normal. If there is an ending channel, the channel with the highest priority is selected from the normally ending channels. If the priority of each channel is, for example, highest in channel CHO and smaller in the order of channel CH1, channel CH2, channel CH3, the abnormal interrupt in channel CHO is given the highest priority, and the abnormal interrupt in channel CH1 and channel C
H2 error interrupt, channel CH3 error interrupt, channel C
H0 normal interrupt, channel CH1 normal interrupt, channel C
The H2 normal interrupt and the channel CH3 normal interrupt have priority.

Then, the read control circuit 112 outputs a signal indicating the number of the selected channel and whether the channel ends normally or abnormally.
To the CPU 31, whose channel that generates an interrupt from the terminal 113 (terminal 93 in FIG. 3) is being controlled.
The interrupt request signals IRQ1 and IRQ2 are output to one of 41.

The read control circuit 112 is connected to the slave control unit 74 via the terminal 114.
When the vector request signal is supplied from the vector register 115, the signal from the interrupt channel determination circuit 111 is decoded to
Address is generated and supplied to the vector register 115 and the data selector 116.

The vector register 115 stores an interrupt vector of a normal interrupt and an abnormal interrupt for each of four channels (CHO to CH3). These interrupt vectors are generated when the decoder 117 decodes a predetermined address from the CPU 31, 41. ,Four
It is supplied and stored from 1 via the internal data bus 102.
If the internal data bus 102 has, for example, 16 bits, each interrupt vector has 8 bits, and a data selector 116 is provided to send the interrupt vector from the vector register 115 to, for example, the lower 8 bits of the internal data bus.

The vector register 115 reads an interrupt vector of a normal interrupt or an abnormal interrupt from the address output from the read control circuit 112 and sends it to the internal data bus 102. This interrupt vector is supplied to the CPU 31 or 41 through the input / output control unit 87.

Here, when the interrupt request signal IRQ1 is output from the terminal 113, the CPU 31 asserts the interrupt request response signal IACK1 at L (L level) as shown in FIG. 4 (I), and executes the interrupt acknowledge cycle.

The clock C shown in FIG.
LK is supplied. In the interrupt acknowledge cycle,
When IACK1 of the L level interrupt request response signal shown in (I) of the figure is supplied from the CPU 31, in cycle Ts ₁ , the same figure (B),
The control signals ABEN1 and AIN1 shown in (C) are set to L level.

Further, an H level read / write signal shown in FIG.
The control signal DBEN1 shown in (D) of the figure is set to the L level in the cycle Ts ₄ by R / W1 (the signal DIN1 is at the H level as shown in (E) of the figure). This makes the vector register
The interrupt vector shown in FIG. 9 (G) read from 115 is output and sent to the CPU 31. Further, the data complete signal DC1 shown in FIG.

In this way, by supplying the abnormal interrupt vector to the CPU31, 41 with priority over the normal interrupt vector, the CPU31, 41 can know the cause of the system failure preferentially and early,
Can handle system failures. This prevents secondary failures.

〔The invention's effect〕

As described above, according to the DMA controller of the present invention, the cause of the system failure can be notified to the CPU at an early stage, and thus the secondary failure can be prevented, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a DMA controller of the present invention, FIG. 2 is a configuration diagram of a system using the DMA controller of the present invention, FIG. 3 is a block diagram of an interrupt control unit, and FIG. It is a wave form diagram of an interrupt acknowledge cycle. In the figure, 30,40 is a bus, 31,41 is a CPU, 32,42 is an I / O interface, 33,43 is a memory, 50 is a DMA controller, 51a, 51b, 52
a and 52b are buffers, 70 is a transfer request control unit, 72 is a central processing unit, 73 is an operation determination unit, 74 is a slave control unit, 77 is a register, 80 is a bus right control unit, 83 is a terminal control unit, and 87 is An input / output control unit, 91 is a communication register, 92 is an interrupt control unit, 111 is an interrupt channel determination circuit, 112 is a read control circuit, and 115 is a vector register.

Claims (1)

(57) [Claims] 1. A DMA controller having a plurality of channels for performing direct data transfer separately, wherein when the plurality of channels simultaneously finish data transfer,
An interrupt channel determination circuit that prioritizes a channel that has abnormally terminated due to a system failure over a channel that has normally completed data transfer, and then selects and determines a single channel for interrupting in accordance with a predetermined priority of the plurality of channels ( 111), a vector register (115) storing an interrupt vector for each of the normal interrupt corresponding to the normal end and the abnormal interrupt corresponding to the abnormal end for each of the plurality of channels, and the interrupt channel determination circuit (111) And a read control circuit (112) for reading an interrupt vector from the vector register (115) in accordance with the normal termination or abnormal termination of the channel determined by A DMA controller characterized by being supplied to a processing device.