JP2021022901A - Transimpedance amplifier circuit - Google Patents

Abstract

To improve the signal quality.SOLUTION: In a transimpedance amplifier circuit 10C: a control circuit 51C generates control currents Iagc1cnt and Iagc2cnt based on a control current Icnt; a drain of a field effect transistor 57 of a variable resistance circuit 53 is electrically connected to an input terminal 10a; a reference voltage signal Vref is supplied to a source of the field effect transistor 57; the reference voltage signal Vref is supplied to a drain of a field effect transistor 82 of a variable resistance circuit 80; a source of the field effect transistor 82 is electrically connected to the input terminal 10a; the variable resistance circuit 53 causes an AC bypass current Iagc1 to flow from the drain to the source of the field effect transistor 57 according to the control current Iagc1cnt; and the variable resistance circuit 80 causes an AC bypass current Iagc2 to flow from the source to the drain of the field effect transistor 82 according to the control current Iagc2cnt.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a transimpedance amplifier circuit.

Conventionally, there is a transimpedance amplifier circuit that converts an optical signal for optical communication into an electric signal (see, for example, Patent Document 1 and Patent Document 2). Patent Document 1 describes a TIA unit including a transistor for drawing a direct current, a transistor for pulling out an alternating current, an inverting amplifier circuit, and a feedback resistance element provided on the cathode and the anode of the photodiode, respectively. A transimpedance amplifier circuit comprising, is described. In this transimpedance amplifier circuit, the source potential of the transistor for drawing out the AC current is given by the buffer so as to match the input potential of the TIA section, the gate of the transistor is connected to the control circuit, and the drain of the transistor is It is connected to the input terminal of the TIA section. The gate voltage is adjusted so that the amplitude of the differential output signal is constant, and the amplitude is controlled so that the input current from the photodiode is not distorted at the output of the TIA unit.

U.S. Pat. No. 9,774,305 Japanese Unexamined Patent Publication No. 2012-10107

In the transimpedance amplifier circuit described in Patent Document 1, the source of the transistor for drawing out the alternating current is grounded by a buffer, and the source potential is constant from direct current to high frequency. Further, since a signal in which the error between the signal amplitude and the target potential is integrated is supplied from the control circuit to the gate of the transistor, a constant voltage is supplied at high frequencies. On the other hand, the input impedance of the TIA unit is usually about 10 to 100Ω, and the potential fluctuation may occur with respect to the input current from the photodiode, so that the drain potential of the transistor may fluctuate slightly. The transistor for drawing out the alternating current operates as a resistance element because the source voltage and the drain voltage are almost the same. However, since the drain potential fluctuates slightly, the value of the on-resistance between the drain and the source of the transistor (the resistance value of the resistance element) can change. As a result, the resistance value changes depending on whether the drain potential is high or low, which may cause a difference in the amount of alternating current extracted. This difference becomes distortion and may affect the signal quality.

The present disclosure describes a transimpedance amplifier circuit capable of improving signal quality.

The transimpedance amplifier circuit according to one aspect of the present disclosure is a circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element. This transimpedance amplification circuit generates an input terminal that receives an input current signal, a single-ended amplification circuit that converts a current signal into a voltage signal, and a differential voltage signal according to the difference between the voltage signal and the reference voltage signal. A differential amplification circuit, a control current generation circuit that generates a control current based on the integrated value of the difference, and a bypass circuit that generates a DC bypass current, a first AC bypass current, and a second AC bypass current according to the control current. And. The current signal is generated by extracting the DC bypass current, the first AC bypass current, and the second AC bypass current from the input current signal. The bypass circuit includes a control circuit to which a control current is input, a first variable resistance circuit that generates a first AC bypass current according to the control current, and a second variable that generates a second AC bypass current according to the control current. It is equipped with a resistance circuit. The control circuit generates an offset current having a predetermined offset current value, and amplifies the difference between the generated current and the offset current at the first amplification factor to amplify the first control current and the second. Generates control current. The first variable resistance circuit has a first electric field having a first drain that receives a first control current, a first gate that is electrically connected to the first drain, and a first source to which a reference voltage signal is supplied. The effect transistor, the second drain electrically connected to the input terminal, the second gate electrically connected to the first drain and the first gate, and the second source to which the reference voltage signal is supplied are provided. The second field effect transistor is provided. The first variable resistance circuit causes the first AC bypass current to flow from the second drain to the second source according to the first control current. The second variable resistance circuit has a third drain that receives a second control current, a third gate that is electrically connected to the third drain, and a third source that is electrically connected to the input terminal. The three field effect transistors, the fourth drain to which the reference voltage signal is supplied, the fourth gate electrically connected to the third drain and the third gate, and the fourth source electrically connected to the third source. A fourth field-effect transistor having The second variable resistance circuit causes the second AC bypass current to flow from the fourth source to the fourth drain according to the second control current.

According to the present disclosure, signal quality can be improved.

FIG. 1 is a diagram schematically showing a configuration of an optical receiver including a transimpedance amplifier circuit according to an embodiment. FIG. 2 is a diagram showing a circuit configuration example of the integrating circuit shown in FIG. FIG. 3 is a diagram showing the relationship between the control current supplied to the control circuit shown in FIG. 1 and the current generated by the control circuit. FIG. 4 is a diagram showing a circuit configuration example of the control circuit shown in FIG. FIG. 5A is a diagram showing changes in the total harmonic distortion with respect to the input light average power in the transimpedance amplifier circuit shown in FIG. FIG. 5B is a diagram showing a change in the output amplitude of the TIA unit with respect to the average input light power in the transimpedance amplifier circuit shown in FIG. FIG. 6A is a diagram showing changes in the total harmonic distortion with respect to the input light average power in the transimpedance amplifier circuit of the comparative example. FIG. 6B is a diagram showing a change in the output amplitude of the TIA unit with respect to the average input light power in the transimpedance amplifier circuit of the comparative example.

[Explanation of Embodiments of the present disclosure]
First, the contents of the embodiments of the present disclosure will be listed and described.

The transimpedance amplifier circuit according to one aspect of the present disclosure is a circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element. This transimpedance amplification circuit generates an input terminal that receives an input current signal, a single-ended amplification circuit that converts a current signal into a voltage signal, and a differential voltage signal according to the difference between the voltage signal and the reference voltage signal. A differential amplification circuit, a control current generation circuit that generates a control current based on the integrated value of the difference, and a bypass circuit that generates a DC bypass current, a first AC bypass current, and a second AC bypass current according to the control current. And. The current signal is generated by extracting the DC bypass current, the first AC bypass current, and the second AC bypass current from the input current signal. The bypass circuit includes a control circuit to which a control current is input, a first variable resistance circuit that generates a first AC bypass current according to the control current, and a second variable that generates a second AC bypass current according to the control current. It is equipped with a resistance circuit. The control circuit generates an offset current having a predetermined offset current value, and amplifies the difference between the generated current and the offset current at the first amplification factor to amplify the first control current and the second. Generates control current. The first variable resistance circuit has a first electric field having a first drain that receives a first control current, a first gate that is electrically connected to the first drain, and a first source to which a reference voltage signal is supplied. The effect transistor, the second drain electrically connected to the input terminal, the second gate electrically connected to the first drain and the first gate, and the second source to which the reference voltage signal is supplied are provided. The second field effect transistor is provided. The first variable resistance circuit causes the first AC bypass current to flow from the second drain to the second source according to the first control current. The second variable resistance circuit has a third drain that receives a second control current, a third gate that is electrically connected to the third drain, and a third source that is electrically connected to the input terminal. The three field effect transistors, the fourth drain to which the reference voltage signal is supplied, the fourth gate electrically connected to the third drain and the third gate, and the fourth source electrically connected to the third source. A fourth field-effect transistor having The second variable resistance circuit causes the second AC bypass current to flow from the fourth source to the fourth drain according to the second control current.

In this transimpedance amplifier circuit, since the differential resistances of the second field-effect transistor of the first variable resistance circuit and the fourth field-effect transistor of the second variable resistance circuit each include a component of the voltage between the drain and the source, the drain. It can change depending on the voltage between sources. In the second field effect transistor, a reference voltage signal is supplied to the second source and the second drain is electrically connected to the input terminal, whereas in the fourth field effect transistor, the reference voltage signal is supplied to the fourth drain. Is supplied and the fourth source is electrically connected to the input terminal. Therefore, the polarity of the voltage between the second drain and the second source and the polarity of the voltage between the fourth drain and the fourth source are opposite to each other. Therefore, in the combined resistance of the first variable resistance circuit and the second variable resistance circuit seen from the input terminal, the voltage component between the second drain and the second source and the voltage component between the fourth drain and the fourth source The components of the voltage cancel each other out. As a result, the combined resistance of the first variable resistance circuit and the second variable resistance circuit may fluctuate depending on the voltage between the second drain and the second source and the voltage between the fourth drain and the fourth source. It can be suppressed. As a result, the occurrence of distortion is suppressed, so that the signal quality can be improved.

The bypass circuit may further include a feedback current source that produces a DC bypass current depending on the control current. The control circuit may control the feedback current source so that the DC bypass current increases as the control current increases. In this case, since the control for removing the DC component and the gain control for the transimpedance amplifier circuit can be realized by a single control loop, it is possible to suppress an increase in the circuit scale.

The control circuit may generate a third control current by amplifying the control current at the second amplification factor. The feedback current source is a fifth electric field having a fifth drain that receives a third control current, a fifth gate that is electrically connected to the fifth drain, and a fifth source that is electrically connected to the ground potential. Effect A transistor, a sixth drain electrically connected to the input terminal, a sixth gate electrically connected to the fifth drain and the fifth gate, and a sixth source electrically connected to the fifth source. A sixth electric current effect transistor having the above may be provided. The feedback current source may cause a DC bypass current to flow from the sixth drain to the sixth source according to the third control current. In this case, since the fifth field effect transistor is connected by a diode, when the fifth drain of the fifth field effect transistor receives the third control current, the gate-source voltage between the fifth gate and the fifth source. Is generated. Since the fifth gate and the sixth gate are electrically connected to each other, and the fifth source and the sixth source are electrically connected to each other, the gate-source voltage of the sixth field effect transistor is the first. 5 This is equal to the gate-source voltage of the field effect transistor. In the sixth field effect transistor, since the sixth source is electrically connected to the fifth source, that is, the ground potential, and the sixth drain is electrically connected to the input terminal, the sixth source and the sixth drain are connected. The potential difference becomes large. As a result, the sixth field effect transistor operates in the saturation region. Therefore, the sixth field-effect transistor functions as a current source, and the output impedance of the sixth drain becomes large. Therefore, although the AC component of the input current signal hardly flows into the sixth field-effect transistor, the DC component of the input current signal. Can flow into the sixth field effect transistor as a DC bypass current. Then, as the control current increases, the gate-source voltage of the sixth field effect transistor increases, so that the DC component of the input current signal is extracted from the input current signal as a DC bypass current, and the DC component of the input current signal The removal is done properly.

The DC bypass current may be set to include a second control current flowing out of the second variable resistor circuit. In the second variable resistance circuit, the second control current flows from the third drain of the third field effect transistor to the third source. Since the third source is electrically connected to the input terminal, the second control current flows out to the input terminal and increases the DC component of the input current signal. On the other hand, by setting the DC bypass current to include the second control current, the DC component due to the second control current can be removed from the input current signal.

The transimpedance amplifier circuit may further include a reference voltage generation circuit that generates a reference voltage signal. The reference voltage generation circuit may include an amplifier and a feedback resistor element electrically connected between the input and output of the amplifier. In this case, the output impedance of the reference voltage generation circuit becomes low in a wide frequency range. That is, the impedance of the first variable resistance circuit and the second variable resistance circuit seen from the input terminal of the single-ended amplifier circuit becomes low in a wide frequency range. Therefore, the first AC bypass current and the second AC bypass current can be easily extracted from the input current signal.

[Details of Embodiments of the present disclosure]
A specific example of the transimpedance amplifier circuit according to the embodiment of the present disclosure will be described below with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

FIG. 1 is a diagram schematically showing a configuration of an optical receiver including a transimpedance amplifier circuit according to an embodiment. FIG. 2 is a diagram showing a circuit configuration example of the integrating circuit shown in FIG. FIG. 3 is a diagram showing the relationship between the control current supplied to the control circuit shown in FIG. 1 and the current generated by the control circuit. FIG. 4 is a diagram showing a circuit configuration example of the control circuit shown in FIG.

The optical receiver 1C shown in FIG. 1 receives an optical signal Pin transmitted from an optical transmitter (not shown). The optical receiver 1C includes a light receiving element PD and a transimpedance amplifier circuit 10C. The light receiving element PD receives the optical signal Pin and generates an optical current Ipd (input current signal) corresponding to the optical signal Pin. The photocurrent Ipd may include a modulated AC component (AC component) and a DC component (DC component) superimposed on the AC component. Examples of the light receiving element PD include a photodiode and an avalanche photodiode. One terminal of the light receiving element PD is electrically connected to a predetermined bias voltage VPD, and the other terminal of the light receiving element PD outputs a photocurrent Ipd.

The transimpedance amplifier circuit 10C receives the photocurrent Ipd generated by the light receiving element PD, and generates differential voltage signals Vout and Voutb, which are voltage signals, according to the photocurrent Ipd. The differential voltage signals Vout and Voutb are a pair of complementary signals. The transimpedance amplifier circuit 10C includes an input terminal 10a. The photocurrent Ipd is input to the input terminal 10a.

The transimpedance amplifier circuit 10C includes a TIA (TransImpedance Amplifier) unit 11 (single-ended amplifier circuit), a reference voltage generation circuit 12, a differential amplifier circuit 13, a control current generation circuit 14, and a bypass circuit 15C. Be prepared.

The TIA unit 11 is a circuit that converts the current signal Iin into the voltage signal Vtia. Specifically, the TIA unit 11 includes a voltage amplifier 11a and a feedback resistance element 11b. The input terminal and the output terminal of the voltage amplifier 11a are electrically connected via the feedback resistance element 11b. That is, the feedback resistance element 11b is electrically connected between the input and output of the voltage amplifier 11a. The current signal Iin is generated by extracting the DC bypass current Iaoc, the AC bypass current Iagc1 (first AC bypass current), and the AC bypass current Iagc2 (second AC bypass current) from the optical current Ipd. The DC bypass current Iaoc, the AC bypass current Iagc1, and the AC bypass current Iagc2 are controlled by the bypass circuit 15C, which will be described in detail later. The increase / decrease of the voltage signal Vtia is reversed with respect to the increase / decrease of the current signal Iin. The voltage amplifier 11a is, for example, an inverting amplifier circuit. The TIA unit 11 outputs the voltage signal Vtia to the differential amplifier circuit 13 and the control current generation circuit 14. The gain of the TIA unit 11 (the ratio of the magnitude of the voltage signal Vtia to the magnitude of the current signal Iin) is determined by the resistance value (transimpedance) of the feedback resistance element 11b. The input impedance of the TIA unit 11 is about 10 to 100 Ω.

The reference voltage generation circuit 12 is a circuit that generates a reference voltage signal Vref, which is a DC voltage signal. The reference voltage generation circuit 12 outputs the reference voltage signal Vref to the differential amplifier circuit 13, the control current generation circuit 14, and the bypass circuit 15C. The reference voltage signal Vref has a predetermined voltage value (fixed value). The reference voltage generation circuit 12 may be configured so that the output impedance becomes low impedance over a wide band. In the present embodiment, the reference voltage generation circuit 12 is a dummy TIA including a voltage amplifier 12a (amplifier) and a feedback resistance element 12b, similarly to the TIA unit 11. The input terminal and the output terminal of the voltage amplifier 12a are electrically connected via the feedback resistance element 12b. That is, the feedback resistance element 12b is electrically connected between the input and output of the voltage amplifier 12a. Since the reference voltage generation circuit 12 has the same circuit configuration as the TIA unit 11, the reference voltage signal Vref is generated so as to compensate (cancel) the change in the voltage signal Vtia due to the change in the power supply voltage and temperature of the voltage amplifier 11a. obtain.

The differential amplifier circuit 13 is a circuit that generates differential voltage signals Vout and Voutb according to the difference ΔVtia (error) between the voltage signal Vtia and the reference voltage signal Vref. In other words, the differential amplifier circuit 13 uses the reference voltage signal Vref to convert the single (single-phase) voltage signal Vtia into the differential voltage signals Vout and Voutb. The differential amplifier circuit 13 generates differential voltage signals Vout and Voutb by amplifying the difference ΔVtia. The differential amplifier circuit 13 outputs the differential voltage signals Vout and Voutb to a subsequent circuit (not shown).

The control current generation circuit 14 is a circuit that generates a control current Ict based on the integrated value of the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. The control current generation circuit 14 includes an integrator circuit 41 and an OTA (Operational Transconductance Amplifier) 42.

The integrator circuit 41 is a circuit that integrates the difference ΔVtia. As shown in FIG. 2, the integrating circuit 41 has input terminals 41a and 41b and output terminals 41c and 41d. The input terminal 41a is electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a), and the reference voltage signal Vref is input to the input terminal 41a. The input terminal 41b is electrically connected to the output terminal of the TIA unit 11 (voltage amplifier 11a), and the voltage signal Vtia is input to the input terminal 41b. The output terminal 41c is electrically connected to the inverting input terminal of the OTA 42, and outputs a voltage signal Vinn to the OTA 42. The output terminal 41d is electrically connected to the non-inverting input terminal of the OTA 42, and outputs a voltage signal Vinp to the OTA 42.

The integrator circuit 41 includes an operational amplifier 43, resistance elements 44 and 45, and capacitors 46 and 47. The operational amplifier 43 has a non-inverting input terminal 43a, an inverting input terminal 43b, an inverting output terminal 43c, and a non-inverting output terminal 43d. The non-inverting input terminal 43a is electrically connected to the input terminal 41a via a resistance element 44. The inverting input terminal 43b is electrically connected to the input terminal 41b via a resistance element 45. The inverting output terminal 43c is electrically connected to the output terminal 41c and is also electrically connected to the non-inverting input terminal 43a via the capacitor 46. That is, the capacitor 46 connects the inverting output terminal 43c and the non-inverting input terminal 43a with negative feedback. The non-inverting output terminal 43d is electrically connected to the output terminal 41d and is also electrically connected to the inverting input terminal 43b via a capacitor 47. That is, the capacitor 47 connects the non-inverting output terminal 43d and the inverting input terminal 43b with negative feedback.

Here, the gain of the operational amplifier 43 is infinite, the resistance value R1 of the resistance element 44 and the resistance value R2 of the resistance element 45 are equal to each other, and the capacitance value C1 of the capacitor 46 and the capacitance value C2 of the capacitor 47 are equal to each other. Assuming that, the integrator circuit 41 operates as an integrator having a time constant R1 × C1.

The OTA 42 is a circuit that converts a differential voltage signal (voltage signal Vinp and voltage signal Vinn) into a control current Ict which is a single current signal (error current). The OTA 42 has a known circuit configuration, for example, a configuration in which a current mirror circuit is added to a differential amplifier circuit. The OTA 42 has transconductance, and the input / output impedance of the OTA 42 is, for example, infinite. The control current Icnt is obtained by multiplying the input differential voltage, which is the difference between the voltage signal Vinp input to the OTA 42 and the voltage signal Vinn, by the transconductance. The difference between the voltage signal Vinp and the voltage signal Vinn changes according to the integrated value of the difference ΔVtia. The OTA 42 outputs the control current Icnt to the bypass circuit 15C.

The bypass circuit 15C is a circuit that generates a DC bypass current Iaoc, an AC bypass current Iagc1, and an AC bypass current Iagc2 according to the control current Ict. The bypass circuit 15C includes a control circuit 51C, a feedback current source 52, a variable resistance circuit 53 (first variable resistance circuit), and a variable resistance circuit 80 (second variable resistance circuit).

The control current Icnt is input to the control circuit 51C. The control circuit 51C controls the feedback current source 52 so that the DC bypass current Iaoc increases as the control current Ict increases. The control circuit 51C controls the variable resistance circuits 53 and 80 so that the AC bypass currents Igc1 and Iagc2 increase as the control current Ict increases when the control current Ict exceeds the current value of the offset current Ifs. The current value of the offset current Ifs is a predetermined current value (fixed value). Specifically, the control circuit 51C receives the control current Ict from the control current generation circuit 14 (OTA42), and according to the control current Ict, the control current Iaocct (third control current) and the control current Iagc1ct (first control current). , And the control current Igc2ct (second control current) is generated. The control circuit 51C outputs the control current Iaocct to the feedback current source 52, and controls the feedback current source 52 by the control current Iaocct. The control circuit 51C outputs the control current Iagc1ct to the variable resistance circuit 53, and controls the variable resistance circuit 53 by the control current Iagc1ct. The control circuit 51C outputs the control current Igc2ct to the variable resistance circuit 80, and controls the variable resistance circuit 80 by the control current Igc2ct.

As shown in FIG. 3, the current values of the control current Igc1ct and the control current Igc2ct are proportional to the current value of the control current Ict when the current value of the control current Ict is larger than the current value of the offset current Ifs. In other words, the current values of the control current Igc1ct and the control current Igc2ct are γ times the current value obtained by subtracting the current value of the offset current Ifs from the control current Ictt (Iagc1ct = Iagc2ct = γ × (Icnt-Ifs)). The control circuit 51C generates, for example, an offset current Ifs having a predetermined current value (offset current value), and a current generated by amplifying the control current Ict (here, the control current Ict) and the offset current Ifs. The control current Igc1ct and the control current Igc2ct are generated by amplifying the difference with the amplification factor γ.

The current value of the control current Iacct is a value obtained by adding the current value of the control current Iagc2ct to α times the current value of the control current Ictt (Iaocct = α × Ict + Iagc2ct). The control circuit 51C generates the control current Iacct by, for example, adding the control current Igc2ct to the current generated by amplifying the control current Ict with the amplification factor α. In this way, in the control current Iaocct, the amplification factor α is adjusted, and in the control currents Iagc1ct and Iagc2ct, the offset current value for determining the current for starting automatic gain control (AGC) and the control of the AGC. The amplification factor γ, which determines the sensitivity, is adjusted.

The control circuit 51C shown in FIG. 4 has a circuit configuration for realizing the control current Iaocct, the control current Iagc1ct, and the control current Iagc2ct shown in FIG. As shown in FIG. 4, the control circuit 51C has an input terminal 51a, output terminals 51b, 51c, 51e, and a power supply terminal 51d. The input terminal 51a is electrically connected to the output terminal of the control current generation circuit 14 (OTA42), and the control current Icnt is input to the input terminal 51a. The output terminal 51b is electrically connected to the input terminal 52a of the feedback current source 52, and outputs the control current Iaocct to the feedback current source 52. The output terminal 51c is electrically connected to the control terminal 53a of the variable resistance circuit 53, and outputs the control current Iagc1ct to the variable resistance circuit 53. The power supply terminal 51d is electrically connected to the power supply wiring that supplies the power supply voltage VCS, and the power supply voltage VCS is supplied to the power supply terminal 51d. The output terminal 51e is electrically connected to the control terminal 80a of the variable resistance circuit 80, and outputs the control current Iagc2ct to the variable resistance circuit 80.

The control circuit 51C includes transistors 61 to 69, 71, 72 and a current source 70. The transistors 61 to 69, 71, 72 are, for example, field effect transistors (MOSFETs) having a MOS (Metal-Oxide-Semiconductor) structure. In the example shown in FIG. 4, the transistors 61 to 63 are N-channel MOS transistors, and the transistors 64 to 69, 71, 72 are P-channel MOS transistors.

Transistors 61 to 63 form a current mirror circuit. The transistor 61 functions as an input transistor, and the transistors 62 and 63 function as output transistors. The sources of transistors 61-63 are electrically connected to the ground potential GND. The gate and drain of the transistor 61 are electrically connected to each other, and further electrically connected to the input terminal 51a. Each gate of the transistors 62 and 63 is electrically connected to the gate and drain of the transistor 61. The drain of the transistor 62 is electrically connected to the drain and the gate of the transistor 64. The drain of the transistor 63 is electrically connected to the drain and the gate of the transistor 68 via the node N1.

Since the transistors 61 and 62 and the transistors 61 and 63 each form a current mirror circuit, for example, an output current (drain current) having a magnitude proportional to the magnitude of the drain current (control current Ict) of the transistor 61 is a transistor. It is output from the drains of 62 and 63, respectively. Here, for convenience of explanation, the current mirror ratio is 1: 1: 1. Therefore, the control current Icnt input to the input terminal 51a is copied by the transistors 61 to 63, and the control current Icnt is output from the drains of the transistors 62 and 63, respectively. The control current Icnt flows toward the drains of the transistors 62 and 63.

Transistors 64 and 65 form a current mirror circuit. The transistor 64 functions as an input transistor, and the transistor 65 functions as an output transistor. The sources of the transistors 64 and 65 are electrically connected to the power supply terminal 51d. The gate and drain of the transistor 64 are electrically connected to each other, and further electrically connected to the drain of the transistor 62. The gate of transistor 65 is electrically connected to the gate and drain of transistor 64. The drain of the transistor 65 is electrically connected to the output terminal 51b via the node N2.

The control current Icnt output from the drain of the transistor 62 is input to the drain of the transistor 64, and the output current (drain current) having a magnitude proportional to the magnitude of the drain current (control current Ict) of the transistor 64 is the transistor 65. It is output from the drain of. Here, the current mirror ratio of the current mirror circuit composed of the transistors 64 and 65 is set to 1: α. That is, the drain current of the transistor 65 is a current (α × Ict) of a magnitude obtained by amplifying the control current Icnt by α times. The drain current of the transistor 65 flows from the drain of the transistor 65 toward the node N2.

Transistors 66 and 67 form a current mirror circuit. The transistor 66 functions as an input transistor, and the transistor 67 functions as an output transistor. The sources of the transistors 66 and 67 are electrically connected to the power supply terminal 51d. The gate and drain of the transistor 66 are electrically connected to each other, and further electrically connected to the current source 70. The gate of transistor 67 is electrically connected to the gate and drain of transistor 66. The drain of the transistor 67 is electrically connected to the drain and the gate of the transistor 68 via the node N1.

The reference current Iref supplied from the current source 70 is input to the drain of the transistor 66, and the output current (drain current) having a magnitude proportional to the magnitude of the drain current (reference current Iref) of the transistor 66 is the transistor 67. It is output from the drain as offset current Ifs. Here, the current mirror ratio of the current mirror circuit composed of the transistors 66 and 67 is set to 1: m. That is, the offset current Ifs is a current (m × Iref) of a magnitude obtained by amplifying the reference current Iref m times. The offset current Ifs flows from the drain of the transistor 67 toward the node N1. The value of m is arbitrarily selected according to the optical power at which the AGC is desired to operate. Since the current value of the reference current Iref is a fixed value, the current value (offset current value) of the offset current Ifs is also a fixed value.

The transistors 68 and 69, the transistors 68 and 71, and the transistors 68 and 72 form a current mirror circuit, respectively. The transistor 68 functions as an input transistor, and the transistors 69, 71, 72 function as an output transistor. The sources of the transistors 68, 69, 71, 72 are electrically connected to the power supply terminal 51d. The gate and drain of the transistor 68 are electrically connected to each other, and are further electrically connected to the drain of the transistor 63 and the drain of the transistor 67 via the node N1. The gates of the transistors 69, 71, and 72 are electrically connected to the gate and drain of the transistor 68. The drain of the transistor 69 is electrically connected to the output terminal 51c. The drain of the transistor 71 is electrically connected to the output terminal 51e. The drain of the transistor 72 is electrically connected to the output terminal 51b via the node N2.

The control current Icnt output from the drain of the transistor 63 is combined with the offset current Ifs output from the drain of the transistor 67 at the node N1. Specifically, the offset current Ifs is subtracted (subtracted) from the control current Icnt. At this time, only when the current value of the control current Icnt is larger than the current value of the offset current Ifs, the difference current (Icnt-Iofs) flows to the drain of the transistor 68, and the magnitude of the drain current (difference current) of the transistor 68 An output current (drain current) having a magnitude proportional to the above is output as a control current Igc1ct from the drain of the transistor 69, and is output as a control current Igc2ct from the drains of the transistors 71 and 72, respectively.

Here, the current mirror ratio of the current mirror circuit composed of the transistors 68, 69, 71, and 72 is set to 1: γ: γ: γ. That is, the control currents Igc1ct and Igc2ct are currents (γ × (Icnt-Iofs)) having a magnitude obtained by amplifying the difference current (Ict-Ioffs) by γ times. The control current Igc1ct generated by the current mirror circuits of the transistors 68 and 69 flows from the drain of the transistors 69 toward the output terminal 51c. The control current Igc2ct generated by the current mirror circuit of the transistors 68 and 71 flows from the drain of the transistor 71 toward the output terminal 51e. The control current Igc2ct generated by the current mirror circuits of the transistors 68 and 72 flows from the drain of the transistor 72 toward the node N2, and is combined with the drain current output from the drain of the transistor 65 at the node N2. By synthesizing the drain current of the transistor 65 and the control current Iagc2ct, the control current Iaocct is generated, and the control current Iaocct flows from the node N2 toward the output terminal 51b.

On the other hand, when the current value of the control current Icnt is smaller than the current value of the offset current Ifs, no current flows through the transistor 68. Therefore, the potential of the node N1 is set to the power supply voltage VCC side by the diode-connected transistor 68. It is pulled up with high resistance. Further, since the voltage between the drain and the source of the transistor 67 becomes small, the transistors 66 and 67 do not operate as a current mirror circuit. At this time, since the transistor 67 operates in the triode region (linear region), the potential of the node N1 is pulled up to the power supply voltage VCS side with a low resistance. The triode region is a state in which the result of subtracting the threshold voltage from the gate-source voltage of the transistor is larger than the drain-source voltage.

Since no gate-source voltage is applied to the transistor 68, the resistance value of the transistor 67 to which the gate-source voltage is applied is smaller than the resistance value of the transistor 68. As described above, when the transistor 67 operates in the triode region, the transistor 67 cannot supply the offset current Ifs, and at the same time, all the control current Icnt from the transistor 63 flows through the transistor 67. As a result, the control current Igc1ct is output from the output terminal 51c and the control current Igc2ct is output from the output terminal only when the current value of the control current Ict is larger than the current value of the offset current Ifs (in the region of Ict-Ioffs> 0). It is output from the drain of the 51e and the transistor 72.

In this way, the control current Igc1ct and the control current Igc2ct have the same amount of current and flow in the same direction. That is, the control currents Iagc1ct and Iagc2ct flow so as to be discharged from the power supply voltage VCS toward the ground potential GND.

The input / output characteristics of FIG. 3 can be obtained by the control circuit 51C shown in FIG. 4, but the above-mentioned current mirror ratio can be changed as appropriate. Further, as the circuit configuration of the control circuit 51C, another circuit configuration capable of obtaining the input / output characteristics of FIG. 3 may be adopted.

The feedback current source 52 constitutes an Auto-Offset Control (AOC) circuit. The feedback current source 52 is a circuit that generates a DC bypass current Iaoc according to the control current Ict. More specifically, the feedback current source 52 generates a DC bypass current Iaoc according to the control current Iaocct. The feedback current source 52 has an input terminal 52a, an output terminal 52b, and a ground terminal 52c. The input terminal 52a is electrically connected to the output terminal 51b of the control circuit 51C, and receives the control current Iaocct from the control circuit 51C. The output terminal 52b is electrically connected to the input terminal 10a and outputs a DC bypass current Iaoc. The ground terminal 52c is electrically connected to the ground potential GND. The feedback current source 52 includes a field effect transistor 54 (fifth field effect transistor) and a field effect transistor 55 (sixth field effect transistor).

Each of the field effect transistors 54 and 55 is, for example, an N-channel MOS transistor. The size of the field effect transistor 54 and the size of the field effect transistor 55 may be the same or different from each other. The sources of the field effect transistors 54 and 55 are electrically connected to each other and are electrically connected to the ground potential GND via the ground terminal 52c. The drain of the field effect transistor 54 is electrically connected to the output terminal 51b of the control circuit 51C via the input terminal 52a, and receives the control current Iaocct from the control circuit 51C. The gate of the field effect transistor 54 is electrically connected to the drain of the field effect transistor 54. The drain of the field effect transistor 55 is electrically connected to the input terminal 10a via the output terminal 52b. The gate of the field effect transistor 55 is electrically connected to the drain and gate of the field effect transistor 54.

In the feedback current source 52 configured in this way, the control current Iaocct that flows from the input terminal 52a flows through the field effect transistor 54 that is connected to the diode, so that the gate between the gate and the source of the field effect transistor 54 is gated. -Generate a source-to-source voltage Vgs1. Since the gate of the field effect transistor 54 and the gate of the field effect transistor 55 are electrically connected to each other, and the source of the field effect transistor 54 and the source of the field effect transistor 55 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 55 becomes equal to the gate-source voltage Vgs1. Since the source of the field effect transistor 55 is electrically connected to the ground potential GND, the source potential is approximately 0 V. On the other hand, the input potential of the TIA unit 11 (for example, about 0.5 to 2 V) is applied to the drain of the field effect transistor 55. Therefore, the field effect transistor 55 operates in the saturation region. The saturation region is a state in which the result of subtracting the threshold voltage from the gate-source voltage of the transistor is smaller than the drain-source voltage. In the saturation region, even if the drain voltage of the field effect transistor 55 increases, the degree to which the drain current increases is smaller than that in the linear region. Therefore, the impedance (output impedance) of the output terminal 51b is a relatively large value.

That is, the field effect transistors 54 and 55 form a current mirror circuit, and output a DC bypass current Iaoc proportional to the control current Iaocct. In other words, the feedback current source 52 causes the DC bypass current Iaoc to flow from the drain of the field effect transistor 55 to the source of the field effect transistor 55 according to the control current Iaocct. As will be described later, the control current Igc2ct flows out from the variable resistance circuit 80 toward the input terminal of the TIA unit 11 to increase the DC component of the photocurrent Ipd. Therefore, the DC bypass current Iaoc is set to include the control current Iagc2ct. Specifically, as shown in FIG. 3, the control current Iacct is generated by adding the control current Iagc2ct to the current generated by amplifying the control current Icnt at the amplification factor α. As a result, the DC component and the control current Iagc2ct are extracted from the photocurrent Ipd as the DC bypass current Iaoc. As a result, the DC component and the low frequency component are removed from the difference ΔVtia, and the potential of the voltage signal Vtia is adjusted to the potential of the reference voltage signal Vref (DC offset control).

The variable resistance circuit 53 is a circuit that generates an AC bypass current Iagc1 according to the control current Ict. More specifically, the variable resistance circuit 53 generates an AC bypass current Iagc1 according to the control current Igc1ct. The variable resistance circuit 53 has a control terminal 53a, a resistance terminal 53b, and a resistance terminal 53c. The control terminal 53a is electrically connected to the output terminal 51c of the control circuit 51C, and receives the control current Iagc1ct from the control circuit 51C. The resistance terminal 53b is electrically connected to the input terminal 10a. The resistance terminal 53c is electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a), and receives the reference voltage signal Vref from the reference voltage generation circuit 12. The variable resistance circuit 53 includes a field effect transistor 56 (first field effect transistor) and a field effect transistor 57 (second field effect transistor).

Each of the field effect transistors 56 and 57 is, for example, an N-channel MOS transistor. The size of the field effect transistor 56 and the size of the field effect transistor 57 may be the same or different from each other. The sources of the field effect transistors 56 and 57 are electrically connected to each other and are electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a) via the resistance terminal 53c. A reference voltage signal Vref is input (supplied) to the sources of the field effect transistors 56 and 57. The drain of the field effect transistor 56 is electrically connected to the output terminal 51c of the control circuit 51C via the control terminal 53a, and receives the control current Iagc1ct from the control circuit 51C. The gate of the field effect transistor 56 is electrically connected to the drain of the field effect transistor 56. The drain of the field effect transistor 57 is electrically connected to the input terminal 10a via the resistance terminal 53b. The gate of the field effect transistor 57 is electrically connected to the drain and gate of the field effect transistor 56.

In the variable resistance circuit 53 configured in this way, the control current Igc1ct flowing from the control terminal 53a flows through the field effect transistor 56 connected to the diode, thereby gate between the gate and the source of the field effect transistor 56. -Generate the source voltage Vgs2. Since the gate of the field-effect transistor 56 and the gate of the field-effect transistor 57 are electrically connected to each other, and the source of the field-effect transistor 56 and the source of the field-effect transistor 57 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 57 becomes equal to the gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of the field-effect transistor 57, and the input potential of the TIA unit 11 is applied to the drain of the field-effect transistor 57. Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA unit 11, the field effect transistor 57 operates in a deep triode region (linear region). The deep triode region is a state in which the result of subtracting the threshold voltage from the gate-source voltage of the transistor is much larger than the drain-source voltage. As the drain voltage of the field effect transistor 57 increases in the linear region, the drain current also increases accordingly. Especially when the drain voltage is relatively small, the drain current can be regarded as changing (linear) in proportion to the drain voltage. The ratio of the drain voltage to the drain current of the field effect transistor 57 is expressed as the resistance value _RAGC1 . The resistance value R _AGC1 will be described later.

The drain current Id (that is, the AC bypass current Igc1) of the field-effect transistor 57 biased in the triode region is determined by the equation (1) using the intrinsic gain (gain coefficient) β and the threshold voltage Vth of the field-effect transistor 57. Can be represented by. The intrinsic gain β is a value that depends on the semiconductor process of the field effect transistor 57.

In the triode region, when the potential difference between the drain and the source is small, the magnitude relationship between the drain potential and the source potential may be reversed. In this case, the terminal with the lowest voltage with respect to the gate functions as the source. Since the circuit symbol of the transistor is used for convenience in the expression of the circuit, the terminal notation of the transistor in the circuit diagram may not match the actual operation of the transistor. Here, the terminals are appropriately replaced so that the drain-source voltage Vds becomes 0 or more, and the terminal having a low potential is always regarded as the source.

As shown in the equation (2), the gate-source voltage Vgs2 is expressed by adding the drain-source voltage Vds to the gate-source voltage Vgs0. The gate-source voltage Vgs0 is the gate-source voltage when the drain-source voltage Vds is 0V.

By substituting Eq. (2) into Eq. (1), Eq. (3) is obtained. As shown in the formula (3), the drain current Id (AC bypass current Igc1) is proportional to the square of the drain-source voltage Vds, and therefore contains a non-linear component.

As shown in the equation (4), the differential resistance value Rd (resistance value _RAGC1 ) is obtained by differentiating the equation (3) with the drain-source voltage Vds and calculating the reciprocal of the calculation result. As shown in the equation (4), the resistance value _RAGC1 changes according to the drain-source voltage Vds. Since the drain potential is modulated according to the photocurrent Ipd, the resistance value _RAGC1 fluctuates non-linearly.

As shown in the equation (5), the transconductance gm in the triode region can be obtained by differentiating the equation (3) with the gate-source voltage Vgs0. In the triode region, the drain-source voltage Vds is smaller than the voltage obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs2. Especially in the deep triode region, the drain-source voltage Vds is much smaller than the voltage obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs2, so that the transconductance in the triode region The gm is negligibly small when compared with the transconductance (β × (Vgs-Vth)) in the saturation operation.

That is, although the variable resistance circuit 53 has the same circuit configuration as the feedback current source 52, it does not operate as a current mirror circuit, and the field effect transistor 57 is controlled by the gate-source voltage Vgs2. Operates as a variable resistor. That is, the field effect transistor 57 is AC grounded by the reference voltage generation circuit 12, and the field effect transistor 57 is biased in the deep triode region. Since the potential of the resistance terminal 53b and the potential of the resistance terminal 53c are substantially the same, the DC component of the photocurrent Ipd hardly flows into the variable resistance circuit 53, and a part of the AC component of the photocurrent Ipd is the variable resistance circuit 53 ( It flows into the field effect transistor 57) as an AC bypass current Iagc1. In other words, the variable resistance circuit 53 causes an AC bypass current Iagc1 to flow between the drain and the source of the field effect transistor 57 according to the control current Igc1ct. Since the AC bypass current Iagc1 is an AC component, the AC bypass current Iagc1 may flow from the drain of the field effect transistor 57 to the source or flow from the source of the field effect transistor 57 to the drain depending on the photocurrent Ipd. There is also.

That is, when the optical current Ipd becomes large, the difference ΔVtia becomes large, and the control current Ict exceeds the current value of the offset current Ifs, the control current Igc1ct is supplied to the variable resistance circuit 53. As a result, the gate-source voltage Vgs2 is generated in the field effect transistors 56 and 57. As the gate-source voltage Vgs2 increases, the resistance value _RAGC1 of the field effect transistor 57 decreases, so that a part of the signal component (AC component) excluding the DC component of the photocurrent Ipd is extracted as the AC bypass current Iagc1. .. As a result, the possibility that the TIA unit 11 is saturated by the large signal input is reduced.

As described above, a current proportional to the voltage between the drain and the source flows between the drain and the source of the field effect transistor 57 biased in the deep triode region (linear region). Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA unit 11, no DC current flows, and the AC bypass current Iagc1 does not disturb the DC offset control. The change in the resistance value R _AGC1 of the field effect transistor 57 affects only the characteristics of the AOC control gain.

The variable resistance circuit 80 is a circuit that generates an AC bypass current Igc2 according to the control current Ict. More specifically, the variable resistance circuit 80 generates an AC bypass current Iagc2 according to the control current Igc2ct. The variable resistance circuit 80 has a control terminal 80a, a resistance terminal 80b, and a resistance terminal 80c. The control terminal 80a is electrically connected to the output terminal 51e of the control circuit 51C, and receives the control current Iagc2ct from the control circuit 51C. The resistance terminal 80b is electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a), and receives the reference voltage signal Vref from the reference voltage generation circuit 12. The resistance terminal 80c is electrically connected to the input terminal 10a. The variable resistance circuit 80 includes a field effect transistor 81 (third field effect transistor) and a field effect transistor 82 (fourth field effect transistor).

Each of the field effect transistors 81 and 82 is, for example, an N-channel MOS transistor. The size of the field effect transistor 81 and the size of the field effect transistor 82 may be the same or different from each other. The sources of the field effect transistors 81 and 82 are electrically connected to each other and are electrically connected to the input terminal 10a via the resistance terminal 80c. The drain of the field effect transistor 81 is electrically connected to the output terminal 51e of the control circuit 51C via the control terminal 80a, and receives the control current Iagc2ct from the control circuit 51C. The gate of the field effect transistor 81 is electrically connected to the drain of the field effect transistor 81. The gate of the field-effect transistor 82 is electrically connected to the drain and gate of the field-effect transistor 81. The drain of the field effect transistor 82 is electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a) via the resistance terminal 80b. A reference voltage signal Vref is input (supplied) to the drain of the field effect transistor 82. In other words, the relationship between the resistance terminal connected to the reference voltage generation circuit 12 and the resistance terminal connected to the input terminal 10a is opposite between the variable resistance circuit 53 and the variable resistance circuit 80.

In the variable resistance circuit 80 configured in this way, the control current Igc2ct flowing from the control terminal 80a flows through the field effect transistor 81 connected to the diode, thereby gate between the gate and the source of the field effect transistor 81. -Generate a source-to-source voltage Vgs3. Since the gate of the field effect transistor 81 and the gate of the field effect transistor 82 are electrically connected to each other, and the source of the field effect transistor 81 and the source of the field effect transistor 82 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 82 becomes equal to the gate-source voltage Vgs3. A reference voltage signal Vref is supplied to the drain of the field effect transistor 82, and the input potential of the TIA unit 11 is applied to the source of the field effect transistor 82. Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA unit 11, the field effect transistor 82 operates in a deep triode region (linear region). As the drain voltage of the field effect transistor 82 increases in the linear region, the drain current increases accordingly. Especially when the drain voltage is relatively small, the drain current can be regarded as changing (linear) in proportion to the drain voltage. The ratio of the drain voltage to the drain current of the field effect transistor 82 is expressed as the resistance value _RAGC2 .

As a result, the field effect transistor 82 operates as a variable resistor controlled by the gate-source voltage Vgs3, similarly to the field effect transistor 57. Resistance _{R AGC 2} of the field effect transistor 82, similar to the resistance value _{R AGC1,} the formula (4). That is, the field effect transistor 82 is AC grounded by the reference voltage generation circuit 12, and the field effect transistor 82 is biased in the deep triode region. Since the potential of the resistance terminal 80b and the potential of the resistance terminal 80c are substantially the same, the DC component of the photocurrent Ipd hardly flows into the variable resistance circuit 80, and a part of the AC component of the photocurrent Ipd is the variable resistance circuit 80 ( It flows into the field effect transistor 82) as an AC bypass current Iagc2. In other words, the variable resistance circuit 80 causes the AC bypass current Iagc2 to flow between the drain and the source of the field effect transistor 82 according to the control current Igc2ct. Since the AC bypass current Iagc2 is an AC component, the AC bypass current Iagc2 may flow from the source of the field effect transistor 82 to the drain or flow from the drain of the field effect transistor 82 to the source depending on the photocurrent Ipd. There is also.

That is, when the optical current Ipd becomes large, the difference ΔVtia becomes large, and the control current Ict exceeds the current value of the offset current Ifs, the control current Igc2ct is supplied to the variable resistance circuit 80. As a result, the gate-source voltage Vgs3 is generated in the field effect transistors 81 and 82. As the gate-source voltage Vgs3 increases, the resistance value _RAGC2 of the field effect transistor 82 decreases, so that a part of the signal component (AC component) excluding the DC component of the photocurrent Ipd is extracted as the AC bypass current Iagc2. .. As a result, the possibility that the TIA unit 11 is saturated by the large signal input is reduced.

A current proportional to the voltage between the drain and the source flows between the drain and the source of the field effect transistor 82 biased in the deep triode region (linear region). Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA unit 11, no DC current flows, and the AC bypass current Iagc2 does not disturb the DC offset control. The change in the resistance value R _AGC2 of the field effect transistor 82 affects only the characteristics of the AOC control gain.

In the variable resistance circuit 80, the control current Iagc2ct flowing from the control terminal 80a flows into the field effect transistor 81 connected to the diode, flows out from the resistance terminal 80c toward the input terminal of the TIA unit 11, and the optical current Ipd. Increase the DC component. As described above, the control current Iagc2ct is drawn by the feedback current source 52 as part of the DC bypass current Iaoc. As a result, it is possible to suppress the occurrence of a DC offset in the potential of the voltage signal Vtia due to the control current Iagc2ct.

Next, the relationship between the variable resistance circuit 53 and the variable resistance circuit 80 will be described. At the input terminal of the TIA unit 11, an amplitude of about 100 mV at the maximum is generated by the current signal Iin. Along with this potential fluctuation, the drain-source voltage Vds of the field effect transistors 57 and 82 may fluctuate. As described above, the drain of the field effect transistor 57 and the source of the field effect transistor 82 are commonly connected to the input terminal 10a (the input terminal of the TIA unit 11), and the source of the field effect transistor 57 and the source of the field effect transistor 82 The drain is commonly connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a). Therefore, with the above-mentioned potential fluctuation, the drain-source voltage Vds (variation) in opposite directions (opposite polarities) is generated in the field effect transistor 57 and the field effect transistor 82.

Since the variable resistance circuit 53 and the variable resistance circuit 80 are connected in parallel between the input terminal 10a and the output terminal of the reference voltage generation circuit 12, the variable resistance seen from the input terminal 10a (input of the TIA unit 11). the synthetic resistance value _{R AGCT} the circuit 53 and the variable resistor circuit 80 and the resistance value _{R AGC1} and resistance _{R AGC 2,} the relationship of equation (6) is established. Here, it is assumed that the field effect transistor 57 and the field effect transistor 82 are transistors having the same structure, have the same size, and have the same electrical characteristics as each other. That is, the intrinsic gain β, the gate-source voltage Vgs0, and the threshold voltage Vth of the field-effect transistor 57 are equal to the intrinsic gain β, the gate-source voltage Vgs0, and the threshold voltage Vth of the field-effect transistor 82, respectively. In this case, although neither the resistance value _{R AGC1} and resistance _{R AGC 2} is expressed by Equation (4), the field effect transistor 57 and field-effect transistor 82 has a drain-source voltage Vds of the opposite polarity occurs Therefore, the drain-source voltage Vds generated in the field-effect transistor 57 is set to “+ Vds”, and the drain-source voltage Vds generated in the field-effect transistor 82 is set to “−Vds”.

By rearranging the equation (6), the equation (7) can be obtained. As shown in the formula (7), the combined resistance value R _AGCT does not include the component of the drain-source voltage Vds, and therefore does not change depending on the drain-source voltage Vds. Therefore, the combined resistance value R _AGCT does not depend on the drain-source voltage Vds and does not fluctuate from the resistance value when the drain-source voltage Vds is 0V. As a result, the AC component is extracted from the photocurrent Ipd with low distortion.

For example, when the potential of the input terminal 10a becomes larger by the voltage Δvds than the reference voltage signal Vref due to the potential fluctuation at the input terminal of the TIA unit 11, the drain-source voltage Vds of the field effect transistor 57 becomes + Δvds, and the electric field effect. The drain-source voltage Vds of the transistor 82 is −Δvds. At this time, the current Δids due to the voltage Δvds flows through the variable resistance circuit 53 from the resistance terminal 53b toward the resistance terminal 53c. On the other hand, in the variable resistance circuit 80, the current Δids due to the voltage Δvds flows from the resistance terminal 80b toward the resistance terminal 80c. These currents Δids flow in opposite directions to the reference voltage generation circuit 12 and cancel each other out. Therefore, the reference voltage signal Vref of the reference voltage generation circuit 12 is substantially constant regardless of the photocurrent Ipd. As a result, the reference voltage signal Vref is stabilized, so that the influence of the drain-source voltage Vds on the combined resistance value _RAGCT is further reduced. That is, the variable resistance circuit 53 and the variable resistance circuit 80 are in a relationship of compensating for non-linearity. Therefore, in the transimpedance amplifier circuit 10C, the current signal Iin can be amplified without being distorted.

Next, the operation and effect of the transimpedance amplifier circuit 10C will be described. FIG. 5A is a diagram showing changes in the total harmonic distortion with respect to the input light average power in the transimpedance amplifier circuit shown in FIG. FIG. 5B is a diagram showing a change in the output amplitude of the TIA unit with respect to the average input light power in the transimpedance amplifier circuit shown in FIG. FIG. 6A is a diagram showing changes in the total harmonic distortion with respect to the input light average power in the transimpedance amplifier circuit of the comparative example. FIG. 6B is a diagram showing a change in the output amplitude of the TIA unit with respect to the average input light power in the transimpedance amplifier circuit of the comparative example.

The horizontal axis of FIG. 5A, FIG. 5B, FIG. 6A, and FIG. 6B is the input optical average power Pin_ave, which is the average value of the optical input power of the optical signal Pin. (Unit: dBm) is shown. The vertical axis of (a) of FIG. 5 and (a) of FIG. 6 indicates the total harmonic distortion (THD) (unit:%) of the output waveform (waveform of differential voltage signals Vout and Voutb). Shown. The vertical axis of FIG. 5B and FIG. 6B shows the amplitude (unit: mVpp) of the voltage signal Vtia.

The calculation results shown in FIGS. 5A and 5B are the calculation results in the transimpedance amplifier circuit 10C (hereinafter, referred to as "Examples"). The calculation results shown in FIGS. 6A and 6B are the calculation results in the transimpedance amplifier circuit of the comparative example (hereinafter, referred to as "comparative example"). The transimpedance amplifier circuit of the comparative example is not provided with the variable resistance circuit 80 as compared with the transimpedance amplifier circuit 10C, and the resistance value R _AGC1 of the field effect transistor 57 is set to half of the transimpedance amplifier circuit 10C. The main difference is that they are.

The current value of the offset current Ifs is set so that the AGC operates when the input light average power Pin_ave exceeds the vicinity of -1 dBm. As the total harmonic distortion, the total harmonic distortion is calculated in consideration of the 10th harmonic. In order to prevent distortion in the differential amplifier circuit 13 in the subsequent stage, the size of the field effect transistor 57 is determined so that the amplitude of the voltage signal Vtia does not exceed 500 mVpp at the maximum. The gain (voltage gain) of the TIA unit 11 is set to 10 times, and the resistance value of the feedback resistance element 11b is set to 550Ω. As the optical signal Pin, an optical signal obtained by intensity-modulating with a 1 GHz sine wave is used, and the amplitude of the optical signal Pin is set to be the same as the input optical average power Pin_ave (extinguishing ratio of about 5 dB). Has been done. The photoelectric conversion gain of the light receiving element PD is set to 1.0 A / W in order to simplify the calculation.

Comparing (a) of FIG. 5 and (a) of FIG. 6, when the input light average power Pin_ave is 3 dBm, the THD is 5.2% in the comparative example, whereas the THD is in the embodiment. It can be seen that it is reduced to 4.1%. Comparing (b) of FIG. 5 and (b) of FIG. 6, it can be seen that the amplitudes of the voltage signals Vtia are controlled equally with each other in the comparative example and the embodiment. That is, it can be seen that the THD of the example is improved as compared with the THD of the comparative example even though the withdrawal amount of the AC bypass current Igc1 in the example is the same as that of the comparative example.

In the embodiment, the drain-source voltage Vds in the variable resistance circuit 53 and the drain-source voltage Vds in the variable resistance circuit 80 change in a complementary manner, so that the distortion of the resistance value _RAGC1 of the field effect transistor 57 is increased. The resistance value of the field effect transistor 82 is offset by the distortion of _RAGC2 . That is, since the connection destinations of the drain and the source of the field effect transistor 82 are inverted (replaced) with the connection destinations of the drain and the source of the variable resistance circuit 53, the drain-source voltage Vds in the variable resistance circuit 53 When is a positive value, the drain-source voltage Vds in the field effect transistor 82 becomes a negative value. Thus, the variable resistor circuit 53,80, as shown in equation (6) and (7), and the strain of the resistance value _{R AGC1} of the field effect transistor 57, and the distortion resistance _{R AGC 2} of the field effect transistor 82 , Act to cancel each other.

As described above, in the transimpedance amplification circuit 10C, the bypass circuit 15C generates the DC bypass current Iaoc, the AC bypass current Iagc1, and the AC bypass current Igc2, and the optical current Ipd generated by the light receiving element PD is used for DC bypass. The current signal Iin is generated by pulling out the current Iaoc, the AC bypass current Iagc1, and the AC bypass current Iagc2. Then, the current signal Iin is converted into the voltage signal Vtia by the TIA unit 11, and the differential voltage signals Vout and Voutb are generated by the differential amplification circuit 13 according to the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref.

In the variable resistance circuit 53, since the field effect transistor 56 is diode-connected, when the drain of the field effect transistor 56 receives the control current Iagc1ct, the gate-source voltage Vgs2 between the gate and the source of the field effect transistor 56. Is generated. Since the gate of the field effect transistor 56 and the gate of the field effect transistor 57 are electrically connected to each other, and the source of the field effect transistor 56 and the source of the field effect transistor 57 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 57 becomes equal to the gate-source voltage Vgs2. Since the reference voltage signal Vref is supplied to the source of the field effect transistor 57 and the drain of the field effect transistor 57 is electrically connected to the input terminal 10a, there is almost no potential difference between the drain of the field effect transistor 57 and the source. As a result, the field effect transistor 57 operates in the (deep) triode region. Therefore, the field-effect transistor 57 functions as a variable resistor, and the output impedance of the drain of the field-effect transistor 57 becomes low.

Similarly, in the variable resistance circuit 80, since the field effect transistor 81 is connected by a diode, when the drain of the field effect transistor 81 receives the control current Igc2ct, the gate source is between the gate and the source of the field effect transistor 81. The inter-voltage Vgs3 is generated. Since the gate of the field effect transistor 81 and the gate of the field effect transistor 82 are electrically connected to each other, and the source of the field effect transistor 81 and the source of the field effect transistor 82 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 82 becomes equal to the gate-source voltage Vgs3. Since the reference voltage signal Vref is supplied to the drain of the field effect transistor 82 and the source of the field effect transistor 82 is electrically connected to the input terminal 10a, there is almost no potential difference between the drain and the source of the field effect transistor 82. As a result, the field effect transistor 82 operates in the (deep) triode region. Therefore, the field effect transistor 82 functions as a variable resistor, and the output impedance of the source of the field effect transistor 82 becomes low.

Since there is almost no potential difference between the drain and the source of the field effect transistors 57,82, the DC component of the photocurrent Ipd hardly flows into the field effect transistors 57,82, but the AC component of the photocurrent Ipd is the AC bypass current Igc1, It can flow into the field effect transistors 57 and 82 as Iagc2. Since the control currents Igc1ct and Iagc2ct are obtained by amplifying the difference between the current generated by amplifying the control current Ict and the offset current Ifs with the amplification factor γ, the control current Ict exceeds the current value of the offset current Ifs. In this case, as the control current Ict increases, the control currents Igc1ct and Igc2ct increase, and the gate-source voltage Vgs2 and Vgs3 also increase. Therefore, when the photocurrent Ipd has a small or medium signal strength, the extraction of the AC bypass currents Iagc1 and Iagc2 can be suppressed, and the AC component of the photocurrent Ipd can be prevented from being attenuated. When the photocurrent Ipd has a large signal intensity, the AC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the AC bypass currents Iagc1 and Iagc2, so that the AC component of the photocurrent Ipd can be attenuated. In this way, the gain of the transimpedance amplifier circuit 10C is controlled by the variable resistance circuits 53 and 80.

Resistance _{R AGC 2} of the field effect transistor 82 of the resistance value _{R AGC1} and the variable resistance circuit 80 of the field effect transistor 57 of the variable resistor circuit 53, since it contains a component of the drain-source voltage Vds, the drain-source voltage Vds Can change. In the field effect transistor 57, the reference voltage signal Vref is supplied to the source and the drain is electrically connected to the input terminal 10a, whereas in the field effect transistor 82, the reference voltage signal Vref is supplied to the drain and the source. Is electrically connected to the input terminal 10a. Therefore, the polarity of the drain-source voltage Vds of the field-effect transistor 57 and the polarity of the drain-source voltage Vds of the field-effect transistor 82 are opposite to each other. Therefore, in the combined resistance value R _AGCT by the variable resistance circuit 53 and the variable resistance circuit 80 seen from the input terminal 10a, the component of the drain-source voltage Vds of the field-effect transistor 57 and the drain-source voltage of the field-effect transistor 82 The components of Vds cancel each other out. As a result, the combined resistance value R _AGCT is suppressed from fluctuating due to the drain-source voltage Vds of the field-effect transistor 57 and the drain-source voltage Vds of the field-effect transistor 82. As a result, the occurrence of distortion is suppressed, so that the signal quality can be improved.

The gain of the transimpedance amplifier circuit 10C changes according to the combined output impedance of the output impedance of the resistance terminal 53b and the output impedance of the resistance terminal 80c. The combined output impedance may be determined in consideration of the input impedance Zin of the TIA unit 11. For example, when the gain variable ratio of the TIA unit 11 is A (A is a real number larger than 1), the combined output impedance is set to Zin / (A-1). As a result, assuming that the value of the current signal Iin of the TIA unit 11 when AGC is not performed is Iinoff, the value of the current signal Iin when AGC is performed is Iinon = Iinoff / A. For example, when A = 2, the combined output impedance is substantially equal to Zin, and when A is larger than 2, the combined output impedance is set to be smaller than Zin. Therefore, when AOC and AGC are performed at the same time, the output impedance of the output terminal 52b is set to be larger than the combined output impedance. By the way, when AGC is not performed, the combined output impedance may be 100 × Zin or more. The combined output impedance may be considered to be equal to the above-mentioned combined resistance value R _AGCT . Since the input impedance Zin and the combined output impedance can have different frequency characteristics from each other, it is sufficient that the above relationship is satisfied at least in a predetermined frequency range (band).

The bypass circuit 15C includes a feedback current source 52 that generates a DC bypass current Iaoc according to the control current Ict, a variable resistance circuit 53 that generates an AC bypass current Iagc1 according to the control current Ict, and an AC according to the control current Ict. It includes a variable resistance circuit 80 that generates a bypass current Iagc2. The control circuit 51C controls the feedback current source 52 so that the DC bypass current Iaoc increases as the control current Ict increases, and the control current Ict increases when the control current Ict exceeds the current value of the offset current Ifs. The variable resistance circuits 53 and 80 are controlled so that the AC bypass currents Iagc1 and Iagc2 increase accordingly. According to this configuration, control for removing the DC component (DC offset control) and gain control for the transimpedance amplifier circuit 10C can be realized with a single control loop, so that the circuit scale is suppressed from becoming large. It becomes possible to do.

In the feedback current source 52, the field effect transistor 54 is diode-connected, so that when the drain of the field effect transistor 54 receives the control current Iaocct, the gate-source voltage Vgs1 between the gate and source of the field effect transistor 54 Is generated. Since the gate of the field effect transistor 54 and the gate of the field effect transistor 55 are electrically connected to each other, and the source of the field effect transistor 54 and the source of the field effect transistor 55 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 55 becomes equal to the gate-source voltage Vgs1. Since the source of the field-effect transistor 55 is electrically connected to the source of the field-effect transistor 54, that is, the ground potential GND, and the drain of the field-effect transistor 55 is electrically connected to the input terminal 10a, the field-effect transistor 55 The potential difference between the source and drain becomes large. As a result, the field effect transistor 55 operates in the saturation region. Therefore, the field-effect transistor 55 functions as a current source, and the output impedance of the drain of the field-effect transistor 55 becomes large. Therefore, although the AC component of the photocurrent Ipd hardly flows into the field-effect transistor 55, the DC of the photocurrent Ipd The component can flow into the field effect transistor 55 as a DC bypass current Iaoc. Then, as the control current Icnt increases, the gate-source voltage Vgs1 of the field effect transistor 54 increases, so that the drain current of the field effect transistor 55 increases accordingly, and the DC component of the optical current Ipd increases the DC bypass current. It is extracted from the photocurrent Ipd as an Iaoc, and the DC component is appropriately removed from the photocurrent Ipd. The magnitude of the output impedance of the output terminal 52b may be determined in consideration of the input impedance of the TIA unit 11. For example, when the input impedance of the TIA unit 11 is Zin, the output impedance of the output terminal 52b may be 100 × Zin or more. Since the input impedance Zin and the output impedance of the output terminal 52b can have different frequency characteristics, it is sufficient that such a relationship is satisfied at least in a predetermined frequency range (band).

In the variable resistance circuit 80, the control current Igc2ct flows from the drain of the field effect transistor 81 to the source. Since the source of the field effect transistor 81 is electrically connected to the input terminal 10a, the control current Igc2ct flows out to the input terminal 10a (the input terminal of the TIA unit 11) and increases the DC component of the photocurrent Ipd. On the other hand, since the DC bypass current Iaoc is set to include the control current Iagc2ct, the DC component caused by the control current Iagc2ct can be removed from the photocurrent Ipd. As a result, it is possible to suppress the occurrence of a DC offset in the potential of the voltage signal Vtia due to the control current Iagc2ct.

The reference voltage generation circuit 12 includes a voltage amplifier 12a and a feedback resistor element 12b electrically connected between the input and output of the voltage amplifier 12a. In this configuration, the output impedance of the reference voltage generation circuit 12 becomes low in a wide frequency range. That is, the impedance of the variable resistance circuits 53 and 80 seen from the input terminal of the TIA unit 11 becomes low in a wide frequency range. Therefore, it is possible to easily draw the AC bypass currents Iagc1 and Iagc2 from the photocurrent Ipd.

Since the DC offset control is performed using the high impedance feedback current source 52, the influence of the photocurrent Ipd on the AC component is small (the AC component does not flow). On the other hand, the gain control is performed by bypassing the AC component of the photocurrent Ipd using the variable resistance circuits 53 and 80, and since the drain potential and the source potential of the field effect transistors 57 and 82 are substantially equal, the photocurrent Ipd Has little effect on the DC component (DC component does not flow). As a result, it is possible to avoid interference between the control of removing the DC component and the gain control.

As described above, according to the transimpedance amplifier circuit 10C, the gain control of the transimpedance amplifier circuit 10C and the DC offset control for setting the difference ΔVtia to 0 are controlled by a single control loop without interfering with each other. And gain control can be performed with low distortion.

The transimpedance amplifier circuit according to the present disclosure is not limited to the above embodiment.

The circuit configurations of the TIA unit 11, the reference voltage generation circuit 12, the differential amplifier circuit 13, the control current generation circuit 14, and the bypass circuit 15C are not limited to the configurations shown in the above embodiments. For example, the TIA unit 11 may be configured to convert the current signal Iin into the voltage signal Vtia. The reference voltage generation circuit 12 may be configured to be able to supply the reference voltage signal Vref. The control current generation circuit 14 may be configured to be able to generate a control current Ict based on the integrated value of the difference ΔVtia.

Generally, the input impedance of the dummy TIA is about 10 to 100 Ω, which is the same as the input impedance of the TIA unit 11, and the output impedance of the dummy TIA is about several Ω. Since the input terminal and the output terminal of the dummy TIA both generate the reference voltage signal Vref having substantially the same potential, any terminal may be used as the output terminal of the reference voltage generation circuit 12. Since towards the output impedance of the dummy TIA is lower than the input impedance, by using the output of the dummy TIA as an output terminal of the reference voltage generating circuit 12, it is possible to increase the resistance value R _AGC1 and resistance R _{AGC 2,} It is possible to reduce the size of the field effect transistors 57 and 82. In other words, since the parasitic capacitance of the field effect transistors 57 and 82 can be reduced, the high frequency characteristics of the transimpedance amplifier circuit 10C can be improved.

Further, the control circuit 51C is not limited to the circuit configuration shown in FIG. 4, and may be configured to be capable of generating the control current Iaocct, the control current Iagc1ct, and the control current Iagc2ct shown in FIG. The feedback current source 52 may be configured to be able to generate a DC bypass current Iaoc so that the DC bypass current Iaoc increases as the control current Iaocct increases. The feedback current source 52 includes, for example, a resistance element provided so as to change the gate-source voltage of the field effect transistor 55 according to the control current Iaocct, instead of the diode-connected field effect transistor 54. May be good. The source of the field-effect transistor 55 does not have to be electrically connected to the ground potential GND, and the source potential of the field-effect transistor 55 may be set so that the field-effect transistor 55 operates in the saturation region. .. That is, the source potential of the field effect transistor 55 is set so that the drain potential of the field effect transistor 55 becomes larger than the source potential of the field effect transistor 55. Further, the bypass circuit 15C does not have to control the feedback current source 52, the variable resistance circuit 53, and the variable resistance circuit 80 with a single control loop.

In the above embodiment, the field effect transistor 57 and the field effect transistor 82 are transistors having the same structure, have the same size, and have the same electrical characteristics as each other. However, the electrical characteristics of the field-effect transistor 57 do not have to match the electrical characteristics of the field-effect transistor 82. Even in this case, the variable resistance circuits 53 and 80 can reduce the influence of the drain-source voltage Vds, and can compensate for the non-linearity of the combined resistance value R _AGCT .

Further, the transimpedance amplifier circuit 10C may not include the reference voltage generation circuit 12, and the transimpedance amplifier circuit 10C may supply the reference voltage signal Vref from an external reference voltage generation circuit.

In the above embodiment, the magnitude of the control current Iaocct (DC bypass current Iaoc) is adjusted by the amplification factor α, but instead, it may be adjusted by the current mirror ratio of the transistors 61 and 62, and the amplification factor α And may be adjusted by both the current mirror ratios of the transistors 61 and 62. Similarly, the magnitude of the DC bypass current Iaoc may be adjusted by the current mirror ratio of the field effect transistors 54, 55.

In the above embodiment, the magnitude of the control current Igc1ct (AC bypass current Igc1) is adjusted by the current values of the amplification factor γ and the offset current Ifs, but instead of the amplification factor γ, it is adjusted by the current mirror ratio of the transistors 61 and 63. It may be adjusted, or may be adjusted by the amplification factor γ, the current mirror ratio of the transistors 61 and 63, and the current value of the offset current Ifs. Similarly, the magnitude of the AC bypass current Igc1 may be adjusted by the size of the field effect transistor 56, the size of the field effect transistor 57, and the like.

In the above embodiment, the field effect transistors 54, 55 and the transistors 61 to 69, 71, 72 have been described using the field effect transistors, but the field effect transistors 54, 55 and the transistors 61 to 69, 71, 72 may be a bipolar transistor. When the field effect transistors 54, 55 and the transistors 61 to 69, 71, 72 are bipolar transistors, the gate, source, and drain of the field effect transistors are read as base, emitter, and collector, respectively.

1C ... Optical receiver, 10C ... Transimpedance amplification circuit, 10a ... Input terminal, 11 ... TIA section (single-ended amplification circuit), 11a ... Voltage amplifier, 11b ... Feedback resistance element, 12 ... Reference voltage generation circuit, 12a ... Voltage amplifier (amplifier), 12b ... feedback resistance element, 13 ... differential amplification circuit, 14 ... control current generation circuit, 15C ... bypass circuit, 41 ... integration circuit, 41a ... input terminal, 41b ... input terminal, 41c ... output terminal , 41d ... output terminal, 42 ... OTA, 43 ... operational FET, 43a ... non-inverting input terminal, 43b ... inverting input terminal, 43c ... inverting output terminal, 43d ... non-inverting output terminal, 44 ... resistance element, 45 ... resistance element, 46 ... Condenser, 47 ... Condenser, 51C ... Control circuit, 51a ... Input terminal, 51b ... Output terminal, 51c ... Output terminal, 51d ... Power supply terminal, 51e ... Output terminal, 52 ... Feedback current source, 52a ... Input terminal, 52b ... Output terminal, 52c ... Ground terminal, 53 ... Variable resistance circuit (first variable resistance circuit), 53a ... Control terminal, 53b ... Resistance terminal, 53c ... Resistance terminal, 54 ... Field effect transistor (fifth field effect transistor), 55 ... Field effect transistor (sixth field effect transistor), 56 ... Field effect transistor (first field effect transistor), 57 ... Field effect transistor (second field effect transistor), 61-69, 71, 72 ... Transistor, 70 ... current source, 80 ... variable resistance circuit (second variable resistance circuit), 80a ... control terminal, 80b ... resistance terminal, 80c ... resistance terminal, 81 ... field effect transistor (third field effect transistor), 82 ... field effect transistor (4th field effect transistor), GND ... Ground potential, Iaoc ... DC bypass current, Iaoccnt ... Control current (3rd control current), Iagc1 ... AC bypass current (1st AC bypass current), Iagc1ct ... Control current (1st) Control current), Iagc2 ... AC bypass current (second AC bypass current), Iagc2ct ... Control current (second control current), Icnt ... Control current, Iin ... Current signal, Ifs ... Offset current, Ipd ... Photocurrent (input current) Signal), Iref ... Reference current, N1 ... Node, N2 ... Node, Pin ... Optical signal, PD ... Light receiving element, VCS ... Power supply voltage, Vgs1 ... Gate-source voltage, Vgs2 ... Gate-source voltage, Vgs3 ... Gate -Source-to-source voltage, Vinn ... voltage signal, Vinp ... voltage signal, Vout, Voutb ... differential voltage signal, VPD ... Ear voltage, Vref ... reference voltage signal, Vtia ... voltage signal.

Claims (5)

A transimpedance amplifier circuit that generates a differential voltage signal according to the input current signal generated by the light receiving element.
An input terminal that receives the input current signal and
A single-ended amplifier circuit that converts a current signal into a voltage signal,
A differential amplifier circuit that generates the differential voltage signal according to the difference between the voltage signal and the reference voltage signal.
A control current generation circuit that generates a control current based on the integrated value of the difference,
A bypass circuit that generates a DC bypass current, a first AC bypass current, and a second AC bypass current according to the control current, and
With
The current signal is generated by extracting the DC bypass current, the first AC bypass current, and the second AC bypass current from the input current signal.
The bypass circuit includes a control circuit to which the control current is input, a first variable resistance circuit that generates the first AC bypass current according to the control current, and the second AC bypass current according to the control current. With a second variable resistance circuit, which produces
The control circuit generates an offset current having a predetermined offset current value, and amplifies the difference between the generated current and the offset current by the first amplification factor to amplify the first control current. And generate a second control current,
The first variable resistance circuit is
A first field effect transistor having a first drain that receives the first control current, a first gate that is electrically connected to the first drain, and a first source to which the reference voltage signal is supplied.
A second drain electrically connected to the input terminal, a second gate electrically connected to the first drain and the first gate, and a second source to which the reference voltage signal is supplied are provided. The second field effect transistor to have
With
The first variable resistance circuit causes the first AC bypass current to flow from the second drain to the second source in response to the first control current.
The second variable resistance circuit is
A third field effect transistor having a third drain that receives the second control current, a third gate that is electrically connected to the third drain, and a third source that is electrically connected to the input terminal. When,
A fourth drain to which the reference voltage signal is supplied, a fourth gate electrically connected to the third drain and the third gate, and a fourth source electrically connected to the third source. 4th field effect transistor with
With
The second variable resistance circuit is a transimpedance amplifier circuit that causes the second AC bypass current to flow from the fourth source to the fourth drain in response to the second control current. The bypass circuit further comprises a feedback current source that generates the DC bypass current in response to the control current.
The transimpedance amplifier circuit according to claim 1, wherein the control circuit controls the feedback current source so that the DC bypass current increases as the control current increases. The control circuit generates a third control current by amplifying the control current at a second amplification factor.
The feedback current source is
A fifth field effect transistor having a fifth drain that receives the third control current, a fifth gate that is electrically connected to the fifth drain, and a fifth source that is electrically connected to the ground potential. ,
A sixth drain electrically connected to the input terminal, a sixth gate electrically connected to the fifth drain and the fifth gate, and a sixth source electrically connected to the fifth source. And a sixth field effect transistor with
With
The transimpedance amplifier circuit according to claim 2, wherein the feedback current source causes the DC bypass current to flow from the sixth drain to the sixth source in accordance with the third control current. The transimpedance amplifier circuit according to any one of claims 1 to 3, wherein the DC bypass current is set to include the second control current flowing out of the second variable resistance circuit. A reference voltage generation circuit for generating the reference voltage signal is further provided.
The transimpedance amplifier circuit according to any one of claims 1 to 4, wherein the reference voltage generation circuit includes an amplifier and a feedback resistance element electrically connected between the input and output of the amplifier. ..

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