JP2021027586A - Transimpedance amplifier circuit - Google Patents

Abstract

To suppress fluctuations in a control time constant due to a change in the signal strength of a burst optical signal.SOLUTION: In a transimpedance amplifier circuit 10A: an OTA42A generates a control current Icnt according to a differential integration signal by a first transconductance when a value of the differential integration signal is smaller than a threshold value; generates the control current Icnt according to the differential integration signal by a second transconductance which is larger than the first transconductance when the value of the differential integration signal is larger than the threshold value; and the control circuit 51 controls a feedback current source 52 such that a DC bypass current Iaoc increases as the control current Icnt increases, and controls a variable resistance circuit 53 such that an AC bypass current Iagc increases as the control current Icnt increases when the control current Icnt exceeds an offset current value.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a transimpedance amplifier circuit.

In EPON (Ethernet (registered trademark) Passive Optical Network), which is an optical access system, a transimpedance amplifier circuit is used as an optical receiver of a station-side device (OLT: Optical Line Terminal). The OLT optical receiver receives burst optical signals from a plurality of home-side devices (ONUs: Optical Network Units) by time division multiplexing (TDM). The transmission line loss from each ONU to the OLT differs depending on the distance from the OLT. Therefore, the signal strength from the ONU located relatively close to the OLT is large, and the signal strength from the ONU located farther from the OLT than the ONU is small. In this way, burst optical signals of various signal intensities are input to the optical receiver of the OLT. Therefore, the transimpedance amplifier circuit included in the OLT optical receiver includes a feedback control circuit that extracts a bypass current from the current signal corresponding to the burst optical signal so that burst optical signals of various signal intensities can be received ( For example, see Patent Document 1).

Patent Document 1 describes an amplifier that converts an input current into an output voltage, a differential amplifier that converts an output voltage into a differential output signal, and a bypass circuit that extracts a bypass current from an optical current generated in a photodiode. The amplifier circuit to be provided is described. This amplifier circuit sets the time constant of the feedback control circuit to a small value in order to operate automatic gain control at high speed in the initial stage (preamble) of the burst signal, and in the payload of the burst signal, it has the resistance to continuous signals of the same code. It has a function to set the time constant of the feedback control circuit to a large value in order to raise it.

Japanese Unexamined Patent Publication No. 2012-10107

However, in the amplifier circuit described in Patent Document 1, since the forward voltage of the diode is controlled by the emitter follower circuit provided in the output portion of the bypass circuit, the output voltage of the emitter follower circuit is the on-resistance of the diode. It is divided by the input impedance of the amplifier and fed back. Since the on-resistance of the diode can change according to the signal level (signal strength) of the burst optical signal, the time constant of the feedback control depends on the signal strength of the burst optical signal. For example, when a large signal having a large signal strength is input, the on-resistance of the diode becomes small, so that the one-round transmission gain becomes large and the time constant of feedback control becomes small. It is desired that the time constant of the feedback control be kept constant regardless of the signal strength of the burst optical signal.

In the present disclosure, a transimpedance amplifier circuit capable of suppressing fluctuations in the control time constant due to changes in the signal intensity of a burst optical signal will be described.

The transimpedance amplifier circuit according to one aspect of the present disclosure is a circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element in response to a burst light signal. This transimpedance amplification circuit generates an input terminal that receives an input current signal, a single-ended amplification circuit that converts a current signal into a voltage signal, and a differential voltage signal according to the difference between the voltage signal and the reference voltage signal. It includes a differential amplification circuit, a control current generation circuit that generates a control current based on the difference, and a bypass circuit that generates a DC bypass current and an AC bypass current according to the control current. The current signal is generated by extracting the DC bypass current and the AC bypass current from the input current signal. The bypass circuit includes a control circuit to which a control current is input, a feedback current source that generates a DC bypass current according to the control current, and a variable resistance circuit that generates an AC bypass current according to the control current. The control current generation circuit is an amplifier circuit that integrates the differences to generate a differential integrated signal, and when the value of the differential integrated signal is smaller than the threshold value, the first transconductance generates a control current according to the differential integrated signal. Then, when the value of the differential integrated signal is larger than the threshold value, a transconductance amplifier circuit that generates a control current according to the differential integrated signal by a second transconductance larger than the first transconductance is provided. The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and the AC bypass current increases as the control current increases when the control current exceeds a predetermined offset current value. The variable resistance circuit is controlled so as to be.

According to the present disclosure, it is possible to suppress fluctuations in the control time constant due to changes in the signal intensity of the burst optical signal.

FIG. 1 is a diagram schematically showing a configuration of an optical receiver including a transimpedance amplifier circuit according to an embodiment. FIG. 2 is a diagram showing a circuit configuration example of the integrating circuit shown in FIG. FIG. 3 is a diagram showing an example of DC (Direct Current) input / output characteristics of the integrating circuit shown in FIG. FIG. 4 is a diagram schematically showing the configuration of the OTA shown in FIG. FIG. 5 is a diagram showing the input / output current characteristics of the OTA shown in FIG. FIG. 6 is a diagram showing the transconductance characteristics of the OTA shown in FIG. FIG. 7 is a diagram showing an example of the circuit configuration of the OTA shown in FIG. FIG. 8 is a diagram showing the relationship between the control current supplied to the control circuit shown in FIG. 1 and the current generated by the control circuit. FIG. 9 is a diagram showing a circuit configuration example of the control circuit shown in FIG. FIG. 10 is a diagram showing DC offset characteristics and gain characteristics in the transimpedance amplifier circuit shown in FIG. FIG. 11A is a diagram showing a circular transfer function of the control loop in the transimpedance amplifier circuit shown in FIG. FIG. 11B is a diagram showing a closed loop frequency characteristic in the transimpedance amplifier circuit shown in FIG. FIG. 12A is a diagram showing a round-trip transfer function of the control loop in the transimpedance amplifier circuit of the comparative example. FIG. 12B is a diagram showing a closed loop frequency characteristic in the transimpedance amplifier circuit of the comparative example. FIG. 13 is a diagram showing changes in the transimpedance gain and changes in the low cutoff frequency with respect to the optical input level. FIG. 14 is a diagram showing a change in the control time constant with respect to the optical input level. FIG. 15 is a diagram showing the response of each node in the optical receiver shown in FIG.

[Explanation of Embodiments of the present disclosure]
First, the contents of the embodiments of the present disclosure will be listed and described.

The transimpedance amplifier circuit according to one aspect of the present disclosure is a circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element in response to a burst light signal. This transimpedance amplification circuit generates an input terminal that receives an input current signal, a single-ended amplification circuit that converts a current signal into a voltage signal, and a differential voltage signal according to the difference between the voltage signal and the reference voltage signal. It includes a differential amplification circuit, a control current generation circuit that generates a control current based on the difference, and a bypass circuit that generates a DC bypass current and an AC bypass current according to the control current. The current signal is generated by extracting the DC bypass current and the AC bypass current from the input current signal. The bypass circuit includes a control circuit to which a control current is input, a feedback current source that generates a DC bypass current according to the control current, and a variable resistance circuit that generates an AC bypass current according to the control current. The control current generation circuit is an amplifier circuit that integrates the differences to generate a differential integrated signal, and when the value of the differential integrated signal is smaller than the threshold value, the first transconductance generates a control current according to the differential integrated signal. Then, when the value of the differential integrated signal is larger than the threshold value, a transconductance amplifier circuit that generates a control current according to the differential integrated signal by a second transconductance larger than the first transconductance is provided. The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and the AC bypass current increases as the control current increases when the control current exceeds a predetermined offset current value. The variable resistance circuit is controlled so as to be.

In this transimpedance amplifier circuit, a differential integrated signal is generated by integrating the difference between the voltage signal and the reference voltage signal, and when the value of the differential integrated signal is smaller than the threshold value, the differential integrated signal is generated by the first transconductance. When the value of the differential integrated signal is larger than the threshold value, the control current is generated according to the differential integrated signal, and the control current is generated according to the differential integrated signal by the second transconductance larger than the first transconductance. Until this control current exceeds the offset current value, the AC bypass current is not drawn out, so the resistance value of the variable resistance circuit does not change. On the other hand, when the control current exceeds the offset current value, the variable resistance circuit is controlled so that the AC bypass current increases as the control current increases, so that the resistance value of the variable resistance circuit decreases. In the control current generation circuit, when the value of the differential integrated signal becomes larger than the threshold value, the second transconductance larger than the first transconductance is used. In this way, the decrease in the one-round transmission gain due to the decrease in the resistance value of the variable resistance circuit can be compensated for by the increase in the transconductance of the control current generation circuit. As a result, it is possible to suppress an increase in the control time constant of the feedback control. As a result, it is possible to suppress fluctuations in the control time constant due to changes in the signal strength of the burst optical signal.

The transconductance amplification circuit includes a first transconductance circuit that generates a first output current based on a differential integrated signal, and a second transconductance circuit that generates a second output current based on a differential integrated signal. Alternatively, the control current may be generated by adding the first output current and the second output current. The first transconductance circuit may operate so that the first output current decreases as the value of the differential integrated signal increases in the first range of the value of the differential integrated signal. The second transconductance circuit may operate so that the second output current increases as the value of the differential integrated signal increases in the second range of the value of the differential integrated signal. The upper limit of the second range may be smaller than the upper limit of the first range, and the lower limit of the second range may be larger than the lower limit of the first range. In this case, the first output current that decreases as the value of the differential integration signal increases in the first range and the second output current that increases as the value of the differential integration signal increases in the second range are added. Then, the control current is generated. Therefore, it is possible to simplify the generation of the control current.

The integrator circuit is located between the first output terminal that outputs the negative phase component of the differential integrated signal, the second output terminal that outputs the positive phase component of the differential integrated signal, and the first output terminal and the second output terminal. A diode provided in the above may be provided. The difference may be a value obtained by subtracting the voltage signal from the reference voltage signal. The anode of the diode may be electrically connected to the first output terminal. The cathode of the diode may be electrically connected to the second output terminal. In the absence of a burst optical signal, the voltage signal may be larger than the reference voltage signal due to variations in the characteristics of the single-ended amplifier circuit. Since the feedback current source causes a DC bypass current to flow in the direction of drawing from the input current signal, for example, when the voltage signal is larger than the reference voltage signal, this difference cannot be brought close to zero. On the other hand, the anode of the diode is electrically connected to the first output terminal, and the cathode of the diode is electrically connected to the second output terminal, so that the value obtained by subtracting the voltage signal from the reference voltage signal is negative. If it has a value, the absolute value of the value can be prevented from being greater than the on-voltage of the diode. This makes it possible to shorten the response time when a burst optical signal is input.

The control circuit may generate the first control current by amplifying the control current at the first amplification factor. The feedback current source is a first electric field having a first drain that receives a first control current, a first gate that is electrically connected to the first drain, and a first source that is electrically connected to the ground potential. The effect transistor, the second drain electrically connected to the input terminal, the second gate electrically connected to the first drain and the first gate, and the second source electrically connected to the first source. A second field effect transistor having the above may be provided. The feedback current source may allow a DC bypass current to flow from the second drain to the second source according to the first control current. In this case, since the first field-effect transistor is diode-connected, when the first drain of the first field-effect transistor receives the first control current, the gate-source voltage between the first gate and the first source. Is generated. Since the first gate and the second gate are electrically connected to each other and the first source and the second source are electrically connected to each other, the gate-source voltage of the second field effect transistor is the first. 1 It becomes equal to the gate-source voltage of the field effect transistor. In the second field effect transistor, since the second source is electrically connected to the first source, that is, the ground potential, and the second drain is electrically connected to the input terminal, the second source and the second drain are connected. The potential difference becomes large. As a result, the second field effect transistor operates in the saturation region. Therefore, the second field-effect transistor functions as a current source, and the output impedance of the second drain becomes large. Therefore, although the AC component of the input current signal hardly flows into the second field-effect transistor, the DC component of the input current signal. Can flow into the second field effect transistor as a DC bypass current. Then, as the control current increases, the gate-source voltage of the first field effect transistor increases, so that the DC component of the input current signal is extracted from the input current signal as a DC bypass current, and the DC component of the input current signal The removal is done properly.

The control circuit may generate an offset current set to the offset current value, and the second control is performed by amplifying the difference current between the generated current and the offset current by the second amplification factor by amplifying the control current. An electric current may be generated. The variable resistance circuit is a third field effect transistor having a third drain that receives a second control current, a third gate that is electrically connected to the third drain, and a third source to which a reference voltage signal is supplied. A fourth drain electrically connected to the input terminal, a fourth gate electrically connected to the third drain and the third gate, and a fourth source electrically connected to the third source. A fourth field effect transistor having the above may be provided. The variable resistor circuit may draw an AC bypass current from the input current signal according to the second control current. In this case, since the third field effect transistor is connected by a diode, when the third drain of the third field effect transistor receives the second control current, the gate-source voltage between the third gate and the third source. Is generated. Since the third gate and the fourth gate are electrically connected to each other and the third source and the fourth source are electrically connected to each other, the gate-source voltage of the fourth field effect transistor is the third. Equal to the gate-source voltage of the field effect transistor. In the fourth field effect transistor, since the reference voltage signal is supplied to the fourth source and the fourth drain is electrically connected to the input terminal, there is almost no potential difference between the fourth drain and the fourth source. As a result, the fourth field effect transistor operates in the (deep) triode region (linear region). Therefore, the fourth field effect transistor functions as a variable resistor, and the output impedance of the fourth drain becomes low. Since there is almost no potential difference between the 4th drain and the 4th source, the DC component of the input current signal hardly flows into the 4th field effect transistor, but the AC component of the input current signal is the AC bypass current of the 4th field effect transistor. Can flow into. Then, as the control current increases when the control current exceeds a predetermined offset current value, the gate-source voltage of the third field effect transistor increases. Therefore, when the input current signal is relatively small, the AC bypass current It is possible to suppress the withdrawal of the current and prevent the AC component from being attenuated. When the input current signal is relatively large, the AC component of the input current signal is extracted from the input current signal as an AC bypass current, so that the AC component of the input current signal can be attenuated. Therefore, the variable resistance circuit appropriately controls the gain of the transimpedance amplifier.

The transimpedance amplifier circuit may further include a reference voltage generation circuit that generates a reference voltage signal. The reference voltage generation circuit may include an amplifier and a feedback resistor element electrically connected between the input and output of the amplifier. In this case, the output impedance of the reference voltage generation circuit becomes low in a wide frequency range. That is, the impedance of the variable resistance circuit seen from the input terminal of the single-ended amplifier circuit becomes low in a wide frequency range. Therefore, it is possible to easily draw the AC bypass current from the input current signal.

[Details of Embodiments of the present disclosure]
A specific example of the transimpedance amplifier circuit according to the embodiment of the present disclosure will be described below with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

FIG. 1 is a diagram schematically showing a configuration of an optical receiver including a transimpedance amplifier circuit according to an embodiment. FIG. 2 is a diagram showing a circuit configuration example of the integrating circuit shown in FIG. FIG. 3 is a diagram showing an example of DC input / output characteristics of the integrating circuit shown in FIG. FIG. 4 is a diagram schematically showing the configuration of the OTA shown in FIG. FIG. 5 is a diagram showing the input / output current characteristics of the OTA shown in FIG. FIG. 6 is a diagram showing the transconductance characteristics of the OTA shown in FIG. FIG. 7 is a diagram showing an example of the circuit configuration of the OTA shown in FIG. FIG. 8 is a diagram showing the relationship between the control current supplied to the control circuit shown in FIG. 1 and the current generated by the control circuit. FIG. 9 is a diagram showing a circuit configuration example of the control circuit shown in FIG.

The optical receiver 1A shown in FIG. 1 receives an optical signal Pin transmitted from an optical transmitter (not shown). The optical receiver 1A includes a light receiving element PD, a transimpedance amplifier circuit 10A, and a signal processing circuit 20. The optical receiver 1A may be, for example, an OLT receiver. The light receiving element PD receives the optical signal Pin and generates an optical current Ipd (input current signal) corresponding to the optical signal Pin. The optical signal Pin is, for example, a burst optical signal. The photocurrent Ipd may include an alternating current component (AC (Alternating Current) component) corresponding to the modulated signal and a direct current component (DC component) superimposed on the alternating current component. When the signal intensity (optical power) of the optical signal Pin increases, the AC component and DC component of the optical current Ipd increase, and when the signal intensity (optical power) of the optical signal Pin decreases, the AC component and DC component of the optical current Ipd increase. Becomes smaller. Examples of the light receiving element PD include a photodiode and an avalanche photodiode. One terminal (eg, cathode) of the light receiving element PD is electrically connected to a predetermined bias voltage VPD, and the other terminal (for example, anode) of the light receiving element PD outputs a photocurrent Ipd. Generally, photodiodes are used with a bias in the opposite direction. Here, "be electrically coupled" means that, for example, the cathode of the light receiving element PD is electrically connected to a circuit that generates a bias voltage VPD via wire bonding. It means that they are connected in a state where signals can be transmitted and current and voltage can be supplied between them. Therefore, "electrically connected" may include cases of being directly connected by wiring and cases of being indirectly connected via other electric elements. The term "electrically connected" is used interchangeably in the following description.

The transimpedance amplifier circuit 10A receives the optical current Ipd generated by the light receiving element PD according to the optical signal Pin, and generates the differential voltage signals Vout and Voutb which are voltage signals according to the optical current Ipd. The differential voltage signals Vout and Voutb are a pair of complementary signals. The transimpedance amplifier circuit 10A includes, for example, an input terminal 10a and output terminals 10b and 10c. The photocurrent Ipd is input to the input terminal 10a. The output terminal 10b outputs the positive phase component Vout to the outside of the transimpedance amplifier circuit 10A. The output terminal 10c outputs the reverse phase component Voutb to the outside of the transimpedance amplifier circuit 10A. For example, when the transimpedance amplifier circuit 10A is manufactured as one semiconductor integrated device (for example, a semiconductor chip) by a semiconductor process, the input terminal 10a may be a bonding pad formed on the semiconductor chip. When the semiconductor chip on which the transimpedance amplifier circuit 10A is formed is mounted in a certain package, the input terminal 10a may be an electric terminal provided on the outer surface of the package. The output terminals 10b and 10c are the same as the input terminals 10a, and may be a bonding pad formed on the semiconductor chip or an electric terminal provided on the outer surface of the package. That is, as an embodiment, the transimpedance amplifier circuit 10A may be formed on one semiconductor chip, or may be mounted in one package or on a substrate.

The output terminals 10b and 10c are electrically connected to the signal processing circuit 20 via capacitors 5a and 5b, respectively. The capacitors 5a and 5b are AC coupling capacitors. The capacitors 5a and 5b remove the DC components generated in the differential voltage signals Vout and Voutb in the transimpedance amplifier circuit 10A. By removing the DC component from the differential voltage signals Vout and Voutb, the differential voltage signals Vc and Vcb are generated and supplied to the signal processing circuit 20. For example, the differential voltage signals Vc and Vcb are a pair of complementary signals. The positive phase component Vc (positive phase signal) of the differential voltage signals Vc and Vcb has a phase different from the phase of the negative phase component Vcb (negative phase signal) of the differential voltage signals Vc and Vcb by 180 °. For example, when the positive phase component Vc increases, the negative phase component Vcb decreases, and when the positive phase component Vc decreases, the negative phase component Vcb increases. When the positive phase component Vc reaches the maximum value (peak value), the negative phase component Vcb reaches the minimum value (bottom value), and when the positive phase component Vc reaches the bottom value, the negative phase component Vcc reaches the peak value. The positive phase component Vc and the negative phase component Vcb may have the same amplitude and the same time average value. For example, assuming that the output impedance of the transimpedance amplifier circuit 10A (output amplifier 13b described later) is differential 100Ω, the input impedance of the signal processing circuit 20 is differential 100Ω, the capacitance value of the capacitor 5a and the capacitance value of the capacitor 5b are 1000pF. At the input of the differential voltage signals Vc and Vcb to the signal processing circuit 20, the capacitors 5a and 5b generate a time constant of 100 nsec.

The transimpedance amplifier circuit 10A includes a TIA (TransImpedance Amplifier) unit 11 (single-ended amplifier circuit), a reference voltage generation circuit 12, a differential amplifier circuit 13A, a control current generation circuit 14A, and a bypass circuit 15. Be prepared.

The TIA unit 11 is a circuit that converts the current signal Iin into the voltage signal Vtia. Specifically, the TIA unit 11 includes a voltage amplifier 11a and a feedback resistance element 11b. The input terminal and the output terminal of the voltage amplifier 11a are electrically connected via the feedback resistance element 11b. That is, the feedback resistance element 11b is electrically connected between the input and output of the voltage amplifier 11a. The current signal Iin is generated by extracting the DC bypass current Iaoc and the AC bypass current Iagc from the optical current Ipd. The DC bypass current Iaoc and the AC bypass current Iagc are controlled by the bypass circuit 15, which will be described in detail later. The increase / decrease of the voltage signal Vtia is reversed with respect to the increase / decrease of the current signal Iin. For example, when the magnitude of the current signal Iin increases, the voltage value of the voltage signal Vtia decreases (decreases). The voltage amplifier 11a is, for example, an inverting amplifier circuit. The TIA unit 11 outputs the voltage signal Vtia to the differential amplifier circuit 13A and the control current generation circuit 14A. The gain of the TIA unit 11 (the ratio of the change amount of the voltage signal Vtia to the change amount of the current signal Iin) is determined by the resistance value (transimpedance) of the feedback resistance element 11b. The input impedance of the TIA unit 11 is, for example, about 10 to 100 Ω.

The reference voltage generation circuit 12 is a circuit that generates a reference voltage signal Vref, which is a DC voltage signal. The reference voltage generation circuit 12 supplies the reference voltage signal Vref to the differential amplification circuit 13A, the control current generation circuit 14A, and the bypass circuit 15. The reference voltage signal Vref has, for example, a predetermined voltage value (fixed value). The reference voltage generation circuit 12 may be configured so that the output impedance of the terminal that supplies the reference voltage signal Vref is low impedance over a wide band. In the present embodiment, the reference voltage generation circuit 12 is a dummy TIA including a voltage amplifier 12a (amplifier) and a feedback resistance element 12b, similarly to the TIA unit 11. The input terminal and the output terminal of the voltage amplifier 12a are electrically connected via the feedback resistance element 12b. That is, the feedback resistance element 12b is electrically connected between the input and output of the voltage amplifier 12a. Since the reference voltage generation circuit 12 has the same circuit configuration as the TIA unit 11, the reference voltage signal Vref is generated so as to compensate (cancel) the change in the voltage signal Vtia due to the change in the power supply voltage and temperature of the voltage amplifier 11a. obtain.

The differential amplifier circuit 13A is a circuit that generates differential voltage signals Vout and Voutb according to the difference ΔVtia (error) between the voltage signal Vtia and the reference voltage signal Vref. In other words, the differential amplifier circuit 13A uses the reference voltage signal Vref to convert the single (single-phase) voltage signal Vtia into the differential voltage signals Vout and Voutb. The differential amplifier circuit 13A includes, for example, a differential amplifier 13a and an output amplifier 13b. For example, when the differential amplifier 13a is an inverting amplifier and the output amplifier 13b is a non-inverting amplifier, the differential amplifier circuit 13A performs inverting amplification. For example, when the voltage value of the voltage signal Vtia is larger than the voltage value of the reference voltage signal Vref, the voltage value of the positive phase component Vout of the differential voltage signals Vout and Voutb is the negative phase component of the differential voltage signals Vout and Voutb. It becomes smaller than the voltage value of Voutb. When the voltage value of the voltage signal Vtia is smaller than the voltage value of the reference voltage signal Vref, the voltage value of the positive phase component Vout of the differential voltage signals Vout and Voutb is the negative phase component Voutb of the differential voltage signals Vout and Voutb. It becomes larger than the voltage value.

The differential amplifier 13a generates differential voltage signals Va1 and Va1b by amplifying the difference ΔVtia. The differential amplifier 13a outputs the differential voltage signals Va1 and Va1b to the output amplifier 13b. The output amplifier 13b is a circuit that amplifies the differential voltage signals Va1 and Va1b. The output amplifier 13b generates differential voltage signals Vout and Voutb by amplifying the differential voltage signals Va1 and Va1b. The positive phase component Vout (positive phase signal) of the differential voltage signals Vout and Voutb has a phase different from the phase of the negative phase component Voutb (negative phase signal) of the differential voltage signals Vout and Voutb by 180 °. For example, when the positive phase component Vout increases, the negative phase component Voutb decreases, and when the positive phase component Vout decreases, the negative phase component Voutb increases. When the positive phase component Vout reaches the maximum value (peak value), the negative phase component Voutb reaches the minimum value (bottom value), and when the positive phase component Vout reaches the bottom value, the negative phase component Voutb reaches the peak value. The positive phase component Vout and the negative phase component Voutb may have the same amplitude and the same time mean value. The difference between the time average value of the voltage of the positive phase component and the time average value of the voltage of the negative phase component of the differential voltage signal is called DC offset. For example, the difference between the time average value of the voltage of the positive phase component Vout and the time average value of the voltage of the negative phase component Voutb is a DC offset. In the following description, the term DC offset simply means the difference between the time average value of the voltage of the positive phase component Vout and the time average value of the voltage of the negative phase component Voutb. The DC offset is preferably small in signal transmission. The output amplifier 13b outputs the differential voltage signals Vout and Voutb to the outside of the transimpedance amplifier circuit 10A via the output terminals 10b and 10c.

The control current generation circuit 14A is a circuit that generates a control current Ict based on the integral value of the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. The difference ΔVtia is a signal (voltage value) obtained by subtracting the voltage signal Vtia from the reference voltage signal Vref. The control current generation circuit 14A includes an integrating circuit 41A and an OTA (Operational Transconductance Amplifier) 42A (transconductance amplifier circuit).

The integrating circuit 41A is a circuit that integrates the difference ΔVtia to generate a differential integrated signal (voltage signal Vinp and voltage signal Vinn). As shown in FIG. 2, the integrating circuit 41A has input terminals 41a and 41b and output terminals 41c and 41d. The input terminal 41a is electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a), and the reference voltage signal Vref is input to the input terminal 41a. The input terminal 41b is electrically connected to the output terminal of the TIA unit 11 (voltage amplifier 11a), and the voltage signal Vtia is input to the input terminal 41b. The output terminal 41c (first output terminal) is electrically connected to the input terminal 42b, which is the inverting input terminal of the OTA 42A, and outputs the voltage signal Vinn, which is a reverse phase component of the differential integration signal, to the OTA 42A. The output terminal 41d (second output terminal) is electrically connected to the input terminal 42a, which is a non-inverting input terminal of the OTA 42A, and outputs a voltage signal Vinp, which is a positive phase component of the differential integrated signal, to the OTA 42A. For example, when the voltage value of the voltage signal Vtia is larger than the voltage value of the reference voltage signal Vref, the voltage value of the voltage signal Vimp becomes smaller than the voltage value of the voltage signal Vinn.

The integrator circuit 41A includes an operational amplifier 43, resistance elements 44 and 45, capacitors 46 and 47, and a diode 48. The operational amplifier 43 has a non-inverting input terminal 43a, an inverting input terminal 43b, an inverting output terminal 43c, and a non-inverting output terminal 43d. The non-inverting input terminal 43a is electrically connected to the input terminal 41a via a resistance element 44. The inverting input terminal 43b is electrically connected to the input terminal 41b via a resistance element 45. The inverting output terminal 43c is electrically connected to the output terminal 41c and is also electrically connected to the non-inverting input terminal 43a via the capacitor 46. That is, the capacitor 46 is connected so as to apply negative feedback from the inverting output terminal 43c to the non-inverting input terminal 43a. The non-inverting output terminal 43d is electrically connected to the output terminal 41d and is also electrically connected to the inverting input terminal 43b via a capacitor 47. That is, the capacitor 47 is connected so as to apply negative feedback from the non-inverting output terminal 43d to the inverting input terminal 43b. Regarding the change in the output with respect to the change in the input, for example, when the voltage value of the voltage signal Vtia is larger than the voltage value of the reference voltage signal Vref, the voltage value of the voltage signal Vinp becomes smaller than the voltage value of the voltage signal Vinn. ..

Here, the gain of the operational amplifier 43 is, for example, 1000 times or more, the resistance value R1 of the resistance element 44 and the resistance value R2 of the resistance element 45 are equal to each other, and the capacitance value C1 of the capacitor 46 and the capacitance value C2 of the capacitor 47 are mutually equal. Suppose they are equal. In this case, the gain of the operational amplifier 43 is regarded as infinite, and the integrator circuit 41A operates as an integrator having a time constant R1 × C1.

The diode 48 is provided between the output terminal 41c and the output terminal 41d. The anode of the diode 48 is electrically connected to the output terminal 41c. The cathode of the diode 48 is electrically connected to the output terminal 41d. The on-voltage (forward voltage) of the diode 48 is set to a low voltage from the viewpoint of high-speed operation of the control loop. In the example shown in FIG. 3, the gain (voltage gain) of the operational amplifier 43 is 10000 times (80 dB), and the on voltage of the diode 48 is 0.4 V. The integrator circuit 41A has a characteristic that the difference ΔVin changes by 10 mV when the difference ΔVtia changes by 1 μV. The difference ΔVin is a signal (voltage value) obtained by subtracting the voltage signal Vinn from the voltage signal Vinp, and is the voltage amplitude of the differential integration signal. In this example, when the difference ΔVin is less than −0.4V, the diode 48 is turned on. As a result, even if the difference ΔVtia increases to the minus side, the difference ΔVin is clamped at −0.4V. On the other hand, when the difference ΔVin increases to the plus side, the difference ΔVin does not increase to 1.5 V or more and saturates. As described above, the integrating circuit 41A has an asymmetrical characteristic centered on zero with respect to the difference ΔVin.

The OTA42A is a circuit that converts a differential integrated signal (voltage signal Vinp and voltage signal Vinn) into a control current Ict which is a single current signal (error current). The OTA 42A has an input / output characteristic that when the difference ΔVin is a positive value and the difference ΔVin increases, the transconductance increases.

As shown in FIG. 4, the OTA 42A has input terminals 42a and 42b and output terminals 42c. The input terminal 42a is electrically connected to the output terminal 41d of the integrating circuit 41A, and the voltage signal Vinp is input to the input terminal 42a. The input terminal 42b is electrically connected to the output terminal 41c of the integrating circuit 41A, and the voltage signal Vinn is input to the input terminal 42b. The output terminal 42c is electrically connected to the input terminal 51a of the control circuit 51, which will be described later, and outputs the control current Icnt to the control circuit 51. The OTA 42A includes a transconductance circuit 21 (first transconductance circuit), a transconductance circuit 22 (second transconductance circuit), and a current source 23.

The transconductance circuit 21 is a circuit that generates an output current Iout1 (first output current) based on a differential integrated signal (voltage signal Vinp and voltage signal Vinn). The non-inverting input terminal of the transconductance circuit 21 is electrically connected to the input terminal 42a and receives a voltage signal Vinp. The inverting input terminal of the transconductance circuit 21 is electrically connected to the input terminal 42b and receives a voltage signal Vinn. The output terminal of the transconductance circuit 21 outputs the output current Iout1.

As shown in FIG. 5, the transconductance circuit 21 operates so that the output current Iout1 decreases as the difference ΔVin increases in the range VR1 (first range) of the difference ΔVin. The transconductance circuit 21 has transconductance −gm1 (second transconductance) in the range VR1. Transconductance −gm1 corresponds to the slope of the output current Iout1 in the range VR1 in FIG. Since this slope has a negative value, gm1 is represented as -gm1 as a positive real value for convenience. When the difference ΔVin exceeds the upper limit value of the range VR1, the transconductance circuit 21 holds the current value of the output current Iout1 at the upper limit value of the range VR1. When the difference ΔVin falls below the lower limit of the range VR1, the transconductance circuit 21 holds the current value of the output current Iout1 at the lower limit of the range VR1.

The transconductance circuit 22 is a circuit that generates an output current Iout2 (second output current) based on a differential integrated signal (voltage signal Vinp and voltage signal Vinn). The non-inverting input terminal of the transconductance circuit 22 is electrically connected to the input terminal 42b and receives a voltage signal Vinn. The inverting input terminal of the transconductance circuit 22 is electrically connected to the input terminal 42a and receives a voltage signal Vinp. The output terminal of the transconductance circuit 22 outputs the output current Iout2.

As shown in FIG. 5, the transconductance circuit 22 operates so that the output current Iout2 increases as the difference ΔVin increases in the range VR2 (second range) of the difference ΔVin. The transconductance circuit 22 has transconductance gm2 in the range VR2. The transconductance gm2 corresponds to the slope of the output current Iout2 in the range VR2 in FIG. Here, gm2 is a positive real value. The magnitude (absolute value) of the transconductance gm2 is a value different from the magnitude (absolute value) of the transconductance-gm1 and smaller than the magnitude (absolute value) of the transconductance-gm1. The range VR2 is narrower than the range VR1 and is included in the range VR1. That is, the upper limit of the range VR2 is smaller than the upper limit of the range VR1, and the lower limit of the range VR2 is larger than the lower limit of the range VR1. When the difference ΔVin exceeds the upper limit value of the range VR2, the transconductance circuit 22 holds the current value of the output current Iout2 at the upper limit value of the range VR2. The transconductance circuit 22 holds the current value of the output current Iout2 at the lower limit of the range VR2 when the difference ΔVin is lower than the lower limit of the range VR2. That is, the linear operating range (range VR2) of the transconductance circuit 22 is narrower than the linear operating range (range VR1) of the transconductance circuit 21.

The current source 23 supplies a constant current Innul. The constant current Innul has a current value (fixed value) obtained by adding the current value of the output current Iout1 when the difference ΔVin is 0 and the current value of the output current Iout2 when the difference ΔVin is 0.

The OTA42A generates the control current Ict by adding the output current Iout1 and the output current Iout2. More specifically, the OTA 42A generates the control current Icnt by adding the output current Iout1 and the output current Iout2 and subtracting the addition result from the constant current Inull. By differentiating this control current Icnt with the difference ΔVin, a U-shaped transconductance characteristic having three flat portions shown in FIG. 6 can be obtained. The transconductance (gm1-gm2) (first transconductance) of the flat portion in the center is smaller than the transconductance gm1 of the flat portions on both sides thereof, and the control current Icnt is non-linear with respect to the difference ΔVin. ..

As shown in FIG. 6, when the difference ΔVin is near 0V, the transconductance of OTA42A is small, and as the absolute value of the difference ΔVin increases, the transconductance of OTA42A increases. More specifically, when the absolute value of the difference ΔVin is smaller than the threshold value Vth1, the transconductance of OTA42A is a value (gm1-gm2) obtained by subtracting the transconductance gm2 from the transconductance gm1. When the absolute value of the difference ΔVin is larger than the threshold value Vth2, the transconductance of OTA42A is transconductance gm1. When the absolute value of the difference ΔVin becomes larger and exceeds the linear operating range of the transconductance circuits 21 and 22, the transconductance of the OTA 42A decreases toward 0 again. This transconductance characteristic is line-symmetrical on the plus side and the minus side with the vertical axis of ΔVin = 0 as the center. Therefore, the transconductance (gm1-gm2) of the flat portion near ΔVin = 0 is smaller than the transconductance gm1 of the two flat portions on the outer side thereof.

Due to this characteristic, when the difference ΔVin is larger than the threshold value −Vth1 and smaller than the threshold value Vth1, the OTA42A generates a control current Icnt according to the differential integrated signals Vinp and Vinn by transconductance (gm1-gm2). When the difference ΔVin is smaller than the threshold value −Vth2 or larger than the threshold value Vth2, the OTA42A generates a control current Icnt according to the differential integration signals Vinp and Vinn by the transconductance gm1. The transconductance gm1 is larger than the transconductance (gm1-gm2). In the example shown in FIG. 6, the threshold value Vth2 is larger than the threshold value Vth1, but the threshold value Vth2 may be the same as the threshold value Vth1.

The OTA 42A can operate in both a direction of drawing the control current Ict from the output terminal 42c into the inside of the OTA 42A and a direction of discharging the control current Icnt from the output terminal 42c to the outside of the OTA 42A. Therefore, the transconductance of OTA42A can be obtained even when the control current Icnt is near 0A. By adjusting the transconductance gm1 and gm2 and the ranges VR1 and VR2, the U-shaped characteristic of the transconductance of the OTA42A is arbitrarily set.

The OTA 42A shown in FIG. 7 has a circuit configuration for realizing the OTA 42A shown in FIG. As shown in FIG. 7, the OTA 42A further has a power supply terminal 42d in addition to the input terminals 42a and 42b and the output terminal 42c. The power supply terminal 42d is electrically connected to the power supply wiring that supplies the power supply voltage VCS, and the power supply voltage VCS is supplied to the power supply terminal 42d. The OTA 42A includes, for example, a bias circuit 24 and a synthesis circuit 25 in addition to the transconductance circuits 21 and 22 and the current source 23.

The bias circuit 24 includes a transistor 24a and a current source 24b. The transistor 24a is, for example, a P-channel MOS (Metal-Oxide-Semiconductor) transistor. The source of the transistor 24a is electrically connected to the power supply terminal 42d. The gate and drain of the transistor 24a are electrically connected to each other and further electrically connected to the current source 24b. A reference current Ir is supplied to the drain of the transistor 24a. The reference current Ir flows from the drain of the transistor 24a toward the current source 24b. The value of the reference current Ir is set by the current source 24b.

The transconductance circuit 21 includes transistors 21a, 21b, 21c, 21d and a resistance element 21e. The transistors 21a, 21b, 21c, 21d are, for example, P-channel MOS transistors. The sources of the transistors 21a and 21b are electrically connected to the power supply terminal 42d via the power supply wiring. The gates of the transistors 21a and 21b are electrically connected to the gates and drains of the transistors 24a. The drain of the transistor 21a is electrically connected to the source of the transistor 21c. The drain of the transistor 21b is electrically connected to the source of the transistor 21d.

Each of the transistor 24a and the transistors 21a and 21b constitutes a current mirror circuit. The transistor 24a functions as an input transistor of the current mirror circuit, and the transistors 21a and 21b function as an output transistor of the current mirror circuit. For example, an output current (drain current Id1) having a magnitude proportional to the magnitude of the drain current (reference current Ir) of the transistor 24a is output from the drain of the transistor 21a. That is, when the input current (reference current Ir) is input to the input transistor, the output current (drain current Id1) having a magnitude proportional to the magnitude of the input current (reference current Ir) is output from the output transistor. Similarly, an output current (drain current Id2) having a magnitude proportional to the magnitude of the drain current (reference current Ir) of the transistor 24a is output from the drain of the transistor 21b. Therefore, the transistors 21a and 21b function as a current source of the transconductance circuit 21.

The transistors 21c and 21d form a differential pair. The gate of the transistor 21c is electrically connected to the input terminal 42a, and the voltage signal Vinp is input to the gate of the transistor 21c. The drain of the transistor 21c is electrically connected to the drain and the gate of the transistor 25a described later. The gate of the transistor 21d is electrically connected to the input terminal 42b, and the voltage signal Vinn is input to the gate of the transistor 21d. The drain of the transistor 21d is electrically connected to the ground potential GND. The transistor 21c may have the same electrical characteristics as the electrical characteristics of the transistor 21d. The resistance element 21e is electrically connected between the source of the transistor 21c and the source of the transistor 21d. The resistance element 21e has a resistance value of Rgm1. The size of the transistors 21c and 21d is set so that the transconductance of the transistors 21c and 21d is sufficiently larger than 1 / Rgm1. For example, by adjusting the gate length and the gate width of the transistors 21c and 21d, the transconductance gm1 of the transconductance circuit 21 becomes larger than 1 / Rgm1. The output current Iout1 is output from the drain of the transistor 21c.

The transconductance circuit 22 includes transistors 22a, 22b, 22c, 22d and a resistance element 22e. The transistors 22a, 22b, 22c, 22d are, for example, P-channel MOS transistors. The sources of the transistors 22a and 22b are electrically connected to the power supply terminal 42d. The gates of the transistors 22a and 22b are electrically connected to the gates and drains of the transistors 24a. The drain of the transistor 22a is electrically connected to the source of the transistor 22c. The drain of the transistor 22b is electrically connected to the source of the transistor 22d.

Each of the transistor 24a and the transistors 22a and 22b constitutes a current mirror circuit. The transistor 24a functions as an input transistor of the current mirror circuit, and the transistors 22a and 22b function as an output transistor of the current mirror circuit. An output current (drain current Id3) having a magnitude proportional to the magnitude of the drain current (reference current Ir) of the transistor 24a is output from the drain of the transistor 22a. Similarly, an output current (drain current Id4) having a magnitude proportional to the magnitude of the drain current (reference current Ir) of the transistor 24a is output from the drain of the transistor 22b. Therefore, the transistors 22a and 22b function as a current source of the transconductance circuit 22.

The transistors 22c and 22d form a differential pair. The gate of the transistor 22c is electrically connected to the input terminal 42b, and the voltage signal Vinn is input to the gate of the transistor 22c. The drain of the transistor 22c is electrically connected to the drain and the gate of the transistor 25a described later. The gate of the transistor 22d is electrically connected to the input terminal 42a, and the voltage signal Vinp is input to the gate of the transistor 22d. The drain of the transistor 22d is electrically connected to the ground potential GND. The transistor 22c may have the same electrical characteristics as the electrical characteristics of the transistor 22d. The resistance element 22e is electrically connected between the source of the transistor 22c and the source of the transistor 22d. The resistance element 22e has a resistance value of Rgm2. The size of the transistors 22c and 22d is set so that the transconductance of the transistors 22c and 22d is sufficiently larger than 1 / Rgm2. For example, by adjusting the gate length and gate width of the transistors 22c and 22d, the transconductance gm2 of the transconductance circuit 22 becomes larger than 1 / Rgm2. The output current Iout2 is output from the drain of the transistor 22c.

The current source 23 includes a transistor 23a. The transistor 23a is, for example, a P-channel MOS transistor. The source of the transistor 23a is electrically connected to the power supply terminal 42d. The gate of the transistor 23a is electrically connected to the gate and drain of the transistor 24a. The drain of the transistor 23a is electrically connected to the output terminal 42c. The transistor 24a and the transistor 23a form a current mirror circuit. The transistor 24a functions as an input transistor of the current mirror circuit, and the transistor 23a functions as an output transistor of the current mirror circuit. An output current (drain current) having a magnitude proportional to the magnitude of the drain current (reference current Ir) of the transistor 24a is output from the drain of the transistor 23a toward the output terminal 42c as a constant current Innl.

The synthesis circuit 25 includes transistors 25a and 25b. The transistors 25a and 25b are, for example, N-channel MOS transistors. The sources of the transistors 25a and 25b are electrically connected to the ground potential GND. The gate and drain of the transistor 25a are electrically connected to each other, and are further electrically connected to the drains of the transistors 21c and 22c. The gate of the transistor 25b is electrically connected to the gate of the transistor 25a. The drain of the transistor 25b is electrically connected to the output terminal 42c.

The output current Iout1 output from the transconductance circuit 21 and the output current Iout2 output from the transconductance circuit 22 are combined in the synthesis circuit 25, and the combined current (Iout1 + Iout2) flows through the diode-connected transistor 25a. .. The transistors 25a and 25b form a current mirror circuit. The transistor 25a functions as an input transistor of the current mirror circuit, and the transistor 25b functions as an output transistor of the current mirror circuit. An output current (drain current) having a magnitude proportional to the magnitude of the drain current (Iout1 + Iout2) of the transistor 25a is output from the drain of the transistor 25b. Here, for example, the current mirror ratio is set to 1: 1. The transistor 25b may have the same electrical characteristics as the electrical characteristics of the transistor 25a.

The pull-in current Iout1 + Iout2 generated by the synthesis circuit 25 and the constant current Inull output from the current source 23 are combined, and the combined current (Inull- (Iout1 + Iout2)) is output from the output terminal 42c as the control current Icnt. .. Since the output terminal 42c is electrically connected to the transistor 23a and the transistor 25b that function as a current source, the output impedance of the OTA 42A is very high, and the OTA 42A operates as a transconductance amplifier. When the transistor 23a functions as a current source, the transistor 23a may operate in the saturation region of the drain current-voltage characteristic. The transistor 25b may also operate, for example, in the saturation region of the drain current-voltage characteristic.

The range VR1 of the difference ΔVin in which the transconductance circuit 21 operates linearly can be represented by approximately Rgm1 × (Id1 + Id2) by using the drain current Id1 of the transistor 21a and the drain current Id2 of the transistor 21b. That is, the maximum value of the output current Iout1 is determined by (Id1 + Id2). Similarly, the range VR2 of the difference ΔVin in which the transconductance circuit 22 operates linearly can be represented by approximately Rgm2 × (Id3 + Id4) using the drain current Id3 of the transistor 22a and the drain current Id4 of the transistor 22b. That is, the maximum value of the output current Iout2 is determined by (Id3 + Id4).

The current characteristics shown in FIG. 5 can be realized by satisfying the condition of the equation (1). In this way, the desired current characteristics can be obtained by adjusting the drain currents Id1, Id2, Id3, Id4 and the resistance values Rgm1, Rgm2.

The bypass circuit 15 is a circuit that generates a DC bypass current Iaoc and an AC bypass current Iagc according to the control current Ict. The bypass circuit 15 includes, for example, a control circuit 51, a feedback current source 52, and a variable resistance circuit 53.

The control current Icnt is input to the control circuit 51. The control circuit 51 controls the feedback current source 52 so that the DC bypass current Iaoc increases as the control current Ict increases. The control circuit 51 controls the variable resistance circuit 53 so that when the control current Icnt exceeds the current value of the offset current Ifs, the AC bypass current Iagc increases as the control current Ict increases. The current value of the offset current Ifs is a predetermined current value (fixed value), and is set to, for example, the current value of the control current Icnt when the difference ΔVin is the upper limit value of the range VR1. Specifically, the control circuit 51 receives the control current Icnt from the control current generation circuit 14A (OTA42A), and the control current Iaocct (first control current) and the control current Iagccnt (second control current) according to the control current Icnt. To generate. The control circuit 51 outputs the control current Iaocct to the feedback current source 52, and controls the feedback current source 52 by the control current Iaocct. The control circuit 51 outputs the control current Igccunt to the variable resistance circuit 53, and controls the variable resistance circuit 53 by the control current Igccunt.

As shown in FIG. 8, the current value of the control current Iactnt is proportional to the current value of the control current Ictnt. The current value of the control current Iactnt is α times the current value of the control current Ictnt (Iaocct = α × Ict). The amplification factor α (first amplification factor) is, for example, a real number larger than 1. The control circuit 51 generates the control current Iacct, for example, by amplifying the control current Ict with an amplification factor α. The current value of the control current Igccnt is proportional to the current value of the control current Ict when the current value of the control current Icnt is larger than the current value of the offset current Ifs. In other words, the current value of the control current Igccnt is γ times the current value obtained by subtracting the current value of the offset current Ifs from the control current Icnt (Iagccnt = γ × (Icnt-Ifs)). The amplification factor γ (second amplification factor) is, for example, a real number larger than 1. The control circuit 51 generates, for example, an offset current Ifs having a predetermined current value (offset current value), and a current generated by amplifying the control current Ict (here, the control current Ict) and the offset current Ifs. The control current Igccnt is generated by amplifying the difference (difference current) with the amplification factor γ. In this way, in the control current Iaocct, the amplification factor α is adjusted, and in the control current Iagcctt, the offset current value for determining the current for starting automatic gain control (AGC) and the control sensitivity of the AGC are adjusted. The amplification factor γ to be determined is adjusted.

The control circuit 51 shown in FIG. 9 has a circuit configuration for realizing the control current Iaocct and the control current Iagccnt shown in FIG. As shown in FIG. 9, the control circuit 51 includes, for example, input terminals 51a, output terminals 51b and 51c, and a power supply terminal 51d. The input terminal 51a is electrically connected to the output terminal 42c of the control current generation circuit 14A (OTA42A), and the control current Icnt is input to the input terminal 51a. The output terminal 51b is electrically connected to the input terminal 52a of the feedback current source 52, and supplies the control current Iaocct to the feedback current source 52. The output terminal 51c is electrically connected to the control terminal 53a of the variable resistance circuit 53, and supplies the control current Igccunt to the variable resistance circuit 53. The power supply terminal 51d is electrically connected to the power supply wiring that supplies the power supply voltage VCS, and the power supply voltage VCS is supplied to the power supply terminal 51d.

The control circuit 51 includes transistors 61 to 69 and a current source 70. The transistors 61 to 69 are, for example, field effect transistors (MOSFETs) having a MOS structure. In the example shown in FIG. 9, the transistors 61 to 63 are N-channel MOS transistors (

Transistors 61 to 63 form a current mirror circuit. Specifically, the transistor 61 functions as an input transistor of the current mirror circuit, and the transistors 62 and 63 function as output transistors of the current mirror circuit, respectively. The sources of transistors 61-63 are electrically connected to the ground potential GND. The gate and drain of the transistor 61 are electrically connected to each other, and further electrically connected to the input terminal 51a. Each gate of the transistors 62 and 63 is electrically connected to the gate and drain of the transistor 61. The drain of the transistor 62 is electrically connected to the drain and the gate of the transistor 64. The drain of the transistor 63 is electrically connected to the drain and the gate of the transistor 68 via the node N.

Since the transistors 61 and 62 and the transistors 61 and 63 each constitute a current mirror circuit, for example, an output current (drain current) having a magnitude proportional to the magnitude of the drain current (control current Ict) of the transistor 61 is a transistor. It is output from the drains of 62 and 63, respectively. That is, when an input current (control current Ict) is input to the input transistor (transistor 61), an output current having a magnitude proportional to the magnitude of the input current (control current Ict) is generated from the output transistors (transistors 62 and 63). It is output. Here, for convenience of explanation, the current mirror ratio is set to input current: output current of transistor 62: output current of transistor 63 = 1: 1: 1. Therefore, the control current Icnt input to the input terminal 51a is duplicated by the transistors 61 to 63, and the control current Icnt is output from the drains of the transistors 62 and 63, respectively. The two duplicated control currents Icnt flow from the drains of the transistors 62 and 63 toward the source. In order to realize the current mirror ratio described above, the transistors 61 to 63 may have the same electrical characteristics. The current mirror ratio may be appropriately changed according to the relationship between the control current Iaocct and the control current Iagccnt and the control current Icnt by changing the size of the transistors 62 and 63 to the size of the transistor 61.

Transistors 64 and 65 form a current mirror circuit. The transistor 64 functions as an input transistor of the current mirror circuit, and the transistor 65 functions as an output transistor of the current mirror circuit. The sources of the transistors 64 and 65 are electrically connected to the power supply terminal 51d via the power supply wiring. The gate and drain of the transistor 64 are electrically connected to each other, and further electrically connected to the drain of the transistor 62. The gate of transistor 65 is electrically connected to the gate and drain of transistor 64. The drain of the transistor 65 is electrically connected to the output terminal 51b.

The control current Icnt output from the drain of the transistor 62 is input to the drain of the transistor 64, and the output current (drain current) having a magnitude proportional to the magnitude of the drain current (control current Ict) of the transistor 64 is the transistor 65. It is output as a control current Iaocct from the drain of. That is, when an input current (control current Ict) is input to the input transistor (transistor 64), an output current having a magnitude proportional to the magnitude of the input current (control current Ict) is output from the output transistor (transistor 65). To. The actual input current flows from the source of the transistor 64 toward the drain, and further flows into the drain of the transistor 62. With this configuration, the output current of the transistor 62 is equal to the input current of the transistor 64. Here, the current mirror ratio of the current mirror circuit composed of the transistors 64 and 65 is set to 1: α. That is, the control current Iacct is a current (α × Ict) having a magnitude obtained by amplifying the control current Ictt by α times. The control current Iaocct flows from the drain of the transistor 65 toward the output terminal 51b.

Transistors 66 and 67 form a current mirror circuit. The transistor 66 functions as an input transistor of the current mirror circuit, and the transistor 67 functions as an output transistor of the current mirror circuit. The sources of the transistors 66 and 67 are electrically connected to the power supply terminal 51d via the power supply wiring. The gate and drain of the transistor 66 are electrically connected to each other, and further electrically connected to the current source 70. The gate of transistor 67 is electrically connected to the gate and drain of transistor 66. The drain of the transistor 67 is electrically connected to the drain and the gate of the transistor 68 via the node N.

The reference current Iref supplied from the current source 70 is input to the drain of the transistor 66, and the output current (drain current) having a magnitude proportional to the magnitude of the drain current (reference current Iref) of the transistor 66 is the transistor 67. It is output from the drain as offset current Ifs. Here, the current mirror ratio of the current mirror circuit composed of the transistors 66 and 67 is set to 1: m. That is, the offset current Ifs is a current (m × Iref) of a magnitude obtained by amplifying the reference current Iref m times. That is, when the input current (reference current Iref) is input to the input transistor 66, the output transistor 67 outputs the output current (reference current m × Iref amplified m times). The offset current Ifs flows from the drain of the transistor 67 toward the node N. The value of m is, for example, a real number larger than 1, and is arbitrarily selected according to the optical power at which the AGC is desired to operate. Since the current value of the reference current Iref is a fixed value, the current value (offset current value) of the offset current Ifs is also a fixed value.

Transistors 68 and 69 form a current mirror circuit. The transistor 68 functions as an input transistor of the current mirror circuit, and the transistor 69 functions as an output transistor of the current mirror circuit. The sources of the transistors 68 and 69 are electrically connected to the power supply terminal 51d via the power supply wiring. The gate and drain of the transistor 68 are electrically connected to each other, and are further electrically connected to the drain of the transistor 63 and the drain of the transistor 67 via the node N. The gate of transistor 69 is electrically connected to the gate and drain of transistor 68. The drain of the transistor 69 is electrically connected to the output terminal 51c.

The control current Icnt output from the drain of the transistor 63 is combined with the offset current Ifs output from the drain of the transistor 67 at the node N. Specifically, the offset current Ifs is subtracted (subtracted) from the control current Icnt. At this time, only when the current value of the control current Icnt is larger than the current value of the offset current Ifs, the difference current (Icnt-Iofs) flows to the drain of the transistor 68, and the magnitude of the drain current (difference current) of the transistor 68 An output current (drain current) having a magnitude proportional to the above is output from the drain of the transistor 69 as a control current Igccunt. Here, the current mirror ratio of the current mirror circuit composed of the transistors 68 and 69 is set to 1: γ. That is, the control current Igccnt is a current (γ × (Icnt-Ifs)) having a magnitude obtained by amplifying the difference current (Icnt-Ioffs) by γ times. That is, when an input current (difference current (Icnt-Iofs)) is input to the input transistor 68, the output transistor 69 outputs an output current (difference current γ × (Icnt-Iofs) amplified γ times). The control current Iagcctnt flows from the drain of the transistor 69 toward the output terminal 51c.

On the other hand, when the current value of the control current Icnt is smaller than the current value of the offset current Ifs, no current flows through the transistor 68. Therefore, the potential of the node N is set to the power supply voltage VCS side by the diode-connected transistor 68. It is pulled up with high resistance. Further, since the voltage between the drain and the source of the transistor 67 becomes small, the transistors 66 and 67 do not operate as a current mirror circuit. At this time, since the transistor 67 operates in the triode region (linear region), the potential of the node N is pulled up to the power supply voltage VCS side with a low resistance. The triode region is a state in which, for example, the voltage value obtained by subtracting the threshold voltage from the gate-source voltage of the transistor is larger than the drain-source voltage.

Since no gate-source voltage is applied to the transistor 68, the resistance value of the transistor 67 to which the gate-source voltage is applied is smaller than the resistance value of the transistor 68. As described above, when the transistor 67 operates in the triode region, the transistor 67 cannot supply the offset current Ifs, and at the same time, all the control current Icnt from the transistor 63 flows through the transistor 67. As a result, the control current Igccnt is output from the output terminal 51c only when the current value of the control current Ict is larger than the current value of the offset current Ifs (in the region of Ict-Ioffs> 0). For example, when the current value of the control current Icnt is smaller than the offset current Ifs, the gate-source voltage of the transistor 69, which is a MOSFET, becomes approximately 0V, and the drain current (output current) of the transistor 69 becomes 0.

The input / output characteristics of FIG. 8 can be obtained by the control circuit 51 shown in FIG. 9, but the above-mentioned current mirror ratio can be changed as appropriate. Further, as the circuit configuration of the control circuit 51, another circuit configuration capable of obtaining the input / output characteristics of FIG. 8 may be adopted.

The feedback current source 52 is a current source for forming an automatic offset control (AOC) circuit. The feedback current source 52 is a circuit that generates a DC bypass current Iaoc according to the control current Ict. More specifically, the feedback current source 52 generates a DC bypass current Iaoc according to the control current Iaocct. The feedback current source 52 has, for example, an input terminal 52a, an output terminal 52b, and a ground terminal 52c. The input terminal 52a is electrically connected to the output terminal 51b of the control circuit 51, and receives the control current Iaocct from the control circuit 51. The output terminal 52b is electrically connected to the input terminal 10a and outputs a DC bypass current Iaoc (specifically, it is drawn into the feedback current source 52). The ground terminal 52c is electrically connected to the ground potential GND. The feedback current source 52 includes a field effect transistor 54 (first field effect transistor) and a field effect transistor 55 (second field effect transistor).

Each of the field effect transistors 54 and 55 is, for example, an N-channel MOS transistor. The size of the field effect transistor 54 and the size of the field effect transistor 55 may be the same or different from each other. The sources (first source, second source) of the field effect transistors 54 and 55 are electrically connected to each other and electrically connected to the ground potential GND via the ground terminal 52c. The drain (first drain) of the field effect transistor 54 is electrically connected to the output terminal 51b of the control circuit 51 via the input terminal 52a, and receives the control current Iaoctnt from the control circuit 51. The gate (first gate) of the field-effect transistor 54 is electrically connected to the drain of the field-effect transistor 54. The drain (second drain) of the field effect transistor 55 is electrically connected to the input terminal 10a via the output terminal 52b. The gate (second gate) of the field-effect transistor 55 is electrically connected to the drain and gate of the field-effect transistor 54.

In the feedback current source 52 configured in this way, the control current Iaocct that flows from the input terminal 52a flows through the field effect transistor 54 that is connected to the diode, so that the gate between the gate and the source of the field effect transistor 54 is gated. -Generate a source-to-source voltage Vgs1. Since the gate of the field effect transistor 54 and the gate of the field effect transistor 55 are electrically connected to each other, and the source of the field effect transistor 54 and the source of the field effect transistor 55 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 55 becomes equal to the gate-source voltage Vgs1. Since the source of the field effect transistor 55 is electrically connected to the ground potential GND, the source potential is approximately 0 V. On the other hand, the input potential of the TIA unit 11 (for example, about 0.5 to 2 V) is applied to the drain of the field effect transistor 55. Therefore, the field effect transistor 55 operates in the saturation region of the drain current-voltage characteristic. The saturation region is a state in which the voltage value obtained by subtracting the threshold voltage from the gate-source voltage of the transistor is smaller than the drain-source voltage. In the saturation region, even if the drain voltage of the field effect transistor 55 increases, the degree to which the drain current increases is smaller than that in the linear region. Therefore, the impedance (output impedance) of the output terminal 52b is a relatively large value. For example, by setting the impedance value of the output terminal 52b to be larger than the value of the input impedance of the TIA unit 11, it is possible to suppress the AC component of the optical current Ipd from flowing into the feedback current source 52 while drawing it into the DC bypass current Iaoc. Can be done.

That is, the field effect transistors 54 and 55 form a current mirror circuit, the control current Iaocct becomes the input current, and the DC bypass current Iaoc proportional to the control current Iaocctto is output as the output current. In other words, the feedback current source 52 causes the DC bypass current Iaoc to flow from the drain of the field effect transistor 55 to the source of the field effect transistor 55 according to the control current Iaocct. As a result, the DC bypass current Iaoc is extracted from the photocurrent Ipd. As a result, the DC component and the low frequency component are removed from the difference ΔVtia, and the potential (average potential) of the voltage signal Vtia is adjusted to the potential of the reference voltage signal Vref (DC offset control). As a result, for example, the difference between the time average value of the voltage of the positive phase component Vout and the time average value of the voltage of the negative phase component Voutb is reduced.

The variable resistance circuit 53 is a circuit that generates an AC bypass current Iagc according to the control current Ict. More specifically, the variable resistance circuit 53 generates an AC bypass current Iagc according to the control current Iagccnt. The variable resistance circuit 53 has, for example, a control terminal 53a, a resistance terminal 53b, and a resistance terminal 53c. The control terminal 53a is electrically connected to the output terminal 51c of the control circuit 51, and receives the control current Iagcctnt from the control circuit 51. The resistance terminal 53b is electrically connected to the input terminal 10a. The resistance terminal 53c is electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a), and receives the reference voltage signal Vref from the reference voltage generation circuit 12. The variable resistance circuit 53 includes a field effect transistor 56 (third field effect transistor) and a field effect transistor 57 (fourth field effect transistor).

Each of the field effect transistors 56 and 57 is, for example, an N-channel MOS transistor. The size of the field effect transistor 56 and the size of the field effect transistor 57 may be the same or different from each other. The sources (third source and fourth source) of the field effect transistors 56 and 57 are electrically connected to each other and are electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a) via the resistance terminal 53c. Is connected. A reference voltage signal Vref is input (supplied) to the sources of the field effect transistors 56 and 57. The drain (third drain) of the field effect transistor 56 is electrically connected to the output terminal 51c of the control circuit 51 via the control terminal 53a, and receives the control current Iagcctnt from the control circuit 51. The gate (third gate) of the field effect transistor 56 is electrically connected to the drain of the field effect transistor 56. The drain (fourth drain) of the field effect transistor 57 is electrically connected to the input terminal 10a via the resistance terminal 53b. The gate (fourth gate) of the field-effect transistor 57 is electrically connected to the drain and gate of the field-effect transistor 56.

In the variable resistance circuit 53 configured in this way, the control current Igcctt flowing from the control terminal 53a flows through the field effect transistor 56 connected to the diode, thereby gate between the gate and the source of the field effect transistor 56. -Generate the source voltage Vgs2. Since the gate of the field-effect transistor 56 and the gate of the field-effect transistor 57 are electrically connected to each other, and the source of the field-effect transistor 56 and the source of the field-effect transistor 57 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 57 becomes equal to the gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of the field-effect transistor 57, and the input potential of the TIA unit 11 is applied to the drain of the field-effect transistor 57. Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA unit 11, the field effect transistor 57 operates in a deep triode region (linear region). The deep triode region is a state in which the voltage value obtained by subtracting the threshold voltage from the gate-source voltage of the transistor is much larger than the drain-source voltage. As the drain voltage of the field effect transistor 57 increases in the linear region, the drain current also increases accordingly. Especially when the drain voltage is relatively small, the drain current can be regarded as changing (linear) in proportion to the drain voltage. The ratio of the drain voltage to the drain current of the field effect transistor 57 is expressed _{as the resistance value RAGC.}

The resistance value R _AGC of the field effect transistor 57 is represented by the equation (2) using the intrinsic gain β of the field effect transistor 57 and the threshold voltage Vth. The intrinsic gain β is determined by the process and size of the field effect transistor 57. As shown in equation (2), as the gate-source voltage Vgs2 increases, the resistance value _{R AGC} decreases.

That is, although the variable resistance circuit 53 has the same circuit configuration as the feedback current source 52, it does not operate as a current mirror circuit, and the field effect transistor 57 is controlled by the gate-source voltage Vgs2. Operates as a variable resistor. That is, the field effect transistor 57 is AC grounded by the reference voltage generation circuit 12, and the field effect transistor 57 is biased in the deep triode region. Since the potential of the resistance terminal 53b and the potential of the resistance terminal 53c are substantially the same, the DC component of the photocurrent Ipd hardly flows into the variable resistance circuit 53, and a part of the AC component of the photocurrent Ipd is the variable resistance circuit 53 ( It flows into the field effect transistor 57) as an AC bypass current Iagc. In other words, the variable resistance circuit 53 causes an AC bypass current Iagc to flow between the drain and the source of the field effect transistor 57 according to the control current Iagccnt. Since the AC bypass current Iagc is an AC component, the AC bypass current Iagc may flow from the source of the field effect transistor 57 to the drain or from the drain of the field effect transistor 57 to the source depending on the photocurrent Ipd. There is also. _{The AC bypass current AGC} is also determined depending on the magnitude of the resistance value RAGC of the field effect transistor 57 with respect to the magnitude of the input impedance of the TIA unit 11. AC bypass current Iagc and smaller than the input impedance of the resistance value _{R AGC} the TIA 11 of the field effect transistor 57 is increased. At this time, by suppressing the drain-source voltage Vds of the field effect transistor 57 to be small, it is possible to suppress the DC component of the Ipd of the photocurrent from flowing into the variable resistance circuit 53.

That is, when the optical current Ipd becomes large, the difference ΔVtia becomes large, and the control current Icnt exceeds the current value of the offset current Ifs, the control current Igccnt is supplied to the variable resistance circuit 53. As a result, the gate-source voltage Vgs2 is generated in the field effect transistors 56 and 57. As the gate-source voltage Vgs2 increases, the resistance value R _AGC of the field effect transistor 57 is decreased, the photocurrent part of the signal component excluding the DC component of the photocurrent Ipd (AC component) of the AC bypass current Iagc It is pulled out from the Ipd. As a result, the possibility that the TIA unit 11 is saturated by the large signal input is reduced. More specifically, when the gain (transimpedance) of the TIA unit 11 is set to a substantially constant value, the optical current Ipd becomes large, and when the amplitude of the current signal Iin becomes larger than a predetermined value, the voltage signal Vtia The amplitude is saturated. Therefore, gain control is performed so as to suppress saturation of the amplitude of the voltage signal Vtia by pulling out the AC bypass current Iagc from the photocurrent Ipd. When a burst optical signal is input as an optical signal Pin, the intensity of the optical signal Pin changes significantly before and after the no-signal interval. Therefore, the magnitude of the voltage signal Vtia (actually, the voltage signal Vtia and the reference) are determined by the AGC. The magnitude of the AC bypass current Iagc is automatically adjusted according to the magnitude of the difference ΔVtia from the voltage signal Vref). The AGC adjusts the magnitude of the signal component (AC component) of the current signal Iin, but it is preferable that the control of the DC component and the DC component of the current signal Iin (DC offset control) is not affected at that time.

As described above, a current proportional to the voltage between the drain and the source flows between the drain and the source of the field effect transistor 57 biased in the deep triode region (linear region). Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA unit 11, no DC current flows, and the AC bypass current Iagc does not disturb the DC offset control. _{The change in the resistance value RAGC} of the field effect transistor 57 does not affect the AOC control, and may affect only the gain control.

Next, the frequency characteristics of the control loop in the transimpedance amplifier circuit 10A will be described. The approximate expression of the transmission function of the control loop in the transimpedance amplifier circuit 10A is the open loop gain A _TIA of the voltage amplifier 11a of the TIA section 11, the input impedance R _IN of the TIA section 11, the gain F (s) of the entire feedback circuit, and It is represented by the equation (3) using _{the resistance value RAGC} of the field effect transistor 57. The gain F (s) is the product of the voltage gain of the integrating circuit 41A, the transconductance of the OTA 42A, the gain of the control circuit 51, and the gain of the feedback current source 52 (field effect transistor 55). The gain F (s) has frequency dependence as an integrating circuit 41A at low frequencies. The open-loop gain _ATIA and the input impedance R _IN are constant (fixed value) at low frequencies regardless of the frequency.

Since the resistance value R _AGC is controlled by the same control loop, the frequency characteristic of the control loop does not strictly satisfy the equation (3). Since the drain-source voltage of the field-effect transistor 57 is set to be approximately 0 V, the transconductance of the field-effect transistor 57 biased in the deep triode region is the same as that of the field-effect transistor 55. It is small enough to be ignored in comparison. Therefore, since there is almost no control gain in the field effect transistor 57, the influence of the control gain of the field effect transistor 57 on the control is extremely small. On the other hand, the resistance value R _AGC of the field effect transistor 57 is controlled by the gate-source voltage Vgs2 _{and forms a parallel resistance circuit with the input impedance R IN} . Therefore, with respect to the optical current Ipd and the DC bypass current Iaoc. Can have a great impact. As a result, a simplified equation (3) is obtained.

As described above, the OTA 42A can flow in the direction in which the control current Ict is drawn in or in the direction in which it is discharged, depending on the polarity of the difference ΔVin. As shown in FIG. 6, the transconductance of OTA42A becomes constant when the difference ΔVin is in the vicinity of 0V. On the other hand, since the control circuit 51 and the feedback current source 52 copy the current using the current mirror circuit, the output of the control circuit 51 and the feedback current source 52 is generated by the diode-connected MOS transistor constituting the current mirror circuit. The current is rectified in one direction. Due to this rectifying action, the transconductance decreases in the region where the output current is very small, but in the other regions, the current is accurately copied by the size ratio of the transistor. Therefore, in the control circuit 51 and the feedback current source 52, the transconductance is constant with respect to the input current except in the region where the output current is very small.

If the DC bypass current Iaoc is configured to be generated by controlling the gate potential of the source grounded amplifier instead of the current mirror circuit, the transconductance changes in proportion to the square root of the drain current. Since the DC bypass current Iaoc requires a dynamic range (1 μA to 1 mA) of at least about 60 dB, the change in transconductance is 30 dB. As a result, the one-round transfer function (also referred to as "one-round transfer gain") changes significantly with respect to the feedback current. Further, in the configuration in which the AC component is extracted from the optical current Ipd by controlling the voltage of the cathode of the diode, the resistance component of the diode changes non-linearly with respect to the control voltage, so that the input level dependence of the one-round transmission gain of the control loop becomes growing.

On the other hand, in the transimpedance amplifier circuit 10A, when the optical current Ipd is small and only the AOC is operating, the OTA42A operates linearly, so that the one-round transfer function except for the region where the DC bypass current Iaoc is very small. Is constant regardless of the DC bypass current Iaoc. The transconductance of the OTA42A is designed to increase when the control current Ict exceeds the current value of the offset current Ifs as the photocurrent Ipd increases. When the control current Icnt exceeds the current value of the offset current Iofs, AGC operates, the resistance value _{R AGC} of the field effect transistor 57 is decreased, the transconductance of OTA42A increases. As a result, the decrease in the one-round transmission gain (that is, the increase in the control time constant) is suppressed.

As described above, since the one-round transmission gain of the control loop is controlled to be substantially constant except for the region where the photocurrent Ipd is very small, the time constant of the control loop is substantially constant regardless of the photocurrent Ipd. The above operation is suitable when it is necessary to immediately control the DC offset and gain, such as when a burst optical signal is input to the optical receiver 1A as an optical signal Pin.

Next, the operation and effect of the transimpedance amplifier circuit 10A will be described. FIG. 10 is a diagram showing DC offset characteristics and gain characteristics in the transimpedance amplifier circuit shown in FIG. The horizontal axis of FIG. 10 indicates the optical input level (unit: dBm) of the optical signal Pin. The vertical axis of FIG. 10 shows the DC offset amount (unit: μV) and the transimpedance gain Zt (unit: dBohm). The broken line shown in FIG. 10 indicates the DC offset characteristic. The DC offset characteristic indicates the dependence of the DC offset amount on the optical input level of the optical signal Pin. The solid line in FIG. 10 shows the gain characteristics. The gain characteristic shows the dependence of the transimpedance gain Zt of the transimpedance amplifier circuit 10A on the optical input level of the optical signal Pin.

As described above, when the current is drawn from the optical current Ipd, the DC component (DC bypass current Iaoc) and the AC component (AC bypass current Iagc) can be separated and controlled. Therefore, it is not necessary to extract the AC component from the photocurrent Ipd in the small signal of −30 dBm to −15 dBm. Therefore, in the small signal, only the DC offset is controlled by extracting only the DC bypass current Iaoc from the photocurrent Ipd.

When the signal light input level exceeds -15 dBm, the control current Iagccnt begins to flow into the variable resistor circuit 53, the resistance value _{R AGC} of the field effect transistor 57 becomes small. As a result, the AC bypass current Iagc is extracted from the optical current Ipd, and the transimpedance gain Zt of the transimpedance amplifier circuit 10A begins to decrease. As the transimpedance gain Zt decreases, the one-round transmission gain of the control loop decreases, so that the amount of suppression of the DC offset decreases slightly. However, since this suppression amount is large enough to be expressed in μV units, the fluctuation amount of the DC offset is negligibly small with respect to the signal amplitude. Therefore, in a wide range of optical input levels, distortion due to saturation of the transimpedance amplifier circuit 10A is suppressed, and stable reception characteristics can be obtained.

Further, in the transimpedance amplifier circuit 10A, DC offset control and gain control can be realized by a single control loop (single integrator circuit 41A and single control circuit 51), so that the circuit scale is large. It becomes possible to suppress the occurrence. Further, by adjusting the response of the control circuit 51 (amplification rate α, amplification factor γ, current value of offset current Ifs, etc.), arbitrary control with respect to the optical input level becomes possible.

In the transimpedance amplifier circuit 10A, the control gain that decreases with AGC is compensated by the OTA42A. As a result, fluctuations in the control time constant due to the magnitude of the photocurrent Ipd can be reduced. This operation is particularly suitable when a burst optical signal is input as an optical signal Pin.

FIG. 11A is a diagram showing a circular transfer function of the control loop in the transimpedance amplifier circuit shown in FIG. FIG. 11B is a diagram showing a closed loop frequency characteristic in the transimpedance amplifier circuit shown in FIG. FIG. 12A is a diagram showing a round-trip transfer function of the control loop in the transimpedance amplifier circuit of the comparative example. FIG. 12B is a diagram showing a closed loop frequency characteristic in the transimpedance amplifier circuit of the comparative example. The transimpedance amplifier circuit of the comparative example is mainly different from the transimpedance amplifier circuit 10A in that it includes an OTA that operates linearly instead of the OTA42A. That is, the transimpedance amplifier circuit of the comparative example has a configuration in which the transconductance gm2 of the transconductance circuit 22 of the OTA 42A is set to 0. The horizontal axis of FIG. 11A, FIG. 11B, FIG. 12A, and FIG. 12B indicates the frequency (unit: Hz) of the photocurrent Ipd. The vertical axis of FIG. 11A and FIG. 12A shows the one-round transmission gain (unit: dB). The vertical axis of FIG. 11B and FIG. 12B shows the transimpedance gain (unit: dB).

As shown in FIG. 11A, in the transimpedance amplifier circuit 10A, the one-round transmission gain becomes 0 except when the optical input level of the optical signal Pin is weak (when the optical input level is -10 dBm or more). The frequency is almost constant. As a result, as shown in FIG. 11B, the closed-loop transfer function (transimpedance gain) decreases as the variable resistance circuit 53 operates due to the increase in the optical current Ipd, but the low frequency cutoff The frequency does not change. As shown in FIG. 12A, in the transimpedance amplifier circuit of the comparative example, the frequency at which the one-circle transfer gain becomes 0 depends on the optical input level of the optical signal Pin. As a result, as shown in FIG. 12B, the closed-loop transfer function (transimpedance gain) decreases as the photocurrent Ipd increases, and the low-frequency cutoff frequency also decreases (the time constant becomes longer). ).

FIG. 13 is a diagram showing changes in the transimpedance gain and changes in the low cutoff frequency with respect to the optical input level. FIG. 14 is a diagram showing a change in the control time constant with respect to the optical input level. The horizontal axis of FIGS. 13 and 14 indicates the optical input level (unit: dBm) of the optical signal Pin. The vertical axis of FIG. 13 indicates the low frequency cutoff frequency (unit: MHz) and the transimpedance gain Zt (unit: dBohm). The vertical axis of FIG. 14 shows the control time constant (unit: nsec). The solid line in FIG. 13 shows the low cutoff frequency of the transimpedance amplifier circuit 10A (non-linear OTA). The broken line in FIG. 13 shows the low cutoff frequency of the transimpedance amplifier circuit (linear OTA) of the comparative example. The alternate long and short dash line in FIG. 13 shows the transimpedance gain of the transimpedance amplifier circuit 10A (non-linear OTA). The solid line in FIG. 14 shows the control time constant of the transimpedance amplifier circuit 10A (non-linear OTA). The broken line in FIG. 14 shows the control time constant of the transimpedance amplifier circuit (linear OTA) of the comparative example. The control characteristics of the transimpedance gain of the comparative example with respect to the optical input level are the same as those of the transimpedance amplifier circuit 10A (non-linear OTA), and are not shown.

As shown in FIG. 13, in the transimpedance amplifier circuit of the comparative example, the transimpedance gain Zt decreases and the low cutoff frequency also decreases as the optical input level of the optical signal Pin increases. Specifically, the low-frequency cutoff frequency is also reduced to about 2/5 from the peak value in response to the decrease in transimpedance gain Zt from the peak value (about 58 dBOhm) to 8 dBohm (2/5). On the other hand, in the transimpedance amplifier circuit 10A, even when the transimpedance gain Zt decreases as the optical input level of the optical signal Pin increases, the decrease in the low cutoff frequency is suppressed.

As shown in FIG. 14, in the transimpedance amplifier circuit of the comparative example, the control time constant increases (becomes slower) as the optical input level of the optical signal Pin increases. On the other hand, in the transimpedance amplifier circuit 10A, the increase in the control time constant is suppressed even when the optical input level of the optical signal Pin increases. That is, it is suppressed that the control time constant depends on the optical input level of the optical signal Pin, and the fluctuation of the control time constant is suppressed in a wide range of optical input levels. This operation is suitable for receiving a burst optical signal.

FIG. 15 is a diagram showing the response of each node in the optical receiver shown in FIG. Here, the response when the optical receiving device 1A receives the burst optical signal as the optical signal Pin is shown. When the burst optical signal starts when the time t is 100 nsec, the optical signal Pin increases from no input state to -5 dBm, and when the burst optical signal ends when the time t is 2 μsec, the optical signal Pin increases from -5 dBm to-. It is assumed that it has dropped to 26 dBm. As shown in FIG. 15, since the control time constant is substantially constant except for small signals, the DC component and the AC component are extracted from the photocurrent Ipd in response to the change in the burst optical signal, and several hundred nsec. Converges to a stable state. At the input of the signal processing circuit 20, the DC offset is removed approximately 400 nsec from the start and end of the burst optical signal. This operation is suitable for receiving a burst optical signal.

As described above, in the transimpedance amplification circuit 10A, the DC bypass current Iaoc is generated by the feedback current source 52, the AC bypass current Iagc is generated by the variable resistance circuit 53, and the optical current Ipd generated by the light receiving element PD is used. , DC bypass current Iaoc and AC bypass current Iag are pulled out to generate a current signal Iin. Then, the current signal Iin is converted into the voltage signal Vtia by the TIA unit 11, and the differential voltage signals Vout and Voutb are generated by the differential amplification circuit 13A according to the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref.

Since the control current Ict is generated based on the integrated value of the difference ΔVtia and the feedback current source 52 is controlled so that the DC bypass current Iaoc increases as the control current Ict increases, the DC component of the optical current Ipd is DC bypassed. It is extracted from the photocurrent Ipd as the current Iaoc, and the DC component is removed from the photocurrent Ipd. On the other hand, the variable resistance circuit 53 is controlled so that the AC bypass current Iagc increases as the control current Ict increases when the control current Icnt exceeds the current value of the offset current Ifs. Therefore, when the photocurrent Ipd is relatively small, the DC component of the photocurrent Ipd is extracted as the DC bypass current Iaoc, but the extraction of the AC bypass current Iagc is suppressed, so that the DC component of the photocurrent Ipd is removed. It is possible to prevent the AC component of the photocurrent Ipd from being attenuated. When the photocurrent Ipd is relatively large, the DC component of the photocurrent Ipd is extracted as the DC bypass current Iaoc, and the AC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the AC bypass current Igp. The AC component of the photocurrent Ipd can be attenuated while removing the DC component of. Since the feedback current source 52 and the variable resistance circuit 53 are both controlled by one control circuit 51, it is possible to control the removal of DC components (DC offset control) and gain control in a single control loop. It becomes. As a result, DC offset control and gain control can be performed while suppressing the circuit scale.

Further, a voltage signal Vinp and a voltage signal Vinn are generated by integrating the difference ΔVtia, and when the difference ΔVin obtained by subtracting the voltage signal Vinn from the voltage signal Vinp is smaller than the threshold Vth1, the voltage signal Vinp is performed by transconductance (gm1-gm2). And the control current Icnt is generated according to the voltage signal Vinn, and when the difference ΔVin is larger than the threshold Vth2, the transconductance gm1 generates the control current Ict according to the voltage signal Vinp and the voltage signal Vinn. Until the control current Icnt exceeds the current value of the offset current Iofs, since withdrawal of the AC bypass current Iagc is not performed, the resistance value _{R AGC} of the variable resistance circuit 53 (field-effect transistor 57) does not change. On the other hand, when the control current Icnt exceeds the current value of the offset current Ifs, the variable resistance circuit 53 is controlled so that the AC bypass current Igc increases as the control current Ict increases, so that the variable resistance circuit 53 (field effect). _{The resistance value RAGC} of the transistor 57) becomes smaller. In the control current generation circuit 14A, when the difference ΔVin becomes larger than the threshold value Vth1, the transconductance larger than the transconductance (gm1-gm2) is used. Thus, the decrease in the open-loop transfer gain due to a decrease in the resistance value R _AGC, can be compensated by increasing the transconductance of the control current generating circuit 14A. As a result, it is possible to suppress an increase in the control time constant of the feedback control. As a result, it is possible to suppress fluctuations in the control time constant due to changes in the signal strength of the burst optical signal.

The transconductance circuit 21 operates so that the output current Iout1 decreases as the difference ΔVin increases in the range VR1 of the difference ΔVin, and the transconductance circuit 22 outputs as the difference ΔVin increases in the range VR2 of the difference ΔVin. It operates so that the current Iout2 becomes large. The control current Icnt is generated by adding the output current Iout1 and the output current Iout2. Since the upper limit value of the range VR2 is smaller than the upper limit value of the range VR1, when the difference ΔVin is a positive value, the input / output characteristic of the OTA 42A that the transconductance increases as the difference ΔVin increases can be realized. it can. Therefore, it is possible to simplify the generation of the control current Icnt.

Ideally, the potential of the voltage signal Vtia and the potential of the reference voltage signal Vref match in the absence of the optical signal Pin. However, the potential and reference of the voltage signal Vtia in the absence of the optical signal Pin due to the variation in the characteristics of the TIA unit 11, the variation in the characteristics between the TIA unit 11 and the reference voltage generation circuit 12, external noise, and the like. The potentials of the voltage signals Vref may differ from each other. Therefore, in the absence of the optical signal Pin, the potential of the voltage signal Vtia may be larger than the potential of the reference voltage signal Vref. Since the increase / decrease of the voltage signal Vtia is inverted with respect to the increase / decrease of the current signal Iin, the state where the potential of the voltage signal Vtia is larger than the potential of the reference voltage signal Vref means the state where the current signal Iin is decreasing. To do. Since the feedback current source 52 causes the DC bypass current Iaoc to flow in the direction of drawing from the optical current Ipd, for example, when the voltage signal Vtia is larger than the reference voltage signal Vref, the difference ΔVtia cannot be brought close to 0. In this case, since the difference ΔVtia has a negative value, the difference ΔVin also has a negative value, resulting in open-loop control. As a result, the control time constant becomes slow because there is no control gain. Then, even if the optical signal Pin is input, the control loop cannot respond immediately because the control time constant is slow.

On the other hand, since the anode of the diode 48 is electrically connected to the output terminal 41c and the cathode of the diode 48 is electrically connected to the output terminal 41d, the difference ΔVtia has a negative value when the difference ΔVtia has a negative value. The absolute value of can be prevented from being greater than the on-voltage of the diode 48. As a result, the recovery time from open-loop control to closed-loop control can be shortened. Therefore, even when the optical signal Pin is input in a burst, DC offset control and gain control can be performed immediately. That is, it is possible to shorten the response time when the burst optical signal is input.

In the feedback current source 52, since the field effect transistor 54 is diode-connected, when the drain of the field effect transistor 54 receives the control current Iaocct, the gate-source voltage Vgs1 between the gate and the source of the field effect transistor 54 Is generated. Since the gate of the field effect transistor 54 and the gate of the field effect transistor 55 are electrically connected to each other, and the source of the field effect transistor 54 and the source of the field effect transistor 55 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 55 becomes equal to the gate-source voltage Vgs1. Since the source of the field-effect transistor 55 is electrically connected to the source of the field-effect transistor 54, that is, the ground potential GND, and the drain of the field-effect transistor 55 is electrically connected to the input terminal 10a, the field-effect transistor 55 The potential difference between the source and drain becomes large. As a result, the field effect transistor 55 operates in the saturation region. Therefore, the field-effect transistor 55 functions as a current source, and the output impedance of the drain of the field-effect transistor 55 becomes large. Therefore, although the AC component of the photocurrent Ipd hardly flows into the field-effect transistor 55, the DC of the photocurrent Ipd The component can flow into the field effect transistor 55 as a DC bypass current Iaoc. Then, as the control current Icnt increases, the gate-source voltage Vgs1 of the field effect transistor 54 increases, so that the drain current of the field effect transistor 55 increases accordingly, and the DC component of the optical current Ipd increases the DC bypass current. It is extracted from the photocurrent Ipd as an Iaoc, and the DC component is appropriately removed from the photocurrent Ipd. The magnitude of the output impedance of the output terminal 52b may be determined in consideration of the input impedance of the TIA unit 11. For example, when the input impedance of the TIA unit 11 is Zin, the output impedance of the output terminal 52b may be set to 100 × Zin or more. Since the input impedance Zin and the output impedance of the output terminal 52b can have different frequency characteristics, it is sufficient that such a relationship is satisfied at least in a predetermined frequency range (band).

In the variable resistance circuit 53, since the field effect transistor 56 is diode-connected, when the drain of the field effect transistor 56 receives the control current Iagcctnt, the gate-source voltage Vgs2 between the gate and the source of the field effect transistor 56. Is generated. Since the gate of the field effect transistor 56 and the gate of the field effect transistor 57 are electrically connected to each other, and the source of the field effect transistor 56 and the source of the field effect transistor 57 are electrically connected to each other, the electric field is generated. The gate-source voltage of the effect transistor 57 becomes equal to the gate-source voltage Vgs2. Since the reference voltage signal Vref is supplied to the source of the field effect transistor 57 and the drain of the field effect transistor 57 is electrically connected to the input terminal 10a, there is almost no potential difference between the drain of the field effect transistor 57 and the source. As a result, the field effect transistor 57 operates in the (deep) triode region. Therefore, the field-effect transistor 57 functions as a variable resistor, and the output impedance of the drain of the field-effect transistor 57 becomes low. Since there is almost no potential difference between the drain and the source of the field effect transistor 57, the DC component of the photocurrent Ipd hardly flows into the field effect transistor 57, but the AC component of the photocurrent Ipd is the AC bypass current Iagc of the field effect transistor 57. Can flow into. When the control current Ict exceeds the current value of the offset current Ifs, the gate-source voltage Vgs2 of the field effect transistor 56 increases as the control current Ict increases. Therefore, when the optical current Ipd is relatively small, The withdrawal of the AC bypass current Iagc can be suppressed, and the AC component can be prevented from being attenuated. When the photocurrent Ipd is relatively large, the AC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the AC bypass current Igc, so that the AC component of the photocurrent Ipd can be attenuated. Therefore, the variable resistance circuit 53 controls the gain of the transimpedance amplifier circuit 10A.

The output impedance of the resistance terminal 53b may be determined in consideration of the input impedance Zin of the TIA unit 11. For example, when the gain variable ratio of the TIA unit 11 is A (A is a real number larger than 1), the output impedance of the resistance terminal 53b is set to Zin / (A-1). As a result, assuming that the value of the current signal Iin of the TIA unit 11 when AGC is not performed is Iinoff, the value of the current signal Iin when AGC is performed is Iinon = Iinoff / A. For example, when A = 2, the output impedance of the resistance terminal 53b is substantially equal to Zin, and when A is larger than 2, the output impedance of the resistance terminal 53b is smaller than Zin. Therefore, when AOC and AGC are performed at the same time, the output impedance of the output terminal 52b is set to be larger than the output impedance of the resistance terminal 53b. By the way, when AGC is not performed, the output impedance of the resistance terminal 53b may be set to 100 × Zin or more. The output impedance of the resistance terminal 53b can be considered to be equal to the _{above-mentioned resistance value RAGC.} For example, by making the gate voltage of the field effect transistor 57 substantially equal to the threshold voltage of the field effect transistor 57, the output impedance of the resistance terminal 53b becomes large. Since the input impedance Zin and the output impedance of the resistance terminal 53b may have different frequency characteristics, it is sufficient that the above relationship is satisfied at least in a predetermined frequency range (band).

The reference voltage generation circuit 12 includes a voltage amplifier 12a and a feedback resistor element 12b electrically connected between the input and output of the voltage amplifier 12a. In this configuration, the output impedance of the reference voltage generation circuit 12 becomes low in a wide frequency range. That is, the impedance of the variable resistance circuit 53 seen from the input terminal of the TIA unit 11 becomes low in a wide frequency range. Therefore, the AC bypass current Iagc can be easily extracted from the photocurrent Ipd.

Since the DC offset control is performed using the high impedance feedback current source 52, the influence of the photocurrent Ipd on the AC component is small (the AC component does not flow through the feedback current source 52). On the other hand, the gain control is performed by bypassing the AC component of the photocurrent Ipd using the variable resistance circuit 53, and since the drain potential and the source potential of the field effect transistor 57 are substantially equal, the DC component of the photocurrent Ipd is used. (No DC component flows through the variable resistance circuit 53). As a result, it is possible to avoid interference between the DC offset control and the gain control.

As described above, according to the transimpedance amplifier circuit 10A, the gain control of the transimpedance amplifier circuit 10A and the DC offset control for setting the difference ΔVtia to 0 are controlled by a single control loop without interfering with each other. Can be done.

The transimpedance amplifier circuit according to the present disclosure is not limited to the above embodiment.

The circuit configurations of the TIA unit 11, the reference voltage generation circuit 12, the differential amplifier circuit 13A, the control current generation circuit 14A, and the bypass circuit 15 are not limited to the configurations shown in the above embodiments. For example, the TIA unit 11 may be configured to convert the current signal Iin into the voltage signal Vtia. The reference voltage generation circuit 12 may be configured to be able to supply the reference voltage signal Vref. The differential amplifier circuit 13A does not have to include the output amplifier 13b.

The control current generation circuit 14A does not have to include the diode 48. Even in this case, it is possible to suppress fluctuations in the control time constant due to changes in the signal strength of the burst optical signal. The control current generation circuit 14A may include, instead of the diode 48, another circuit element that clamps the difference ΔVin so that the difference ΔVin does not fall below a predetermined negative value. The OTA 42A is not limited to the circuit configuration shown in FIGS. 4 and 7, and may be configured to be capable of generating the control current Icnt shown in FIG. The OTA42A may generate a control current Ict of 0 or more of the control current Ict shown in FIG.

Further, the control circuit 51 is not limited to the circuit configuration shown in FIG. 9, and may be configured so as to be able to generate the control current Iaocct and the control current Iagccnt shown in FIG. The feedback current source 52 may be configured to be able to generate a DC bypass current Iaoc so that the DC bypass current Iaoc increases as the control current Iaocct increases. The feedback current source 52 includes, for example, a resistance element provided so as to change the gate-source voltage of the field effect transistor 55 according to the control current Iaocct, instead of the diode-connected field effect transistor 54. May be good. The source of the field-effect transistor 55 does not have to be electrically connected to the ground potential GND, as long as the potential of the source of the field-effect transistor 55 is set so that the field-effect transistor 55 operates in the saturation region. Good. That is, the source potential of the field effect transistor 55 is set so that the drain potential of the field effect transistor 55 is larger than the source potential of the field effect transistor 55.

The variable resistance circuit 53 may be configured to be able to generate an AC bypass current Iagc so that the AC bypass current Iagc increases as the control current Iagccnt increases. The variable resistance circuit 53 may include a resistance element provided so as to change the gate-source voltage of the field effect transistor 57 according to the control current Igccnt, instead of the diode-connected field effect transistor 56. .. The source of the field-effect transistor 57 does not have to be electrically connected to the output terminal of the reference voltage generation circuit 12, and the source of the field-effect transistor 57 needs to operate in the triode region so that the field-effect transistor 57 operates in the triode region. It suffices if the potential is set. That is, the source potential of the field effect transistor 57 is set so that the drain potential of the field effect transistor 57 and the source potential of the field effect transistor 57 are substantially equal to each other.

Further, the transimpedance amplifier circuit 10A may not include the reference voltage generation circuit 12, and the transimpedance amplifier circuit 10A may supply the reference voltage signal Vref from an external reference voltage generation circuit.

In the above embodiment, the magnitude of the control current Iaocct (DC bypass current Iaoc) is adjusted by the amplification factor α, but instead, it may be adjusted by the current mirror ratio of the transistors 61 and 62, and the amplification factor α And may be adjusted by both the current mirror ratios of the transistors 61 and 62. Similarly, the magnitude of the DC bypass current Iaoc may be adjusted by the current mirror ratio of the field effect transistors 54, 55.

In the above embodiment, the magnitude of the control current Igccnt (AC bypass current Igcc) is adjusted by the current values of the amplification factor γ and the offset current Ifs, but instead of the amplification factor γ, it is adjusted by the current mirror ratio of the transistors 61 and 63. It may be adjusted, or may be adjusted by the amplification factor γ, the current mirror ratio of the transistors 61 and 63, and the current value of the offset current Ifs. Similarly, the magnitude of the AC bypass current Iagc may be adjusted by the size of the field effect transistor 56, the size of the field effect transistor 57, and the like.

In the above embodiment, the field effect transistors 54 and 55 and the transistors 21a to 21d, 22a to 22d, 23a, 24a, 25a, 25b, 61 to 69 have been described using the field effect transistors. The 54, 55 and the transistors 21a to 21d, 22a to 22d, 23a, 24a, 25a, 25b, 61 to 69 may be bipolar transistors. When the field effect transistors 54, 55 and the transistors 21a to 21d, 22a to 22d, 23a, 24a, 25a, 25b, 61 to 69 are bipolar transistors, the gate, source, and drain of the field effect transistors are the base. , Emitter, and collector, respectively.

The bypass circuit 15 does not have to control the feedback current source 52 and the variable resistance circuit 53 with a single control loop.

Generally, the input impedance of the dummy TIA is about 10 to 100 Ω, which is the same as the input impedance of the TIA unit 11, and the output impedance of the dummy TIA is about several Ω. Since the input terminal and the output terminal of the dummy TIA both generate the reference voltage signal Vref having substantially the same potential, any terminal may be used as the output terminal of the reference voltage generation circuit 12. _{Since the output impedance of the dummy TIA is lower than the input impedance, the resistance value RAGC} can be increased by using the output terminal of the dummy TIA as the output terminal of the reference voltage generation circuit 12, and the field effect transistor 57 can be increased. It is possible to reduce the size.

1A ... Optical receiver 5a ... Capacitor 5b ... Capacitor 10A ... Transimpedance amplifier circuit 10a ... Input terminal 10b ... Output terminal 10c ... Output terminal 11 ... TIA section (single-ended amplifier circuit)
11a ... Voltage amplifier 11b ... Feedback resistance element 12 ... Reference voltage generation circuit 12a ... Voltage amplifier (amplifier)
12b ... Feedback resistance element 13A ... Differential amplification circuit 13a ... Differential amplifier 13b ... Output amplifier 14A ... Control current generation circuit 15 ... Bypass circuit 20 ... Signal processing circuit 21 ... Transconductance circuit (first transconductance circuit)
21a ... Transistor 21b ... Transistor 21c ... Transistor 21d ... Transistor 21e ... Resistance element 22 ... Transconductance circuit (second transconductance circuit)
22a ... Transistor 22b ... Transistor 22c ... Transistor 22d ... Transistor 22e ... Resistance element 23 ... Current source 23a ... Transistor 24 ... Bias circuit 24a ... Transistor 24b ... Current source 25 ... Synthesis circuit 25a ... Transistor 25b ... Transistor 41A ... Integration circuit 41a ... Input terminal 41b ... Input terminal 41c ... Output terminal (first output terminal)
41d ... Output terminal (second output terminal)
42A ... OTA (Transconductance Amplifier Circuit)
42a ... Input terminal 42b ... Input terminal 42c ... Output terminal 42d ... Power supply terminal 43 ... Operational amplifier 43a ... Non-inverting input terminal 43b ... Inverted input terminal 43c ... Inverted output terminal 43d ... Non-inverting output terminal 44 ... Resistance element 45 ... Resistance element 46 ... Condenser 47 ... Condenser 48 ... Diode 51 ... Control circuit 51a ... Input terminal 51b ... Output terminal 51c ... Output terminal 51d ... Power supply terminal 52 ... Feedback current source 52a ... Input terminal 52b ... Output terminal 52c ... Ground terminal 53 ... Variable resistance circuit 53a ... Control terminal 53b ... Resistance terminal 53c ... Resistance terminal 54 ... Field effect transistor (first field effect transistor)
55 ... Field effect transistor (second field effect transistor)
56 ... Field effect transistor (third field effect transistor)
57 ... Field effect transistor (fourth field effect transistor)
61-69 ... Transistor 70 ... Current source GND ... Ground potential Iaoc ... DC bypass current Iaocct ... Control current (first control current)
Iagc ... AC bypass current Iagccnt ... Control current (second control current)
Icnt ... Control current Id1 ... Drain current Id2 ... Drain current Id3 ... Drain current Id4 ... Drain current Iin ... Current signal Inwl ... Constant current Ifs ... Offset current Iout1 ... Output current (first output current)
Iout2 ... Output current (second output current)
Ipd ... Photocurrent (input current signal)
Ir ... Reference current Iref ... Reference current N ... Node Pin ... Optical signal PD ... Light receiving element Va1, Va1b ... Differential voltage signal Vc, Vbc ... Differential voltage signal VCS ... Power supply voltage Vgs1 ... Gate-source voltage Vgs2 ... Gate Source-to-source voltage Vinp, Vinn ... Differential integration signal Vinn ... Voltage signal (opposite phase component)
Vimp ... Voltage signal (positive phase component)
Vout, Voutb ... Differential voltage signal Vout ... Positive phase component Voutb ... Reverse phase component VPD ... Bias voltage VR1 ... Range (first range)
VR2 ... Range (second range)
Vref ... Reference voltage signal Vth1 ... Threshold Vth2 ... Threshold Vtia ... Voltage signal

Claims (6)

A transimpedance amplifier circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element in response to a burst light signal.
An input terminal that receives the input current signal and
A single-ended amplifier circuit that converts a current signal into a voltage signal,
A differential amplifier circuit that generates the differential voltage signal according to the difference between the voltage signal and the reference voltage signal.
A control current generation circuit that generates a control current based on the difference,
A bypass circuit that generates a DC bypass current and an AC bypass current according to the control current, and
With
The current signal is generated by extracting the DC bypass current and the AC bypass current from the input current signal.
The bypass circuit includes a control circuit to which the control current is input, a feedback current source that generates the DC bypass current according to the control current, and a variable resistance circuit that generates the AC bypass current according to the control current. And with
The control current generation circuit is an amplifier circuit that integrates the difference to generate a differential integrated signal, and when the value of the differential integrated signal is smaller than the threshold value, it responds to the differential integrated signal by the first transconductance. Transconductance amplification that generates the control current and generates the control current according to the differential integrated signal by a second transconductance that is larger than the first transconductance when the value of the differential integrated signal is larger than the threshold value. With a circuit,
The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and the control current increases when the control current exceeds a predetermined offset current value. A transimpedance amplification circuit that controls the variable resistance circuit so that the AC bypass current increases as the current increases. The transconductance amplification circuit includes a first transconductance circuit that generates a first output current based on the differential integrated signal, and a second transconductance circuit that generates a second output current based on the differential integrated signal. , And the control current is generated by adding the first output current and the second output current.
The first transconductance circuit operates so that the first output current decreases as the value of the differential integrated signal increases in the first range of the value of the differential integrated signal.
The second transconductance circuit operates so that the second output current increases as the value of the differential integrated signal increases in the second range of the value of the differential integrated signal.
The transimpedance amplifier circuit according to claim 1, wherein the upper limit value of the second range is smaller than the upper limit value of the first range, and the lower limit value of the second range is larger than the lower limit value of the first range. .. The integrator circuit includes a first output terminal that outputs a negative phase component of the differential integrated signal, a second output terminal that outputs a positive phase component of the differential integrated signal, a first output terminal, and the second output terminal. A diode provided between the output terminal and
The difference is a value obtained by subtracting the voltage signal from the reference voltage signal.
The anode of the diode is electrically connected to the first output terminal.
The transimpedance amplifier circuit according to claim 1 or 2, wherein the cathode of the diode is electrically connected to the second output terminal. The control circuit generates a first control current by amplifying the control current at a first amplification factor.
The feedback current source is
A first field effect transistor having a first drain that receives the first control current, a first gate that is electrically connected to the first drain, and a first source that is electrically connected to the ground potential. ,
A second drain electrically connected to the input terminal, a second gate electrically connected to the first drain and the first gate, and a second source electrically connected to the first source. And a second field effect transistor with
With
The transimpedance amplifier circuit according to any one of claims 1 to 3, wherein the feedback current source causes the DC bypass current to flow from the second drain to the second source according to the first control current. .. The control circuit generates an offset current set to the offset current value, and a second by amplifying the difference current between the generated current and the offset current by amplifying the control current at the second amplification factor. Generates control current,
The variable resistance circuit is
A third field effect transistor having a third drain that receives the second control current, a third gate that is electrically connected to the third drain, and a third source to which the reference voltage signal is supplied.
A fourth drain electrically connected to the input terminal, a fourth gate electrically connected to the third drain and the third gate, and a fourth source electrically connected to the third source. And a fourth field effect transistor with
With
The transimpedance amplifier circuit according to any one of claims 1 to 4, wherein the variable resistance circuit draws the AC bypass current from the input current signal in response to the second control current. A reference voltage generation circuit for generating the reference voltage signal is further provided.
The transimpedance amplifier circuit according to any one of claims 1 to 5, wherein the reference voltage generation circuit includes an amplifier and a feedback resistance element electrically connected between the input and output of the amplifier. ..