JP2020017263A - Memory system - Google Patents

Abstract

To provide a memory system capable of reduce energy consumption of the system and increase performance at the same time.SOLUTION: A memory system 10 includes processors 20, a fabric network 30, and pooled memories 100. The pooled memories include multiple memories 120 configured to store data, and a pooled memory controller 110 configured to perform map computation by reading data stored in the multiple memories and store resultant data from the map computation in the multiple memories.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a memory system, and more particularly, to a technique related to an accelerator of a large capacity memory device.

  Recently, mobile communication terminals such as smartphones and tablet PCs have become popular. In addition, the use of social network services (SNS, Social Network Service), networks of objects (machines) (M2M, Machine to Machine), and sensor networks (Sensor Network) is increasing. As a result, the amount of data, the generation speed, and the variety thereof are geometrically increased. For processing big data, the speed of the memory is also important, but a memory device and a memory module having a large storage capacity are required.

To this end, the memory system includes a plurality of integrated memories to increase the data storage capacity while overcoming the physical limitations of the memory. For example, a server structure (Server Architecture) of a cloud data center (Cloud Data Center) has been changed to a structure for efficiently executing a big data application (Big-Data Application).
In order to process big data efficiently, a pooled memory (Pooled Memory) in which a plurality of memories are integrated is used. The pool memory can provide a large capacity and a high bandwidth, and can be usefully used in an in-memory database (In-memory Database) or the like.

  Embodiments of the present invention provide a memory system that includes an accelerator inside a pool memory to reduce energy consumption of the system and at the same time improve performance.

  A memory system according to an embodiment of the present invention includes a plurality of memories that store data, a pool memory that reads data stored in the plurality of memories, performs a map operation, and stores result data of the map operation in the plurality of memories. And a controller.

  Also, a memory system according to another embodiment of the present invention relays a packet to and from a processor via a fabric network connected to a processor, and transmits data stored in a memory to the processor when requested by the processor. A pool memory, wherein the pool memory comprises a pool memory controller for reading data stored in the memory, off-loading the map operation, and storing the result of the map operation in the memory.

  Embodiments of the present invention provide the advantage of improving system performance and saving energy required for data operations.

1 is a diagram illustrating a concept of a memory system according to an embodiment of the present invention. 1 is a diagram illustrating a configuration of a memory system according to an embodiment of the present invention. 3 is a diagram illustrating a detailed configuration of a pool memory controller of FIG. 2. 5 is a diagram illustrating an operation of the memory system according to the embodiment of the present invention. 5 is a diagram illustrating an operation of the memory system according to the embodiment of the present invention. 5 is a diagram illustrating an operation of the memory system according to the embodiment of the present invention. 4 is a diagram illustrating performance improvement of the memory system according to the embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the embodiments of the present invention, when one part is “coupled” to another part, it means not only that the part is “directly connected” but also other elements in between. Also includes the case where they are electrically connected with each other. Also, when an element is referred to as "including" or "comprising" an element, that element does not exclude the other element, but does not exclude the other element, unless specifically stated to the contrary. Include or include. Further, in the description of the entire specification, it is understood that the present invention is not limited to the case where some components are described in singular form, and the components may be plural.

  Data center applications require more hardware resources as data sizes increase. The server architecture has evolved to use hardware resources more efficiently.

  As an example, in a cloud data center (Cloud Data Center), many machine learning (Machine Learning) applications including deep learning (Deep Learning) are executed. Applications such as deep learning and machine learning are mostly low in temporal locality, so that a central processing unit (CPU) is more likely to be a graphic processing unit (GPU) than a central processing unit (GPU). Generally, the calculation is performed via a hardware accelerator (Hardware Accelerator) such as an FPGA or a Field Programmable Gate Array (FPGA).

  Here, temporal locality means that the data approaches again within a relatively close time to the data once approached. That is, the application uses cold data that has not been accessed for a while than hot data that is frequently accessed.

  A process in which a processor (e.g., a central processing unit) off-loads a job to an accelerator (Accelerator) will be described as follows. First, data is transferred from the local memory of the processor (Local Memory) to the local memory of the accelerator. Thereafter, when the accelerator finishes the operation, the result data must be transferred to the processor again.

  If the cost of moving the data is higher than the cost of operating the data, implementing the architecture to move the data as little as possible can reduce the overall cost. To this end, recently, a Memory-Driven Computing Concept has been proposed.

FIG. 1 is a diagram illustrating a concept of a memory system according to an embodiment of the present invention.
The embodiment of FIG. 1 illustrates that the architecture is changed from a system-on-chip (SoC), i.e., a processor-centric computing structure to a memory-centric computing structure. In a processor-based computing structure, one system-on-a-chip is connected to one memory in a one-to-one manner.

  Memory-driven computing uses a unified memory in which a plurality of system-on-chips are connected via a fabric network. When data is exchanged between system-on-chips (SoCs), data is exchanged with a memory bandwidth.

  In addition, one integrated memory connected by the fabric network does not have to perform a memory copy as in the related art in order to exchange data. In order for the above-mentioned memory-driven computing to be commonly used, a high bandwidth (Bandwidth), a low latency (Latency), and a consistency (Low) of a memory semantic interconnect are required. Coherency) must be supported.

  In this regard, in the technical field to which the embodiments of the present invention pertain, research on the interconnection of a transaction-based memory system is actively underway.

  In connection with the accelerator, research on the position of the accelerator based on the characteristics of a workload such as near data processing (NDP) or processing in memory (PIM) has been widely performed. . Here, the processing-in-memory refers to a memory in which processor logic is closely coupled to a memory cell in order to increase a data processing speed and a data transfer speed.

  Embodiments of the present invention relate to a technology related to a pooled memory architecture in which a large number of memories are integrated and an in-memory database operation adapted to the pooled memory architecture. Hereinafter, features of the Map-Reduce Application according to the embodiment of the present invention will be described, and a process of processing a Map operation by an accelerator (described later) in a pooled memory (Pooled Memory) will be described. explain.

FIG. 2 is a diagram illustrating a configuration of a memory system according to an embodiment of the present invention.
The memory system 10 according to an embodiment of the present invention is based on the memory-driven computing structure described above. Such a memory system 10 includes a plurality of processors (for example, a central processing unit, a CPU) 20, a fabric network 30, a plurality of channels 40, and a plurality of pool memories 100.

  Here, the plurality of processors 20 are connected to the fabric network 30 via the node CND. The plurality of processors 20 are connected to the plurality of pool memories 100 via the fabric network 30. Further, the pool memory 100 is connected to the fabric network 30 via a plurality of channels 40. That is, each of the plurality of pool memories 100 may be connected to the fabric network 30 via the N channels 40.

  Each of the plurality of pool memories 100 includes a plurality of memories 120 and a pooled memory controller (PMC) 110 for controlling the plurality of memories 120 (or memory devices). The pool memory controller 110 is connected to each memory 120 via a bus (BUS).

  Each memory 120 may be directly connected to the fabric network 30. However, a plurality of memories 120 may be included in one integrated pool memory 100, and the pool memory 100 may be connected to the fabric network 30.

  When the pool memory 100 includes a plurality of memories 120, the pool memory controller 110 manages each memory 120 between the fabric network 30 and the plurality of memories 120.

  Here, the pool memory controller 110 performs memory interleaving in order to increase the processing rate (Throughput), or increases reliability (Reliability), availability (Availability), durability (Serviceability), and the like. Supports Address Remapping.

  An in-memory database is a database management system that stores a database (DB) in a main memory (Main Memory) that is not a storage (Storage) for quick access.

  Current server systems have a physical limitation in increasing the capacity of a memory. As a result, the application cannot increase the size of the database beyond the memory capacity of each server. As the size of the database increases, the database is inevitably divided into a plurality of servers and the database is stored, and there is a part where the performance is reduced in the process of combining the plurality of servers. The pool memory 100 can be advantageously used in an in-memory database to provide a large capacity and a high bandwidth.

FIG. 3 is a diagram illustrating a detailed configuration of the pool memory controller 110 of FIG.
The pool memory controller 110 includes an interface 111 and an accelerator 112. Here, the interface 111 relays a packet between the fabric network 30 and the accelerator 112 and the memory 120. The interface 111 is connected to the accelerator 112 via a plurality of channels CN.

  In an embodiment of the present invention, the interface 111 may include a switch for relaying a packet between the fabric network 30 and the accelerator 112 and the memory 120. In the embodiment of the present invention, an example has been described in which the interface 111 includes a switch, but the means for relaying a packet is not limited to this.

  Then, the accelerator 112 performs an arithmetic process on data applied via the interface 111. For example, the accelerator 112 performs a map operation on the data applied from the memory 120 via the interface 111, and stores data corresponding to the map operation result in the memory 120 via the interface 111.

  In the embodiment of the present invention, an example in which the pool memory controller 110 includes one accelerator 112 will be described. However, embodiments of the present invention are not limited thereto, and the pool memory controller 110 may include a plurality of accelerators 112.

  The Map-Reduce application is a software framework (Software Framework) created for the purpose of processing large-capacity data processing by distributed parallel computing. Various applications use this map-reduce library. In the map-reduce application, if the map operation extracts intermediate information in a (key, value) form, the reduce operation collects the intermediate information and outputs a desired final result.

  For example, assuming that the "highest global temperature of each year" is retrieved via the map-reduce application, the map operation reads the text file and extracts information on the year and temperature, and lists the (year, temperature) form. Is output. Then, the reduce operation collects the results, arranges them in order of temperature, and outputs a desired final result. Here, it should be noted that while the data used for the map calculation has a large capacity, the result data of the map calculation has a relatively small size.

  Although the embodiment of the present invention processes a large amount of data like the map operation of the map-reduce application, the operation with less data reuse is performed by the accelerator 112 in the pool memory controller 110 in off-loading (Off). -Loading). Here, the off-loading refers to a series of processes of receiving and interpreting a request from the processor 20, performing an operation, and outputting a result of the operation. If data is processed in the pool memory 100, energy for transmitting data to the node CND of the processor 20 can be saved, and performance can be further improved.

  The accelerator 112 according to an embodiment of the present invention may be included in the pool memory controller 110 or may be located in the memory 120. In terms of proximity data processing, processing data within each memory 120 is more efficient than processing data within the pool memory controller 110.

  The pool memory controller 110 performs memory interleaving in order to provide a high bandwidth. In such a case, the data is separately stored in the plurality of memories 120. In such a case, the data required by the accelerator 112 may also be divided into a plurality of memories 120. Therefore, in the embodiment of the present invention, it is required that the physical location of the accelerator 112 be located in the pool memory controller 110. This will be described as an example.

  From now on, it will be examined how much the off-loading of the map operation of the map-reduce application by the accelerator 112 is gain in the memory system 10 as a whole in terms of performance (Performance) and energy (Energy).

  If the operation performed by the accelerator 112 is simple, such as the map operation of the map-reduce application, the operation time in the accelerator 112 depends on the bandwidth for reading data from the memory. Therefore, the operation time of the accelerator 112 can be reduced by increasing the bandwidth of the accelerator 112.

  As shown in FIG. 3, the nodes CND of the series of processors 20 are connected to the pool memory 100 via the fabric network 30. It is assumed that each node CND has one link L1 for each processor 20 and that the accelerator 112 inside the pool memory controller 110 has four links L2. That is, a wider bandwidth is allocated to the link L2 of the accelerator 112 than to the link L1 of the processor 20. Then, when the map calculation is off-loaded to the accelerator 112, the calculation can be performed four times faster than the processing performed by the processor 20.

  When the processor 20 performs all the map operations and the reduce operations, it is assumed that the time required for the map operations is 99% of the total execution time. Also, it is assumed that a plurality of applications are executed by one processor 20, and that the execution time of the map-reduce application accounts for 10% of the execution time of the entire application. When off-loading the map operation to the accelerator 112, the overall system performance can be improved by 81% as the map operation time is reduced to 1/4.

4 to 6 are views for explaining the operation of the memory system 10 according to the embodiment of the present invention.
First, as indicated by a path 1 in FIG. 4, the processor 20 transmits a map operation request packet to the pool memory 100 side. That is, the map operation request packet transmitted from the processor 20 is transmitted to the accelerator 112 via the interface 111 of the pool memory controller 110 via the fabric network 30. Here, the map operation request packet may include information on an address at which data used for the map operation is stored, data size, an address at which the map operation result data is stored, and the like.

  Next, the pool memory controller 110 transmits the map operation response packet to the processor 20 via the fabric network 30, as indicated by the path 2 in FIG. That is, the pool memory controller 110 transmits a signal indicating that the accelerator 112 has received the map operation request packet to the processor 20.

  Thereafter, as indicated by the path 3 in FIG. 5, the pool memory controller 110 reads the data required for the map calculation in each memory 120 and transmits the data to the accelerator 112. Here, data required by the accelerator 112 may be divided into a plurality of memories 120, and in such a case, the accelerator 112 reads data from a number of memories 120. Then, the accelerator 112 performs a map operation based on the data read from the memory 120.

  Next, the pool memory controller 110 reads the map operation result data calculated by the accelerator 112 as in the four paths in FIG. The data calculated by the accelerator 112 may be separately stored in a number of memories 120.

  Next, the pool memory controller 110 transmits an interrupt packet to the processor 20 as in the five paths in FIG. That is, the pool memory controller 110 transmits an interrupt packet indicating that the map calculation of the accelerator 112 has been completed to the processor 20 via the fabric network 30.

  Thereafter, the pool memory controller 110 reads the map operation result data stored in the memory 120 and transmits the read data to the processor 20 via the interface 111 and the fabric network 30, as indicated by the six paths in FIG.

  FIG. 7 is a diagram illustrating a performance improvement of a memory system according to an embodiment of the present invention. FIG. 7 is a result graph showing how the performance of the entire system is increased by increasing the number of channels CN of the accelerator 112 when performing a map operation in the accelerator 112.

  It can be seen that the performance increases as the number of channels CN of the accelerator 112 increases. However, since the amount of performance increase becomes smaller than the cost of increasing the number of channels CN, in the embodiment of the present invention, setting the number of channels CN of the accelerator 112 to two to four will be described as an example.

  Assume that 1 pJ (energy consumption) / beat (bit) is consumed per link L1 to move data through the node CND of the processor 20. In order for the processor 20 to process data, the bus BUS of the memory 120, the channel 40 of the fabric network 30 and the node CND of the processor 20 in FIG. 3, that is, 3 pJ / bit must be passed. Is consumed. However, when the map operation is off-loaded by the accelerator 112, the data passes through only the bus BUS of the memory 120, and the energy consumed for moving the data is reduced to 1 pJ / bit, which is 1/3. Can be reduced to In order to calculate how much energy is saved in the overall system, all the static power of each hardware must be considered.

  As described above, the pool memory 100 according to the embodiment of the present invention can provide a large capacity and a high bandwidth, and can be effectively used for an in-memory database or the like. By adding an accelerator 112 inside the pool memory controller 110 and off-loading the map operation of the map-reduce application by the accelerator 112, it is possible to improve the performance of the entire system and save energy.

  Those skilled in the art to which the present invention pertains will appreciate that the embodiments described above may be embodied in other specific forms without altering the technical spirit and essential characteristics thereof, and thus the embodiments described above may be modified in all respects. It should be understood as exemplary and not limiting. The scope of the present invention will be expressed by the claims described below rather than the detailed description, and the meaning and scope of the claims, and all modified or modified forms derived from the equivalents thereof, It should be construed as falling within the scope of the invention.

10: Memory system 20: Multiple processors 30: Fabric network 40: Multiple channels 100: Multiple pool memories

Claims (20)

Multiple memories for storing data,
A pool memory controller that performs the map operation by reading the data stored in the plurality of memories and stores the result data of the map operation in the plurality of memories;
Memory system with The pool memory controller,
An interface for relaying packets between a processor and the pool memory controller via a fabric network;
An accelerator that performs the map operation on the data transmitted through the interface, and stores the result data of the map operation in the plurality of memories via the interface;
The memory system according to claim 1, comprising: The interface is
The memory system according to claim 2, wherein the memory system is connected to the accelerator through a plurality of channels.   The memory system according to claim 3, wherein the number of links of the plurality of channels is greater than the number of links of the processor. The pool memory controller,
The memory system according to claim 2, wherein a map operation request packet is received from the processor via the interface. The map operation request packet is
6. The memory system according to claim 5, wherein the memory system includes at least one of an address at which data used for the map operation is stored, a size of the data, and an address at which result data of the map operation are stored. . The pool memory controller,
The memory system according to claim 2, wherein a map operation response packet is transmitted to the processor via the interface. The pool memory controller,
The memory system according to claim 2, wherein data required for the map operation is read from the plurality of memories and transmitted to the accelerator. The pool memory controller,
3. The memory system according to claim 2, wherein the result data of the map operation calculated by the accelerator is read and stored in the plurality of memories. The pool memory controller,
3. The memory system according to claim 2, wherein an interrupt packet is transmitted to the processor via the interface at the end of the map operation. The pool memory controller,
3. The memory system according to claim 2, wherein the result data of the map operation stored in the plurality of memories is read and transmitted to the processor via the interface. The pool memory controller,
The memory system according to claim 1, wherein interleaving is performed on the plurality of memories. The pool memory controller,
2. The memory system according to claim 1, wherein address remapping is performed on the plurality of memories. The pool memory controller,
The memory system according to claim 1, wherein a map-reduce application is used during the map calculation. A fabric network connected to the processor,
A pool memory for relaying packets to and from the processor through the fabric network and transmitting data stored in the memory to the processor when requested by the processor;
With
Said pool memory,
A memory system comprising: a pool memory controller for reading data stored in the memory, off-loading a map operation, and storing result data of the map operation in the memory. The pool memory controller,
An interface for relaying packets between the processor and the pool memory controller via the fabric network;
An accelerator for off-loading the map operation with respect to the data transmitted through the interface, and storing result data of the map operation in the memory via the interface;
The memory system according to claim 15, comprising: The pool memory controller,
17. The memory system of claim 16, receiving a map operation request packet from the processor via the interface, and transmitting a map operation response packet to the processor via the interface. The pool memory controller,
17. The memory system according to claim 16, wherein data necessary for the map operation is read from the memory and transmitted to the accelerator, and the result data of the map operation calculated by the accelerator is stored in the memory. The pool memory controller,
17. The method according to claim 16, wherein at the end of the map operation, an interrupt packet is transmitted to the processor via the interface, the result data of the map operation stored in the memory is read, and transmitted to the processor via the interface. The described memory system. The pool memory controller,
The memory system according to claim 15, wherein at least one of an interleaving operation and an address remapping operation is performed on the memory.

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