CN104199685A - I/O device and computer system with same - Google Patents
I/O device and computer system with same Download PDFInfo
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- CN104199685A CN104199685A CN201410399672.4A CN201410399672A CN104199685A CN 104199685 A CN104199685 A CN 104199685A CN 201410399672 A CN201410399672 A CN 201410399672A CN 104199685 A CN104199685 A CN 104199685A
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Abstract
The invention relates to the technical field of computers, in particular to an I/O device and a computer system with the same. The I/O device with a built-in processor or microprocessor is arranged in the system to process some repeated task operations, or some noncritical operations in which an ALU in the processor of the computer does not need to involve substantially, or some simple tasks relevant to resources of the I/O device, a high-performance homogeneous or heterogeneous multi-core processor of the system can complete some other critical complex operations, or one or more processor cores in the multi-core processor are closed at idle time, therefore, system efficiency can be increased, system performance can be improved, and power consumption is reduced.
Description
Technical field
The present invention relates to field of computer technology, relate in particular to a kind of I/O equipment and there is the computer system of this I/O equipment.
Background technology
Polycaryon processor just progressively replaces with its high-performance, low-power consumption advantage the main flow that traditional single core processor becomes market.Along with the expansion of application demand and the continuous progress of technology, polycaryon processor shows its powerful performance advantage.Polycaryon processor is integrated in a plurality of cores in same chip, and whole chip externally provides service, output performance as a unified structure.First polycaryon processor processes core by integrated a plurality of single-threaded processing cores or integrated a plurality of while multithreading, the several times that make Thread Count that whole processor can carry out simultaneously or number of tasks be single core processor, this has greatly promoted the parallel performance of processor.Secondly, a plurality of cores are integrated in sheet, have greatly shortened internuclear interconnection line, and internuclear communication delay step-down, has improved communication efficiency, and data transfer bandwidth is also improved.Moreover, the effective shared resource of coenocytism, the utilization factor of Resources on Chip is improved, and power consumption is also along with the minimizing of device has obtained reduction.Finally, coenocytism is simple, is easy to optimal design, and extendability is strong.These advantages have finally promoted the development of multinuclear and have replaced gradually single core processor to become main flow.The many advantages such as polycaryon processor structure not only has that performance potential is large, integrated level is high, degree of parallelism is high, simple in structure and design verification is convenient, and its some achievement in can also the research of inheriting tradition single core processor, such as while multithreading, wide firing order, reduce power consumption technology etc.
At present, the core texture of polycaryon processor mainly contains two kinds of isomorphism and isomeries.Isomorphism and isomery are two kinds of main structural forms of polycaryon processor.As its name suggests, isomorphism polycaryon processor refers to that its structure of all cores of processor chips inside is identical, and the status of each core is also equal to.Current isomorphism polycaryon processor great majority are comprised of general processor core, and each processor core can be executed the task independently, close with general purpose single core processor structure.Isomorphism is used for general polycaryon processor structure, for example, a kind of processor architecture as shown in Figure 1, it is inner there are 4 cores that are equal to, and the structure of each core is identical.In the sorting technique of multicomputer system structure, multi-processor structure and multicomputer structure are because its interconnection mode and data storage are different with sharing mode, correspondingly, the polycaryon processor of isomorphism also can structurally be distinguished according to the level of its interconnection, be can interconnect by shared storage between core, also can interconnect in Cache (high-speed cache) aspect (or local storage).Heterogeneous multi-nucleus processor chip internal adopts the different core of several functions.If any being in charge of the main core of scheduling and the polycaryon processor forming from core of being responsible for calculating; The polycaryon processor that has again the core formation of the different computing functions such as the fixed point born, floating-point, specific calculations.Current heterogeneous multi-nucleus processor is while integrated universal processor, DSP (Digital Signal Processor conventionally, digital signal processor), polytype processor core such as Media Processor, network processing unit, for different demands, improve the calculated performance of application.Wherein, general processor core Chang Zuowei processor is controlled the main core with the use of general-purpose computations, other processor cores for for accelerate specific application from core.For example, Cell processor as shown in Figure 2, the Cell processor STI (Sony of alliance, Toshiba, IBM) the heterogeneous multi-nucleus processor chip of a very-high performance of joint development, it comprises a general PowerPC processor core PPE (Power Processing Element) and 8 special-purpose duplicate coprocessor core SPE (synergistic processor element), and they are connected by cell interconnection bus EIB (Element interconnect Bus).1 PPE and 8 SPE in Cell have great independence.Wherein, the task of PPE processing unit is operation system, this task for a similar PowerPC 970 of structure, frequency up to 4GHz and can support the processing core of two-wire journey running simply with the slightest effort.But except operating system, PPE is regardless of any thing, and the thread computing that application program is relevant is moved by SPE coprocessor completely.Each SPE coprocessor in Cell is keeping again height independence, except completing the calculation task of the machine, SPE can also accept the computation requests from other equipment in Cell computational grid, and carries out relevant calculation task, acquired results again by Internet Transmission to task promoter.
Although polycaryon processor superior performance, its design also faces numerous challenges.First, along with improving constantly of technology, leaking power consumption also constantly increases, although the coprocessor core in heterogeneous polynuclear structure can adopt more backward process node, due to insulating oxide thickness reduction, also can cause the Lou increase of power consumption.Secondly, due to the increase of core number, chip area also can increase, and the cost of chip also constantly increases, and along with the reduction of process, chip price also can increase.The 3rd, because chip transistor size is more and more, chip yield loss problem is particularly serious, and the reliability of chip also can reduce.IBM Corporation points out in one piece of report of 2006, eight core chips as Cell, and yield rate only has 10%～20%, and this can further make chip price rise, and this is that those skilled in the art are reluctant to see.
Summary of the invention
For the problem of above-mentioned existence, the invention discloses a kind of I/O equipment and there is the computer system of this I/O equipment.
An I/O equipment, wherein, is applied to be provided with in the computer system of cpu bus, and described I/O equipment comprises:
Processor;
Nonvolatile memory, is connected with described processor communication, stores I/O data and/or application program;
Interface, described cpu bus is connected with described processor communication by described interface, to control described processor, calls described I/O data and/or application program, completes predetermined application function.
Above-mentioned I/O equipment, wherein, described interface comprises I/O interface and/or bus interface.
Above-mentioned I/O equipment, wherein, described cpu bus comprises north bridge high-speed bus and south bridge low speed bus.
Above-mentioned I/O equipment, wherein, described I/O equipment is connected with described north bridge high-speed bus or south bridge low speed bus by described I/O interface and/or described bus interface.
Above-mentioned I/O equipment, wherein, described I/O equipment is connected with described north bridge high-speed bus by described bus interface, and is connected with described south bridge low speed bus by described I/O interface.
Above-mentioned I/O equipment, wherein, described application program and described I/O data are independently stored in described nonvolatile memory simultaneously.
Above-mentioned I/O equipment, wherein, described application program and described I/O data realize the storage space of multiplexing described nonvolatile memory by handoff technique.
A computer system with above-mentioned I/O equipment, wherein, comprising: polycaryon processor or single core processor;
Described polycaryon processor or single core processor are connected with described I/O device talk by described cpu bus, complete communication and the data processing of all I/O equipment in described computer system with the processor by described polycaryon processor or single core processor and described I/O equipment.
Foregoing invention tool has the following advantages or beneficial effect:
I/O equipment disclosed by the invention and there is the computer system of this I/O equipment, by being set in system, the I/O equipment of embedded processor or microprocessor processes some repeated task operatings, or some the nonessential ALU without high-performance monokaryon or polycaryon processor in system (Arithmetic Logical Unit, arithmetical unit) a large amount of operations that participate in, or some simple tasks relevant to this I/O device resource, and the high performance isomorphism of system or heterogeneous multi-nucleus processor can complete some other critical complex operations, or in idle, close one or more processor core in polycaryon processor, thereby can improve system effectiveness and performance, reduce system power dissipation.
Concrete accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, the present invention and feature thereof, profile and advantage will become more apparent.In whole accompanying drawings, identical mark is indicated identical part.Can proportionally not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is processor architecture schematic diagram in background technology of the present invention;
Fig. 2 is Cell processor architecture schematic diagram in background technology of the present invention;
Fig. 3 is the structural representation of conventional art Computer system;
Fig. 4 is the structural representation of I/O equipment in the embodiment of the present invention;
Fig. 5 is the structural representation in the embodiment of the present invention with the computer system that the I/O equipment of embedded processor or microprocessor function is connected with south bridge low speed bus;
Fig. 6 is the structural representation in the embodiment of the present invention with the embodiment Computer system that the I/O equipment of embedded processor or microprocessor function is connected with north bridge high-speed bus;
Fig. 7 is the structural representation in the embodiment of the present invention with the computer system that the I/O equipment of embedded processor or microprocessor function is connected with north bridge high-speed bus with south bridge low speed bus respectively;
Fig. 8 is the structural representation of I/O equipment in another embodiment of the present invention;
Fig. 9 is the structural representation of BIOS chip in the concrete application one of the present invention;
Figure 10 is the structural representation of the concrete application of the present invention one Computer system;
Figure 11 is the structural representation of test macro in the specific embodiment of the invention one;
The structural representation of test macro when Figure 12 is the specific embodiment of the invention one test machine A fault;
Figure 13 is the structural representation of client searching resource or information in the specific embodiment of the invention two;
Figure 14 is the knot schematic diagram of the specific embodiment of the invention two hollow idle client searching resources or information.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
Traditional Computer Systems Organization as shown in Figure 3, isomorphism or heterogeneous multi-nucleus processor are by north bridge high-speed bus and south bridge low speed bus and I/O device talk, the communication of all I/O equipment and data processing all need to process by system processor, thereby power consumption can be very large.
For the problems referred to above, the present invention proposes a kind of I/O equipment, is applied to be provided with in the computer system of cpu bus, and in an embodiment of the present invention, this cpu bus comprises north bridge high-speed bus and south bridge low speed bus; This I/O equipment specifically comprises: processor; Nonvolatile memory, interface (this interface can comprise bus interface and/or I/O interface), wherein, nonvolatile memory is connected with processor communication, and in this nonvolatile memory, store I/O data and/or application program, cpu bus is connected with processor communication by this interface, with control processor, call I/O data and/or application program, complete predetermined application function; In an embodiment of the present invention, the application program of storing in nonvolatile memory can be configured according to the actual requirements by user, the predetermined application function configuration that for example need to complete according to processor.
In one embodiment of the invention, I/O equipment is connected with north bridge high-speed bus or south bridge low speed bus by bus interface and/or I/O interface, the bus interface and/or the I/O interface that are I/O equipment are all connected with north bridge high-speed bus, or the bus interface of I/O equipment and/or I/O interface are all connected with south bridge low speed bus.
In another embodiment of the present invention, I/O equipment is connected with north bridge high-speed bus by bus interface, is connected by I/O interface with south bridge low speed bus simultaneously; The bus interface that is I/O equipment is connected with north bridge high-speed bus, and I/O interface is connected with south bridge low speed bus.
In an embodiment of the present invention, application program and I/O data can independently be stored in nonvolatile memory simultaneously, also can realize by handoff technique the storage space of multiplexing described nonvolatile memory.
As shown in Figure 4, wherein 1 represents I/O interface, and this I/O interface i.e. the legacy interface of this I/O equipment; 2 represent bus interface, i.e. control and the communication interface of this I/O equipment and south bridge low speed bus or north bridge high-speed bus, 3 be in this I/O equipment with processor or microprocessor, 4 is the nonvolatile memory in I/O equipment, 5 is original data and instruction (in this I/O equipment, original data and instruction also can be referred to as I/O data) in the I/O equipment of storing in nonvolatile memory, 6 is the special application function program (being application program) of storing in nonvolatile memory, and 7 are referred to as other functional modules in this I/O equipment.I/O interface 1 and bus interface 2 can be two independently interfaces, also interface of reusable.Special applications function program 6 of the present invention can regular update, to support different application.If nonvolatile memory 4 spaces are enough large, the I/O data 5 of storing in I/O equipment so and application program 6 can independently be stored in nonvolatile memory 4 simultaneously; If nonvolatile memory 4 spaces are smaller, be not enough to arrange storage this I/O equipment I/O data 5 and application program 6 simultaneously, can realize by handoff technique the storage space of I/O data 5 and application program 6 multiplexing nonvolatile memories so.Generally, the I/O equipment of embedded processor function of the present invention moves in a conventional manner, in nonvolatile memory 4, store its original data and instruction, and preprepared particular application for example can be stored in, in the nonvolatile memory (hard disk) in computer system.When the I/O of embedded processor function of the present invention device start special applications function, can be by the raw data of this I/O equipment and instruction unloading for example, to the nonvolatile memory (hard disk) of computer system, then particular application for example, is stored in nonvolatile memory 4 in the nonvolatile memory from system (hard disk), thereby processor or microprocessor in this I/O equipment can complete special application function.After the use of special applications function finishes, also the legacy data in I/O equipment and instruction can be imported in its internal non-volatile memory 4 again.Like this, by the storage space of multiplexing nonvolatile memory 4, both can realize the function of traditional I/O equipment, also can realize special application function.
The present invention also provides a kind of computer system with above-mentioned I/O equipment, comprising: polycaryon processor (this polycaryon processor can be isomorphism or heterogeneous multi-nucleus processor) or single core processor; This polycaryon processor or single core processor are connected with I/O device talk by cpu bus, take and complete the communication of all I/O equipment in computer system and data processing (all I/O equipment all I/O equipment in this computer system, comprises and have embedded processor or microprocessor function I/O equipment and do not have embedded processor or microprocessor function I/O equipment) by the processor in polycaryon processor or single core processor and I/O equipment.
In an embodiment of the present invention, computer system also comprises internal memory, and this internal memory is connected with north bridge high-speed bus.
Concrete, as shown in Figure 5 or Figure 6: embedded processor or microprocessor function in certain the I/O equipment being connected with south bridge low speed bus or north bridge high-speed bus, 1 represents I/O interface, this I/O interface i.e. the legacy interface of this I/O equipment; 2 represent bus interface, i.e. control and the communication interface of this I/O equipment and south bridge low speed bus or north bridge high-speed bus, in an embodiment of the present invention, interface 1 and interface 2 can be stand-alone interfaces separately, also can be the interface merging, by multiplex interface 1, control the communication between this I/O equipment and south bridge low speed bus or north bridge high-speed bus.
To can embedded processor or the I/O equipment of microprocessor function at least need two requirements: first, in this I/O equipment with processor or microprocessor, its performance can be less than or equal to the arbitrary processor core in isomorphism polycaryon processor, or the coprocessor core in heterogeneous multi-nucleus processor; The second, in this I/O equipment, with nonvolatile memory, be used for storing special application function program (i.e. predetermined application program).For example, in BIOS chip, contain microprocessor, traditional BIOS chip only completes the series operations such as startup self-detection and hardware initialization, if deposited the application program of specific function in the nonvolatile memory in BIOS, for example control the repeated like this simple task of data transmission between internal storage and external network, so when system is busy, the task of these simple repeatability can transfer to the microprocessor in BIOS to go operation, thereby the high-performance processor in solution place system goes to process the tasks of needing ALU to participate in a large number of some complexity; When system is not busy, even can shutdown system high-performance processor and internal memory, thus greatly reduce power consumption.
Traditional isomery or isomorphism processor forward south bridge low speed bus to by north bridge high-speed bus again and control I/O equipment and complete specific task (tasks).In the present invention, in nonvolatile memory 4, stored special applications function program 6, thereby make in this I/O equipment processor or microprocessor 3 control the simple communication between I/O equipment and south bridge low speed bus or north bridge high-speed bus by interface 2, for example control the data transmission of data between computer-internal storer and external network, thus the utilization rate of the isomorphism of greatly reducing or heterogeneous processor.Special applications function program 6 may be some repeated tasks, also or some are nonessential without a large amount of participating in of the tasks of ALU in system high-performance processor, also or more relevant to this I/O equipment process operation, such as the transmission of data between internal storage and external network, the tasks such as data screening.With processor or the microprocessor of this I/O device interior, complete above-mentioned special applications function, reduce the occupation rate of system processor, can greatly reduce power consumption on the one hand, also can improve system performance on the one hand.This be because, when system is not busy, the processor in I/O equipment or microprocessor can replace system isomorphism or heterogeneous processor to carry out special applications feature operation, now system isomorphism or heterogeneous processor can be closed, and greatly reduce system power dissipation; When system is busy, processor in I/O equipment or microprocessor can replace system isomorphism or heterogeneous processor to process some special applications functions, and system processor can go to process some complicated tasks, the performance of system also can access and mention like this.
In another embodiment of the present invention, another kind of Computer Systems Organization as shown in Figure 7, with the Computer Systems Organization difference of the first be that interface 2 represents this I/O equipment and north bridge high-speed bus communication interfaces, traditional I/O equipment interface 1 and interface 2 are two independently ports.In the first computer system, the I/O equipment of integrated specific function application can be by controlling and the communicating by letter of south bridge low speed bus with south bridge low speed bus communication interface, and in the second computer system, the I/O equipment of integrated specific function application can by and thereby north bridge high-speed bus communication interface is controlled and north bridge high-speed bus between communication, by north bridge high-speed bus, control again the data communication on South Bridge chip.Generally speaking, in the first system architecture, the I/O equipment of integrated specific function application directly control and south bridge low speed bus between communication, and in the second system architecture, the I/O equipment of integrated specific function application directly controls and north bridge high-speed bus between communication, thereby the communication between indirect control and south bridge low speed bus.In the present embodiment, the structural representation of I/O equipment as shown in Figure 8.
Lifting concrete application is below further elaborated.
The I/O equipment of supposing embedded processor or microprocessor function is BIOS chip.BIOS chip is Basic Input or Output System (BIOS), be mainly used in initialization and the detection of various hardware devices in computer booting process, with Flash, be stored as example, along with capacity is increasing, in Flash chip, generally can manage and control Flash storage array by integrated microprocessor (MCU).The BIOS chip structure of the embedded microprocessor function of application the present invention as shown in Figure 9, if Flash storage space is enough large, can store simultaneously so by bios program and particular application.After system electrifying startup, system processor reads by traditional B ios interface (such as SPI or LPC interface etc.) initial work that BIOS information completes power-on self-test and hardware.When needs complete some application specific functionality, the for example transmission of data between network and internal system storer, BIOS internal microprocessor can be by completing this specific function with south bridge communication interface, thereby the participation without system high-performance processor, the system free time, system processor can also be closed, thereby reach the object of saving power consumption, system architecture as shown in figure 10, wherein close, power supply 2 opens by power supply 1.If Flash insufficient memory is large, particular application can be stored in internal system storer so.After system electrifying startup, read BIOS information and complete power-on self-test and hardware initialization work, when system starts complete, can be by the BIOS information unloading of storing in Flash to internal system storer, then particular application is stored in BIOS chip, so just can carries out when being necessary particular application.When exiting specific function application, then the BIOS information in internal system storer is stored in the Flash storage array in BIOS chip again.This BIOS chip of the present invention and South Bridge chip communication interface also can multiplexing traditional BIOS interfaces (SPI or LPC interface etc.), thereby saving resource, but corresponding, on South Bridge chip, necessary change need be done with the communication interface of BIOS chip, to meet BIOS chip, the communication of data between south bridge low speed bus and BIOS can be controlled.
Lifting specific embodiment is below further elaborated.
VLSI (very large scale integrated circuit) test machine is as one of instrument conventional in chip testing field, its functional coverage integrated circuit testing (numeral, simulation and hybrid circuit, storer), and circuit board testing (online and functional test).Teradyne (Teradyne) J750 test machine for example, its system architecture mainly can be divided into two large divisions, as shown in figure 11, a part is huge and complicated test macro, a part is data handling system, and it comprises advanced processor (CPU), internal memory (DRAM) and some I/O equipment.Processor in data handling system is controlled test macro by transmission order, and then test macro starts to carry out complicated test operation, after test finishes, test macro is sent to test result data in data handling system, and data handling system is analyzed test data and shown.Obviously, the data handling system most of the time, in idle condition, could be sent to end product in data handling system because test macro needs the plenty of time to test.If test machine is because CPU or DRAM break down, although test macro can normally move, but data cannot be processed in time, test machine is by paralyzed state so, unique solution please be keeped in repair exactly master worker and be solved, but this at least needs several days one week above time even, thereby has inevitably caused the wasting of resources.If adopt this novel Computer Systems Organization of the present invention, just can alleviate this situation.For example, if the I/O equipment of embedded processor of the present invention or microprocessor (BIOS chip) can be processed the externally transmission between network and internal storage of test data, in a test machine LAN (Local Area Network), as shown in figure 12, test machine A data handling system fault causes working, and the I/O equipment of embedded processor of the present invention or microprocessor can be transferred to test data in LAN (Local Area Network), by other the idle test machines in LAN (Local Area Network), complete data processing, for example test machine C tests, and its data handling system is in idle condition, the test data of test machine A can be controlled and transferred in test machine C by the I/O equipment of embedded processor of the present invention or microprocessor so, data handling system by test machine C completes corresponding data processing, after data processing completes, again result is controlled and transferred to its test macro by the I/O equipment of LAN (Local Area Network) embedded processor of the present invention or microprocessor in test machine A, to complete follow-up test operation.Originally because causing test machine, advanced processor or memory failure in test machine system cannot normally work, and the I/O equipment of application embedded processor of the present invention or microprocessor just can make the test machine still can deal with data, maximum possible is retrieved a loss, and improves machine work efficiency.It should be noted that, different test macros may have different testers, different driving and different agreements, but these are all interchangeable, does to upgrade and change in the special applications functional area in nonvolatile memory.
Lifting specific embodiment two is below further elaborated.
Switched LAN, as a kind of energy, by increasing the network segment, improve the technology of lan capacity, promptly established its status, its structure as shown in figure 13, client is connected to numerous private server resources by virtualized LAN (Local Area Network), is connected to memory devices again below server by virtualized storer LAN (Local Area Network).When client need to be searched for certain resource or information, client sends a command to each private server, and then processor-server starts to search the needed resource information of client in storer, and then this resource information is back to client by LAN (Local Area Network).In this process, the processor of server is being done a large amount of data processing operations, in storer, search in a large number the required resources of client, obviously such operation is repeatability and nonessential operation, and the super performance processor of server and memory source are consuming a large amount of power consumptions.If adopt Computer Systems Organization of the present invention, processor can be avoided this repeatability but not critical processing operation so, can transfer to processor or the microprocessor in certain I/O equipment in system to complete completely, the high-performance processor of server can complete a large amount of complex process operations that participate in of other critical ALU of needs, save on the one hand power consumption, improve on the one hand performance.The server free time, even can close some of them processor, and only allow processor or microprocessor in certain I/O equipment carry out executable operations, greatly reduce power consumption.As shown in figure 14, in idle, the processor of direct closing server 3,4,5,6, and only open the I/O equipment of its embedded processor of the present invention or microprocessor, complete some repeated data search tasks, and the server of other unlatchings can be used for processing the complicated processing operation of some keys, thereby the power consumption of greatly reducing does not reduce the performance of whole LAN (Local Area Network) simultaneously yet.Again such as, server is in order to improve system performance, non-when busy in system, data in storer need to be arranged and storage again, be referred to as data maintenance (data maintain), be that server high-performance processor dumps to another address by the data of storer from an address, this simple data conversion storage operation participates in without ALU at all in a large number, thereby can transfer to the microprocessor in certain the I/O equipment in the present invention to go, the operation of other complexity can directly be closed or go to high-performance processor in server, thereby the power consumption of greatly reducing, the performance of system also can increase.The computer system that the present invention is novel and traditional computer contrast as shown in table 1 in performance and power consumption.
| ? | Conventional computer system structure | The computer system that the present invention is novel |
| Performance | Higher | Higher |
| Power consumption | High | Significantly reduce |
Table 1
In sum, I/O equipment disclosed by the invention and there is the computer system of this I/O equipment, the I/O equipment that embedded processor or microprocessor are set in system is processed some repeated task operatings, or the operations without a large amount of participations of ALU in computer processor that some are nonessential, or some simple tasks relevant to this I/O device resource, and the high performance isomorphism of system or heterogeneous multi-nucleus processor can complete some other critical complex operations, or in idle, close one or more processor core in polycaryon processor, thereby can improve system effectiveness and performance, reduce power consumption.
It should be appreciated by those skilled in the art that those skilled in the art, realizing described variation example in conjunction with prior art and above-described embodiment, do not repeat at this.Such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. an I/O equipment, is characterized in that, is applied to be provided with in the computer system of cpu bus, and described I/O equipment comprises:
Processor;
Nonvolatile memory, is connected with described processor communication, stores I/O data and/or application program;
Interface, described cpu bus is connected with described processor communication by described interface, to control described processor, calls described I/O data and/or application program, completes predetermined application function.
2. I/O equipment as claimed in claim 1, is characterized in that, described interface comprises I/O interface and/or bus interface.
3. I/O equipment as claimed in claim 2, is characterized in that, described cpu bus comprises north bridge high-speed bus and south bridge low speed bus.
4. the I/O equipment of stating as claim 3, is characterized in that, described I/O equipment is connected with described north bridge high-speed bus or south bridge low speed bus by described I/O interface and/or described bus interface.
5. I/O equipment as claimed in claim 3, is characterized in that, described I/O equipment is connected with described north bridge high-speed bus by described bus interface, and is connected with described south bridge low speed bus by described I/O interface.
6. I/O equipment as claimed in claim 1, is characterized in that, described application program and described I/O data are independently stored in described nonvolatile memory simultaneously.
7. I/O equipment as claimed in claim 1, is characterized in that, described application program and described I/O data realize the storage space of multiplexing described nonvolatile memory by handoff technique.
8. a computer system with the I/O equipment as described in any one in claim 1-7, is characterized in that, comprising: polycaryon processor or single core processor;
Described polycaryon processor or single core processor are connected with described I/O device talk by described cpu bus, complete communication and the data processing of all I/O equipment in described computer system with the processor by described polycaryon processor or single core processor and described I/O equipment.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112087359A (en) * | 2020-09-28 | 2020-12-15 | 北京东土科技股份有限公司 | Serial communication system |
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