JP2019097121A - Latched comparator - Google Patents

Abstract

To reduce an input error due to a kickback noise.SOLUTION: A latch-type preamplifier part 310 is one construction element used for a sequential comparison-type ADC. The latch-type preamplifier part 310 generates a positive side pre-output signal PREOUTP and a negative side pre-output signal PREOUTM by sequentially amplifying a difference value between a DAC output voltage DACOUT and a reference voltage VCMOUT. Specifically, the latch-type pre-amplifier part 310 includes: a main difference stage MS of outputting the positive side pre-output signal PREOUTP and the negative side pre-output signal PREOUTM in response to reception of the input of the DAC output voltage DACOUT and the reference voltage VCMOUT; and a dummy difference stage DS which is operated in an opposite phase to the main difference MS in response to reception of the input of the DAC output voltage DACOUT and the reference voltage VCMOUT.SELECTED DRAWING: Figure 8

Description

  The invention disclosed herein relates to a latched comparator.

  Conventionally, a latched comparator that operates in synchronization with a clock signal is used in a successive approximation ADC [analog-to-digital converter].

  In addition, patent document 1 can be mentioned as an example of the prior art relevant to the above.

JP, 2017-135616, A

  However, in the conventional latched comparator, there is a problem that an input error due to kickback noise occurs when the differential input is high impedance.

  In view of the above problems found by the inventors of the present application, the invention disclosed in the present specification aims to provide a latched comparator capable of reducing an input error due to kickback noise. Do.

  The latched comparator disclosed in the specification generates a positive side pre-output signal and a negative side pre-output signal by sequentially amplifying the difference value between the DAC output voltage and the reference voltage; A latch unit that generates a positive latch output signal and a negative latch output signal by sequentially comparing the positive pre-output signal and the negative pre-output signal, the positive latch output signal, and the negative latch output An SR latch unit that latches and outputs a comparison output signal according to a signal, and is used for a successive approximation ADC, wherein the latch-type preamplifier unit receives the DAC output voltage and the reference voltage A main differential stage for outputting the positive side pre-output signal and the negative side pre-output signal, and the main differential stage receiving the DAC output voltage and the reference voltage. A dummy differential stage operating in reverse phase, and is configured to include (first configuration).

  In the latched comparator having the first configuration, the latch type preamplifier unit fixes the high impedance node of each of the main differential stage and the dummy differential stage to a fixed potential in the sampling period of the successive approximation type ADC. It is preferable to have a configuration (second configuration) having the function of

  In the latched comparator having the first or second configuration, the drain of the main differential stage is connected to the output end of the negative side pre-output signal and the gate is connected to the input end of the DAC output voltage. First NMOSFET, a second NMOSFET having a drain connected to the output end of the positive side pre-output signal and a gate connected to the input end of the reference voltage, and a drain at the source of each of the first NMOSFET and the second NMOSFET A third NMSOFET connected with the source connected to the ground terminal and turned off in the first phase and turned on in the second phase, the source connected to the power supply terminal, and the drain connected to the drain of the first NMOSFET The first PMOSFET which is turned on in the phase and turned off in the second phase, the source is the power supply A second PMOSFET connected to the drain and connected to the drain of the second NMOSFET and turned on in the first phase and turned off in the second phase, and the dummy differential stage has a gate connected to the DAC output voltage A fourth NMOSFET connected to the input terminal of the second NMOSFET, a fifth NMOSFET having a gate connected to the input terminal of the reference voltage, and a drain connected to respective sources of the fourth NMOSFET and the fifth NMOSFET and a source connected to the ground terminal A sixth NMSOFET which is turned on in the first phase and turned off in the second phase, a source is connected to the power supply end, a drain is connected to a drain of the fourth NMOSFET, and is turned off in the first phase The third PMOSFET turned on in the second phase, and the source is the power supply terminal A first 4PMOSFET which is turned to the second phase connected to the drain is connected to the drain of the second 5NMOSFET off the first phase, it may be a configuration including (third configuration).

  In the latched comparator having the third configuration, the latch-type preamplifier unit has a drain connected to the drain of the third NMOSFET and a source connected to the ground terminal, and the sampling period of the successive approximation ADC And a fifth PMOSFET having a source connected to the power supply terminal and a drain connected to the drain of the fourth NMOSFET to turn on during the sampling period of the successive approximation ADC; a source connected to the power supply terminal And a sixth PMOSFET which is connected to the drain of the fifth NMOSFET and turned on in the sampling period of the successive approximation type ADC (fourth configuration).

  The latched comparator having any one of the first to fourth configurations further has a configuration (fifth configuration) further including a calibration unit that calibrates the positive side pre-output signal and the negative side pre-output signal. It is good to do.

  Further, in the latched comparator having the fifth configuration, the calibration unit adjusts a capacitance value of a capacitor connected to each of a positive output terminal and a negative output terminal of the latch-type preamplifier unit. Configuration 6).

  The successive approximation ADC disclosed in the present specification is a capacitor array DAC that generates a DAC output voltage for bit determination by sampling an analog input signal using a plurality of capacitors, and a predetermined reference. A reference voltage generation unit for generating a voltage, a latched comparator having the first to sixth configurations and sequentially comparing the DAC output voltage with the reference voltage to generate a comparison output signal, and the comparison output A register for storing signals, a latch output unit for parallel output of all bits simultaneously as a digital output signal, and a feedback input of the comparison output signal stored in the register A controller for controlling the capacitor array type DAC (seventh configuration)

  In the successive approximation ADC having the seventh configuration, the capacitor array DAC includes a positive coupling capacitor and a negative coupling capacitor; and a first end connected to the first end of the positive coupling capacitor. A first positive side capacitor group; a first negative side capacitor group having a first end connected to a first end of the negative side coupling capacitor; and a first end connected to a second end of the positive side coupling capacitor A second positive capacitor group; a second negative capacitor group having a first end connected to a second end of the negative coupling capacitor; and the first positive capacitor group and the first negative capacitor group respectively A first selector group having a second end connected to any one of the input end of the analog input signal, the power supply end, and the ground end; the second of each of the second positive side capacitor group and the second negative side capacitor group End to the analog A second selector group connected to any one of a power signal input end, a power supply end, and a ground end; a PMOSFET connected between the second end of the positive side coupling capacitor and the power supply end; An NMOSFET connected between the second end of the side coupling capacitor and the ground end; a positive side switch connected between the second end of the positive side coupling capacitor and the output end of the DAC output voltage; The negative side switch connected between the second end of the negative side coupling capacitor and the output end of the DAC output voltage may have a configuration (eighth configuration).

  In the successive approximation type ADC having the eighth configuration described above, the first positive capacitor group, the first negative capacitor group, the second positive capacitor group, and the second negative capacitor group It is preferable that the configuration (ninth configuration) have capacitance values weighted by a predetermined ratio.

  In the successive approximation type ADC having the eighth or ninth configuration, the reference voltage generation unit may include a PMOSFET whose source is connected to the power supply terminal, an NMOSFET whose source is connected to the ground terminal, The first switch has one end connected to the drain of the PMOSFET and the second end connected to the output end of the reference voltage, and the first end connected to the drain of the NMOSFET and the second end connected to the drain of the NMOSFET. A second switch connected to the output end, a first capacitor having a first end connected to the drain of the PMOSFET and a second end connected to the ground end, and a first end connected to the drain of the NMOSFET The second capacitor may have a configuration (tenth configuration) including a second capacitor whose second end is connected to the ground terminal.

  According to the invention disclosed in the present specification, it is possible to provide a latched comparator capable of reducing an input error due to a kickback noise.

Diagram showing overall configuration of successive approximation ADC Diagram showing an example of the internal configuration of CDAC A diagram showing an example of the internal configuration of a reference voltage generation unit Diagram showing an example of the internal configuration of a latched comparator Timing chart showing an operation example of successive approximation ADC The figure which shows the comparative example of a latch type preamplifier part Diagram showing the occurrence of an input error due to kickback noise FIG. 5 shows a first embodiment of a latch type preamplifier unit. Figure showing how input error due to kickback noise is eliminated Diagram showing the node potential of each part becomes an indefinite value The figure which shows 2nd Embodiment of a latch type | mold preamplifier part. A diagram showing how the node potential of each part becomes a fixed value

<Successive comparison type ADC>
FIG. 1 is a diagram showing an entire configuration of a successive approximation ADC. The successive approximation type ADC 1 of this configuration example includes a capacitor array DAC [digital-to-analog converter] 100 (hereinafter referred to as CDAC 100), a reference voltage generation unit 200, a latched comparator 300, a register 400, and a latch. An output unit 500 and a controller 600 are provided to convert an analog input signal AIN into a digital output signal DOUT.

  The CDAC 100 samples the analog input signal AIN using a plurality of capacitors, and redistributes the charge of each capacitor according to the instruction of the controller 600 to generate a DAC output voltage DACOUT for bit determination.

  The reference voltage generation unit 200 generates a predetermined reference voltage VCMOUT.

  The latched comparator 300 sequentially compares the DAC output voltage DACOUT with the reference voltage VCMOUT to generate a comparison output signal COMPOUT.

  The register 400 stores a comparison output signal COMPOUT (= corresponding to each bit value of the digital output signal DOUT) sequentially output from the latched comparator 300.

  The latch output unit 500 simultaneously outputs all bits of the comparison output signal COMPOUT stored in the register 400 in parallel as a digital output signal DOUT.

  The controller 600 receives the feedback input of the comparison output signal COMPOUT stored in the register 400 to control the CDAC 100.

<CDAC>
FIG. 2 shows an example of the internal configuration of CDAC 100. As shown in FIG. The CDAC 100 according to this configuration example includes capacitors 101P and 101M, capacitors 111P to 115P, capacitors 111M to 115M, capacitors 121P to 127P, capacitors 121M to 127M, capacitors 131P and 131M, selectors 141 to 145, a selector 151 to 157, a PMOSFET 171P, an NMOSFET 171M, and switches 181P and 181M.

  Capacitors 101P and 101M correspond to a positive coupling capacitor and a negative coupling capacitor, respectively. The capacitance value of each of the capacitors 101P and 101M is [1C] (where C is a unit capacitance value, and the same applies to the following).

Capacitors 111P to 115P correspond to the first positive-side capacitor group (lower 5 bits) whose first ends are commonly connected to the first end of capacitor 101P. The capacitance values of the capacitors 111P to 115P are [1C], [2C], [4C], [8C], and [16C]. That is, capacitors 111P to 115P each have a capacitance value (= 2 ^x C (where x is an integer from 0 to 4)) weighted at a predetermined ratio.

The capacitors 111M to 115M correspond to a first negative capacitor group (lower 5 bits) whose first ends are commonly connected to the first end of the capacitor 101M. The capacitance values of the capacitors 111M to 115M are [1C], [2C], [4C], [8C], and [16C]. That is, each of the capacitors 111M to 115M has a capacitance value (= 2 ^x C (where x is an integer from 0 to 4)) weighted at a predetermined ratio.

Capacitors 121P to 127P correspond to the second positive-side capacitor group (for the upper 7 bits) whose first ends are commonly connected to the second end of capacitor 101P. The capacitance values of the capacitors 121P to 127P are [1C], [2C],..., [32C], and [64C]. That is, capacitors 121P to 127P each have a capacitance value (= 2 ^y C (where y is an integer from 0 to 6)) weighted at a predetermined ratio.

The capacitors 121M to 127M correspond to the second negative capacitor group (for the upper 7 bits) whose first ends are commonly connected to the second end of the capacitor 101M. The capacitance values of the capacitors 121M to 127M are [1C], [2C],..., [32C], and [64C]. That is, capacitors 121M to 127M each have a capacitance value (= 2 ^y C (where y is an integer of 0 to 6)) weighted at a predetermined ratio.

  The capacitors 131P and 131M are respectively connected between the second end of each of the capacitors 101P and 101M and the ground end, and function as an attenuator.

  The selectors 141 to 145 correspond to the first selector group (lower 5 bits). In response to an instruction from the controller 600, the selector 141 sets the second end of both the capacitors 111P and 111M to the analog input end (= input end of the analog input signal AIN), power supply end (= application end of power supply voltage AVDD), And, it is connected to any one of the ground terminal (= application terminal of ground voltage GND). Similarly to the above, selectors 142 to 145 each receive the second end of each of capacitors 112P to 115P and 112M to 115M as an analog input end, a power supply end, or a ground end according to an instruction from controller 600. Connect to

  The selectors 151 to 157 correspond to the second selector group (upper 7 bits). In response to an instruction from the controller 600, the selector 151 connects the second ends of both the capacitors 121P and 121M to any of the analog input end, the power supply end, and the ground end. Similarly to the above, selectors 152 to 157 each receive the second end of each of capacitors 122P to 127P and 122M to 127M as an analog input end, a power supply end, or a ground end according to an instruction from controller 600. Connect to

  The source of the PMOSFET 171P is connected to the power supply terminal. The drain of the PMOSFET 171P is connected to the second end of the capacitor 101P. The gate of the PMOSFET 171P is connected to the input end of the inverted clock signal CLK1B (= logically inverted signal of the clock signal CLK1). Therefore, the PMOSFET 171P turns on when CLK1B = L and turns off when CLK1B = H.

  The source of the NMOSFET 171M is connected to the ground terminal. The drain of the NMOSFET 171M is connected to the second end of the capacitor 101M. The gate of the NMOSFET 171M is connected to the input end of the clock signal CLK1. Therefore, the NMOSFET 171M turns on when CLK1 = H and turns off when CLK1 = L.

  The switch 181 P corresponds to a positive side switch connected between the second end of the capacitor 101 P (= corresponding to the application end of the positive side DAC output voltage DAOUTP) and the output end of the DAC output voltage DACOUT. It is turned on / off in response to the inverted clock signal CLK2B (= logic inverted signal of clock signal CLK2). More specifically, the switch 181P turns on when CLK2 = H (CLK2B = L) and turns off when CLK2 = L (CLK2B = H).

  The switch 181M corresponds to a negative switch connected between the second end of the capacitor 101M (= corresponding to the application end of the negative DAC output voltage DAOUTM) and the output end of the DAC output voltage DACOUT, and the clock signal CLK2 It is turned on / off according to the inverted clock signal CLK2B. More specifically, the switch 181M turns on when CLK2 = H (CLK2B = L) and turns off when CLK2 = L (CLK2B = H).

  The controller 600 receives the feedback input of the comparison output signal COMPOUT stored in the register 400 and controls the selectors 141-145 and 151-157.

  For example, in the sampling period (CLK1 = H) of the analog input signal AIN, the capacitors 111P to 115P and 111M to 115M and the second ends of the capacitors 121P to 127P and 121M to 127M are all connected to the analog input terminal. As such, the selectors 141-145 and 151-157 are controlled.

  Also, for example, when determining the most significant bit (MSB [most significant bit]), the second ends of the capacitors 127P and 127M are connected to the power supply end, and the second ends of the other capacitors are all connected to the ground end. The selectors 141 to 145 and 151 to 157 are controlled.

  However, the CDAC 100 of this configuration example is merely an example, and an internal configuration other than this may be adopted.

<Reference voltage generator>
FIG. 3 is a diagram showing an example of the internal configuration of the reference voltage generation unit 200. As shown in FIG. The reference voltage generation unit 200 of this configuration example includes a PMOSFET 211, an NMOSFET 212, switches 213 and 214, and capacitors 215 and 216.

  The source of the PMOSFET 211 is connected to the power supply end (= the application end of the power supply voltage AVDD). The gate of the PMOSFET 211 is connected to the input end of the inverted clock signal CLK1B. Therefore, the PMOSFET 211 turns on when CLK1B = L and turns off when CLK1B = H.

  The source of the NMOSFET 212 is connected to the ground terminal (= application terminal of the ground voltage GND). The gate of the NMOSFET 212 is connected to the input end of the clock signal CLK1. Therefore, the NMOSFET 212 turns on when CLK1 = H and turns off when CLK1 = L.

  The switch 213 corresponds to a first switch connected between the drain of the PMOSFET 211 (= corresponding to the application terminal of the positive side reference voltage VCMP) and the output terminal of the reference voltage VCMOUT, and corresponds to the clock signal CLK2 and the inverted clock signal CLK2B. It will be turned on / off accordingly. More specifically, the switch 213 turns on when CLK2 = H (CLK2B = L) and turns off when CLK2 = L (CLK2B = H).

  The switch 214 corresponds to a second switch connected between the drain of the NMOSFET 212 (= corresponding to the application terminal of the negative reference voltage VCMM) and the output terminal of the reference voltage VCMOUT, and corresponds to the clock signal CLK2 and the inverted clock signal CLK2B. It will be turned on / off accordingly. More specifically, the switch 214 turns on when CLK2 = H (CLK2B = L) and turns off when CLK2 = L (CLK2B = H).

  The first end of the capacitor 215 is connected to the drain of the PMOSFET 211. The second end of the capacitor 215 is connected to the ground end. The capacitance value of the capacitor 215 is [XC] (X is arbitrary).

  The first end of the capacitor 216 is connected to the drain of the NMOSFET 212. The second end of the capacitor 216 is connected to the ground end. The capacitance value of the capacitor 216 is [XC].

  In the reference voltage generation unit 200 of this configuration example, when CLK1 = H (CLK1B = L) and CLK2 = L (CLK2B = H), the capacitor 215 is charged and the capacitor 216 is discharged. On the other hand, when CLK1 = L (CLK1B = H) and CLK2 = H (CLK2B = L), charges are redistributed between the capacitors 215 and 216, and the reference voltage VCMOUT is output. At this time, the reference voltage VCMOUT is a voltage value (= AVDD / 2) obtained by dividing the power supply voltage AVDD into a half.

  However, the reference voltage generation unit 200 of this configuration example is merely an example, and an internal configuration other than this may be adopted.

<Latched Comparator>
FIG. 4 is a diagram showing an example of the internal configuration of the latched comparator 300. As shown in FIG. The latched comparator 300 of this configuration example includes a latch-type preamplifier unit 310, a calibration unit 320, a latch unit 330, and an SR latch unit 340.

  The latch-type preamplifier unit 310 calculates a difference value (= VCMOUT−DACOUT) between the DAC output voltage DACOUT input to the negative input terminal (−) and the reference voltage VCMOUT input to the positive input terminal (+), A positive side pre-output signal PREOUTP and a negative side pre-output signal PREOUTM are generated by sequentially amplifying in synchronization with the clock signal CLK3.

  The calibration unit 320 adjusts the capacitance values of the capacitors 321 and 322 connected between the positive output terminal (+) and the negative output terminal (−) of the latch-type preamplifier unit 310 and the power supply terminal. The rising waveforms of the positive side pre-output signal PREOUTP and the negative side pre-output signal PREOUTM are respectively calibrated. By providing such a calibration unit 320, it is possible to cancel the input offset between the DAC output voltage DACOUT and the reference voltage VCMOUT and the offset error between the latch-type preamplifier unit 310 and the latch unit 330, respectively. However, when priority is given to reduction of the circuit size and reduction of the current consumption, the calibration unit 320 can be omitted.

  The latch unit 330 synchronizes the positive side pre-output signal PREOUTP input to the positive side input end (+) and the negative side pre-output signal PREOUTM input to the negative side input end (-) with the clock signal CLK3. The comparator is a comparator that generates the positive latch output signal LATOUTP and the negative latch output signal LATOUTM by sequentially comparing. When PREOUTP> PREOUTM, LATOUTP = H and LATOUTM = L. Conversely, when PREOUTP <PREOUTM, LATOUTP = L and LATOUTM = H.

  The SR latch unit 340 outputs a comparison output from the output end (Q) according to the positive side latch output signal LATOUTP input to the set end (S) and the negative side latch output signal LATOUTM input to the reset end (R). A sequential circuit for latching output of signal COMPOUT, which includes inverters 341 and 342 and NANDs 343 and 344.

  The input terminal of the inverter 341 corresponds to the reset terminal (R) of the SR latch unit 340, and generates a logic inversion signal of the negative side latch output signal LATOUTM.

  The input end of the inverter 342 corresponds to the set end (S) of the SR latch unit 340, and generates a logic inversion signal of the positive side latch output signal LATOUTP.

  NAND 343 generates a non-conjunction signal of the output signal of inverter 341 and the output signal of NAND 344 (= digital output signal DOUT).

  NAND 344 generates an NAND signal of the output signals of inverter 342 and NAND 343, and outputs this as comparison output signal COMPOUT. That is, the output end of the NAND 344 corresponds to the output end (Q) of the SR latch unit 340.

  The SR latch unit 340 sets the comparison output signal COMPOUT to high level at the rising timing of the positive side latch output signal LATOUTP, and resets the comparison output signal COMPOUT to low level at the rising timing of the negative side latch output signal LATOUTM.

  In the case of the latched comparator 300 of this configuration example, the current consumption can be suppressed to a low level, so power consumption can be reduced. In addition, since an operational amplifier is not required, it is suitable for voltage reduction.

<Timing chart>
FIG. 5 is a timing chart showing an operation example of the successive approximation type ADC 1. The clock signal CLK3, the positive side reference voltage VCMP (solid line) and the negative side reference voltage VCMM (dashed line), positive side DAC output voltage DAOUTP (solid line) and negative side DAC output voltage DAOUTM (dashed line), reference voltage VCMOUT, DAC output voltage DACOUT, positive side pre-output signal PREOUTP (solid line) and negative side pre-output signal PREOUTM (dashed line), positive side latch output Signal LATOUTP, negative latch output signal LATOUTM, and comparison output signal COMPOUT are depicted.

  First, the sampling period TS of the analog input signal AIN will be described. During this sampling period TS, the successive comparison operation of the latched comparator 300 is stopped by fixing CLK3 = H. At this time, PREOUTP = PREOUTM = AVDD, and LATOUTP = LATOUTM = GND. Further, the comparison output signal COMPOUT holds the previous data.

  Further, in the reference voltage generation unit 200, the PMOSFET 211 and the NMOSFET 212 are turned on and the switches 213 and 214 are turned off according to CLK1 = H and CLK2 = L. Therefore, VCMP = AVDD, VCMM = GND, and VCMOUT = GND.

  On the other hand, in the CDAC 300, the PMOSFET 171P and the NMOSFET 171M are turned on and the switches 181P and 181M are turned off according to CLK1 = H and CLK2 = L. Therefore, DAOUTP = AVDD and DAOUTM = GND. At this time, the capacitors 111P to 115P and 111M to 115M and the second ends of the capacitors 121P to 127P and 121M to 127M are all connected to the analog input terminal. Therefore, these capacitors are charged according to the analog input signal AIN. This charging operation corresponds to the sampling operation of the analog input signal AIN.

  Next, the successive approximation period TC between the DAC output voltage DACOUT and the reference voltage VCMOUT will be described.

  During the successive approximation period TC, the PMOSFET 211 and the NMOSFET 212 in the reference voltage generation unit 200 are turned off and the switches 213 and 214 are turned on in accordance with CLK1 = L and CLK2 = H. Accordingly, charge redistribution between the capacitors 215 and 216 results in VCMP = VCMM = VCMOUT = AVDD / 2.

  On the other hand, in the CDAC 100, the PMOSFET 171P and the NMOSFET 171M are turned off and the switches 181P and 181M are turned on according to CLK1 = L and CLK2 = H. Accordingly, the charge redistribution among the capacitors 111P to 115P and 111M to 115M and the capacitors 121P to 127P and 121M to 127M results in DAOUTP = DAOUTM = DACOUT. At this time, the voltage value of the DAC output voltage DACOUT is determined according to the sampling value of the analog input signal AIN (= total charge amount charged in the capacitor array) and the selection state of each of the selectors 141 to 145 and 151 to 157.

  For example, at the time of MSB determination, the second ends of the capacitors 127P and 127M are connected to the power supply end, and the second ends of the other capacitors are all connected to the ground end. Therefore, the voltage value of the DAC output voltage DACOUT is determined according to the sampling value of the analog input signal AIN and the analog conversion value corresponding to the intermediate value "1000 0000 0000b" of the digital output signal DOUT.

  Here, when DACOUT> VCMOUT, the comparison result of COMPOUT = L is obtained by the successive comparison operation of the latched comparator 300 described later. Thus, the MSB of the digital output signal DOUT can be determined to be "0". On the other hand, when DACOUT <VCMOUT, the comparison result of COMPOUT = H is obtained by the successive comparison operation of the latched comparator 300. Thus, the MSB of the digital output signal DOUT can be determined to be "1".

  When it is determined that MSB = “0”, selectors 141 to 145 and 151 to 157 are selected to select an analog conversion value equivalent to “0100 0000 0000b” at the time of determination of the next bit. The state is switched.

  On the other hand, if it is determined that MSB = “1”, selectors 141 to 145 and 151 to 157 are selected to select an analog conversion value corresponding to “1100 0000 0000b” at the time of determination of the next bit. The state is switched.

  Thereafter, the voltage value of the DAC output voltage DACOUT is sequentially switched in order to determine all bits of the digital output signal DOUT from MSB to LSB [least significant bit] in the same manner as described above.

  Further, in the latched comparator 300, a sequential comparison operation of the DAC output voltage DACOUT and the reference voltage VCMOUT is performed by pulse driving of the clock signal CLK3.

  First, in the latch-type preamplifier unit 310, when the clock signal CLK3 falls from the high level to the low level, the positive side pre-output signal PREOUTP and the negative side pre-output signal PREOUTM both start to fall from the power supply voltage AVDD.

  However, depending on the difference between the DAC output voltage DACOUT and the reference voltage VCMOUT (= VCMOUT-DACOUT), there is a gap between the falling waveform of the positive side pre-output signal PREOUTP and the falling waveform of the negative side pre-output signal PREOUTM. It occurs.

  Specifically, when the DAC output voltage DACOUT is higher than the reference voltage VCMOUT, the larger the difference, the steeper the falling of the negative side pre-output signal PREOUTM and the slower the falling of the positive side pre-output signal PREOUTP. . Conversely, when the DAC output voltage DACOUT is lower than the reference voltage VCMOUT, the larger the difference, the steeper the falling of the positive side pre-output signal PREOUTP and the slower the falling of the negative side pre-output signal PREOUTM.

  Subsequently, in the latch unit 330, the positive latch output signal LATOUTP and the negative latch output signal LATOUTM are generated by successive comparison of the positive pre output signal PREOUTP and the negative pre output signal PREOUTM. If PREOUTP> PREOUTM, the positive side latch output signal LATOUTP rises to the high level, and if PREOUTP <PREOUTM, the negative side latch output signal LATOUTM rises to the high level.

  Next, in the SR latch unit 340, latch output of the comparison output signal COMPOUT is performed according to the positive side latch output signal LATOUTP and the negative side latch output signal LATOUTM. The comparison output signal COMPOUT is set to the high level at the rising timing of the positive side latch output signal LATOUTP, and is reset to the low level at the rising timing of the negative side latch output signal LATOUTM.

  The last one cycle corresponds to the latch output period TL. In the latch output period TL, the comparison output signal COMPOUT stored in the register 400 is simultaneously output in parallel as all the bits as the digital output signal DOUT. After this latch output period TL, a series of successive approximation AD conversion processes are completed.

<Latch Type Preamplifier Part (Comparative Example)>
Next, prior to describing the novel embodiment of the latch-type preamplifier unit 310, first, a comparative example to be compared with this will be briefly described. FIG. 6 is a view showing a comparative example of the latch type preamplifier unit 310. As shown in FIG. The latch-type preamplifier unit 310 of this comparative example includes NMOSFETs 311 to 313 and PMOSFETs 314 and 315.

  The drain of the NMOSFET 311 is connected to the output end of the negative side pre-output signal PREOUTM. The gate of the NMOSFET 311 is connected to the input end of the DAC output voltage DACOUT.

  The drain of the NMOSFET 312 is connected to the output end of the positive side pre-output signal PREOUTP. The gate of the NMOSFET 312 is connected to the input end of the reference voltage VCMOUT.

  The drain of the NMOSFET 313 is connected to the source of each of the NMOSFETs 311 and 312. The source of the NMOSFET 313 is connected to the ground terminal. The gate of the NMOSFET 313 is connected to the input end of the inverted clock signal CLK3B (= logically inverted signal of the clock signal CLK3).

  The source of the PMOSFET 314 is connected to the power supply end. The drain of the PMOSFET 314 is connected to the drain of the NMOSFET 311. The gate of the PMOSFET 314 is connected to the input end of the inverted clock signal CLK3B.

  The source of the PMOSFET 315 is connected to the power supply end. The drain of the PMOSFET 315 is connected to the drain of the NMOSFET 312. The gate of the PMOSFET 315 is connected to the input end of the inverted clock signal CLK3B.

  Next, the basic operation of the latch-type preamplifier unit 310 will be described. In the first phase (CLK3 = H, CLK3B = L), the NMOSFET 313 is turned off and the PMOSFETs 314 and 315 are turned on. Therefore, the positive side pre-output signal PREOUTP and the negative side pre-output signal PREOUTM are both pulled up to the power supply voltage AVDD.

  On the other hand, in the second phase (CLK3 = L, CLK3B = H), the NMOSFET 313 is turned on and the PMOSFETs 314 and 315 are turned off. Therefore, the positive side pre-output signal PREOUTP and the negative side pre-output signal PREOUTM both start to fall from the power supply voltage AVDD. However, when the DAC output voltage DACOUT is higher than the reference voltage VCMOUT, the larger the difference, the steeper the falling of the negative side pre-output signal PREOUTM and the slower the falling of the positive side pre-output signal PREOUTP. Conversely, when the DAC output voltage DACOUT is lower than the reference voltage VCMOUT, the larger the difference, the steeper the falling of the positive side pre-output signal PREOUTP and the slower the falling of the negative side pre-output signal PREOUTM. This point is as described above.

  FIG. 7 is a diagram showing that an input error occurs due to kickback noise, and from the top, the inverted clock signal CLK3B, the DAC output voltage DACOUT, the reference voltage VCMOUT, and the positive side pre-output signal PREOUTP and the negative side. The pre-output signal PREOUTM is depicted.

  In the latch-type preamplifier unit 310 of this comparative example, when the differential input end is high impedance (= noise component superimposed on the DAC output voltage DACOUT or the reference voltage VCMOUT is hard to escape to the CDAC 100 or the reference voltage generation unit 200 in the previous stage. In the case (1), the change amount Δ1 of the DAC output voltage DACOUT and the change amount Δ2 of the reference voltage VCMOUT do not match (Δ1 不一致 Δ2) due to the kickback noise. This is because the circuit constants of the DAC output voltage DACOUT and the reference voltage VCMOUT are different. When such an input error occurs, the conversion accuracy of the successive type ADC 1 is lowered, so some measures are required.

  As a general countermeasure, it is conceivable to provide a buffer in the front stage of the latch-type preamplifier unit 310 and convert the differential input end of the latch-type preamplifier unit 310 from high impedance to low impedance. However, such measures increase power consumption by the amount of the added buffer. Below, the novel embodiment which can solve such a subject is explained in full detail.

<Latch Type Preamplifier Part (First Embodiment)>
FIG. 8 is a diagram showing a first embodiment of the latch-type preamplifier unit 310. As shown in FIG. The latch-type preamplifier unit 310 of the present embodiment further includes NMOSFETs 311D to 313D and PMOSFETs 314D and 315D based on the above-described comparative example (FIG. 6). Therefore, the same components as those of the comparative example described above are denoted by the same reference numerals as those in FIG. 6 to omit redundant descriptions, and the following description focuses on the features of the present embodiment.

  The gate of the NMOSFET 311D is connected to the input end of the DAC output voltage DACOUT. The gate of the NMOSFET 312D is connected to the input end of the reference voltage VCMOUT. The drain of the NMOSFET 313D is connected to the source of each of the NMOSFETs 311D and 312D. The source of the NMOSFET 313D is connected to the ground terminal. The gate of the NMOSFET 313D is connected to the input end of the clock signal CLK3.

  The source of the PMOSFET 314D is connected to the power supply end. The drain of the PMOSFET 314D is connected to the drain of the NMOSFET 311D. The gate of the PMOSFET 314D is connected to the input end of the clock signal CLK3.

  The source of the PMOSFET 315D is connected to the power supply end. The drain of the PMOSFET 315D is connected to the drain of the NMOSFET 312D. The gate of the PMOSFET 315D is connected to the input end of the clock signal CLK3.

  As described above, the latch-type preamplifier unit 310 of the present embodiment synchronizes with the main differential stage MS (NMOSFETs 311 to 313 and PMOSFETs 314 and 315) operating in synchronization with the inverted clock signal CLK3B and the clock signal CLK3. And a dummy differential stage DS (NMOSFETs 311D to 313D and PMOSFETs 314D and 315D) operating in reverse phase to the main differential stage MS.

  FIG. 9 is a diagram showing that the input error due to the kickback noise is eliminated, sequentially from the top, the inverted clock signal CLK3B, the DAC output voltage DACOUT, the reference voltage VCMOUT, and the positive side pre-output signal PREOUTP and the negative side. The pre-output signal PREOUTM is depicted.

  As shown in the figure, with the latch-type preamplifier unit 310 of this embodiment, kickback noises of the DAC output voltage DACOUT and the reference voltage VCMOUT can be canceled without providing a buffer in the previous stage. Therefore, the conversion accuracy of the successive approximation ADC 1 can be improved without unnecessarily increasing the power consumption.

  However, in the latch-type preamplifier unit 310 of this embodiment, the drains of the NMOSFETs 313, 311D, and 312D become high impedance nodes when the clock signal CLK3 is fixed at high level (= sampling period TS of successive approximation ADC 1). . Therefore, each of node potentials VA to VC has an indefinite value.

  FIG. 10 is a diagram showing how node potentials VA to VC have undefined values, and from top to bottom, clock signal CLK3, inverted clock signal CLK3B, DAC output voltage DACOUT, reference voltage VCMOUT, node potentials VA to VC, And the positive side pre-output signal PREOUTP and the negative side pre-output signal PREOUTM are depicted.

  As shown by the broken line frames α, β and γ in the figure, when the clock signal CLK3 is fixed at high level, the node potentials VA to VC become indeterminate values, so the operation of the latch type preamplifier portion 310 becomes unstable. I will. Below, 2nd Embodiment which can solve such a subject is explained in full detail.

<Latch Type Preamplifier Part (Second Embodiment)>
FIG. 11 is a view showing a second embodiment of the latch-type preamplifier unit 310. As shown in FIG. The latch-type preamplifier unit 310 according to the present embodiment is further based on the first embodiment (FIG. 8), and further includes an NMOSFET 316 and PMOSFETs 317 and 318.

  The drain of the NMOSFET 316 is connected to the drain of the NMOSFET 313. The source of the NMOSFET 316 is connected to the ground terminal. The gate of the NMOSFET 316 is connected to the input end of the clock signal CLK1. Therefore, the NMOSFET 316 turns on when CLK1 = H and turns off when CLK1 = L. That is, the NMOSFET 316 functions as a pull-down element for setting the drain of the NMOSFET 313 to a fixed potential (= GND) in the sampling period (CLK1 = H) of the successive approximation ADC 1.

  The source of the PMOSFET 317 is connected to the power supply end. The drain of the PMOSFET 317 is connected to the drain of the NMOSFET 311D. The gate of the PMOSFET 317 is connected to the input end of the inverted clock signal CLK1B. Therefore, the PMOSFET 317 turns on when CLK1B = L and turns off when CLK1B = H. That is, the PMOSFET 317 functions as a pull-up element for setting the drain of the NMOSFET 311 D to a fixed potential (= AVDD) in the sampling period (CLK 1 B = L) of the successive approximation type ADC 1.

  The source of the PMOSFET 318 is connected to the power supply end. The drain of the PMOSFET 318 is connected to the drain of the NMOSFET 312D. The gate of the PMOSFET 318 is connected to the input end of the inverted clock signal CLK1B. Therefore, the PMOSFET 318 turns on when CLK1B = L and turns off when CLK1B = H. That is, the PMOSFET 318 functions as a pull-up element for setting the drain of the NMOSFET 312 D to a fixed potential (= AVDD) in the sampling period (CLK 1 B = L) of the successive approximation ADC 1.

  FIG. 12 is a diagram showing how node potentials VA to VC become fixed values, and from the top, clock signal CLK1, clock signal CLK3, DAC output voltage DACOUT, reference voltage VCMOUT, node potentials VA to VC, and The positive side pre-output signal PREOUTP and the negative side pre-output signal PREOUTM are depicted.

  In the sampling period (CLK1 = H) of successive approximation ADC 1 as shown by broken line frames α, β and γ in the figure, even if clock signal CLK3 is fixed at high level, node potentials VA to VC It becomes a fixed value. Therefore, the operation of the latch-type preamplifier unit 310 can be stabilized.

<Other Modifications>
In addition to the embodiments described above, various technical features disclosed in the present specification can be modified in various ways without departing from the scope of the technical creation. For example, mutual replacement of a bipolar transistor and a MOS field effect transistor or logic level inversion of various signals is optional. That is, the above embodiment should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is not limited to the above embodiment, and the claims It should be understood that the scope and the meaning and meaning of the scope and all the modifications that fall within the scope are included.

  The invention disclosed herein can be used, for example, for a latched comparator used as one component of a successive approximation ADC.

1 Successive approximation ADC
100 CDAC
101P, 101M capacitor 111P to 115P capacitor 111M to 115M capacitor 121P to 127M capacitor 121P to 127M capacitor 131P, 131M capacitor 141 to 145 selector 151 to 157 selector 171P PMOSFET
171M NMOSFET
181P, 181M switch 200 reference voltage generator 211 PMOSFET
212 NMOSFET
213, 214 switches 215, 216 capacitors 300 latched comparators 310 latch type preamplifiers 311, 312, 313 NMOSFETs
314, 315 PMOSFET
316 NMOSFET (pull-down MOSFET)
317, 318 PMOSFET (pull-up MOSFET)
311D, 312D, 313D NMOSFET
314D, 315D PMOSFET
320 calibration unit 321, 322 capacitor 330 latch unit 340 SR latch unit 341, 342 inverter 343, 344 NAND
400 register 500 latch output part 600 controller MS main differential stage DS dummy differential stage

Claims (10)

A latch-type preamplifier unit that generates a positive side pre-output signal and a negative side pre-output signal by sequentially amplifying the difference value between the DAC output voltage and the reference voltage;
A latch unit that generates a positive latch output signal and a negative latch output signal by sequentially comparing the positive pre-output signal and the negative pre-output signal;
An SR latch unit that latches and outputs a comparison output signal according to the positive latch output signal and the negative latch output signal;
Have
A latched comparator used in a successive approximation ADC,
The latch type preamplifier unit
A main differential stage that receives the DAC output voltage and the reference voltage and outputs the positive side pre-output signal and the negative side pre-output signal;
A dummy differential stage that receives the DAC output voltage and the reference voltage and operates in reverse phase to the main differential stage;
And a latched comparator.   The latch type preamplifier unit has a function of setting the high impedance node of each of the main differential stage and the dummy differential stage to a fixed potential during a sampling period of the successive approximation ADC. The latched comparator according to 1. The main differential stage is
A first NMOSFET having a drain connected to the output of the negative side pre-output signal and a gate connected to the input of the DAC output voltage;
A second NMOSFET having a drain connected to the output end of the positive side pre-output signal and a gate connected to the input end of the reference voltage;
A third NMSOFET having a drain connected to a source of each of the first NMOSFET and the second NMOSFET, a source connected to a ground terminal, and turned off in a first phase and turned on in a second phase;
A first PMOSFET having a source connected to the power supply end and a drain connected to the drain of the first NMOSFET to be turned on in the first phase and turned off in the second phase;
A second PMOSFET having a source connected to the power supply terminal and a drain connected to the drain of the second NMOSFET to be turned on in the first phase and turned off in the second phase;
Including
The dummy differential stage is
A fourth NMOSFET having a gate connected to the input end of the DAC output voltage;
A fifth NMOSFET having a gate connected to the input end of the reference voltage;
A sixth NMSOFET having a drain connected to a source of each of the fourth NMOSFET and the fifth NMOSFET, a source connected to the ground terminal, and turned on in the first phase and turned off in the second phase;
A third PMOSFET having a source connected to the power supply terminal and a drain connected to the drain of the fourth NMOSFET to be turned off in the first phase and turned on in the second phase;
A fourth PMOSFET having a source connected to the power supply terminal and a drain connected to the drain of the fifth NMOSFET to be turned off in the first phase and turned on in the second phase;
The latched comparator according to claim 1 or claim 2, comprising The latch type preamplifier unit
A seventh NMOSFET having a drain connected to the drain of the third NMOSFET and a source connected to the ground terminal to turn on during a sampling period of the successive approximation ADC;
A fifth PMOSFET whose source is connected to the power supply terminal and whose drain is connected to the drain of the fourth NMOSFET to be turned on during the sampling period of the successive approximation ADC;
A sixth PMOSFET whose source is connected to the power supply terminal and whose drain is connected to the drain of the fifth NMOSFET and turned on during the sampling period of the successive approximation ADC;
The latched comparator according to claim 3, comprising:   The latched comparator according to any one of claims 1 to 4, further comprising: a calibration unit that calibrates the positive side pre-output signal and the negative side pre-output signal.   The latched comparator according to claim 5, wherein the calibration unit adjusts capacitance values of capacitors respectively connected to a positive output terminal and a negative output terminal of the latch-type preamplifier unit. A capacitor array DAC that generates a DAC output voltage for bit determination by sampling an analog input signal using a plurality of capacitors;
A reference voltage generation unit that generates a predetermined reference voltage;
The latched comparator according to any one of claims 1 to 6, wherein a comparison output signal is generated by sequentially comparing the DAC output voltage and the reference voltage.
A register for storing the comparison output signal;
A latch output unit for parallelly outputting all bits simultaneously as a digital output signal of comparison output signals for a plurality of bits stored in the register;
A controller that receives the feedback input of the comparison output signal stored in the register and controls the capacitor array DAC;
Successive approximation ADC characterized by having. The capacitor array DAC is
Positive coupling capacitor and negative coupling capacitor;
A first positive capacitor group whose first end is connected to the first end of the positive coupling capacitor;
A first negative capacitor group whose first end is connected to the first end of the negative coupling capacitor;
A second positive capacitor group whose first end is connected to the second end of the positive coupling capacitor;
A second negative capacitor group whose first end is connected to the second end of the negative coupling capacitor;
A first selector group connecting a second end of each of the first positive side capacitor group and the first negative side capacitor group to any one of the input end of the analog input signal, the power supply end, and the ground end;
A second selector group in which the second end of each of the second positive capacitor group and the second negative capacitor group is connected to any one of the input end of the analog input signal, the power supply end, and the ground end;
A PMOSFET connected between the second end of the positive coupling capacitor and the power supply end;
An NMOSFET connected between the second end of the negative coupling capacitor and the ground end;
A positive switch connected between the second end of the positive coupling capacitor and the output of the DAC output voltage;
A negative switch connected between the second end of the negative coupling capacitor and the output of the DAC output voltage;
The successive approximation ADC according to claim 7, characterized in that   The first positive capacitor group, the first negative capacitor group, the second positive capacitor group, and the second negative capacitor group each have a capacitance value weighted at a predetermined ratio. The successive approximation ADC according to claim 8, characterized in that: The reference voltage generation unit
A PMOSFET whose source is connected to the power supply terminal,
An NMOSFET whose source is connected to the ground terminal,
A first switch having a first end connected to the drain of the PMOSFET and a second end connected to the output end of the reference voltage;
A second switch having a first end connected to the drain of the NMOSFET and a second end connected to the output end of the reference voltage;
A first capacitor having a first end connected to the drain of the PMOSFET and a second end connected to the ground end;
A second capacitor having a first end connected to the drain of the NMOSFET and a second end connected to the ground end;
The successive approximation ADC according to claim 8 or 9, characterized in that

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