JP5210289B2 - Successive comparison type A / D converter - Google Patents

Description

  The present invention relates to an A / D converter applied to an input circuit of a digital device, and more particularly to a successive approximation A / D converter (A / D converter) that operates at high speed.

As a conventional successive approximation A / D converter, for example, the one shown in Non-Patent Document 1 below has been proposed.
FIG. 10 is a configuration diagram of a conventional successive approximation A / D converter based on the principle described in Non-Patent Document 1.
The successive approximation A / D converter converts an analog input signal Ain into an n-bit (n: natural number of 3 or more) digital output Vout. Therefore, it has one capacitor 506_1 whose electrostatic capacitance is set to the reference capacitance C. Further, each of the capacitances is set to a capacitance “C / 2,..., C / 2 ⁽ⁿ⁻²⁾ ” in which the reference capacitance C is weighted stepwise by the reciprocal of the power of 2 ^(n−2). ) Capacitors 506_2,... 506_ (n−1). Further, the capacitor has one capacitor 506_n whose capacitance is set to a capacitance “C / 2 ⁽ⁿ⁻²⁾ ” obtained by weighting the reference capacitance C by “1/2 ⁽ⁿ⁻²⁾ ”.

In addition, the right ends of the capacitors 506_1 to 506_ (n−1) and the capacitor 506_n are connected to a storage node (SN in FIG. 10) that can store charges.
The left ends of the capacitors 506_1 to 506_ (n-1) are connected to the terminals O of the switch groups 505_1, 505_2, ..., 505_ (n-1), respectively.
The switch groups 505_1, 505_2,..., 505_ (n−1) have terminals C, P, and N in addition to the terminal O. The switch 503d_k (k is 1 to (n) according to the switching signal CTRL from the control unit 501. When the natural number (-1) is turned on, the terminal C and the terminal O are short-circuited.

Further, when the switch 503e_k is turned on, the terminal P and the terminal O are short-circuited, and when the switch 503f_k is turned on, the terminal N and the terminal O are short-circuited.
Two or more of the switches 503d_k, 503e_k, and 503f_k are not turned on at the same time.
The terminals C of the switch groups 505_1 to 505_ (n−1) and the left end of the capacitor 506_n are connected to the switch 503b and the switch 503c.

Then, when the switch 503 c is turned on, the terminal C of the switch 505_1~505_ (n-1), and the left end of the capacitor 506_N, is connected to the input node (Ain in Figure 7).
Further, if the switch 503 b is turned on, the terminal C of the switch 505_1~505_ (n-1), and the left end of the capacitor 506_N, is connected to the analog common voltage VC (for convenience VC = 0V).

The terminals P of the switch groups 505_1 to 505_ (n−1) are connected to the positive-side full-scale reference voltage VRP with reference to VC, and the terminals N of the switch groups 505_1 to 505_ (n−1) are based on VC. To the negative full-scale reference voltage VRN.
The right ends of the capacitors 506_1 to 506_ (n−1) and the right end of the capacitor 506_n are connected to the switch 503a and the inverting input terminal of the comparator 504 via the SN. When switch 503a is turned on, SN is shorted to VC. The output of the comparator 504 is represented by DO, and DO is input to the control unit 501 and the output register 502.

  The control unit 501 includes a combinational circuit and the like, and outputs a control signal CTRL that controls switching of the switch groups 505_1 to 505_ (n−1) and the switches 503a to 503c. Specifically, the control unit 501 generates a control signal CTRL based on the determination signal DO and sequentially switches the switch groups 505_1 to 505_ (n−1) to obtain an internal voltage VX corresponding to the analog input voltage Ain. A combination of signals CTRL is determined.

In addition, the control unit 501 outputs a trigger clock CLK to the comparator 504. The comparator 504 determines the magnitude of the SN voltage and the normal input node voltage VC (reference voltage) in synchronization with the CLK, and outputs “DO = H (1)” when “SN <VC”. When “SN> VC”, “DO = L (0)” is output.
The control unit 501 outputs a trigger clock CLK to the output register 502, and the comparator 504 outputs a determination signal DO to the output register 502.

  In the output register 502 according to CLK, “DN = 1” (N: N is a natural number of “1 to n”) when the determination signal “DO = 1”, and “DN” when the determination signal “DO = 0”. = 0 ”is held in the output register 502. Then, after the output register 502 determines n output values D1 to Dn in the comparator 504, the held D1 to Dn are output as a digital output signal Vout by a known method. .

Next, the operation of the circuit when “n = 6” will be described with reference to FIG.
Here, FIG. 11A is a diagram illustrating an example in which the voltage of the inversion polarity of the voltage of the storage node SN, which is the determination target voltage, is plotted. In FIG. 11A, the vertical axis represents voltage, the horizontal axis represents time, and the MSB determination time of the comparator 504 is “t = 0”. FIG. 11B is a diagram illustrating an example of a change in the CLK output from the control unit 501 after time “t = 0”, and represents a determination timing of the comparator 504 at regular intervals. FIG. 11C is a diagram illustrating an example of the value of the output determination signal DO of the comparator 504.

FIG. 11 shows a case where “VRP−VC = VC−VRN = VR” as an example and the input voltage Ain of “Ain = (10.8 / 16) × VR” is sampled.
When the voltages of the capacitors 506_1 to 506_n follow the analog input voltage Ain as an initial state, the switches 503a to 503c and the switch groups 505_1 to 505_ (n−1) are in a state in which the switch 503a and the switch 503c are turned on. The switch 503b is turned off. In the switch groups 505_1 to 505_ (n-1), the switches 503d_1 to 503d_ (n-1) are turned on, and the switches 503e_1 to 503e_ (n-1) and 503f_1 to 503f_ (n-1) are turned off. It becomes a state.

  At the time when the analog input voltage Ain is sampled (discretized) by the capacitors 506_1 to 506_n, the switch 503a is turned off by the control signal CTRL, and the switch 503c is turned off immediately. When the switch 503b is subsequently turned on, the polarity of the sampled Ain is inverted and appears as -Ain [V] on the storage node SN. Here, the switch 503b and the switch 503c have a non-overlapping relationship that does not turn on at the same time.

  When the charge redistribution is sufficiently performed after the switch is switched and the parasitic capacitance is ignored for convenience, the first determination rising clock (FIG. 11B) is reached at the time when the voltage of the storage node SN sufficiently converges to “−Ain”. T = 0) is input to the comparator 504. Then, the comparator 504 compares the voltage of the storage node SN with the reference voltage VC by the first determination rising clock. The comparator 504 outputs “DO = 1” when “−Ain <VC”, that is, “Ain> VC”, and “DO = 0 when“ −Ain> VC ”, that is,“ Ain <VC ”. Is output.

When the first determination result is “DO = 1”, the control unit 501 controls the switch group 505_1, the switch 503d_1 is turned off, and the switch 503e_1 is turned on. As a result, the voltage of the storage node SN becomes “− (Ain−VR / 2) [V]” by charge redistribution.
When the first determination result is “DO = 0”, the control unit 501 controls the switch group 505_1, the switch 503d_1 is turned off, and the switch 503f_1 is turned on. As a result, the voltage of the storage node SN becomes “− (Ain + VR / 2) [V]” by charge redistribution.

Similarly, the voltage of the storage node SN is compared with the reference voltage VC at the time when the yth determination rising clock which is the yth determination rising clock (y is a natural number of 2 to (n-1)) is input. The switch group 505 — y is controlled according to the determination result.
Then, the voltage of the storage node SN is compared with the reference voltage VC at the time when the (n−1) th determination rising clock is input, and the switch group 505_ (n−1) is controlled according to the result. At the time when the n determination rising clock is input, the voltage of the storage node SN and the reference voltage VC are compared. As a result, the 1-n bit successive approximation operation is completed, and n-bit output data Vout is output from the output register 502.

  As an example, FIG. 11A shows the transition of the determination target signal when “SN = − (10.8 / 16) × VR” is sampled. Since “− (10.8 / 16) × VR <VC” in the first determination rising clock, “D1 = 1” is output as shown in FIG. As a result, the switch group 505_1 is controlled, and the potential of the storage node SN becomes “SN = − (10.8 / 16) × VR + VR / 2 = − (2.8 / 16) × VR”.

Subsequently, since “− (2.8 / 16) × VR <VC” in the second determination rising clock, “D2 = 1” is output as shown in FIG. As a result, the switch group 505_2 is controlled, and the potential of the storage node SN becomes “SN = − (2.8 / 16) × VR + VR / 4 = (1.2 / 16) × VR”.
Subsequently, the same processing is repeated up to (n−1) times. When Dn is determined by the nth determination rising clock and the n-bit successive approximation operation is completed, the output register 502 is based on the stored D1 to Dn. Output n-bit output data Vout.

  Here, FIG. 12 is a diagram illustrating an example of Vout output based on the determination results D1 to D6 of the upper 6 bits. As shown in FIG. 11C, the determination result of the upper 6 bits is “D1 =“ 1 ”, D2 =“ 1 ”, D3 =“ 0 ”, D4 =“ 1 ”, D5 =“ 0 ”, D6 = “1” ”. As shown in FIG. 12, the output register 502 arranges these in order from the upper bits, and outputs the upper 6 bits “110101” of Vout. Here, the output register 502 is configured by a shift register, for example.

The operation principle of the conventional successive approximation A / D converter has been described above.
In the conventional successive approximation type A / D converter, for example, a method as shown in the following Patent Document 1 has been proposed as a method for realizing high speed by minimizing each bit determination time.
FIG. 13 shows an embodiment of the invention described in Non-Patent Document 1. Here, FIG. 13 is a diagram illustrating an internal structure of the control unit 501 for minimizing each bit determination time of the successive approximation A / D converter.

As illustrated in FIG. 13, the control unit 501 includes a shift register 701 and logic circuits 702_1 to 702_ (n−1). In the example of FIG. 12, the case of “n = 6” is illustrated. Here, an output clock from a sufficiently high-speed oscillator is input to the shift register 701.
The logic circuits 702_1 to 702_5 are realized by AND gates, and the output of the logic circuit 702_1 determines the switching time of the switch group 505_1 and the determination time width of the corresponding bit.

Further, the output of the logic circuit 702_2 determines the switching time of the switch group 505_2 and the determination time width of the corresponding bit, and the output of the logic circuit 702_2 determines the switching time of the switch group 505_3 and the determination time width of the corresponding bit.
The output of the logic circuit 702_4 determines the switching time of the switch group 505_4 and the determination time width of the corresponding bit, and the output of the logic circuit 702_5 determines the switching time of the switch group 505_5 and the determination time width of the corresponding bit.

The input widths of the logic circuits 702_1 to 702_5 configured by AND gates so that the switching time of the switch groups 502_1 to 502_5 and the width of the determination time of the corresponding bit become the “minimum necessary time” shown in Patent Document 1. (The number of N1 to N5 in FIG. 13) is determined.
14 shows an output waveform of a sufficiently high-speed oscillator (high-speed oscillator), output waveforms of the logic circuits 702_1 to 702_5 generated by the control unit 501 in FIG. 13, and a comparator 504 and an output register 502 in FIG. It is a figure which shows an example of the trigger clock CLK which operates.

  In FIG. 14, the H period (period in which the signal is at a high level) of the control signals CTRL 502_1 to 502_5 represents the CTRL control period for the switch groups 502_1 to 502_5, respectively. The CTRL control period includes switching of the switch groups 502_1 to 502_5 and the determination time of the corresponding bit. The CTRL control period is the minimum time required for switch switching and bit determination.

FIG. 15 shows an example of a timing chart of each output signal when similar CTRL control is realized using a variable frequency oscillator instead of a high-speed oscillator.
As described above, in the conventional successive approximation type A / D converter, in the method of realizing high speed by minimizing the determination time of each bit, a high-speed oscillator sufficiently fast with respect to the determination clock or a variable frequency Requires an oscillator.

Japanese Patent Laid-Open No. 51-15363

“Introduction to Illustrated A / D Converter”, Ohm, p. 99-104

  For example, in the case of a successive approximation A / D converter with an output rate of 1 MHz and a resolution of 14 bits, the operation clock is 15 MHz. In this successive approximation A / D converter, in order to realize the drive control of the switch group based on the “minimum time T” shown in Patent Document 1, for example, it is assumed that a clock 100 times the operation clock is required. For example, a high-speed oscillator having an oscillation frequency of 1.5 GHz is required. However, it is impractical to employ a high-speed oscillator of 1.5 GHz in the successive approximation A / D converter.

In order to realize a high-speed oscillator with an oscillation frequency as high as 1.5 GHz, for example, when an LC oscillator is used, an increase in the area when the semiconductor is integrated cannot be avoided.
On the other hand, when a variable frequency oscillator is used instead of a high-speed oscillator, a complicated circuit is required to realize the variable frequency oscillator, making the design difficult, increasing the area when semiconductors are integrated, and driving power. The increase of can not be avoided.
Therefore, the present invention has been devised to solve these problems, and is a successive approximation type A suitable for realizing drive control of a switch group with a minimum necessary time T with a simple circuit configuration. An object is to provide a / D converter.

[Invention 1] In order to achieve the above object, a successive approximation A / D converter according to Invention 1 comprises:
A charge comparison type successive approximation A / D converter that converts an analog input signal into a digital output signal of n bits (n is a natural number of 3 or more),
One end of each output side is commonly connected, and the reference capacitance C is set such that the capacitance is set to the reference capacitance C and the combined capacitance is “C−C / 2 ⁿ⁻² ”. Second to (n-1) th capacitors set to a capacity (C / 2 ^m (m is a natural number of 1 to (n-2))) weighted stepwise by the reciprocal of the power of 2; N capacitors with the nth capacitor set to a capacitance weighted by “1/2 ⁿ⁻² ” of the reference capacitance C;
The first to (n-1) th capacitors are connected to the other ends of the capacitors, respectively, and the connection between the first to (n-1) th capacitors, the analog signal input unit, and a node having a predetermined potential is switched. First to (n-1) switch groups;
A comparator that compares an input potential based on a holding potential of the n capacitors with a reference potential and outputs a determination signal according to the comparison result;
A control unit that controls a switching operation of the first to (n-1) th switch groups and a comparison determination operation of the comparator so that the comparison determination operation is sequentially performed in order from a predetermined bit;
The controller is
A counter circuit for counting clock signals;
A delay circuit that delays the clock signal by a delay amount necessary for a driving time of a switch group corresponding to a count value of the counter circuit;
A control signal generation circuit that generates a control signal for controlling the switching operation of the first to (n-1) th switch groups based on the clock signal delayed by the delay circuit;
The delayed clock signal is supplied to the comparator to control the operation of the comparator, and the generated control signal is supplied to the (n-1) switch groups to control the switching operation of the switch group. To do.

  With such a configuration, when the clock signal is input, the clock signal can be counted by the counter circuit. Further, when the counting of the clock signal is started, the delay circuit can delay the clock signal by a delay amount necessary for the driving time of the switch group corresponding to the count value of the counter circuit. Further, when the clock signal is delayed (including the delay amount “0”), the control signal generation circuit performs the first to (n−1) th based on the delayed clock signal (hereinafter referred to as a delayed clock signal). ) Can generate a control signal for controlling the switching operation of the switch group. For example, a control signal that rises in response to the rising edge of the delayed clock signal and falls in response to the rising edge of the next delayed clock signal can be generated for the corresponding switch group. For the remaining switch groups, for example, a control signal that maintains the current state of on / off of the switch groups can be generated. Then, the delayed clock signal is supplied to the comparator to control the comparison determination operation of the comparator, and the generated control signal is supplied to the first to (n−1) th switch groups to provide the first to first ( The switching operation of the switch group n-1) can be controlled.

  Therefore, when the control signal is supplied to the switch group, the switching operation of the first to (n-1) th switch groups is controlled, and the on / off states of the switches constituting the switch group corresponding to the count value are controlled. Switches. The remaining switch groups maintain the current on / off state. On the other hand, when the delayed clock signal is supplied to the comparator, the comparator performs a comparison determination operation in accordance with, for example, the rising or falling edge of the delayed clock signal and outputs a determination signal.

For example, the driving time of the corresponding switch group includes the comparison determination time in the comparator, the time for switching the on / off state of each switch constituting the corresponding switch group based on the determination result, and the charge recycle after the switching. This is the total time taken to stabilize the input potential to the comparator due to the distribution. Among these, the time taken for the input potential to stabilize varies depending on the on / off state of the switches constituting each switch group.
In this case, the switching operation of the switch group is controlled in accordance with the next rising or falling edge of the delay clock so that the comparator can immediately perform the comparison determination operation for the next determination target bit. .

As described above, a corresponding switch can be obtained by combining a relatively simple circuit such as a counter circuit that counts a clock signal, a delay circuit that delays the clock signal, and a control signal generation circuit that generates a control signal based on the delayed clock signal. A control signal can be generated that brings the group into a drive state for the required time.
As a result, the “minimum required time T” of the above problem can be realized while suppressing the occurrence of an increase in area, an increase in driving power, a complicated design, and the like as compared with the conventional case. can get.

[Invention 2] Further, the successive approximation A / D converter of Invention 2 is the successive approximation A / D converter of Invention 1.
The time for driving the switch group defined by the control signal corresponding to the capacitor whose capacitance is weighted to C / 2 ^k (k is a natural number of k ≦ (n−2)), and the capacitance is C The delay circuit so that a time d which is a difference from a time for driving the switch group defined by the control signal corresponding to the capacitor weighted to / 2 ^k−1 becomes a time proportional to the natural logarithm “ln2”. Set the delay amount.

With such a configuration, there is an effect that an appropriate delay amount can be set as the delay amount corresponding to the drive time of each switch group.
Specifically, the time change of the voltage change amount of the signal input unit of the comparator connected to the common connection unit of the first to nth capacitors is, for example, when the signal input unit can hold a charge. When the amount of change in voltage of the part is represented by A, “A × (1-exp (−t / τ))” is obtained. Here, τ is a value depending on the capacitance of the capacitor and the on-resistance of the switches constituting the switch group.

When the driving time of a certain switch group is T1, and the difference between the voltage change amount of the signal input unit at “t = T1” and the target voltage change amount “A / 2 ^k−1 ” is equal to or less than ΔV, T1 is , “Τ × ln (A / ΔV)”.
In the present invention, the capacitance of the second to (n−1) th capacitors is set to a value obtained by weighting the reference capacitance C by the reciprocal of a power of 2. Therefore, if τ is a constant value, “C The voltage change amount of the signal input section after the connection switching from the capacitor of “/ 2 ^k−1 ” to the capacitor of “C / 2 ^k ” is “A / 2”. Therefore, the amount of change d with respect to the driving time T1 can be expressed as “τ × ln2” in natural logarithm.

[Invention 3] Further, the successive approximation A / D converter of Invention 3 is the successive approximation A / D converter of Invention 1 or 2,
When the n bits are 2 (m + 1) bits (m is a natural number), the rising edge of the clock signal at the time of comparing and determining the most significant bit is set as the first rising edge, and z (z is 2 ≦ z ≦ 2) (M + 1) (natural number) The clock signal is delayed by a delay amount calculated by the following equation (1) with respect to the rising edge.
Delay amount = {(z−1) × m− (z−2) × (z−1) / 2} × d (1)
With such a configuration, in the n-bit successive approximation A / D converter, it is possible to easily set an appropriate delay amount as a delay amount necessary for the determination operation of each bit. .

[Invention 4] Further, the successive approximation A / D converter according to Invention 4 is the successive approximation A / D converter according to any one of Inventions 1 to 3,
The comparator has an input potential which is a difference potential between a holding potential of the n capacitors and a holding potential of a storage node capable of holding a charge formed in a signal input portion of the comparator, and a reference potential. It comes to compare.
In such a configuration, after switching the switch group, after the n capacitors are redistributed, the storage node has the holding potential of the n capacitors after the charge redistribution and the holding potential of the storage node before the switching. Can be held as the input potential of the comparator.

It is a figure which shows the structure of the successive approximation type A / D converter 1 of this invention. (A) is a figure for demonstrating the minimum time required for each bit determination time, (b) is a figure for demonstrating the difference of the control period for every bit determination. 2 is a block diagram showing an internal configuration of a control unit 101. FIG. 3 is a block diagram showing an internal configuration of a delay amount control circuit 301. FIG. It is a figure which shows an example of the relationship between a counter value and an additional delay amount. 3 is a diagram illustrating an example of a circuit configuration of an arbitrary delay circuit 302. FIG. It is a figure which shows an example of the relationship between a counter value and delay amount control signal (phi) 1-phi4. 3 is a block diagram showing an internal configuration of a control signal generation circuit 303. FIG. 3 is an example of a timing chart of various input / output signals of a control unit 101. It is a block diagram of the conventional successive approximation type A / D converter based on the principle described in the nonpatent literature 1. (A) is a figure which shows an example which plotted the voltage of the inversion polarity of the voltage of storage node SN which is a to-be-determined voltage, (b) is the time "t = of CLK output from the control part 501. It is a figure which shows an example of the change after "0", (c) is a figure which shows an example of the value of the output determination signal DO of the comparator 504. It is a figure which shows an example of Vout output based on the determination result D1-D6 of upper 6 bits. It is a figure which shows the internal structure of the control part 501 for making each bit determination time of a successive approximation type A / D converter minimum. It is a figure which shows an example of clock CLK which operates the output of a high-speed oscillator, the output of AND gate 702_1-702_5 produced | generated by the control part 501 and the comparator 504 and the output register 502. FIG. It is a figure which shows an example of the timing chart of each output signal at the time of implement | achieving using a variable frequency oscillator.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 9 are diagrams showing an embodiment of a successive approximation A / D converter according to the present invention.
First, the configuration of the successive approximation A / D converter according to the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a configuration of a successive approximation A / D converter 1 of the present invention.
The successive approximation A / D converter 1 performs A / D conversion of an analog input signal Ain into a digital output signal Vout of n bits (n is a natural number of 3 or more), as shown in FIG. The control unit 101, the output register 102, and the comparator 104 are configured.

Further, the successive approximation A / D converter 1 includes switches 103a to 103c, switch groups 105_1 to 105_ (n−1), capacitors 106_1 to 106_n, and a storage node SN.
The capacitor 106_1 is a capacitor whose electrostatic capacity is set to the reference capacitance C. Capacitors 106_2 to 106_ (n−1) have capacitances (C / 2, C / 4,..., C / 2 ⁿ⁻⁾ in which the capacitance is weighted by the reciprocal of the reference capacitance C to the power of 2, respectively. ² ) Capacitor set to. Further, the capacitor 106_n has the same capacitance as the capacitor 106_ (n-1), and has a capacitance “C / 2 ^n-2 ” obtained by weighting the reference capacitance C by “1/2 ^n-2 ”. It is.

For example, when “n = 6”, the capacitances of the capacitors 106_1 to 106_6 are “C, C / 2, C / 4, C / 8, C / 16, C / 16”, respectively.
Each of the switch groups 105_1 to 105_ (n−1) includes three switches, which are a switch 103d_k (k is a natural number of 1 to (n−1)), a switch 103e_k, and a switch 103f_k. .

Specifically, the switch groups 105_1 to 105_ (n−1) are configured to include switches 103d_k to 103f_k having the same numbers at the end (1 to (n−1)) as the switch groups.
For example, the switch group 105_1 includes three switches, a switch 103d_1, a switch 103e_1, and a switch 103f_1. In addition, the switch group 105_ (n−1) includes the switch 103d_ (n−1), the switch 103e_ (n−1), and the switch 103f_ (n−1).

Further, the switches 103d_k to 103f_k are configured by switching elements such as MOS transistors, and include a common terminal O to which each right end is connected.
A terminal C is formed at the left end of the switches 103d_1 to 103d_ (n−1), a terminal P is formed at the left end of the switches 103e_1 to 103e_ (n−1), and a left end of the switches 103f_1 to 103f_ (n−1). Has a terminal N formed thereon.
The common terminals O of the switches 103d_k to 103f_k are each connected to the left end of the kth capacitor.

Specifically, the common terminal O of the switches 103d_1 to 103f_1 is at the left end of the capacitor 106_1, the common terminal O of the switches 103d_2 to 103f_2 is at the left end of the capacitor 106_2,..., The switches 103d_ (n−1) to 103f_ ( The common terminal O of (n-1) is connected to the left end of the capacitor 106_ (n-1).
A terminal C of the switches 103d_1 to 103d_ (n−1) is connected to the right ends of the switches 103b and 103c.

The terminals P of the switches 103e_1 to 103e_ (n-1) are connected to a power supply node (hereinafter referred to as a power supply node VRP) of the positive full-scale reference potential VRP with respect to the potential VC.
Further, the terminals N of the switches 103f_1 to 103f_ (n−1) are connected to a power supply node (hereinafter referred to as a power supply node VRN) of the negative full-scale reference potential VRN with reference to VC.
In other words, in the present embodiment, the range from the negative potential VRN to the positive potential VRP is the full scale reference potential range with the potential VC (0 [V] in the present embodiment) as the reference (center).

The switches 103d_1 to 103d_ (n−1) switch the on / off state in accordance with the control signal CTRL from the control unit 101, and short-circuit the terminal C and the terminal O when in the on state. Thus, the left ends of the capacitors 106_1 to 106_ (n−1) are connected to the left end of the capacitor 106_n and the right ends of the switches 103b and 103c.
Further, the switches 103e_1 to 103e_ (n−1) switch on / off according to the control signal CTRL from the control unit 101, and short-circuit the terminal P and the terminal O when in the on state. Thereby, the left ends of the capacitors 106_1 to 106_ (n−1) are connected to the power supply node VRP.

The switches 103f_1 to 103f_ (n−1) are switched on / off according to the control signal CTRL from the control unit 101, and short-circuit the terminal N and the terminal O when in the on state. Thereby, the left ends of the capacitors 106_1 to 106_ (n−1) are connected to the power supply node VRN.
The storage node SN is a node that can store charges, formed at a connection point between the right ends of the capacitors 106_1 to 106_n, the inverting input terminal of the comparator 104, and the upper end of the switch 103a.

  The switch 103a is composed of a switching element such as a MOS transistor, and has an upper end connected to the storage node SN and a lower end connected to a power supply node having a potential VC (hereinafter referred to as a power supply node VC). Then, the on / off state is switched according to the control signal CTRL from the control unit 101, and the storage node SN is connected to the power supply node VC in the on state.

Switch 103 c is composed of switching elements such as MOS transistors, and the right end of the rightmost switch 103 b is connected to the terminal C of the switch 103d_1~103d_ (n-1), the input left end of the analog input signal Ain Connected to the node. Then, the on / off state is switched in accordance with the control signal CTRL from the control unit 101, and the terminals C of the switches 103d_1 to 103d_ (n−1) are connected to the input node of the analog input signal A in in the on state. To do.

Switch 103 b is composed of switching elements such as MOS transistors, the right end is connected to the terminal C of the right and the switch 103d_1~103d_ switch 103 c (n-1), it is connected the left end to the power supply node VC . Then, on / off is switched according to the control signal CTRL from the control unit 101, and the terminals C of the switches 103d_1 to 103d_ (n−1) are connected to the power supply node VC in the on state.

Note that the switching operation is controlled (non-overlap control) so that the switch 103b and the switch 103c are not simultaneously turned on.
The control unit 101 has a function of generating control signals CTRL105_1 to 105_ (n−1) for controlling the switching operations of the switches 103a to 103c and the switches constituting the switch groups 105_1 to 105_ (n−1). Yes. Further, the control unit 101 has a function of generating a delayed clock signal DCLK that controls operations of the comparator 104 and the output register 102.

The output register 102 holds a value (DO1 to DOn) of a signal indicating the comparison determination result output from the comparator 104, and an n-bit digital output signal using a known method based on the held determination results DO1 to DOn. And a function of outputting Vout.
The comparator 104 compares the input potential VSN of the inverting input terminal with the reference potential VC according to the rising edge of the delayed clock signal DCLK from the control unit 101. When “VSN <VC”, a high-level signal (“DON = 1”) is output as the determination output DON (N is a natural number of 1 to n). When “VSN ≧ VC”, a low-level signal (“DON = 0”) is output as the determination output DON.

Next, the control signals CTRL 105_1 to 105_ (n−1) supplied from the control unit 101 to the switch groups 105_1 to 105_ (n−1) will be described with reference to FIG.
Here, FIG. 2A is a diagram for explaining the minimum time required for each bit determination time, and FIG. 2B is a diagram for explaining a difference in control period for each bit determination. .
The waveform shown in FIG. 2A is a waveform showing a part including a high level section of the control signals CTRL 105_1 to 105_ (n−1). This high level section (H section) represents the control period of the switch groups 105_1 to 105_ (n−1).
As shown in FIG. 2A, when the time of the control period (H section) is Tk, the section of time Tk can be classified into three time sections of time Tc, time Tl, and time Ts_k. it can.

The time Tc is a finite time required for the determination by the comparator 104.
Note that the time Tc is the same for all the determinations from the first determination to the nth determination, which are the comparison determination operations of the comparator 104 from the first bit to the nth bit, in order from the upper bit.
In response to the determination result of the comparator 104, the control unit 101 outputs a control signal CTRL105_k for controlling the switch group 105_k to be switched, and the control signal CTRL105_k is reflected in the switch group 105_k so that the switch switching is performed. It is a finite time until The time Tl is the same for all determinations from the first determination to the nth determination.

The time Ts_k is a finite time until the connection destination at the left end of the capacitor 106_k is changed with the switching of the switch group 105_k and the voltage of the storage node SN is sufficiently settled by charge redistribution.
Note that the amount of charge redistributed for each bit determination from the 1st bit to the nth bit changes in the time Ts_k, and therefore a difference occurs for each bit determination.

For example, it is assumed that the switch 103d_1 in the switch group 105_1 is turned off and the switch 103e_1 or 103f_1 is turned on in the period of time Tl in accordance with the control signal CTRL105_1. By this switching process, the left end of the capacitor 106_1 is connected to either the power supply node VRP or VRN.
In this case, the charge redistribution caused by the switching of the switches 103d_1 to 103f_1 changes the voltage of the storage node SN by “+ VR / 2” or “−VR / 2”. In other words, the charge redistribution causes the movement of the charge amount corresponding to the potential displacement “+ VR / 2” or “−VR / 2”.

  Subsequently, it is assumed that the switch 103d_2 in the switch group 105_2 is turned off and the switch 103e_2 or 103f_2 is turned on in the section of the time Tl in accordance with the control signal CTRL 105_2 while keeping the switch state of the switch group 105_1. By this switching process, the left end of the capacitor 106_2 is connected to either the power supply node VRP or VRN.

In this case, the voltage of the storage node SN further changes by “+ VR / 4” or “−VR / 4” due to the charge redistribution caused by the switching of the switches 103d_2 to 103f_2. In other words, the charge redistribution causes the movement of the charge amount corresponding to the potential displacement “+ VR / 4” or “−VR / 4”.
As described above, since the amount of the electric charge that moves is changed by switching the switch, the time taken for the potential of the storage node SN to settle also changes.

  Here, when the time from the (p−1) th determination time to the pth determination time is expressed as T (p−1) (p is a natural number of 2 to n), for example, when “p = 2”, It is a time T1 from the first determination time to the second determination time. Further, in the case of “p = n”, it is a time T (n−1) from the (n−1) th determination time to the nth determination time. In this case, T1 = Tc + Tl + Ts_1 and T (n-1) = Tc + Tl + Ts_ (n-1).

  Next, based on FIG. 2B, the time required for settling the potential of the storage node SN by charge redistribution at time Ts_k will be described. In FIG. 2B, the horizontal axis represents time, and the vertical axis represents the amount of change in the voltage of the storage node SN. In the present embodiment, the settling accuracy required at the time of each bit determination is constant, and here is ΔV as an example.

After the first determination, the capacitance of the capacitor 106_1 that is switched by the switch group 105_1 at Ts_1 is C. When the amount of change in the voltage of the storage node SN with respect to the amount of change is represented by A, the time change of the amount of change in the voltage of the storage node SN Is expressed by the following equation.
Vsn = A × {1-exp (−t / τ)} (2)
Here, in the above equation (2), Vsn is the voltage change amount of the storage node SN, and τ is the on resistance of the switches constituting the capacitors 106_1 to 106_ (n−1) and the switch groups 105_1 to 105_ (n−1). Here, it is always a constant value for convenience.

As shown in FIG. 2B, the difference between the amount of change in the voltage of the storage node SN at “t = Ts_1 (k = 1)” and the target value “A / 2 ^(k−1) ” is ΔV or less. Therefore, the minimum required Ts_1 is expressed by the following equation (3).
ΔV ≧ A−A × {1-exp (−Ts — 1 / τ)}
A−ΔV ≦ A × {1−exp (−Ts — 1 / τ)}
Ts_1 ≧ τ × ln (A / ΔV) (3)
In the above equation (3), when “τ × ln (A / ΔV) = Tx” is set, the following equation (4) is obtained.
Ts_1 ≧ Tx (4)

After the second determination, the capacitance of the capacitor 106_2 switched by the switch group 105_2 at Ts_2 is “C / 2”, and the change amount of the SN voltage with respect to the change amount is represented by “A / 2”. The time change of the voltage change amount of SN is expressed by the following equation (5).
Ts_2 ≧ τ × {ln (A / ΔV) −ln2} (5)
In the above equation (5), when “τ × ln2 = d” is set, the following equation (6) is obtained.
Ts_2 ≧ Tx−d (6)

Similarly, after the (n−1) th determination, the capacitance of the capacitor 106_ (n−1) switched by the switch group 105_ (n−1) in Ts_ (n−1) is “C / 2 ⁽ⁿ⁻²⁾ ”. It is. Therefore, since the change amount of the voltage of the storage node SN with respect to the change amount is represented by “A / 2 ⁽ⁿ⁻²⁾ ”, the time change of the voltage change amount of the storage node SN is represented by the following equation (7). The
Ts_ (n−1)> Tx− (n−2) × d (7)
As described above, the time Tk is shortened by the constant time d when the determination bit is lowered by one bit. That is, the time Tk is shortened by a certain time d.

Next, a detailed configuration of the control unit 101 will be described with reference to FIGS.
Here, FIG. 3 is a block diagram showing an internal configuration of the control unit 101. FIG. 4 is a block diagram showing the internal configuration of the delay amount control circuit 301. FIG. 5 is a diagram illustrating an example of the relationship between the counter value and the additional delay amount. FIG. 6 is a diagram illustrating an example of a circuit configuration of the arbitrary delay circuit 302. FIG. 7 is a diagram illustrating an example of the relationship between the counter value and the delay amount control signals φ1 to φ4. FIG. 8 is a block diagram showing the internal configuration of the control signal generation circuit 303.

As shown in FIG. 3, the control unit 101 includes a delay amount control circuit 301, an arbitrary delay circuit 302, and a control signal generation circuit 303. The delay amount control circuit 301 and the arbitrary delay circuit 302 include A clock signal MCLK is supplied from an external oscillator.
As shown in FIG. 4, the delay amount control circuit 301 includes a counter 301a and a control circuit 301b.
The counter 301a counts the rising edge of the clock signal MCLK supplied from the oscillator, counts up from the initial value “0” by “1”, and resets to the initial value “0” with the count value (n−1). The up operation is repeated.

  Based on a count value (hereinafter referred to as a counter value) output from the counter 301a, the control circuit 301b arbitrarily sets the delay amount of the arbitrary delay circuit 302 to a delay amount set in advance corresponding to the counter value. The delay amount control signals φ1 to φL (L is a natural number and depends on the configuration of the arbitrary delay circuit) for controlling the operation of the delay circuit 302 are generated.

In the present embodiment, in the n-bit successive approximation A / D converter 1, as “n = 2 × (m + 1) (m is a natural number)”, as shown in FIG. Thus, an additional delay amount to be added to the clock signal MCLK is set.
Specifically, as shown in FIG. 5, when the counter value is “0”, the additional delay amount is “0”, when the counter value is “1”, the additional delay amount is “m × d”, and when the count value is “2”. Is set such that the additional delay amount is “(m + (M−1)) × d”,..., And when the counter value is “2 × (m + 1)”, the additional delay amount is “0”.
The relationship of FIG. 5 can be expressed by the following formula (8).
Additional delay amount = {(Z−1) × m− (Z−2) × (Z−1) / 2} × d (8)
In the above equation (8), Z is a counter value of the counter 301a and is a natural number of “0 to 2 × (m + 1)”.

Next, a configuration example of the arbitrary delay circuit 302 corresponding to the successive approximation A / D converter 1 when the number of bits n is 6 bits (m = 2) will be described with reference to FIG.
As shown in FIG. 6, the arbitrary delay circuit 302 includes a buffer circuit 304 </ b> _ <b> 1 to 304 </ b> _ <b> 3, each of which adds a delay amount d to an input signal as a delay circuit, and outputs a normal rotation; To 305_5. Note that the delay circuit is not limited to the buffer circuit that delays the input signal and outputs it in the normal direction, and other circuits such as an inverter circuit that delays and outputs the input signal may be used.

The input end of the buffer circuit 304_1 is connected to the right end of the switch 305_2, and the output end of the buffer circuit 304_1 is connected to the input end of the buffer circuit 304_2.
The output end of the buffer circuit 304_2 is connected to the left ends of the switches 305_3 and 305_5, and the right end of the switch 305_3 is connected to the input end of the buffer circuit 304_3.
The output end of the buffer circuit 304_3 is connected to the left end of the switch 305_4. The right end of the switch 305_4 is connected to the right ends of the switches 305_1 and 305_5. The left end of the switch 305_1 is the input node of the clock signal MCLK and the left end of the switch 305_2. And connected to.

Further, as shown in FIG. 6, the switch 305_1 is controlled by a delay amount control signal φ1, the switch 305_2 is controlled by a delay amount control signal φ2, and the switch 305_5 is controlled by a delay amount control signal φ3. The switches 305_3 and 305_4 are controlled by a delay amount control signal φ4.
Therefore, when the arbitrary delay circuit 302 has the configuration shown in FIG. 6, the delay amount control circuit 301 generates delay amount control signals φ1 to φ4 (L = 4).
When the number of bits n is 6, the relationship between the counter value, the on / off of the switches 305_1 to 305_5, and the additional delay amount is as shown in FIG.

Here, when n is 6, the delay amount control circuit 301 counts up one by one up to the counter value “5”, using the counter value 0 as an initial value, and resets the counter value “5” to “0”. Repeat the up operation.
Then, as shown in FIG. 7, when the counter value is “0” and “5”, the delay amount control signal φ1 for turning on the switch 305_1 so that the additional delay amount becomes “0”, and the switch Delay amount control signals φ2 to φ4 that turn off 305_2 to 305_5 are generated.

Further, when the counter value is “1” and “4”, the delay amount control signal φ1 for turning off the switch 305_1 and the switches 305_2 and 305_5 are turned on so that the additional delay amount becomes “2d”. The delay amount control signals φ2 and φ3 to be generated and the delay amount control signal φ4 to turn off the switches 305_3 and 305_4 are generated.
Further, when the counter value is “2” and “3”, the delay amount control signal φ1 for turning off the switch 305_1 and the delay for turning off the switch 305_5 so that the additional delay amount becomes “3d”. An amount control signal φ3 and delay amount control signals φ2 and φ4 that turn on the switches 305_2, 305_3, and 305_4 are generated.

Next, the internal configuration of the control signal generation circuit 303 will be described with reference to FIG.
As shown in FIG. 8, the control signal generation circuit 303 includes a control circuit 303a and a transmission path 303b for the delayed clock signal DCLK.
The control circuit 303a receives control signals CTRL105_1 to 105_ (n−1) for controlling the switching operation of the switch groups 105_1 to 105_ (n−1) based on the comparison determination result Dk from the comparator 104 and the delayed clock signal DCLK. Generate.

Note that the control signals CTRL 105_1 to 105_ (n−1) are signals for controlling the switching operation of the switches constituting the switch groups 105_1 to 105_ (n−1) having the same suffix number.
The transmission path 303 b is a path for supplying the delayed clock signal DCLK supplied from the arbitrary delay circuit 302 to the output register 102 and the comparator 104 as they are.

Specifically, for the switch group 105_k to be switched, the control circuit 303a generates a control signal CTRL105_k that rises at the rising edge of the delayed clock signal DCLK and falls at the next rising edge of the delayed clock signal DCLK.
Further, the counter values “1” to “n−1” respectively correspond to the switch groups 105_1 to 105_ (n−1) having the same end number.

For example, when the counter value is “1”, the switch group to be switched is the switch group 105_1.
Then, the control circuit 303a generates the control signal CTRL105_1 that rises at the first rising edge of the delayed clock signal DCLK supplied from the arbitrary delay circuit 302 and falls at the second rising edge. That is, the control signal CTRL105_1 has a signal waveform that is at a high level in a period (time Tk) from the first rising edge to the second rising edge of the delayed clock signal DCLK.

Further, since the delay amount of the delayed clock signal DCLK varies depending on the counter value, the control signals CTRLs 105_1 to 105_ (n−1) have a length corresponding to the delay amount in which the length of the high level time Tk is set in advance. Become.
Specifically, when the number of bits n is 6, the delay amount of the delayed clock signal DCLK with respect to the control signals CTRL105_1 to CTRL105_5 (counter values 1 to 5) is “2 × d”, “3” as shown in FIG. × d ”,“ 3 × d ”,“ 2 × d ”,“ 0 ”.

Next, the operation of this embodiment will be described with reference to FIG.
Here, FIG. 9 is an example of a timing chart of various input / output signals of the control unit 101.
The operation of the 6-bit successive approximation A / D converter 1 will be described below assuming that the number of bits n is 6 (m = 2). The operation after the analog input signal Ain is sampled by the capacitors 106_1 to 106_6 and after the switches 103a and 103c are turned off and the switch 103b is turned on will be described.

At this time, the counter value of the counter 301a is “0”, and in accordance with the first rising edge (delay amount 0) of the delayed clock signal DCLK, in the comparator 104, the potential “−Vin” and the reference potential “ VC "is compared and determined. The comparison determination result D1 is output to the control unit 101 and the output register 102, respectively.
On the other hand, the delay amount control circuit 301 increments the count value by 1 in response to the rising edge of the clock signal MCLK from the oscillator, and transitions to the state of the counter value “1”. Thus, delay amount control signals φ1 to φ4 that delay MCLK by a delay amount “2d” set in advance for the switch group 105_1 corresponding to the counter value “1” are generated.

Specifically, as shown in FIG. 9, delay amount control signals φ1 and φ4 that are low level and delay amount control signals φ2 and φ3 that are high level are generated at the counter value “1”, and the generated delay is generated. The quantity control signals φ1 to φ4 are supplied to the arbitrary delay circuit 302.
Here, the corresponding switch is turned on when the delay amount control signals φ1 to φ4 are at the high level, and the corresponding switch is turned off when the delay amount control signals φ1 to φ4 are at the low level.

On the other hand, in the arbitrary delay circuit 302, at the counter value “0”, the switch 305_1 is on and the switches 305_2 to 305_5 are off. That is, the delay clock signal DCLK with the delay amount “0” is output.
When the delay value control signals φ1 to φ4 shown in FIG. 9 are supplied from the delay amount control circuit 301 at the counter value “1”, the switch 305_1 is turned off and the switches 305_2 and 305_5 are turned on.

Accordingly, in the arbitrary delay circuit 302, the switches 305_1, 305_3, and 305_4 are turned off, the switches 305_2 and 305_5 are turned on, and the clock signal MCLK is output through the two buffer circuits of the buffer circuits 304_1 and 304_2. .
That is, as shown in FIG. 9, the second rising edge of the delayed clock signal DCLK rises with a delay of “2d” from the clock signal MCLK.

Then, in response to the second rising edge of the delayed clock signal DCLK, the comparator 104 has the potential “− (Vin−VR / 2)” or “− (Vin + VR / 2)” and the reference potential “VC” at the storage node SN. Are compared. The comparison determination result D2 is output to the control unit 101 and the output register 102, respectively.
On the other hand, when the control signal generation circuit 303 receives the delayed clock signal DCLK signal from the arbitrary delay circuit 302, the control circuit 303a rises in response to the first rising edge of the delayed clock signal as shown in FIG. A control signal CTRL105_1 that falls at the rising edge is generated.

Specifically, as shown in FIG. 9, the control signal CTRL 105_1 becomes a signal that becomes a high level during the time when the delay amount “2d” is added to the time of one cycle of the clock signal MCLK.
This comparison and determination operation is performed within the time interval Tc in the high level period T1 of the control signal CTRL105_1.
Although not illustrated, when the control circuit 303a receives the comparison determination result D1 from the comparator 104, when “D1 = 0”, the switch 103d_1 of the switch group 105_1 is switched from on to off, and the switch 103e is switched from off to on. A control signal CTRL for switching to is generated.

  Further, when “D1 = 1”, the control circuit 303a generates the control signal CTRL that switches the switch 103d_1 of the switch group 105_1 from on to off and switches the switch 103f from off to on. That is, if “D1 = 0”, a control signal for connecting the left end of the capacitor 106_1 to the power supply node VRN is generated, and if “D1 = 1”, a control signal for connecting the left end of the capacitor 106_1 to the power supply node VRP is generated.

  When the switch group 105_1 is switched by these control signals, the connection destination at the left end of the capacitor 106_1 is changed. This switching is performed during the period Tl in the high level period T1 of the control signal CTRL105_1. After the switch is switched, the time until the potential of the storage node SN changes due to charge redistribution and stabilizes to a constant potential (settling time) becomes the period of Ts_1 in the high level period T1 of the control signal CTRL105_1. .

Subsequently, in the delay amount control circuit 301, the counter 301a increments by 1 in response to the next rising edge of the clock signal MCLK, and transitions to the state of the counter value “2”. Thereby, delay amount control signals φ1 to φ4 that delay MCLK by a delay amount “3d” set in advance for the switch group 105_2 corresponding to the counter value “2” are generated.
Specifically, as shown in FIG. 9, the delay amount control signals φ1 and φ3 that are low level and the delay amount control signals φ2 and φ4 that are high level are generated at the counter value “2”, and the generated delay is generated. The quantity control signals φ1 to φ4 are supplied to the arbitrary delay circuit 302.

In the arbitrary delay circuit 302, the switches 305_1, 305_3, and 305_4 are turned off and the switches 305_2 and 305_5 are turned on at the counter value “1”.
When the delay amount control signal φ1 to φ4 shown in FIG. 9 is supplied from the delay amount control circuit 301 at the counter value “2”, the switch 305_5 is turned off and the switches 305_3 and 305_4 are turned on.

Accordingly, in the arbitrary delay circuit 302, the switches 305_1 and 305_5 are turned off, the switches 305_2, 305_3, and 305_4 are turned on, and the clock signal MCLK is output through the three buffer circuits of the buffer circuits 304_1 to 304_3. .
That is, as shown in FIG. 9, the third rising edge of the delayed clock signal DCLK rises with a delay amount “3d” from the clock signal MCLK.

Then, in accordance with the third rising edge of the delayed clock signal DCLK, the comparator 104 compares and determines the potential (substantially) of the storage node SN and the reference potential “VC”. Then, the comparison determination result D3 is output to the control unit 101 and the output register 102, respectively.
On the other hand, when the control signal generation circuit 303 receives the delayed clock signal DCLK signal from the arbitrary delay circuit 302, the control circuit 303a rises in response to the second rising edge of the delayed clock signal as shown in FIG. A control signal CTRL105_2 that falls in response to a rising edge is generated.

Specifically, as shown in FIG. 9, the control signal CTRL 105_2 is a signal that becomes a high level during the time when the delay amount “3d” is added to the time of one cycle of the clock signal MCLK.
Further, when the switch group 105_2 is switched by the control signal CTRL, the connection destination at the left end of the capacitor 106_2 is changed. This switching is performed during the period T1 in the high level period T2 of the control signal CTRL105_2. After the switch is switched, the time until the potential of the storage node SN changes due to charge redistribution and stabilizes to a constant potential (settling time) becomes the period of Ts_2 in the high level period T2 of the control signal CTRL105_2. .

Subsequently, in the delay amount control circuit 301, the counter 301a increments by one in response to the next rising edge of the clock signal MCLK, and transitions to the state of the counter value “3”. Thereby, delay amount control signals φ1 to φ4 that delay MCLK by a delay amount “3d” set in advance for the switch group 105_3 corresponding to the counter value “3” are generated.
In the counter value “3”, the additional delay amount is “3d” as in the case of the counter value “2”. Therefore, as shown in FIG. 9, the same delay amount control signal as in the case of the counter value “2” is obtained. φ1 to φ4 are supplied to the arbitrary delay circuit 302.

As a result, as shown in FIG. 9, the fourth rising edge of the delayed clock signal DCLK rises with a delay of “3d” from the clock signal MCLK.
Then, in accordance with the fourth rising edge of the delayed clock signal DCLK, the comparator 104 compares and determines the potential (substantially) of the storage node SN and the reference potential “VC”. The comparison determination result D4 is output to the control unit 101 and the output register 102, respectively.

On the other hand, when the control signal generation circuit 303 receives the delayed clock signal DCLK signal from the arbitrary delay circuit 302, the control circuit 303a rises in response to the third rising edge of the delayed clock signal as shown in FIG. A control signal CTRL105_3 that falls in response to the rising edge is generated.
Specifically, as shown in FIG. 9, the control signal CTRL 105 — 3 is a signal that becomes a high level during the time when the delay amount “3d” is added to the time of one cycle of the clock signal MCLK.

  Further, when the switch group 105_3 is switched by the control signal CTRL, the connection destination at the left end of the capacitor 106_3 is changed. This switching is performed during the period T1 in the high level period T3 of the control signal CTRL105_3. After the switch is switched, the time until the potential of the storage node SN changes due to charge redistribution and stabilizes to a constant potential (settling time) becomes the period of Ts_3 in the high level period T3 of the control signal CTRL105_3. .

Subsequently, in the delay amount control circuit 301, the counter 301a increments by one in response to the next rising edge of the clock signal MCLK, and transitions to the state of the counter value “4”. Thus, delay amount control signals φ1 to φ4 that delay MCLK by a delay amount “2d” set in advance for the switch group 105_4 corresponding to the counter value “4” are generated.
Specifically, as shown in FIG. 9, delay amount control signals φ1 and φ4 that are low level and delay amount control signals φ2 and φ3 that are high level are generated at the counter value “4”, and the generated delay is generated. The quantity control signals φ1 to φ4 are supplied to the arbitrary delay circuit 302.

Accordingly, in the arbitrary delay circuit 302, the switches 305_1, 305_3, and 305_4 are turned off, the switches 305_2 and 305_5 are turned on, and the clock signal MCLK is output through the two buffer circuits of the buffer circuits 304_1 and 304_2. .
That is, as shown in FIG. 9, the third rising edge of the delayed clock signal DCLK rises with a delay of “2d” with respect to the clock signal MCLK.

Then, in response to the fifth rising edge of the delayed clock signal DCLK, the comparator 104 compares and determines the potential (substantially) of the storage node SN and the reference potential “VC”. The comparison determination result D5 is output to the control unit 101 and the output register 102, respectively.
On the other hand, when the control signal generation circuit 303 receives the delayed clock signal DCLK signal from the arbitrary delay circuit 302, the control circuit 303a rises in response to the fourth rising edge of the delayed clock signal as shown in FIG. A control signal CTRL105_4 that falls in response to the rising edge is generated.

Specifically, as shown in FIG. 9, the control signal CTRL105_4 becomes a signal that becomes a high level during the time when the delay amount “2d” is added to the time of one cycle of the clock signal MCLK.
Further, when the switch group 105_4 is switched by the control signal CTRL, the connection destination at the left end of the capacitor 106_4 is changed. This switching is performed during the period Tl in the high level period T4 of the control signal CTRL105_4. After the switch is switched, the time (settling time) until the potential of the storage node SN changes due to charge redistribution and stabilizes to a constant potential (settling time) is the period of Ts_4 in the high level period T4 of the control signal CTRL105_4. .

Subsequently, in the delay amount control circuit 301, the counter 301a is incremented by 1 in response to the next rising edge of the clock signal MCLK, and transitions to the state of the counter value “5”. Accordingly, delay amount control signals φ1 to φ4 that delay MCLK by a delay amount “0” set in advance for the switch group 105_5 corresponding to the counter value “5” are generated.
Specifically, as shown in FIG. 9, at the counter value “5”, a delay amount control signal φ1 that becomes high level and delay amount control signals φ2 to φ4 that become low level are generated, and the generated delay amount control is generated. Signals φ1 to φ4 are supplied to the arbitrary delay circuit 302.

Accordingly, in the arbitrary delay circuit 302, the switch 305_1 is turned on, the switches 305_2 to 305_5 are turned off, and the clock signal MCLK is output without passing through any of the buffer circuits 304_1 to 304_3.
That is, as shown in FIG. 9, the sixth rising edge of the delayed clock signal DCLK rises with a delay amount “0” with respect to the clock signal MCLK.

Then, in response to the sixth rising edge of the delayed clock signal DCLK, the comparator 104 compares and determines the potential (substantially) of the storage node SN and the reference potential “VC”. The comparison determination result D6 is output to the control unit 101 and the output register 102, respectively.
On the other hand, when receiving the delayed clock signal DCLK signal from the arbitrary delay circuit 302, the control signal generation circuit 303 rises in response to the fifth rising edge of the delayed clock signal, as shown in FIG. A control signal CTRL105_5 that falls in response to the rising edge is generated.

Specifically, as shown in FIG. 9, the control signal CTRL105_5 is a signal that becomes a high level at the same time as the time of one cycle of the clock signal MCLK.
Further, when the switch group 105_5 is switched by the control signal CTRL, the connection destination at the left end of the capacitor 106_5 is changed. This switching is performed during the period T1 in the high level period T5 of the control signal CTRL105_5. After the switch is switched, the time until the potential of the storage node SN changes due to charge redistribution and stabilizes to a constant potential (settling time) is the period of Ts_5 in the high level period T5 of the control signal CTRL105_5. .

Here, the time required for T1 is “T1 = Tc + Tl + Ts_1”, and “T1 ≧ Tc + Tl + Tx” from the above equation (4).
Further, the time required for T2 is “T2 ≧ Tc + Tl + Tx−d” from the above equation (6).
Also, the time required for T3, T4, and T5 is “T3 ≧ Tc + Tl + Tx−2d”, “T4 ≧ Tc + Tl + Tx−3d”, and “T5 ≧ Tc + Tl + Tx−4d” from the above equation (7).

Here, when the oscillation cycle of the oscillator is “Tc + Tl + Tx−2d”, “T1 ≧ Tc + Tl + Tx”, “T2 ≧ Tc + Tl + Tx−d”, “T3 ≧ Tc + Tl + Tx−2d”, “T4 ≧ Tc + Tl + Tx−3d” are shown in FIG. “T5 ≧ Tc + Tl + Tx−4d” can be realized.
Subsequently, in response to the next rising edge of the clock signal MCLK, the delay amount control circuit 301 resets the counter value “5” and transitions to the state of the counter value “0”.

Further, in the period of the counter value “0”, the capacitors 106_1 to 106_6 sample the analog input signal Vin following the sampling, so the control signal generation circuit 303 generates a control signal CTRL for that purpose.
Then, after sampling a new point of the analog input signal Vin, the above series of operations is executed.

The operation of the output register 102 is the same as that of the output register 502 of FIG. 10, and as shown in FIG. 12, the determination results “0” or “1” of D1 to D6 stored in the register are sequentially applied from the upper bit. These are arranged and output as a digital output signal Vout.
As described above, the successive approximation A / D converter 1 according to this embodiment includes a delay amount control circuit 301 including a counter 301a having a simple circuit configuration and a control circuit 301b that controls a switch of the arbitrary delay circuit 302 based on the counter value. Thus, the delay amount of the arbitrary delay circuit 302 in each bit determination can be controlled in order from the upper bit.

Further, the arbitrary delay circuit 302 delays the clock signal MCLK from the oscillator, generates control signals CTRL105_1 to CTRL105_ (n-1) based on the delayed clock signal DCLK, and switches 105_1 to 105_ by these control signals CTRL. A necessary minimum time can be set as the control period Tk of (n-1).
Thereby, compared with the past, the oscillation frequency of the oscillator can be kept low, so that an increase in area and power consumption in the case of semiconductor integration can be suppressed. In addition, since the circuit can be realized with a simple configuration, design design in semiconductor integration can be easily performed.

In the above embodiment, the capacitors 106_1 to 106_n correspond to the first to nth capacitors described in the invention 1, and the switch groups 105_1 to 105_ (n−1) include the first to nth (nth) described in the invention 1. -1) corresponding to the switch group.
In the above embodiment, the comparator 104 corresponds to the comparator described in the invention 1 or 4, and the control unit 101 corresponds to the control unit described in the invention 1.

In the above embodiment, the counter 301a corresponds to the counter circuit described in Invention 1, the control circuit 301b and the arbitrary delay circuit 302 correspond to the delay circuit described in Invention 1, and the control signal generation circuit 303 This corresponds to the control signal generation circuit according to the first aspect.
In the above embodiment, the configuration of the arbitrary delay circuit 302 has been described by taking the configuration illustrated in FIG. 6 as an example. It is good also as a structure of.

The above embodiments are preferable specific examples of the present invention, and various technically preferable limitations are given. However, the scope of the present invention is described in particular in the above description to limit the present invention. As long as there is no, it is not restricted to these forms. In the drawings used in the above description, for convenience of illustration, the vertical and horizontal scales of members or parts are schematic views different from actual ones.
Further, the present invention is not limited to the above-described embodiment, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.

DESCRIPTION OF SYMBOLS 1 ... Successive comparison type A / D converter, 101 ... Control part, 102 ... Output register, 104 ... Comparator, 103a-103c, 103d_1-103d_ (n-1), 103e_1-103e_ (n-1), 103f_1-103f_ (N-1), 305_1 to 305_5 ... switch, 301 ... delay amount control circuit, 302 ... arbitrary delay circuit, 303 ... control signal generation circuit, 301a ... counter, 301b ... control circuit, 303a ... control circuit, 303b ... transmission path , 304_1 to 304_3... Buffer circuit

Claims (4)

A charge comparison type successive approximation A / D converter that converts an analog input signal into a digital output signal of n bits (n is a natural number of 3 or more),
One end of each output side is commonly connected, and the reference capacitance C is set such that the capacitance is set to the reference capacitance C and the combined capacitance is “C−C / 2 ⁿ⁻² ”. Second to (n-1) th capacitors set to a capacity (C / 2 ^m (m is a natural number of 1 to (n-2))) weighted stepwise by the reciprocal of the power of 2; N capacitors with the nth capacitor set to a capacitance weighted by “1/2 ⁿ⁻² ” of the reference capacitance C;
The first to (n-1) th capacitors are connected to the other ends of the capacitors, respectively, and the connection between the first to (n-1) th capacitors, the analog signal input unit, and a node having a predetermined potential is switched. First to (n-1) switch groups;
A comparator that compares an input potential based on a holding potential of the n capacitors with a reference potential and outputs a determination signal according to the comparison result;
A control unit that controls a switching operation of the first to (n-1) th switch groups and a comparison determination operation of the comparator so that the comparison determination operation is sequentially performed in order from a predetermined bit;
The controller is
A counter circuit for counting clock signals;
A delay circuit that delays the clock signal by a delay amount necessary for a driving time of a switch group corresponding to a count value of the counter circuit;
A control signal generation circuit that generates a control signal for controlling the switching operation of the first to (n-1) th switch groups based on the clock signal delayed by the delay circuit;
The delayed clock signal is supplied to the comparator to control the operation of the comparator, and the generated control signal is supplied to the (n-1) switch groups to control the switching operation of the switch group. A successive approximation A / D converter characterized in that: The time for driving the switch group defined by the control signal corresponding to the capacitor whose capacitance is weighted to C / 2 ^k (k is a natural number of k ≦ (n−2)), and the capacitance is C The delay circuit so that a time d which is a difference from a time for driving the switch group defined by the control signal corresponding to the capacitor weighted to / 2 ^k−1 becomes a time proportional to the natural logarithm “ln2”. The successive approximation A / D converter according to claim 1, wherein the delay amount is set. When the n bits are 2 (m + 1) bits (m is a natural number), the rising edge of the clock signal at the time of comparing and determining the most significant bit is set as the first rising edge, and z (z is 2 ≦ z ≦ 2) 3. The successive approximation A / D converter according to claim 2, wherein the clock signal is delayed by a delay amount calculated by the following equation (1) with respect to a rising edge of a natural number (m + 1).
Delay amount = {(z−1) × m− (z−2) × (z−1) / 2} × d (1)   The comparator has an input potential which is a difference potential between a holding potential of the n capacitors and a holding potential of a storage node capable of holding a charge formed in a signal input portion of the comparator, and a reference potential. 4. The successive approximation type A / D converter according to claim 1, wherein the successive approximation type A / D converter is configured to perform comparison.

Images