JP2019096682A - Light emitting component, print head, image forming apparatus, and method for manufacturing light emitting component - Google Patents

Abstract

To provide a light emitting component that reduces the voltage of a signal supplied to a transfer element, compared with a case where a semiconductor element and a transfer element having the same layer structure as that of a light emitting element are laminated.SOLUTION: A light emitting chip C comprises: a substrate 80; a plurality of laser diodes LD that are provided on the substrate 80; a plurality of setting thyristors S that are laminated respectively on the plurality of laser diodes LD and are turned on to set the plurality of laser diodes LD to emit light or increase the amount of light emission; and a plurality of transfer thyristors T that are provided on the substrate 80 in the lateral direction of the plurality of laser diodes LD, connected respectively to the plurality of setting thyristors S, and upon sequential transfer of an on-state, allow a transition of the setting thyristors S connected thereto to an on-state.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a light emitting component, a print head, an image forming apparatus, and a method of manufacturing the light emitting component.

  In Patent Document 1, a large number of light emitting elements whose threshold voltage or threshold current can be controlled from the outside are arrayed one-dimensionally, two-dimensionally or three-dimensionally, and the threshold voltage or threshold current of each light emitting element A light emitting element array is described in which electrodes controlling the light emitting diodes are electrically connected to each other, and a clock line for applying a voltage or current from the outside to each light emitting element is connected.

  Patent Document 2 discloses a substrate, a surface emitting semiconductor laser disposed in an array on the substrate, and a thyristor as a switch element arranged on the substrate to selectively turn on / off the light emission of the surface emitting semiconductor laser. And a self-scanning light source head is disclosed.

  In Patent Document 3, a light emitting element having a pnpn pn 6-layer semiconductor structure is configured, and electrodes are provided on the p-type first layer and the n-type sixth layer at both ends, and the p-type third layer and the n-type fourth layer in the center. There is described a self-scanning light emitting device in which a pn layer has a light emitting diode function and a pnpn 4 layer has a thyristor function.

Unexamined-Japanese-Patent No. 1-238962 JP, 2009-286048, A JP 2001-308385 A

By the way, for example, in a self-scanning light emitting element array including a light emitting unit and a driving unit, light emitting elements in the light emitting unit and transfer elements for sequentially driving the light emitting elements in the driving unit are made of the same stacked semiconductor layers. It was difficult to set the light emission characteristics of the device and the drive characteristics of the transfer device independently. For this reason, it is conceivable to configure the light emitting element with another laminated semiconductor layer and to set the light emission characteristic and the drive characteristic independently. At this time, when the light emitting element in the light emitting portion and the element for controlling light emission of the light emitting element are stacked, and the semiconductor element and the transfer element having the same layer configuration as the light emitting element are stacked in the driving portion, The voltage increases and the power consumption increases.
Therefore, it is an object of the present invention to provide a light emitting component or the like in which the voltage of a signal supplied to a transfer element is reduced as compared to the case where a semiconductor element having the same layer configuration as the light emitting element and the transfer element are stacked.

According to the first aspect of the present invention, the substrate, the plurality of light emitting elements provided on the substrate, and the plurality of light emitting elements are stacked, and are turned on to emit light from the plurality of light emitting elements. Alternatively, it is provided on a plurality of setting thyristors set to increase the light emission amount, and on the substrate in the lateral direction of the plurality of light emitting elements, connected to each of the plurality of setting thyristors, and ON states are sequentially transferred Thus, the light emitting component is provided with a plurality of transfer thyristors that can shift the connected setting thyristor to the on state.
The invention according to claim 2 is characterized in that the setting thyristor and the transfer thyristor are constituted by laminated semiconductor layers of the same layer configuration in which a plurality of semiconductor layers are laminated. It is a light emitting component.
The invention according to claim 3 is characterized in that the laminated semiconductor layer constituting the setting thyristor and the transfer thyristor includes a voltage reduction layer which reduces a rising voltage of the setting thyristor and the transfer thyristor. It is a light emitting component as described in 2.
In the invention according to claim 4, the light emitting element is constituted by another laminated semiconductor layer in which a plurality of semiconductor layers are laminated, and the voltage reduction layer is any semiconductor layer constituting the other laminated semiconductor layer The light emitting component according to claim 3, wherein the band gap energy is smaller than that of the light emitting component.
The invention according to claim 5 is the light-emitting component according to claim 4, wherein the voltage reduction layer has a band gap energy smaller than that of the semiconductor layer constituting the light-emitting layer of the light-emitting element.
The invention according to claim 6 is characterized in that the light emitting element and the setting thyristor are connected in series via a tunnel junction layer or a group III-V compound layer having metallic conductivity. It is a light emitting component according to item 1.
The invention according to claim 7 causes the light emitting element to emit light or the light emission amount when the setting thyristor is shifted to the on state by the voltage applied to the light emitting element and the setting thyristor connected in series. The light emitting component according to claim 6, characterized in that
The invention according to claim 8 is the light-emitting component according to claim 1 or 2, wherein the light-emitting element has a narrowed current path.
The invention according to claim 9 is a print head comprising light emitting means including the light emitting component according to claim 1 and optical means for forming an image of light emitted from the light emitting means.
The invention according to claim 10 includes an image carrier, charging means for charging the image carrier, and a light emitting component according to claim 1, and an exposure means for exposing the image carrier through an optical means. And developing means for developing the electrostatic latent image exposed by the exposing means and formed on the image carrier, and transfer means for transferring the image developed on the image carrier to a transferee. It is a forming device.
The invention according to claim 11 is a step of forming a first laminated semiconductor layer, which constitutes a plurality of light emitting elements, and which forms a first laminated semiconductor layer in which a plurality of semiconductor layers are laminated on a substrate; A first stacked semiconductor layer etching step of etching the first stacked semiconductor layer on the substrate except a region in which an element is formed; and on the substrate and the first stacked semiconductor layer left on the substrate. The plurality of setting thyristors set to increase the light emission or the light emission amount of each of the plurality of light emitting elements by being in the on state, and the on state is transferred in order and the connection is made in the on state. A second stacked semiconductor layer forming a second stacked semiconductor layer in which a plurality of semiconductor layers are stacked to form a plurality of transfer thyristors for bringing the setting thyristor into a state in which the setting thyristor can be shifted to the on state It is a manufacturing method of a light-emitting component comprising a layer formation step.

According to the first aspect of the present invention, the voltage of the signal supplied to the transfer element can be reduced compared to the case where the transfer element and the semiconductor element having the same layer configuration as the light emitting element are stacked.
According to the second aspect of the present invention, manufacture is facilitated as compared with the case where the same laminated semiconductor layer is not used.
According to the third aspect of the present invention, the power consumption in the ON state of the element used for driving is reduced as compared with the case where the voltage reduction layer is not provided.
According to the fourth and fifth aspects of the invention, selection of the voltage reduction layer is facilitated as compared with the case where the voltage reduction layer is not set by the band gap energy.
According to the invention of claim 6, the voltage supplied for light emission can be reduced as compared with the case where the tunnel junction layer or the group III-V compound layer having metallic conductivity is not interposed.
According to the seventh aspect of the present invention, lighting control becomes easier as compared with the case where control is not performed by the voltage applied to the series connection.
According to the invention of claim 8, power consumption can be reduced as compared with the case where the current path is not narrowed.
According to the invention of claim 9, the power consumption of the print head can be reduced as compared to the case where the semiconductor element having the same layer configuration as the light emitting element and the transfer element are stacked.
According to the tenth aspect of the present invention, power consumption of the image forming apparatus can be reduced as compared to the case where the semiconductor element having the same layer configuration as the light emitting element and the transfer element are stacked.
According to the eleventh aspect of the present invention, the voltage of the signal supplied to the transfer element can be reduced as compared with the case where the semiconductor element having the same layer configuration as the light emitting element and the transfer element are stacked and manufactured.

FIG. 1 is a diagram showing an example of the entire configuration of an image forming apparatus to which a first embodiment is applied. It is a sectional view showing an example of composition of a print head. It is a top view of an example of a light-emitting device. FIG. 3 is a diagram showing an example of the configuration of a light emitting chip, the configuration of a signal generation circuit of a light emitting device, and the configuration of wirings (lines) on a circuit board. FIG. 2 is an equivalent circuit diagram for explaining a circuit configuration of a light emitting chip on which a self-scanning light emitting element array (SLED) according to the first embodiment is mounted. It is an example of the plane layout figure and sectional drawing of a light emitting chip concerning a 1st embodiment. (A) is a planar layout figure of a light emitting chip, (b) is a sectional view in the VIB-VIB line of (a). FIG. 7 is an enlarged cross-sectional view of an island provided with a laser diode and a setting thyristor, an island provided with a transfer thyristor and the like, and an island provided with a power supply line resistance in the light emitting chip according to the first embodiment. It is a figure which further demonstrates the laminated structure of a laser diode and a setting thyristor. (A) is a schematic energy band diagram in the laminated structure of the laser diode and the setting thyristor, (b) is an energy band diagram in the reverse bias state of the tunnel junction layer, (c) is a current voltage of the tunnel junction layer Show the characteristics. 5 is a timing chart illustrating the operation of the light emitting device and the light emitting chip. It is a figure explaining the manufacturing method of a light emitting chip. (A) is a first laminated semiconductor layer forming step, (b) is a first laminated semiconductor layer etching step, and (c) is a second laminated semiconductor layer formation. It is a figure explaining the manufacturing method of a light emitting chip. (D) is a cathode electrode formation process, (e) is a cathode region formation process, and (f) is an anode electrode formation process. It is a figure explaining the manufacturing method of a light emitting chip. (G) is a separation etching process, (h) is a current blocking portion forming process, and (i) is a protective layer forming process. It is a figure explaining the manufacturing method of a light emitting chip. (J) is a wiring formation process, (k) is a back surface electrode formation process, and (l) is a light emitting surface formation process. It is sectional drawing of the light emitting chip shown for comparison. It is a figure explaining the material which comprises metallic electroconductive III-V compound layer. (A) is the band gap of InNAs to the composition ratio x of InN, (b) is the band gap of InNSb to the composition ratio x of InN, (c) is the lattice constant of the group VI element and the III-V compound It is a figure shown with respect to a band gap. It is an expanded sectional view of an island etc. in which a laser diode and a setting thyristor provided with a voltage reduction layer were laminated. It is a figure explaining the structure of a thyristor, and the characteristic of a thyristor. (A) is a sectional view of a thyristor provided with a voltage reduction layer, (b) is a sectional view of a thyristor not provided with a voltage reduction layer, and (c) is a thyristor characteristic. It is a figure explaining the band gap energy of the material which comprises a semiconductor layer. It is an expanded sectional view of the island in which the laser diode and the setting thyristor which laminated | stacked the laser diode explaining the modification 1-1. It is an expanded sectional view of the island in which the laser diode and the setting thyristor which laminated | stacked on which the modification 1-2 is demonstrated. It is an expanded sectional view of the island in which the laser diode and the setting thyristor which laminated | stacked on which the modification 1-3 is demonstrated. It is an expanded sectional view of the island where the light emitting diode and the setting thyristor in the light emitting chip concerning a 2nd embodiment were laminated. It is an expanded sectional view of the island in which the light emitting diode and the setting thyristor which laminated | stacked the light source explaining the modification 2-1. It is an expanded sectional view of the island in which the light emitting diode and the setting thyristor which laminated | stacked on which the modification 2-2 is demonstrated. It is an expanded sectional view of the island in which the light emitting diode and the setting thyristor which laminated | stacked the light-emitting diode explaining modification 2-3. It is an expanded sectional view of the island where the vertical cavity surface emitting laser of the light emitting chip concerning a 3rd embodiment and the setting thyristor S were laminated. It is an expanded sectional view of the island in which the vertical-cavity surface-emitting laser and the setting thyristor are stacked for explaining the modified example 3-1. It is an expanded sectional view of the island in which the vertical-cavity surface-emitting laser and the setting thyristor are stacked for explaining the modification 3-2.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.
In addition, below, it describes using elemental symbol, such as setting aluminum to Al.

First Embodiment
Here, the light emitting chip C, which is an example of the light emitting component, will be described as being applied to the image forming apparatus 1 as an example.
(Image forming apparatus 1)
FIG. 1 is a view showing an example of the entire configuration of an image forming apparatus 1 to which the first embodiment is applied. The image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 for forming an image according to image data of each color, an image output control unit 30 for controlling the image forming process unit 10, such as a personal computer (PC) 2 or an image reading apparatus 3 and an image processing unit 40 which performs predetermined image processing on image data received from these.

The image forming process unit 10 includes image forming units 11Y, 11M, 11C, and 11K (in the case of no distinction, described as the image forming unit 11) arranged in parallel at predetermined intervals. The image forming unit 11 includes a photosensitive drum 12 as an example of an image holder that forms an electrostatic latent image and holds a toner image, and an example of a charging unit that charges the surface of the photosensitive drum 12 at a predetermined potential. And a print head 14 for exposing the photosensitive drum 12 charged by the charger 13, and a developing unit 15 as an example of a developing unit for developing an electrostatic latent image obtained by the print head 14. The image forming units 11Y, 11M, 11C, and 11K form toner images of yellow (Y), magenta (M), cyan (C), and black (K), respectively.
Further, the image forming process unit 10 performs multiple transfer of toner images of respective colors formed on the photosensitive drums 12 of the respective image forming units 11Y, 11M, 11C, and 11K on a recording sheet 25 as an example of a transfer target. A sheet conveying belt 21 for conveying the recording sheet 25, a driving roll 22 for driving the sheet conveying belt 21, and a transfer roll 23 as an example of a transfer unit for transferring the toner image of the photosensitive drum 12 onto the recording sheet 25. And a fixing unit 24 for fixing the toner image on the recording sheet 25.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 is subjected to image processing by the image processing unit 40 and supplied to the image forming unit 11 under the control of the image output control unit 30. Ru. Then, for example, in the black (K) color image forming unit 11 K, the photosensitive drum 12 is charged to a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image supplied from the image processing unit 40 It is exposed by the print head 14 which emits light based on the data. Thereby, an electrostatic latent image relating to a black (K) color image is formed on the photosensitive drum 12. Then, the electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. Also in the image forming units 11Y, 11M, and 11C, toner images of respective colors of yellow (Y), magenta (M), and cyan (C) are formed.

Each color toner image on the photosensitive drum 12 formed by each image forming unit 11 is applied to the transfer roll 23 to the recording sheet 25 supplied along with the movement of the sheet conveyance belt 21 moving in the arrow B direction. By the transfer electric field, electrostatic transfer is sequentially performed to form a composite toner image in which the toners of the respective colors are superimposed on the recording sheet 25.
Thereafter, the recording sheet 25 on which the composite toner image is electrostatically transferred is conveyed to the fixing device 24. The composite toner image on the recording sheet 25 conveyed to the fixing unit 24 is subjected to a fixing process by heat and pressure by the fixing unit 24, fixed on the recording sheet 25, and discharged from the image forming apparatus 1.

(Print head 14)
FIG. 2 is a cross-sectional view showing an example of the configuration of the print head 14. The print head 14 as an example of the exposure unit includes a housing 61 and a light source unit 63 having a plurality of light emitting elements (in the first embodiment, the light emitting element is a laser diode LD) for exposing the photosensitive drum 12. A light emitting device 65 as an example of the means, and a rod lens array 64 as an example of an optical means for forming the light emitted from the light source unit 63 on the surface of the photosensitive drum 12 are provided.
The light emitting device 65 includes a circuit board 62 on which the light source unit 63 and the signal generation circuit 110 (see FIG. 3 described later) for driving the light source unit 63 described above are mounted.

  The housing 61 is made of metal, for example, and supports the circuit board 62 and the rod lens array 64. The light emitting surface of the light emitting element of the light source unit 63 is set to be the focal plane of the rod lens array 64. The rod lens array 64 is disposed along the axial direction of the photosensitive drum 12 (the main scanning direction, which is the X direction in FIGS. 3 and 4 (b) described later).

(Light-emitting device 65)
FIG. 3 is a top view of an example of the light emitting device 65.
In the light emitting device 65 shown as an example in FIG. 3, the light source unit 63 is a light emitting chip C1 to C40 as an example of 40 light emitting components on the circuit board 62 (if not distinguished, it is described as a light emitting chip C). Are arranged in a staggered manner in two rows in the X direction, which is the main scanning direction. The configuration of the light emitting chips C1 to C40 may be the same.
As used herein, "-" refers to a plurality of components that are each distinguished by a number, and is meant to include those described before and after "-" and those in between. For example, the light emitting chips C1 to C40 include the light emitting chips C1 to the light emitting chips C40 in numerical order.

In the first embodiment, a total of 40 light emitting chips C are used, but the present invention is not limited to this.
The light emitting device 65 is mounted with a signal generating circuit 110 for driving the light source unit 63. The signal generation circuit 110 is configured by, for example, an integrated circuit (IC). The light emitting device 65 may not have the signal generation circuit 110 mounted thereon. At this time, the signal generation circuit 110 is provided outside the light emitting device 65, and supplies a control signal or the like for controlling the light emitting chip C through a cable or the like. Here, the light emitting device 65 is described as including the signal generating circuit 110.
Details of the arrangement of the light emitting chips C will be described later.

  FIG. 4 is a view showing an example of the configuration of the light emitting chip C, the configuration of the signal generation circuit 110 of the light emitting device 65, and the configuration of the wirings (lines) on the circuit board 62. FIG. 4A shows the configuration of the light emitting chip C, and FIG. 4B shows the configuration of the signal generation circuit 110 of the light emitting device 65 and the configuration of the wiring (line) on the circuit board 62. In FIG. 4B, of the light emitting chips C1 to C40, portions of the light emitting chips C1 to C9 are shown.

First, the configuration of the light emitting chip C shown in FIG. 4A will be described.
The light emitting chip C has a plurality of laser diodes LD1 to LD128 provided in a row along the long side on the side closer to one side of the long side on the surface of the substrate 80 whose surface shape is rectangular (in the case of no distinction, laser And a light emitting unit 102 configured to include the diode LD. Further, the light emitting chip C has terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) which are a plurality of bonding pads for capturing various control signals and the like at both ends in the long side direction of the surface of the substrate 80 Prepare. Note that these terminals are provided in the order of the φI terminal and the φ1 terminal from one end of the substrate 80, and in the order of the Vga terminal and the φ2 terminal from the other end of the substrate 80. The light emitting unit 102 is provided between the φ1 terminal and the φ2 terminal. Furthermore, a back surface electrode 91 (see FIG. 6 described later) is provided on the back surface of the substrate 80 as a Vsub terminal. The laser diode LD is an example of a light emitting element (an element used for light emission). Here, on the surface of the substrate 80, the direction of arrangement of the laser diodes LD1 to LD128 is taken as the x direction, and the direction orthogonal to the x direction is taken as the y direction.

  Note that “in a row” is not limited to the case where a plurality of light emitting elements (laser diodes LD in the first embodiment) are disposed on a straight line as shown in FIG. The respective light emitting elements of the light emitting elements may be arranged with different amounts of deviation with respect to the direction orthogonal to the column direction. For example, each light emitting element may be disposed with a shift amount in a direction orthogonal to the column direction. Alternatively, the light emitting elements may be alternately arranged between adjacent light emitting elements, or may be arranged in a zigzag manner for each of a plurality of light emitting elements.

Next, the configuration of the signal generation circuit 110 of the light emitting device 65 and the configuration of the wirings (lines) on the circuit board 62 will be described with reference to FIG. 4B.
As described above, the signal generating circuit 110 and the light emitting chips C1 to C40 are mounted on the circuit board 62 of the light emitting device 65, and the wiring (line) connecting the signal generating circuit 110 and the light emitting chips C1 to C40 is provided. ing.

First, the configuration of the signal generation circuit 110 will be described.
The signal generation circuit 110 receives image data subjected to image processing and various control signals from the image output control unit 30 and the image processing unit 40 (see FIG. 1). The signal generation circuit 110 rearranges the image data, corrects the light amount, and the like based on the image data and various control signals.
The signal generation circuit 110 includes a transfer signal generation unit 120 that transmits the first transfer signal φ1 and the second transfer signal φ2 to the light emitting chips C1 to C40 based on various control signals.
Further, the signal generation circuit 110 transmits a lighting signal generation unit to the lighting chips φI1 to φI40 (if not distinguished, the lighting signal φI is written) to the light emitting chips C1 to C40 based on various control signals. 140 is provided.
Furthermore, the signal generation circuit 110 supplies a reference potential supply unit 160 for supplying a reference potential Vsub serving as a potential reference to the light emitting chips C1 to C40, and a power supply potential for supplying a power supply potential Vga for driving the light emitting chips C1 to C40. The supply unit 170 is provided.

  The reference potential Vsub and the power supply potential Vga do not necessarily have to be fixed values, and may fluctuate within the range where the light emitting chip C performs an operation described later. The same applies to the first transfer signal φ1, the second transfer signal φ2, and the lighting signals φI1 to φI40.

Next, the arrangement of the light emitting chips C1 to C40 will be described.
The light emitting chips C1, C3, C5,... Of odd numbers are arranged in a line at intervals in the long side direction of the respective substrates 80. The even-numbered light emitting chips C2, C4, C6,... Are similarly arranged in a line at intervals in the long side direction of the respective substrates 80. The odd numbered light emitting chips C1, C3, C5,... And the even numbered light emitting chips C2, C4, C6,. They are arranged in a staggered manner while rotating 180 °. The positions are set so that the laser diodes LD are arranged at predetermined intervals in the main scanning direction (X direction) also between the light emitting chips C. In the light emitting chips C1 to C40 illustrated in FIG. 4B, directions of the arrangement order of the laser diodes LD illustrated in FIG.

Wirings (lines) connecting the signal generation circuit 110 and the light emitting chips C1 to C40 will be described.
The circuit substrate 62 is connected from the reference potential supply unit 160 of the signal generation circuit 110 to the back surface electrode 91 (see FIG. 6 described later) which is a Vsub terminal provided on the back surface of the substrate 80 of the light emitting chip C. A power supply line 200a for supplying Vsub is provided.
Then, the circuit board 62 is provided with a power supply line 200 b connected to the Vga terminal provided in the light emitting chip C from the power supply potential supply unit 170 of the signal generation circuit 110 and supplying the power supply potential Vga for driving There is.

  The first transfer signal line 201 for transmitting the first transfer signal φ1 to the φ1 terminals of the light emitting chips C1 to C40 from the transfer signal generation unit 120 of the signal generating circuit 110 on the circuit board 62, and the light emitting chips C1 to C40. A second transfer signal line 202 for transmitting a second transfer signal φ2 to the φ2 terminal is provided. The first transfer signal φ1 and the second transfer signal φ2 are transmitted to the light emitting chips C1 to C40 in common (in parallel).

  Further, to the circuit board 62, the lighting signal generating unit 140 of the signal generating circuit 110 transmits the lighting signals φI1 to φI40 to the respective φI terminals of the light emitting chips C1 to C40 via the current limiting resistors RI. Lighting signal lines 204-1 to 204-40 (in the case of no distinction, they are described as lighting signal lines 204) are provided.

  As described above, the reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips C1 to C40 on the circuit board 62. The first transfer signal φ1 and the second transfer signal φ2 are also transmitted to the light emitting chips C1 to C40 in common (in parallel). On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips C1 to C40.

(Light emitting chip C)
FIG. 5 is an equivalent circuit diagram for explaining the circuit configuration of the light emitting chip C on which the self-scanning light emitting element array (SLED: Self-Scanning Light Emitting Device) according to the first embodiment is mounted. The elements described below are arranged based on the layout on the light emitting chip C (see FIG. 6 described later) except for the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal). The positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for the explanation of the connection with the signal generating circuit 110. . The Vsub terminal provided on the back surface of the substrate 80 is shown drawn out of the substrate 80.
Here, the light emitting chip C will be described taking the light emitting chip C1 as an example in relation to the signal generating circuit 110. Therefore, in FIG. 5, the light emitting chip C is referred to as a light emitting chip C1 (C). The configuration of the other light emitting chips C2 to C40 is the same as that of the light emitting chip C1.

The light emitting chip C1 (C) includes a light emitting unit 102 (see FIG. 4A) configured by the laser diodes LD1 to LD128 arranged in a line.
The light emitting chip C1 (C) includes setting thyristors S1 to S128 (in the case of no distinction, the setting thyristor S is described) arranged in a row as in the laser diode LD. In the laser diodes LD1 to LD128 and the setting thyristors S1 to S128, the laser diode LD of the same number and the setting thyristor S are connected in series. Here, the cathode of the laser diode LD and the anode of the setting thyristor S are connected. As shown in FIG. 6B described later, the setting thyristors S are stacked on the laser diodes LD arranged in a line on the substrate 80. Thus, the setting thyristors S1 to S128 are also arranged in a row.

  The setting thyristor S emits light or increases the light emission amount of the laser diode LD by being turned on as described later. That is, the setting thyristor S sets the laser diode LD in a light emitting state or a light emitting amount increasing state. Therefore, it is described as a setting thyristor S. In addition, a current is supplied to the laser diode LD via the setting thyristor S. From this, the setting thyristor S may be referred to as an element that controls light emission of the laser diode LD or an element that drives the laser diode LD. The set thyristor S may be described as a thyristor.

  Further, in the light emitting chip C1 (C), transfer thyristors T1 to T128 (in the case of no distinction, they are referred to as transfer thyristor T) are arranged in a row like the laser diodes LD1 to LD128 and setting thyristors S1 to S128. Prepare.

Here, although the transfer thyristor T is described as an example of the transfer element, another circuit element may be used as long as the element is turned on in order. For example, a circuit combining a shift register or a plurality of transistors An element may be used.
In the light emitting chip C1 (C), two transfer thyristors T1 to T128 are paired in order of number, and coupling diodes D1 to D127 (in the case of no distinction, they are denoted as coupling diodes D). ).
Furthermore, the light emitting chip C1 (C) includes power supply line resistances Rg1 to Rg128 (when not distinguished, it is described as a power supply line resistance Rg).

In addition, the light emitting chip C1 (C) includes one start diode SD. Then, it is provided to prevent an excessive current from flowing in a first transfer signal line 72 to which a first transfer signal φ1 described later is transmitted and a second transfer signal line 73 to which a second transfer signal φ2 is transmitted. Current limiting resistors R1 and R2.
Here, the drive unit 101 includes the setting thyristors S1 to S128, the transfer thyristors T1 to T128, the power supply line resistances Rg1 to Rg128, the coupling diodes D1 to D127, the start diode SD, and the current limiting resistances R1 and R2.

  The laser diodes LD1 to LD128 of the light emitting unit 102, the setting thyristors S1 to S128, and the transfer thyristors T1 to T128 of the driving unit 101 are arranged in numerical order from the left side in FIG. Furthermore, the coupling diodes D1 to D127 and the power supply line resistances Rg1 to Rg128 are also arranged in numerical order from the left side in the drawing.

  The light emitting chip C includes a power supply line 71 to which the power supply potential Vga is supplied, a first transfer signal line 72 to which the first transfer signal φ1 is supplied, and a second transfer signal line 73 to which the second transfer signal φ2 is supplied. A lighting signal line 75 for supplying a current for lighting the laser diode LD is provided.

In the first embodiment, the number of laser diodes LD in the light emitting unit 102, the setting thyristors S in the driving unit 101, the transfer thyristors T, and the power supply line resistance Rg are 128, respectively. The number of coupling diodes D is 127, which is one less than the number of transfer thyristors T.
The number of laser diodes LD and the like is not limited to the above, and may be a predetermined number. The number of transfer thyristors T may be larger than the number of laser diodes LD.

The diode (laser diode LD, coupling diode D, start diode SD) is a two-terminal semiconductor device having an anode terminal (anode) and a cathode terminal (cathode), and the thyristor (setting thyristor S, transfer thyristor T) is an anode The semiconductor device has three terminals: a terminal (anode), a gate terminal (gate), and a cathode terminal (cathode).
As described later, the diodes (laser diode LD, coupling diode D, start diode SD) and thyristors (setting thyristor S, transfer thyristor T) do not necessarily have an anode terminal configured as an electrode, a gate terminal, and a cathode terminal. It may not be. Therefore, in the following, a terminal may be abbreviated and described in ().

Next, electrical connection of each element in the light emitting chip C1 (C) will be described.
The respective anodes of the laser diodes LD are connected to the substrate 80 of the light emitting chip C1 (C) (anode common). These anodes are connected to the power supply line 200a (see FIG. 4B) via the back surface electrode 91 (see FIG. 6B described later) which is a Vsub terminal provided on the back surface of the substrate 80. The power supply line 200 a is supplied with the reference potential Vsub from the reference potential supply unit 160.
Note that this connection is a configuration when using a p-type substrate 80, and when using an n-type substrate, the polarity is reversed, and when using an intrinsic (i) -type substrate to which no impurity is added. A terminal connected to the power supply line 200a for supplying the reference potential Vsub is provided on the side where the driving unit 101 and the light emitting unit 102 of the substrate are provided.

The cathodes of the laser diodes LD are connected to the anodes of the setting thyristors S.
The cathodes of the setting thyristors S are connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal. In the light emitting chip C1, the φI terminal is connected to the lighting signal line 204-1 via the current limiting resistor RI provided outside the light emitting chip C1 (C), and the lighting signal φI1 is transmitted from the lighting signal generation unit 140 (See Figure 4 (b)). The lighting signal φI1 supplies a current for lighting to the laser diodes LD1 to LD128. The lighting signal lines 204-2 to 204-40 are connected to the φI terminals of the other light emitting chips C2 to C40 through the current limiting resistors RI, and the lighting signals φI2 to φI40 are transmitted from the lighting signal generation unit 140. (See FIG. 4 (b)).

The cathodes of the odd-numbered transfer thyristors T 1, T 3,... Are connected to the first transfer signal line 72 along the arrangement of the transfer thyristors T. The first transfer signal line 72 is connected to the φ1 terminal through the current limiting resistor R1. The first transfer signal line 201 (see FIG. 4B) is connected to the φ1 terminal, and the first transfer signal φ1 is transmitted from the transfer signal generation unit 120.
On the other hand, along the arrangement of the transfer thyristors T, the cathodes of the even-numbered transfer thyristors T 2, T 4,... Are connected to the second transfer signal line 73. The second transfer signal line 73 is connected to the φ2 terminal through the current limiting resistor R2. The second transfer signal line 202 (see FIG. 4B) is connected to the φ2 terminal, and the second transfer signal φ2 is transmitted from the transfer signal generation unit 120.

  The gates Gt1 to Gt128 (in the case of no distinction, denoted as the gate Gt) of the transfer thyristors T1 to T128 are denoted as gates Gs1 to Gs128 (in the case of not being distinguished, the gate Gs) of the setting thyristors S1 to S128 of the same number. ) Are connected one-on-one. Therefore, the gates Gt1 to Gt128 and the gates Gs1 to Gs128 have the same numbers and are electrically at the same potential. Therefore, for example, the gate Gt1 (gate Gs1) indicates that the potential is the same.

  Coupling diodes D1 to D127 are respectively connected between the gates Gt in which the gates Gt1 to Gt128 of the transfer thyristors T1 to T128 are paired in order of number. That is, the coupling diodes D1 to D127 are connected in series so as to be respectively sandwiched between the gates Gt1 to Gt128. The direction of the coupling diode D1 is connected in the direction in which current flows from the gate Gt1 to the gate Gt2. The same applies to the other coupling diodes D2 to D127.

  The gates Gt of the transfer thyristors T are connected to the power supply line 71 via power supply line resistances Rg provided corresponding to the respective transfer thyristors T. The power supply line 71 is connected to the Vga terminal. The power supply line 200b (see FIG. 4B) is connected to the Vga terminal, and the power supply potential Vga is supplied from the power supply potential supply unit 170. Since the gate Gs of the setting thyristor S is connected to the gate Gt of the transfer thyristor T, the gate Gs of the setting thyristor S is also connected to the power supply line 71 via the power supply line resistance Rg.

  The gate Gt1 of the transfer thyristor T1 is connected to the cathode of the start diode SD. On the other hand, the anode of the start diode SD is connected to the second transfer signal line 73.

  FIG. 6 is an example of a plan layout view and a cross sectional view of the light emitting chip C according to the first embodiment. 6 (a) is a plan layout view of the light emitting chip C, and FIG. 6 (b) is a cross-sectional view taken along the line VIB-VIB of FIG. 6 (a). Here, since the connection relationship between the light emitting chip C and the signal generation circuit 110 is not shown, it is not necessary to take the light emitting chip C1 as an example. Therefore, the light emitting chip C is described.

  FIG. 6A shows a portion centered on the laser diodes LD1 to LD4, the setting thyristors S1 to S4, and the transfer thyristors T1 to T4. The positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the drawing for the sake of convenience. The Vsub terminal (back electrode 91) provided on the back surface of the substrate 80 is drawn out of the substrate 80 and shown. Assuming that terminals are provided corresponding to FIG. 4A, the φ2 terminal, the φI terminal, and the current limiting resistor R2 are provided at the right end of the substrate 80. The start diode SD may be provided at the right end of the substrate 80.

  Then, in FIG. 6A, the arrow indicates the direction in which the light of the laser diode LD is emitted. Here, the surface from which the light of the laser diode LD is emitted is taken as a cleavage surface. The reason why the surface from which the light of the laser diode LD is emitted is a cleavage surface will be described later.

In FIG. 6B, which is a cross-sectional view taken along the line VIB-VIB of FIG. 6A, the setting thyristor S1 / laser diode LD1, the transfer thyristor T1, the coupling diode D1, and the power supply line resistance Rg1 are shown from the bottom of the figure. ing. The setting thyristor S1 is stacked on the laser diode LD1.
And in the figure of FIG. 6 (a), (b), the main element and terminal are described by the name. In the front surface of the substrate 80, the arrangement direction of the laser diodes LD (laser diodes LD1 to LD4) is the x direction, and the direction orthogonal to the x direction is the y direction. The direction from the back surface to the front surface of the substrate 80 is taken as the z direction. Note that the direction along the xy plane may be referred to as the lateral direction, the z direction as the upper side, and the −z direction as the lower side.

The planar layout of the light emitting chip C will be described with reference to FIG. The light emitting chip C includes a plurality of islands (islands 301 to 306, etc.).
The island 301 is provided with a laser diode LD1 and a setting thyristor S1. The island 302 is provided with a transfer thyristor T1 and a coupling diode D1. The island 303 is provided with a power supply line resistance Rg1. The island 304 is provided with a start diode SD. The island 305 is provided with a current limiting resistor R1 and the island 306 is provided with a current limiting resistor R2.
In the light emitting chip C, a plurality of islands similar to the islands 301, 302, and 303 are formed in parallel. In these islands, laser diode LD2, LD3, LD4, ..., setting thyristors S2, S3, S4, ..., transfer thyristors T2, T3, T4, ..., coupling diodes D2, D3, D4, ..., etc., island 301 , 302, 303 in the same manner.

Here, the islands 301 to 306 will be described in detail with reference to FIGS. 6 (a) and 6 (b).
The island 301, as shown in FIG. 6B, includes a p-type anode layer 81 (p-anode layer 81), a light-emitting layer 82, and an n-type cathode layer 83 (p-type substrate 80 (substrate 80)). n cathode layer 83), tunnel junction (tunnel diode) layer 84 (tunnel junction layer 84), p-type anode layer 85 (p-anode layer 85), n-type gate layer 86 (n-gate layer 86), p-type A gate layer 87 (p gate layer 87) and an n-type cathode layer 88 (n cathode layer 88) are sequentially provided.

  The laser diode LD1 provided in the island 301 is composed of the p anode layer 81, the light emitting layer 82, and the n cathode layer 83, and the setting thyristor S1 similarly provided in the island 301 is the p anode layer 85, the n gate layer 86, The p gate layer 87 and the n cathode layer 88 are formed. The setting thyristor S1 uses the n-type ohmic electrode 321 (n ohmic electrode 321) provided on the n cathode layer 88 (region 311) as a cathode electrode, and the p gate is exposed by removing the n cathode layer 88. The p-type ohmic electrode 331 (p ohmic electrode 331) provided on the layer 87 is an electrode of the gate Gs1 (sometimes referred to as a gate terminal Gs1).

  The p-anode layer 81 includes a current confinement layer 81 b (see FIG. 7 described later). The current confinement layer 81 b is provided to limit (current confinement) the current flowing through the laser diode LD to the central portion of the laser diode LD. That is, the peripheral portion of the laser diode LD has many defects due to the mesa etching. Therefore, non-radiative recombination is likely to occur. Therefore, the current narrowing layer 81b is provided such that the central portion of the laser diode LD becomes a current passing portion α where current easily flows and the peripheral portion becomes a current blocking portion β where current hardly flows. As shown in the laser diode LD1 of FIG. 6A, the inside of the broken line is the current passing portion α, and the outside of the broken line is the current blocking portion β.

  If the current blocking portion β is on the side from which the light of the laser diode LD is emitted, a loss may occur and the light amount may be reduced. Therefore, the light emitting surface (end surface) from which the light indicated by the arrow of the laser diode LD is emitted is a cleavage surface so as to remove the current blocking portion β. For this reason, there is no current blocking portion β on the light emitting surface side (the −y direction in FIG. 6A) of the laser diode LD. The surface from which the light of the laser diode LD is emitted may be formed by etching, and when the loss is small, it is not necessary to remove the portion of the current blocking portion β. In addition, as a merit not to remove the portion of the current blocking portion β, by providing a portion (window structure) which does not emit light in a portion from which light is emitted, COD (Catastrophic Optical Damage) which becomes a problem at high light output in the end surface emission type is avoided. It can.

  When the current confinement layer 81b is provided, the power consumed for non-radiative recombination is suppressed, so power consumption can be reduced and the light extraction efficiency is improved. The light extraction efficiency is the amount of light that can be extracted per power.

When the current blocking portion β is formed by oxidation as described later, a region equidistant from the periphery of the island 301 is the current blocking portion β, but in FIG. 6A, the current blocking portion β is schematically shown. , And not equidistant from the perimeter of the island 301. That is, the width of the current blocking portion β in the y direction of the island 301 in FIG. 6A is different from the width of the current blocking portion β in the ± x direction.
The current confinement layer 81b will be described later.

The island 302 is configured by sequentially providing a p anode layer 85, an n gate layer 86, a p gate layer 87, and an n cathode layer 88 on a p-type substrate 80. The p anode layer 85, the n gate layer 86, the p gate layer 87, and the n cathode layer 88 are the same as the laminated semiconductor layers constituting the setting thyristor S1.
The transfer thyristor T <b> 1 provided in the island 302 is composed of ap anode layer 85, an n gate layer 86, ap gate layer 87, and an n cathode layer 88. The n ohmic electrode 323 provided on the n cathode layer 88 (region 313) is used as a cathode terminal, and the p ohmic electrode 332 provided on the p gate layer 87 exposed by removing the n cathode layer 88 is gated. A terminal of Gt1 (sometimes referred to as a gate terminal Gt1) is used.

  Similarly, the coupling diode D1 provided in the island 302 is composed of ap gate layer 87 and an n cathode layer 88. The n ohmic electrode 324 provided on the n cathode layer 88 (region 314) is used as a cathode terminal, and the p ohmic electrode 332 provided on the p gate layer 87 exposed by removing the n cathode layer 88 is used as an anode. Use as a terminal. That is, the coupling diode D1 uses the p gate layer 87 as an anode and the n cathode layer 88 as a cathode. Here, the p-ohmic electrode 332 which is the anode terminal of the coupling diode D1 is the same as the gate Gt1 (gate terminal Gt1).

The island 303 is configured by sequentially providing a p anode layer 85, an n gate layer 86, and a p gate layer 87 on a p-type substrate 80. The p-anode layer 85, the n-gate layer 86, and the p-gate layer 87 are the same as the laminated semiconductor layers constituting the setting thyristor S1.
The power supply line resistance Rg1 provided in the island 303 is configured by the p gate layer 87. That is, the power supply line resistance Rg1 uses the p gate layer 87 between the p ohmic electrode 333 and the p ohmic electrode 334 provided on the p gate layer 87 as a resistance.

  Similar to the island 302, the island 304 is configured by sequentially providing a p anode layer 85, an n gate layer 86, a p gate layer 87, and an n cathode layer 88 on a p-type substrate 80. The start diode SD provided in the island 304 is composed of the p gate layer 87 and the n cathode layer 88. That is, the start diode SD uses the n ohmic electrode 325 provided on the n cathode layer 88 (region 315) as a cathode terminal. Furthermore, the p ohmic electrode 335 provided on the p gate layer 87 exposed by removing the n cathode layer 88 is used as an anode terminal. That is, the start diode SD uses the p gate layer 87 as an anode and the n cathode layer 88 as a cathode.

  Similar to the island 303, the islands 305 and 306 are configured by sequentially providing a p anode layer 85, an n gate layer 86, and a p gate layer 87 on a p-type substrate 80. The current limiting resistor R1 provided in the island 303 and the current limiting resistor R2 provided in the island 306 are each provided with two p-ohmic electrodes (no reference numeral) like the power supply line resistance Rg1 provided in the island 303. ) Between the p-gate layers 87).

Then, as shown in FIG. 6B, the light emitting chip C is provided with a protective layer 90 made of an insulating material provided so as to cover the surfaces and the side surfaces of these islands.
In FIG. 6A, the arrow indicates the direction in which the light of the laser diode LD is emitted. The surface from which the light of the laser diode LD is emitted is a cleavage surface as described above. For this reason, the protective layer 90 is not provided on the surface from which the light of the laser diode LD is emitted.
When the light of the laser diode LD is emitted through the protective layer 90 without removing the protective layer 90, the protective layer 90 should be translucent to the light emitted by the laser diode LD. Good.

  Then, through-holes (FIG. 6A) in which these islands and wirings such as the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, and the lighting signal line 75 are provided in the protective layer 90. It is connected via)). In the following description, descriptions of the protective layer 90 and the through holes will be omitted.

  Further, as shown in FIG. 6B, on the back surface of the substrate 80, a back surface electrode 91 to be a Vsub terminal is provided.

The p anode layer 81, the light emitting layer 82, the n cathode layer 83, the tunnel junction layer 84, the p anode layer 85, the n gate layer 86, the p gate layer 87, and the n cathode layer 88 are semiconductor layers, It is laminated monolithically by epitaxial growth.
Then, the semiconductor layer between the islands is removed by etching (mesa etching) so as to be a plurality of islands separated from one another (such as the islands 301 to 306). The p anode layer 81 may double as the substrate 80.

  Here, the notation of the p anode layer 81 and the n cathode layer 83 corresponds to the function (function) in the case of constituting the laser diode LD. That is, the p anode layer 81 functions as an anode, and the n cathode layer 83 functions as a cathode. In the laser diode LD, each of the p anode layer 81 and the n cathode layer 83 functions as a cladding. Therefore, it may be described as the p anode (cladding) layer 81 and the n cathode (cladding) layer 83.

The notations of the p anode layer 85, the n gate layer 86, the p gate layer 87, and the n cathode layer 88 correspond to the functions (functions) in the case of configuring the setting thyristor S and the transfer thyristor T. That is, the p anode layer 85 functions as an anode, the n gate layer 86, the p gate layer 87 functions as a gate, and the n cathode layer 88 functions as a cathode.
When the coupling diode D and the power supply line resistance Rg are formed, they have different functions as described above.

The connection relationship between each element will be described with reference to FIG.
The lighting signal line 75 includes a trunk 75a and a plurality of branches 75b. The trunk 75a is provided to extend in the column direction of the setting thyristor S / laser diode LD. The branch 75 b branches from the trunk 75 a and is connected to an n-ohmic electrode 321 which is a cathode terminal of the setting thyristor S 1 provided on the island 301. The cathode terminals of the other setting thyristors S are similarly connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal.

The first transfer signal line 72 is connected to an n-ohmic electrode 323 which is a cathode terminal of the transfer thyristor T <b> 1 provided in the island 302. The first transfer signal line 72 is also connected to cathode terminals of other odd-numbered transfer thyristors T provided on an island similar to the island 302. The first transfer signal line 72 is connected to the φ1 terminal through the current limiting resistor R1 provided in the island 305.
On the other hand, the second transfer signal line 73 is connected to an n-ohmic electrode (no reference numeral) which is a cathode terminal of the even-numbered transfer thyristor T provided in the island not having a reference numeral. The second transfer signal line 73 is connected to the φ2 terminal through the current limiting resistor R2 provided in the island 306.

  The power supply line 71 is connected to a p-ohmic electrode 334 which is one terminal of the power supply line resistance Rg1 provided on the island 303. One terminal of the other power supply line resistance Rg is also connected to the power supply line 71. The power supply line 71 is connected to the Vga terminal.

  The p ohmic electrode 331 which is the gate terminal Gs1 of the setting thyristor S1 provided in the island 301 is connected to the p ohmic electrode 332 which is the gate terminal Gt1 of the transfer thyristor T1 provided in the island 302 by the connection wiring 76. There is.

The p ohmic electrode 332 which is the gate terminal Gt1 of the transfer thyristor T1 provided in the island 302 is connected to the p ohmic electrode 333 which is the other terminal of the power supply line resistance Rg1 of the island 303 by the connection wiring 77.
An n-ohmic electrode 324 which is a cathode terminal of the coupling diode D1 provided in the island 302 is connected to a p-type ohmic electrode (without a reference numeral) which is a gate terminal Gt2 of the adjacent transfer thyristor T2 by a connection wiring 79.
Although the description is omitted here, the same applies to other laser diodes LD, setting thyristors S, transfer thyristors T, coupling diodes D, and the like.

The p ohmic electrode 332 which is the gate terminal Gt1 of the transfer thyristor T1 of the island 302 is connected to the n ohmic electrode 325 which is the cathode terminal of the start diode SD provided in the island 304 by the connection wiring 78. A p-ohmic electrode 335 which is an anode terminal of the start diode SD is connected to the second transfer signal line 73.
The above connection and configuration are those when using a p-type substrate 80, and when using an n-type substrate, the polarity is reversed. Further, in the case of using an i-type substrate, a terminal connected to the power supply line 200a for supplying the reference potential Vsub is provided on the side of the substrate where the driver portion 101 and the light emitting portion 102 are provided. The connection and configuration are the same as either of the cases of using an n-type substrate when using a p-type substrate.

(Basic operation of light emitting chip C)
In FIG. 7, in the light emitting chip C according to the first embodiment, the island 301 provided with the laser diode LD1 and the setting thyristor S1, the island 302 provided with the transfer thyristor T and the like, and the power supply line resistance Rg1 are provided. It is an expanded sectional view of island 303. As shown in FIG. 7 is a cross-sectional view taken along the line VIB-VIB in FIG. 6A, but is a cross-sectional view seen from the -x direction opposite to FIG. 6B.

  The laminated structure of the laser diode LD1 and the setting thyristor S1 in the island 301 and the transfer thyristor T1 in the island 302 will be described in detail below.

  As shown in the island 301, the laser diode LD1 is composed of ap anode layer 81 acting as a cladding layer, a light emitting layer 82, and an n cathode layer 83 acting as a cladding layer. Therefore, the p anode layer 81 is referred to as the p anode (cladding) layer 81 and the n cathode (cladding) layer 83, and in FIG. 7, the p anode (cladding) layer 81 is p (cladding) and n cathode (cladding) layer 83 Is denoted by n (cladding).

  The p anode (cladding) layer 81 is configured to include a current confinement layer 81 b. That is, the p-anode (cladding) layer 81 is composed of a lower p-anode (cladding) layer 81a, a current confinement layer 81b, and an upper p-anode (cladding) layer 81c.

  The light emitting layer 82 is a quantum well structure in which well layers and barrier layers are alternately stacked. The light emitting layer 82 may be an intrinsic (i) layer to which no impurity is added. The light emitting layer 82 may have a structure other than the quantum well structure, and may be, for example, a quantum wire (quantum wire) or a quantum box (quantum dot).

  While the light emitted from the light emitting layer 82 is confined between the p anode (cladding) layer 81 and the n cathode (cladding) layer 83, the p anode ( A cladding layer 81, an n cathode (cladding) layer 83, and a light emitting layer 82 are set. In this case, light is emitted parallel to the substrate 80 with the side surface (end surface) of the light emitting layer 82 as a light emission surface, as shown by the arrow.

  The setting thyristor S <b> 1 includes ap anode layer 85, an n gate layer 86, ap gate layer 87, and an n cathode layer 88. In FIG. 7, the p anode layer 85 is described as a p anode or p, the n gate layer 86 as an n gate or n, the p gate layer 87 as a p gate or p, and an n cathode layer 88 as an n cathode or n.

  On the other hand, the transfer thyristor T1 provided in the island 302 is composed of the p anode layer 85, the n gate layer 86, the p gate layer 87, and the n cathode layer 88 as in the setting thyristor S1. That is, the setting thyristor S and the transfer thyristor T have a pnpn four-layer structure.

  As described above, the laser diode LD1 and the setting thyristor S1 in the island 301 are stacked via the tunnel junction layer 84. That is, the laser diode LD1 and the setting thyristor S1 are connected in series. The n-ohmic electrode 321 which is the cathode terminal of the setting thyristor S1 is connected to the lighting signal line 75 to which the lighting signal φI1 is supplied, and the p anode (cladding) layer 81 which is the anode of the laser diode LD1 has the reference potential Vsub. Are connected to a p-type substrate 80 to be supplied. That is, a voltage between the reference potential Vsub and the potential of the lighting signal φI1 is applied to the laser diode LD1 and the setting thyristor S1 connected in series.

  On the other hand, the n-ohmic electrode 323 which is the cathode terminal of the transfer thyristor T1 in the island 302 is connected to the first transfer signal line 72 to which the first transfer signal φ1 is supplied. The p-anode layer 85, which is the anode of the transfer thyristor T1, is connected to the p-type substrate 80 to which the reference potential Vsub is supplied. That is, a voltage between the reference potential Vsub and the potential of the first transfer signal φ1 is applied to the transfer thyristor T1.

<Tunnel junction layer 84>
Here, the tunnel junction layer 84 will be described.
FIG. 8 is a diagram further illustrating the laminated structure of the laser diode LD and the setting thyristor S. As shown in FIG. 8 (a) is a schematic energy band diagram in the laminated structure of the laser diode LD and the setting thyristor S, FIG. 8 (b) is an energy band diagram in the reverse bias state of the tunnel junction layer 84, FIG. ) Shows the current-voltage characteristic of the tunnel junction layer 84.

Tunnel junction layer 84 is n-type impurity (dopant) is constituted by a n ⁺⁺ layer 84a was added at a high concentration (dope) was added p-type impurity at a high concentration and p ⁺⁺ layer 84b.
As shown in the energy band diagram of FIG. 8A, when a voltage is applied between the n ohmic electrode 321 and the back surface electrode 91 of FIG. 7 so that the laser diode LD and the setting thyristor S have a forward bias, A reverse bias occurs between the n ⁺⁺ layer 84 a and the p ⁺⁺ layer 84 b of the tunnel junction layer 84.

Tunnel junction layer 84 is bonded to the n ⁺⁺ layer 84a doped with an n-type impurity at a high concentration, the p ⁺⁺ layer 84b doped with the p-type impurity at a high concentration. Therefore, when the width of the depletion region is narrow and forward biased, electrons tunnel from the conduction band (conduction band) on the n ⁺⁺ layer 84 a side to the valence band (valence band) on the p ⁺⁺ layer 84 b side. At this time, negative resistance characteristics appear.
On the other hand, as shown in FIG. 8B, when the tunnel junction layer 84 (tunnel junction) is reverse biased (-V), the potential Ev of the valence band (valence band) on the p ⁺⁺ layer 84b side is It is higher than the potential Ec of the conduction band (conduction band) on the n ⁺⁺ layer 84 a side. ^The valence band of the ^{p ++} layer 84b from (valence ^band), electrons tunnel to the ^{n ++} layer 84a side of the conduction band (conduction band). Then, as the reverse bias voltage (-V) increases, electrons are more likely to tunnel. That is, as shown in FIG. 8C, in the tunnel junction layer 84 (tunnel junction), current easily flows in the reverse bias.

Therefore, as shown in FIG. 8A, when the setting thyristor S is turned on, current flows between the laser diode LD and the setting thyristor S even if the tunnel junction layer 84 is reverse biased. Thereby, the laser diode LD emits light (lights up).
As described later, when the connected transfer thyristor T is turned on to be in the on state, the setting thyristor S is in a state in which the transition to the on state is possible (transition possible state). Then, when the lighting signal φI becomes “L” as described later, the setting thyristor S is turned on and turned on, and the laser diode LD is turned on (lighting is set).

<Thyristor>
Next, the basic operation of the thyristor (transfer thyristor T, setting thyristor S) will be described. As described above, a thyristor is a semiconductor device having three terminals of an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate), and is a p-type semiconductor layer made of GaAs, GaAlAs, AlAs, etc. (P anode layer 85, p gate layer 87), and n type semiconductor layers (n gate layer 86, n cathode layer 88) are stacked on the substrate 80. That is, the thyristor has a pnpn structure. Here, the forward potential (diffusion potential) Vd of the pn junction formed of the p-type semiconductor layer and the n-type semiconductor layer will be described as 1.5 V as an example.

Hereinafter, as an example, reference potential Vsub supplied to back surface electrode 91 (see FIGS. 5 and 6) which is a Vsub terminal is 0 V (hereinafter referred to as “H”) as a high level potential (hereinafter referred to as “H”). Or "H" (0 V). -3.3 V as the first low level potential (hereinafter referred to as "L1" (-3.3 V)), -5 V as the second low level potential. " (Hereinafter, it is described as "L2" (-5V).).
The power supply potential Vga supplied to the Vga terminal is “L1” (−3.3 V). The first transfer signal φ1 and the second transfer signal φ2 are signals having “H” (0 V) and “L1” (−3.3 V). The lighting signal φI is a signal having “H” (0 V) and “L2” (−5 V).

First, the operation of the thyristor alone will be described. Here, it is assumed that the anode of the thyristor is 0V.
An off-state thyristor in which no current flows between the anode and the cathode is turned on when a potential lower than the threshold voltage (a negative potential greater than the absolute value) is applied between the anode and the cathode. Transition (turn on). Here, the threshold voltage of the thyristor is a value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate.
When turned on, the gate of the thyristor is at a potential close to the potential of the anode terminal. Here, since the anode is at 0V, the gate is at 0V. In addition, the cathode of the thyristor in the on state has a potential close to the potential obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the anode. Here, since the anode is at 0 V, the cathode of the thyristor in the on state has a potential close to -1.5 V (a negative potential greater than 1.5 V in absolute value). The potential of the cathode is set in relation to a power supply that supplies a current to the thyristor in the on state.

The thyristor in the on state has a potential (negative potential with a small absolute value, 0 V or positive potential) higher than the potential required to maintain the on state (potential close to -1.5 V above) , Transition to the off state (turn off).
On the other hand, a potential lower than the potential required to maintain the on state (a negative potential equal to or greater than the absolute value) is continuously applied to the cathode of the on-state thyristor to maintain the on-state current When the current is supplied, the thyristor maintains the on state.

The operation of the transfer thyristor T1 will be specifically described. In the transfer thyristor T1, the reference potential Vsub ("H" (0 V)) is applied to the anode, and the potential ("H" (0 V) or "L1" (-3.3 V)) of the first transfer signal φ1 is applied to the cathode. . Here, assuming that the first transfer signal φ1 is “L1” (−3.3 V), −3.3 V is applied between the anode and the cathode of the transfer thyristor T1. Therefore, when the threshold voltage of the transfer thyristor T1 is a potential of -3.3 V or less (a negative potential exceeding the absolute value), that is, the potential of the gate Gt1 is -1.8 V or more (a negative value of the absolute value or less) , The transfer thyristor T1 is turned on. In addition, when a voltage equal to or lower than the threshold voltage of the transfer thyristor T1 (a voltage higher than the absolute value) is applied between the cathode and the anode, the transfer thyristor T1 is turned on.
The same applies to the other transfer thyristors T.

Next, operations of the laser diode LD and the setting thyristor S connected in series will be described using the laser diode LD1 and the setting thyristor S1.
For the laser diode LD1 and the setting thyristor S1 connected in series, the reference potential Vsub (“H” (0 V)) and the potential of the lighting signal φ I1 (“H” (0 V) or “L2” (−5 V)) Applied. Assuming that the lighting signal φI1 is “L2” (−5 V), −5 V is divided into the laser diode LD1 and the setting thyristor S1. Here, it is assumed that the voltage applied to the laser diode LD1 is -1.7 V, for example. Then, when the setting thyristor S1 is in the off state, -3.3 V is applied to the setting thyristor S1. As in the case of the transfer thyristor T1 described above, in the case where the threshold voltage of the setting thyristor S1 is a potential of -3.3 V or less (a negative potential which exceeds the absolute value), that is, the potential of the gate Gs1 is -1.8 V or more In the case of (a negative potential which is less than the absolute value), the setting thyristor S1 is turned on. Then, current flows through the laser diode LD1 and the setting thyristor S1 connected in series, and the laser diode LD1 is lighted (emitted).

On the other hand, when the threshold voltage of the setting thyristor S1 is larger than -3.3 V in absolute value, the setting thyristor S1 is not turned on and maintains the off state. Therefore, the laser diode LD1 also maintains non-lighting (non-emission).
When the setting thyristor S1 is turned on, the voltage applied to the laser diode LD1 and the setting thyristor S1 connected in series decreases at an absolute value. However, if the voltage applied to the setting thyristor S1 is a voltage that maintains the on state of the setting thyristor S1, the setting thyristor S1 maintains the on state. As a result, the laser diode LD1 also continues lighting (emission).
The same applies to the other laser diodes LD and the setting thyristors S.

  In this way, since control of the setting thyristor S for driving the laser diode LD and the laser diode LD can be performed by the lighting signal φI, lighting control becomes easy.

  The voltage shown above is an example, and changes according to the characteristics of the setting thyristor S, the transfer thyristor T, and / or the light emission wavelength or the light amount of the laser diode LD. In that case, “L1” or / and “L2” may be adjusted.

  Since the thyristors (setting thyristors S and transfer thyristors T) are made of a semiconductor such as GaAs, they may emit light between the n gate layer 86 and the p gate layer 87 in the on state. The amount of light emitted from the thyristor is determined by the area of the cathode and the current flowing between the cathode and the anode. Therefore, when light emission from a thyristor is not used, for example, the area of the cathode is reduced, or an electrode (n ohmic electrode 321 in setting thyristor S1 and / or n ohmic electrode 323 in transfer thyristor T1) or wiring is formed. Unwanted light may be suppressed by light shielding with a material or the like.

(Operation of light emitting device 65)
Next, the operation of the light emitting device 65 will be described.
As described above, the light emitting device 65 includes the light emitting chips C1 to C40 (see FIGS. 3 and 4).
Since the light emitting chips C1 to C40 are driven in parallel, it suffices to explain the operation of the light emitting chip C1.
<Timing chart>
FIG. 9 is a timing chart for explaining the operation of the light emitting device 65 and the light emitting chip C.
FIG. 9 shows a timing chart of a portion for controlling (referred to as lighting control) the lighting (emission) or non-lighting (non-emission) of the five laser diodes LD of the laser diode LD1 to LD5 of the light emitting chip C1. There is. In FIG. 9, the laser diodes LD1, LD2, LD3, and LD5 of the light emitting chip C1 are turned on, and the laser diode LD4 is turned off (no light emission).

In FIG. 9, it is assumed that time passes in alphabetical order from time a to time l. The laser diode LD1 is turned on in period T (1), the laser diode LD2 is turned on in period T (2), the laser diode LD3 is turned on in period T (3), and the laser diode LD4 is turned on in period T (4). ) Or non-lighting (non-lighting) control (lighting control). Hereinafter, the laser diode LD of which the number is 5 or more is controlled to be lit in the same manner.
Here, the periods T (1), T (2), T (3),... Have the same length, and are referred to as the period T when they are not distinguished from one another.

  The first transfer signals φ1 and φ2 transmitted to the φ1 terminal (see FIGS. 5 and 6) and the second transfer signal φ2 transmitted to the φ2 terminals (see FIGS. 5 and 6) are “H” (0 V) and “L1”. Signal having two potentials (“-3.3 V”). The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, period T (1) and period T (2)). In the following, “H” (0 V) and “L1” (−3.3 V) may be abbreviated as “H” and “L1”.

The first transfer signal φ1 shifts from “H” (0 V) to “L1” (−3.3 V) at start time b of period T (1), and shifts from “L1” to “H” at time f. . Then, at the end time i of the period T (2), the state transitions from “H” to “L1”.
The second transfer signal φ2 is “H” (0 V) at the start time b of the period T (1), and shifts from “H” (0 V) to “L1” (−3.3 V) at time e. Then, at time j after the end time i of the period T (2), the state changes from “L1” to “H”.
When the first transfer signal φ1 and the second transfer signal φ2 are compared, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted behind the period T on the time axis. On the other hand, in the second transfer signal φ2, the waveform indicated by the broken line and the waveform in the period T (2) in the period T (1) are repeated after the period T (3). The waveform of the period T (1) of the second transfer signal φ2 is different from that of the period T (3) or later, because the period T (1) is a period in which the light emitting device 65 starts operation.

  The pair of transfer signals of the first transfer signal φ1 and the second transfer signal φ2 is the same as the transfer thyristor T in the on state by transferring (propagating) the on state of the transfer thyristor T in order of numbers as described later. The laser diode LD of the number is designated as a target of lighting (emission) or non-lighting (non-emission) control (lighting control).

Next, the lighting signal φI1 transmitted to the φI terminal of the light emitting chip C1 will be described. The lighting signals φI2 to φI40 are transmitted to the other light emitting chips C2 to C40, respectively. The lighting signal φI1 is a signal having two potentials of “H” (0 V) and “L2” (−5 V). Below, "H" (0 V) and "L2" (-5 V) may be abbreviated as "H" and "L2".
Here, the lighting signal φI1 will be described in a period T (1) of lighting control of the laser diode LD1 of the light emitting chip C1. The lighting signal φI1 is “H” (0 V) at the start time b of the period T (1), and shifts from “H” (0 V) to “L2” (−5 V) at time c. Then, at time d, "L2" shifts to "H", and at time e, "H" is maintained.

  The operations of the light emitting device 65 and the light emitting chip C1 will be described according to the timing chart shown in FIG. 9 with reference to FIGS. 4, 5, 6 and 7. In the following, periods T (1) and T (2) in which the laser diodes LD1 and LD2 are controlled to light will be described.

(1) Time a
<Light Emitting Device 65>
At time a, the reference potential supply unit 160 of the signal generation circuit 110 of the light emitting device 65 sets the reference potential Vsub to “H” (0 V). Power supply potential supply unit 170 sets power supply potential Vga to “L1” (−3.3 V). Then, the power supply line 200a on the circuit substrate 62 of the light emitting device 65 becomes "H" (0 V) of the reference potential Vsub, and the Vsub terminals of the light emitting chips C1 to C40 become "H" (see FIG. 4).
Similarly, the power supply line 200b becomes "L1" (-3.3 V) of the power supply potential Vga, and the Vga terminals of the light emitting chips C1 to C40 become "L1" (see FIG. 4). As a result, the power supply lines 71 of the light emitting chips C1 to C40 become “L1” (see FIG. 5).

  Then, the transfer signal generation unit 120 of the signal generation circuit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to “H” (0 V). Then, the first transfer signal line 201 and the second transfer signal line 202 become “H” (see FIG. 4). As a result, the φ1 terminal and the φ2 terminal of each of the light emitting chips C1 to C40 become “H”. The potential of the first transfer signal line 72 connected to the φ1 terminal through the current limiting resistor R1 also becomes “H”, and the second transfer signal line 73 connected to the φ1 terminal through the current limiting resistor R2 is also It becomes "H" (see FIG. 5).

  Furthermore, the lighting signal generation unit 140 of the signal generating circuit 110 sets the lighting signals φI1 to φI40 to “H” (0 V). Then, the lighting signal lines 204-1 to 204-40 become "H" (see FIG. 4). As a result, each φI terminal of the light emitting chips C1 to C40 becomes “H” via the current limiting resistance RI, and the lighting signal line 75 connected to the φI terminal also becomes “H” (0 V) (FIG. 5) reference).

<Light-emitting chip C1>
The anode (p anode layer 85) of the transfer thyristor T is connected to the Vsub terminal set to “H” (0 V) via the back surface electrode 91 provided on the back surface of the substrate 80 (see FIG. 6). .

  The respective cathodes (n cathode layers 88) of the odd-numbered transfer thyristors T1, T3, T5,... Are connected to the first transfer signal line 72 via n ohmic electrodes (n ohmic electrodes 323 in the transfer thyristor T1). It is set to “H” (0 V). The cathode (n cathode layer 88) of each of the even-numbered transfer thyristors T2, T4, T6,... Is set to “H” (0 V) of the second transfer signal line 73 via the n ohmic electrode. Therefore, the transfer thyristor T has both the anode and the cathode at “H” (0 V), and is in the off state.

  The anode (p anode (cladding) layer 81) of the laser diode LD is connected to the Vsub terminal set to “H” (0 V) via the back surface electrode 91 provided on the back surface of the substrate 80 (see FIG. 6). On the other hand, the cathode (n cathode layer 88) of the setting thyristor S is connected to the lighting signal line 75 through the n ohmic electrode 321, and is set to "H" (0 V). Therefore, in each of the laser diode LD and the setting thyristor S connected in series, the anode and the cathode both become “H” (0 V) and are in the off state.

  The gate Gt1 is connected to the cathode of the start diode SD, as described above. The gate Gt1 is connected to the power supply line 71 of the power supply potential Vga ("L1" (-3.3 V)) through the power supply line resistance Rg1. The anode of the start diode SD is set to “H” (0 V) of the second transfer signal line 73. Therefore, the start diode SD is forward biased, and the cathode (gate Gt1) of the start diode SD changes from the potential ("H" (0 V)) of the anode of the start diode SD to the forward potential Vd (1.5 V) of the pn junction. It becomes the subtracted value (-1.5 V). Also, when the gate Gt1 becomes -1.5 V, the coupling diode D1 has the anode (gate Gt1) at -1.5 V and the cathode at the power supply line 71 ("L1" (-3.3 V) via the power supply line resistance Rg2. Because it is connected to), it becomes forward bias. Therefore, the potential of the gate Gt2 is −3 V obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (−1.5 V) of the gate Gt1. Further, the coupling diode D2 has an anode (gate Gt1) of -3 V and a cathode connected to the power supply line 71 ("L1" (-3.3 V)) via the power supply line resistance Rg2. However, since the potential difference is -0.3 V, which is smaller than the forward potential Vd (1.5 V) in absolute value, the potential of the gate Gt3 becomes the power supply potential Vga ("L1" (-3.3 V)). That is, the gate Gt of three or more numbers is not affected by the fact that the anode of the start diode SD is connected to the second transfer signal line 73 of "H" (0 V), and the potentials of these gates Gt are The potential of the power supply line 71 is the power supply potential Vga ("L1" (-3.3 V)).

  Since the gate Gt is the gate Gs, the potential of the gate Gs is the same as the potential of the gate Gt. Therefore, the threshold voltage of the transfer thyristor T and the setting thyristor S is a value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate Gt (gate Gs). That is, the threshold voltage of the transfer thyristor T1 and the setting thyristor S1 is -3 V, the transfer thyristor T2 and the threshold voltage of the setting thyristor S2 are -4.5 V, the transfer thyristor T3, the transfer thyristor T having a number of 3 or more, and the setting thyristor S The threshold voltage is -4.8V.

(2) Time b
At time b shown in FIG. 9, the first transfer signal φ1 shifts from “H” (0 V) to “L1” (−3.3 V). Thereby, the light emitting device 65 starts operation.
When the first transfer signal φ1 shifts from “H” to “L1”, the potential of the first transfer signal line 72 changes from “H” (0 V) to “L1” (−) through the φ1 terminal and the current limiting resistor R1. Transition to 3.3V). Then, the cathode of the transfer thyristor T1 becomes "L1", and -3.3 V is applied between the anode and the cathode of the transfer thyristor T1. The transfer thyristor T1 is turned on because the threshold voltage is −3V. As the transfer thyristor T1 is turned on, the potential of the first transfer signal line 72 is obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (“H” (0 V)) of the anode of the transfer thyristor T1. It becomes a potential close to -1.5 V (a negative potential whose absolute value is greater than 1.5 V). Here, the potential of the first transfer signal line 72 will be described as being -1.5V.

In addition, the threshold voltage of the transfer thyristor T having an odd number of 3 or more is -4.8V. The voltage (potential of the first transfer signal line 72) applied to the odd-numbered transfer thyristors T whose number is 3 or more is -1.5 V, so the odd-numbered transfer thyristors T whose number is 3 or more do not turn on .
On the other hand, the even-numbered transfer thyristors T can not be turned on because the second transfer signal φ2 is “H” (0 V) and the second transfer signal line 73 to which the cathode is connected is “H” (0 V).

When the transfer thyristor T1 is turned on, the potential of the gate Gt1 (gate Gs1) becomes “H” (0 V) which is the potential of the anode of the transfer thyristor T1. Then, the potential of the gate Gt2 (gate Gs2) is −1.5 V, the potential of the gate Gt3 (gate Gs3) is −3 V, and the potential of the gate Gt (gate Gs) whose number is 4 or more is “L1” (power potential Vga) -3.3V).
When the potential of the gate Gs1 becomes “H” (0 V), the threshold voltage of the setting thyristor S1 becomes −1.5 V. The threshold voltage of the transfer thyristor T2 and the setting thyristor S2 is -3 V, the threshold voltage of the transfer thyristor T3 and the setting thyristor S3 is -4.5 V, and the threshold voltage of the transfer thyristor T and the setting thyristor S is 4 or more. Becomes -4.8V.

  However, since the first transfer signal line 72 is set to -1.5 V by the on-state transfer thyristor T1, the odd-numbered transfer thyristors T in the off state are not turned on. Since the second transfer signal line 73 is “H” (0 V), the even-numbered transfer thyristors T are not turned on. Since the lighting signal line 75 is "H" (0 V), none of the laser diodes LD are lit.

  Immediately after time b (in this case, a change in the potential of the signal at time b causes a change in the thyristor or the like and then a steady state is obtained. The same applies to the other cases). In the on state, the other transfer thyristors T, the setting thyristors S, and the laser diode LD are in the off state.

(3) Time c
At time c, the lighting signal φI1 shifts from “H” (0 V) to “L2” (−5 V).
When the lighting signal φI1 shifts from “H” to “L2”, the lighting signal line 75 shifts from “H” (0 V) to “L2” (−5 V) via the current limiting resistors RI and φI terminals. Then, since -1.7 V is applied to the laser diode LD, -3.3 V is applied to the setting thyristor S1. Then, the setting thyristor S1 whose threshold voltage is −1.5 V is turned on. As a result, the laser diode LD1 connected in series with the setting thyristor S1 is lit (emitted). Then, the potential of the lighting signal line 75 becomes a potential close to -3.2V. Here, it is assumed that the potential of the lighting signal line 75 is −3.2V. The setting thyristor S2 has a threshold voltage of -3V. However, since -1.7V is applied to the laser diode LD2, the voltage applied to the setting thyristor S2 is -1.5V. Thus, the setting thyristor S2 is not turned on.
Immediately after time c, the transfer thyristor T1 and the setting thyristor S1 are in the on state, and the laser diode LD1 is lit (emit light).

(4) Time d
At time d, the lighting signal φI1 shifts from “L2” (−5 V) to “H” (0 V).
When the lighting signal φI1 shifts from “L2” to “H”, the potential of the lighting signal line 75 shifts from −3.2 V to “H” (0 V) through the current limiting resistors RI and φI terminals. Then, the cathode and the anode of each of the setting thyristor S1 and the laser diode LD1 turn to "H" (0 V), and the setting thyristor S1 is turned off and the laser diode LD1 is turned off . During the lighting period of the laser diode LD1, the lighting signal .phi.I1 is "d" from time c when the lighting signal .phi.I1 shifts from "H" to "L2" to It is a period of "L2".
Immediately after time d, the transfer thyristor T1 is in the on state.

(5) Time e
At time e, the second transfer signal φ2 shifts from “H” (0 V) to “L1” (−3.3 V). Here, the period T (1) for controlling the lighting of the laser diode LD1 ends, and the period T (2) for controlling the lighting of the laser diode LD2 starts.
When the second transfer signal φ2 shifts from “H” to “L1”, the potential of the second transfer signal line 73 shifts from “H” (0 V) to “L1” (−3.3 V) via the φ2 terminal. . As described above, the transfer thyristor T2 is turned on because the threshold voltage is −3V.
Thus, the potential of the gate Gt2 (gate Gs2) is “H” (0 V), the potential of the gate Gt3 (gate Gs3) is −1.5 V, the potential of the gate Gt4 (gate Gs4) is −3 V, and the number is 5 or more. The potential of the gate Gt (gate Gs) becomes “L1” (−3.3 V).
Immediately after time e, the transfer thyristors T1 and T2 are in the on state.

(6) Time f
At time f, the first transfer signal φ1 shifts from “L1” (−3.3 V) to “H” (0 V).
When the first transfer signal φ1 shifts from “L1” to “H”, the potential of the first transfer signal line 72 shifts from “L1” to “H” via the φ1 terminal. Then, both the anode and the cathode of the transfer thyristor T1 in the on state become “H” (0 V) and are turned off.
Then, the potential of the gate Gt1 (gate Gs1) changes toward the power supply potential Vga (“L1” (−3.3 V)) of the power supply line 71 via the power supply line resistance Rg1. As a result, a potential is applied (reverse bias) in the direction in which the coupling diode D1 does not flow current. Therefore, the influence that the gate Gt2 (gate Gs2) is "H" (0 V) does not affect the gate Gt1 (gate Gs1). That is, in the transfer thyristor T having the gate Gt connected by the reverse bias coupling diode D, the threshold voltage becomes −4.8 V, and the first transfer signal φ1 or the second transfer signal φ2 is “L1” (− Even if it becomes 3.3V, it does not turn on.
Immediately after time f, the transfer thyristor T2 is in the on state.

(7) Others At time g, when the lighting signal φI1 shifts from “H” (0 V) to “L2” (−5 V), the setting thyristor S2 is turned on similarly to the laser diode LD1 and setting thyristor S1 at time c. Then, the laser diode LD2 lights up (emits light).
When the lighting signal φI1 shifts from “L2” (−5 V) to “H” (0 V) at time h, the setting thyristor S2 is turned off as in the case of the laser diode LD1 and setting thyristor S1 at time d. , The laser diode LD2 is turned off.
Furthermore, when the first transfer signal φ1 shifts from “H” (0 V) to “L1” (−3.3 V) at time i, it is similar to the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. The transfer thyristor T3 having a threshold voltage of -3 V is turned on. At time i, the period T (2) for controlling the lighting of the laser diode LD2 ends, and the period T (3) for controlling the lighting of the laser diode LD3 starts.
The following is a repetition of what has been described.

  When the laser diode LD is not lighted (emitted) and kept non-lighted (not lighted), the lighting shown from time k to time l in the period T (4) in which the laser diode LD4 in FIG. 9 is lighted is controlled. As with the signal φI1, the lighting signal φI may be kept at “H” (0 V). By doing this, even if the threshold voltage of the setting thyristor S4 is -1.5 V, the setting thyristor S4 is not turned on, and the laser diode LD4 remains unlit (not emitting light).

As described above, the gates Gt of the transfer thyristors T are mutually connected by the coupling diode D. Therefore, when the potential of the gate Gt changes, the potential of the gate Gt connected to the gate Gt whose potential has changed via the forward-biased coupling diode D changes. Thereby, the threshold voltage of the transfer thyristor T having the gate whose potential has changed is changed. In the transfer thyristor T, the threshold voltage is −3.3 V or more (absolute value is a negative value below), and the first transfer signal φ1 or the second transfer signal φ2 is “H” (0 V) to “L1” ( Turn on at the timing of transition to −3.3 V).
Then, when the transfer thyristor T is turned on, the potential of the gate Gt becomes 0V. As a result, in the setting thyristor S whose gate Gt is connected to the gate Gt, the threshold voltage becomes -1.5V. Therefore, when the lighting signal φI shifts from “H” (0 V) to “L2” (−5 V), the setting thyristor S is applied with −3.3 V between the anode and the cathode and turned on. Then, the laser diode LD connected in series to the setting thyristor S lights up (emits light).

That is, when the transfer thyristor T is turned on, the setting thyristor S can be shifted to the on state. That is, when the transfer thyristor T is turned on, the laser diode LD to be subjected to lighting control is designated. Then, when the lighting signal φI becomes “L2” (−5 V), the setting thyristor S connected in series to the laser diode LD to be subjected to lighting control is turned on, and the laser diode LD is lit (lighted).
When the lighting signal φI is maintained at “H” (0 V), the setting thyristor S is maintained in the OFF state, and the laser diode LD is maintained in non-lighting (non-emission). That is, the lighting signal φI sets lighting / non-lighting of the laser diode LD.
Thus, the lighting signal φI is set according to the image data to control lighting or non-lighting of each laser diode LD.

(Method of manufacturing light emitting chip C)
A method of manufacturing the light emitting chip C will be described.
10, 11, 12 and 13 are diagrams for explaining a method of manufacturing the light emitting chip C. As shown in FIG. 10 (a) is a first laminated semiconductor layer forming step, FIG. 10 (b) is a first laminated semiconductor layer etching step, and FIG. 10 (c) is a second laminated semiconductor layer formation. 11 (d) shows a cathode electrode forming step, FIG. 11 (e) shows a cathode region forming step, FIG. 11 (f) shows an anode electrode forming step, FIG. 12 (g) shows a separation etching step, FIG. h) shows a current blocking portion forming step, and FIG. 12 (i) shows a protective layer forming step. FIG. 13 (j) shows a wiring formation step, FIG. 13 (k) shows a back surface electrode formation step, and FIG. 13 (l) shows a light emitting surface formation step.
Here, it demonstrates with sectional drawing of the island 301,302 shown in FIG. The cross-sectional views of these islands are cross-sectional views taken along the line VIB-VIB in FIG. 6A, but are cross-sectional views seen from the −x direction reverse to FIG. The island 303 is omitted because it is the same as the island 302. Also, the conductivity type of the impurity is denoted by p and n.
These will be described in order.

  In the first laminated semiconductor layer forming step shown in FIG. 10A, the p anode (cladding) layer 81, the light emitting layer 82, the n cathode (cladding) layer 83, the tunnel junction layer 84 and p are formed on the p type substrate 80. The p-anode layer 85p functioning as a part of the anode layer 85 is epitaxially grown in order to form a first stacked semiconductor layer. In the drawings for explaining the manufacturing method, the p anode (cladding) layer 81 is denoted as p, and the n cathode (cladding) layer 83 is denoted as n.

  Here, although the substrate 80 is described using p-type GaAs as an example, n-type GaAs or intrinsic (i) GaAs not doped with impurities may be used. In addition, semiconductor substrates made of InP, GaN, InAs, other III-V, II-VI materials, sapphire, Si, Ge, etc. may be used. When the substrate is changed, the material monolithically stacked on the substrate uses a material that substantially matches (including a strain structure, a strain relaxation layer, and metamorphic growth) the lattice constant of the substrate. As an example, InAs, InAsSb, GaInAsSb or the like is used on an InAs substrate, InP, InGaAsP or the like is used on an InP substrate, and GaN, AlGaN, InGaN is used on a GaN substrate or sapphire substrate. On the Si substrate, Si, SiGe, GaP or the like may be used.

Here, the current blocking portion β (see FIG. 6A) is formed by oxidizing a layer containing Al. Therefore, the p-anode (cladding) layer 81 is configured by sequentially laminating a lower p-anode (cladding) layer 81a, a current confinement layer 81b, and an upper p-anode (cladding) layer 81c.
The lower p anode (cladding) layer 81 a and the upper p anode (cladding) layer 81 c of the p anode (cladding) layer 81 are, for example, p-type Al _0.9 GaAs with an impurity concentration of 5 × 10 ¹⁷ / cm ³ . Al composition may be changed in the range of 0-1. Note that GaInP may be used.
Here, the current confinement layer 81 b is, for example, p-type AlGaAs having a high impurity concentration of AlAs or Al. Any material may be used as long as Al is oxidized to form Al ₂ O ₃ to increase the electric resistance and narrow the current path.

  The light emitting layer 82 has a quantum well structure in which well layers and barrier layers are alternately stacked. The well layer is, for example, GaAs, AlGaAs, InGaAs, GaAsP, AlGaInP, GaInAsP, GaInP or the like, and the barrier layer is AlGaAs, GaAs, GaInP, GaInAsP or the like. The light emitting layer 82 may be a quantum wire (quantum wire) or a quantum box (quantum dot).

The n cathode (cladding) layer 83 is, for example, n-type Al _0.9 GaAs having an impurity concentration of 5 × 10 ¹⁷ / cm ³ . Al composition may be changed in the range of 0-1. Note that GaInP may be used.

The tunnel junction layer 84 is formed of a junction of an n ⁺⁺ layer 84 a to which an n-type impurity is heavily doped and a p ⁺⁺ layer 84 b to which an n-type impurity is heavily doped. n ⁺⁺ layer 84a and ^{p ++} layer 84b is a high concentration of, for example an impurity concentration of 1 × ¹⁰ 20 / cm ^3. The impurity concentration of the normal junction is 10 ¹⁷ / cm ³ to 10 ¹⁸ / cm ³ . The combination ^{(hereinafter,} referred to with ^{n ++} layer 84a ^{/ p ++} layer 84b.) between the n ⁺⁺ layer 84a and the ^{p ++} layer 84b is, for example ^{n ++ GaInP / p ++ GaAs,} n ++ GaInP / p ++ AlGaAs, n ⁺⁺ GaAs / p ⁺⁺ GaAs, n ⁺⁺ AlGaAs / p ⁺⁺ AlGaAs, n ⁺⁺ InGaAs / p ⁺⁺ InGaAs, n ⁺⁺ GaInAsP / p ⁺⁺ GaInAsP, n ⁺⁺ GaAsSb / p ⁺⁺ GaAsSb. The combinations may be mutually changed.

The p-anode layer 85p, which is a part of the p-anode layer 85, is a protective (cap) layer provided to suppress deterioration of the tunnel junction layer 84 to which impurities are added at high concentration by contact with air or the like. is there. Here, although a part of the p anode layer 85 is used as the cap layer, the cap layer may be made of another material as long as deterioration of the tunnel junction layer 84 is suppressed. Also, the cap layer p anode layer 85p may be removed before the p anode layer 85 is formed next.
The p-anode layer 85p is, for example, p-type Al _0.9 GaAs with an impurity concentration of 1 × 10 ¹⁸ / cm ³ . Al composition may be changed in the range of 0-1. Note that GaInP may be used.

In the first stacked semiconductor layer etching step shown in FIG. 10 (b), the first stacked semiconductor layer is exposed to a known photo, leaving a portion to be the island 301 (see FIGS. 6 (a) and 6 (b) and FIG. 7). After providing a resist pattern using a lithography technique, the first laminated semiconductor layer is etched to expose the surface of the substrate 80. A portion of the lower p anode (cladding) layer 81 a in the thickness direction may remain without exposing the surface of the substrate 80.
This etching can be performed by wet etching using a sulfuric acid-based etching solution (sulfuric acid: hydrogen peroxide water: water = 1: 10: 300 in weight ratio) or the like. Alternatively, anisotropic dry etching (RIE) using, for example, boron chloride may be performed.

  Next, in the second stacked semiconductor layer forming step shown in FIG. 10C, the substrate 80 exposed by etching the first stacked semiconductor layer and the first stacked semiconductor layer left in the first stacked semiconductor layer etching step. The p anode layer 85, the n gate layer 86, the p gate layer 87, and the n cathode layer 88 are sequentially epitaxially grown on the surface of the second semiconductor layer to form a second stacked semiconductor layer. The p-anode layer 85 is formed on the p-anode layer 85p functioning as a cap layer on the first stacked semiconductor layer. The p-anode layer 85p functions as an anode integrally with the p-anode layer 85. Hereinafter, the p-anode layer 85p and the p-anode layer 85 will be referred to.

The p anode layer 85 has a thickness that acts as the p anode layer 85 only in this layer. The p-anode layer 85 is, for example, p-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁸ / cm ³ , like the p-anode layer 85 p which is a cap layer. Al composition may be changed in the range of 0-1. Note that GaInP may be used.

The n gate layer 86 is, for example, n-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . Al composition may be changed in the range of 0-1. Note that GaInP may be used.
The p gate layer 87 is, for example, p-type Al _0.9 GaAs with an impurity concentration of 1 × 10 ¹⁷ / cm ³ . Al composition may be changed in the range of 0-1. Note that GaInP may be used.
The n cathode layer 88 is, for example, n-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . Al composition may be changed in the range of 0-1. Note that GaInP may be used.

  The first stacked semiconductor layer and the second stacked semiconductor layer are stacked by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like.

In the cathode electrode forming step shown in FIG. 11D, an n ohmic electrode (n ohmic electrodes 321, 323, 324, etc.) is formed on the n cathode layer 88.
For the n-ohmic electrode, for example, Au (AuGe) containing Ge that can easily make ohmic contact with the n-type GaAs semiconductor layer of the n cathode layer 88 is used.
The n-ohmic electrode is formed by, for example, a lift-off method.

  In the cathode region forming step shown in FIG. 11E, the n cathode layer 88 is etched so that the n cathode layer 88 remains in the region 311 in the island 301, the regions 313, 314 in the island 302, etc. (see FIG. 6A). Do. Similarly, the n cathode layer 88 is left also in the region 315 of the start diode SD in the island 304 (see FIG. 6A). Thus, the p gate layer 87 is exposed at the portion where the n cathode layer 88 is removed (see FIG. 6B, FIG. 7).

In the anode electrode forming step shown in FIG. 11F, p ohmic electrodes (such as p ohmic electrodes 331 and 332) are formed on the p gate layer 87.
For the p-ohmic electrode, for example, Au (AuZn) containing Zn, which easily makes ohmic contact with a p-type GaAs semiconductor layer such as the p gate layer 87, or the like is used.
The p-ohmic electrode is formed by, for example, a lift-off method.

  In the separation etching process shown in FIG. 12G, the p anode layer 85, the n gate layer 86, the p gate layer 87, and the n cathode layer 88 that constitute the second stacked semiconductor layer are etched to form islands (FIG. Into islands 301, 302, 303, etc.). This etching may be performed in the same manner as the first stacked semiconductor layer etching step of FIG. The etching in this separation etching step may be referred to as mesa etching or post etching.

In the current blocking portion forming step in FIG. 12H, the current blocking portion β blocking the current by oxidizing the current narrowing layer 81b in the p-anode layer 81 of the first laminated semiconductor layer exposed in the separation etching step Form. The portion left without being oxidized becomes the current passing portion α.
Oxidation of the current confinement layer 81b is performed by, for example, steam oxidation at 300 to 400 ° C. to oxidize Al of the current confinement layer 81b made of AlAs, AlGaAs, or the like. At this time, oxidation proceeds from the exposed side surface, and a current blocking portion β is formed of Al ₂ O ₃ which is an oxide of Al around the island (such as the island 301) where the laser diode LD is formed. The portion other than the current blocking portion β is the current passing portion α.

The current blocking portion β may be formed by implanting hydrogen ions (H ⁺ ) into a semiconductor layer such as GaAs or AlGaAs instead of using a semiconductor layer having a large Al composition ratio such as AlAs. (H ⁺ ion implantation). That is, the p anode (cladding) layer 81 is formed by integrating the lower p anode (cladding) layer 81 a and the upper p anode (cladding) layer 81 c without dividing the current constriction layer 81 b and forming a current blocking By implanting H ⁺ into the portion to be the portion β, a current blocking portion β with high electrical resistance in which impurities are inactivated is formed.

In the protective layer forming step in FIG. 12I, a protective layer 90 is formed so as to cover the surfaces of the islands (islands 301, 302, etc.) with an insulating material such as SiO ₂ , SiON, SiN or the like.
Then, through holes (openings) are formed in the protective layer 90 on the n ohmic electrodes (n ohmic electrodes 321, 322, 323, 234, etc.) and the p ohmic electrodes (p ohmic electrodes 331, 333, etc.).

In the wiring formation step in FIG. 13J, the n-ohmic electrodes (n-ohmic electrodes 321, 323, 324, etc.) and the p-ohmic electrodes (p-ohmic electrodes 331, 332, etc.) through through holes provided in the protective layer 90. Wiring (a power supply line 71, a first transfer signal line 72, a second transfer signal line 73, a lighting signal line 75, etc.) for connecting the
Au, Al or the like is used for the wiring.

In the back surface electrode forming step in FIG. 13K, the back surface electrode 91 is formed on the back surface of the p-type substrate 80.
The back electrode 91 is made of, for example, Au (AuZn) containing Zn that can easily form an ohmic contact with the p-type GaAs semiconductor layer.

In the light emitting surface forming step shown in FIG. 13L, in order to form a light emitting surface for emitting light from the laser diode LD, the first stacked semiconductor layer and the first stacked semiconductor layer are formed in the portion of the island 301 where the laser diode LD is formed. The two-layered semiconductor layer is cleaved together with the substrate 80.
Cleavage at this time is performed such that the current blocking portion β is not included in the light emission direction from the laser diode LD.

  As described above, the light emitting surface may be formed by etching. In addition, light may be emitted from the side surface of the light emitting layer 82 without performing the light emitting surface forming step.

  As described above, in the light emitting chip C according to the first embodiment, the first stacked semiconductor layers (p anode layer 81, light emitting layer 82, and n cathode layer 83), which constitute the laser diode LD, and the setting thyristor S and A second stacked semiconductor layer (p anode layer 85, n gate layer 86, p gate layer 87 and n cathode layer 88) constituting the transfer thyristor T is separately provided. The first stacked semiconductor layer and the second stacked semiconductor layer are formed in accordance with the characteristics required for each.

That is, in the first embodiment, light emission is performed by the laser diode LD formed of the first laminated semiconductor layer, and driven by the transfer thyristor T and the setting thyristor S formed of the second laminated semiconductor layer. The characteristics and the drive characteristics can be set separately (independently).
The setting thyristor S and the transfer thyristor T do not need to emit light. Therefore, the laser diode LD can have a quantum well structure to improve the light emission characteristic and the like, and can also improve the drive characteristic and the like of the setting thyristor S and the transfer thyristor T. That is, the laser diode LD of the light emitting unit 102, and the transfer thyristor T and the setting thyristor S of the drive unit 101 can be set separately (independently). As a result, it is possible to realize high-speed driving, high light output, high efficiency, low power consumption, low cost and the like.

On the other hand, the setting thyristor S may be used as a laser thyristor (light emitting element) without providing the setting thyristor S on the laser diode LD.
In this case, the light emission characteristic and the drive characteristic can not be set separately (independently).

  The light emitting chip C is a self-scanning type in which the laser diode LD is sequentially lighted by the transfer thyristor T and the setting thyristor S. As a result, the number of terminals provided in the light emitting chip C decreases, and the light emitting chip C and the light emitting device 65 become smaller.

  FIG. 14 is a cross-sectional view of the light emitting chip C ′ shown for comparison. FIG. 14 shows the islands 301, 302, and 303, similarly to the cross-sectional view of the light emitting chip C shown in FIG.

In the light emitting chip C ′, the semiconductor element UD formed of the same first laminated semiconductor layer as the laser diode LD is provided below the transfer thyristor T1. By doing this, in the method of manufacturing light emitting chip C shown in FIG. 10, the first laminated semiconductor layer forming step of FIG. 10A and the second laminated semiconductor layer forming step shown in FIG. This can be performed continuously, and the first stacked semiconductor layer etching step of FIG.
However, since the semiconductor element UD is provided below the transfer thyristor T, the first transfer signal φ1 and the second transfer signal φ2 supplied to the transfer thyristor T are “H” (0 V) as with the lighting signal φI. ) And “L2” (−5 V) are required.

  That is, in the light emitting chip C according to the first embodiment, the laser diode LD and the setting thyristor S are stacked, but the transfer thyristor T is not stacked with other elements. Thus, the lighting signal φI supplied to the stacked laser diode LD and the setting thyristor S is a signal having “H” (0 V) and “L2” (−5 V), while the transfer thyristor T is The first transfer signal φ1 and the second transfer signal φ2 supplied to the signal may be a signal having “H” (0 V) and “L1” (−3.3 V). That is, the voltage of the first transfer signal φ1 and the second transfer signal φ2 can be lowered, and power consumption can be reduced.

In the first embodiment, the laser diode LD and the setting thyristor S are stacked via the tunnel junction layer 84. In this case, although the laser diode LD is reverse biased in the tunnel junction layer 84, the tunnel junction layer 84 has a characteristic that current flows even in the reverse bias state.
If the tunnel junction layer 84 is not provided, the junction between the laser diode LD and the setting thyristor S is reverse biased. For this reason, in order to flow a current to the laser diode LD and the setting thyristor S, a voltage at which the junction of the reverse bias breaks down is applied. Therefore, the voltage of the lighting signal φI is increased.
That is, by laminating the laser diode LD and the setting thyristor S via the tunnel junction layer 84, the voltage of the lighting signal φI can be suppressed to a low level as compared with the case where the tunnel junction layer 84 is not interposed.

Furthermore, the tunnel junction layer 84 has a high impurity concentration as described above. For example, the impurity concentration of the tunnel junction layer ^84, and ¹⁰ 19 / cm ^3, higher than the impurity concentration of ¹⁰ 17 ^~10 18 / cm ³ of the other layers. Si used as an impurity is different from GaAs, which is an example of a base semiconductor material, in lattice constant, bond strength, number of outermost electrons, and the like. Therefore, if a semiconductor layer such as GaAs is grown on the tunnel junction layer 84, a defect is likely to occur. The probability of occurrence of defects increases as the impurity concentration increases. Then, the defect propagates to the semiconductor layer formed thereon.
Also, as in the case of the tunnel junction layer 84, low temperature growth must be performed in order to make the impurity concentration higher than that of the other layers. That is, the growth conditions (temperature, growth rate, ratio) must be changed. Therefore, the semiconductor layer provided on the tunnel junction layer 84 deviates from the optimum growth conditions.
As a result, the semiconductor layer provided on the tunnel junction layer 84 contains many defects.

  In particular, the light emission characteristics of the light emitting element such as the laser diode LD are easily affected by the defects contained in the semiconductor layer. On the other hand, the thyristors (setting thyristors S and transfer thyristors T) may be turned on to supply current to the laser diode LD and the lower diode. That is, the thyristors (setting thyristors S, transfer thyristors T) are less susceptible to defects.

  Therefore, in the first embodiment, the laser diode LD is provided on the substrate 80, and the setting thyristor S is provided on the laser diode LD via the tunnel junction layer 84. As a result, the occurrence of defects in the laser diode LD is suppressed, and the light emission characteristics are less affected by the defects. The setting thyristors S are epitaxially grown and monolithically stacked.

<Metallically conductive III-V compound layer>
In the light emitting chip C described above, the setting thyristor S is stacked on the laser diode LD via the tunnel junction layer 84.
Instead of the tunnel junction layer 84, a III-V group compound layer having metallic conductivity and epitaxially grown on the III-V group compound semiconductor layer may be used. In this case, the “tunnel junction layer 84” in the above description may be replaced with the “metallic conductive III-V compound layer 84” described below.

FIG. 15 is a view for explaining the material constituting the metallic conductive group III-V compound layer. 15 (a) shows the band gap of InNAs to the composition ratio x of InN, FIG. 15 (b) shows the band gap of InNSb to the composition ratio x of InN, FIG. 15 (c) shows the group VI element and III-V. It is a figure which shows the lattice constant of group compound with respect to a band gap.
FIG. 15A shows the band gap energy (eV) for InNAs which is a compound of InN having a composition ratio x (x = 0 to 1) and InAs having a composition ratio (1-x).
FIG. 15 (b) shows the band gap energy (eV) for InNSb which is a compound of InN of composition ratio x (x = 0 to 1) and InSb of composition ratio (1-x).

  InNAs and InNSb described as an example of the material of the metallic conductive group III-V compound layer have a negative band gap energy in a range of a composition ratio x as shown in FIGS. 15 (a) and 15 (b). It is known to be. The fact that the band gap energy is negative means that there is no band gap. Therefore, the conductive property (conductive property) similar to that of metal is exhibited. That is, the metallic conductive property (conductive property) means that a current flows if there is a gradient in electric potential as in the case of metal.

As shown in FIG. 15A, InNAs has a negative band gap energy, for example, when the composition ratio x of InN is in the range of about 0.1 to about 0.8.
As shown in FIG. 15B, InNSb has a negative band gap energy, for example, when the composition ratio x of InN is in the range of about 0.2 to about 0.75.
That is, InNAs and InNSb show metallic conductive properties (conductivity) in the above-mentioned range.

In the region where the band gap energy outside the above range is small, since the electrons have energy by the thermal energy, it is possible to make a small band gap transition, and as in the case where the band gap energy is negative or metal. When the potential has a gradient, it has a characteristic that current easily flows.
Then, even if Al, Ga, Ag, P, etc. are contained in InNAs and InNSb, the band gap energy can be maintained near 0 or negative depending on the composition, and a current flows if the potential has a gradient.

Furthermore, as shown in FIG. 15C, the lattice constant of III-V compounds (semiconductors) such as GaAs and InP is in the range of 5.6 Å to 5.9 Å. And, this lattice constant is close to about 5.43 Å of the lattice constant of Si and about 5.66 Å of the lattice constant of Ge.
On the other hand, the lattice constant of InN, which is also a III-V compound, is about 5.0 Å in the zinc blende structure, and the lattice constant of InAs is about 6.06 Å. Therefore, the lattice constant of InNAs, which is a compound of InN and InAs, can be a value close to 5.6 Å to 5.9 Å of GaAs or the like.
In addition, the lattice constant of InSb, which is a III-V compound, is about 6.48 Å. Accordingly, since the lattice constant of InN is about 5.0 Å, the lattice constant of InNSb, which is a compound of InSb and InN, can be a value close to 5.6 Å to 5.9 Å such as GaAs.

  That is, InNAs and InNSb can be epitaxially grown monolithically on a layer of a group III-V compound (semiconductor) such as GaAs. In addition, a layer of a III-V compound (semiconductor) such as GaAs can be monolithically laminated on the layer of InNAs or InNSb by epitaxial growth.

  Therefore, if the laser diode LD and the setting thyristor S are stacked in series via the metallic conductive III-V compound layer instead of the tunnel junction layer 84, the n cathode of the laser diode LD ( Reverse bias of the cladding layer 83 and the p anode layer 85 of the setting thyristor S is suppressed.

Although the metallic conductive III-V group compound layer composed of InNAs, InNSb, etc. theoretically has a negative band gap, it is difficult to grow and inferior in quality as compared with GaAs, InP and the like. In particular, when the N composition is increased, the degree of difficulty in growth rises dramatically. Therefore, if a semiconductor layer such as GaAs is grown on the metallic conductive III-V compound layer, defects are likely to occur.
As described above, the light emission characteristics of the light emitting element such as the laser diode LD are susceptible to the defects contained in the semiconductor layer. On the other hand, the setting thyristor S may be turned on to supply current to the laser diode LD. That is, the setting thyristor S is less susceptible to defects.

  Therefore, when forming the first laminated semiconductor layer on the substrate 80, the laser diode LD is provided as in the tunnel junction layer 84, and the setting thyristor is formed thereon via the metallic conductive III-V compound layer. S may be provided. As a result, the generation of defects in the laser diode LD is suppressed, and the light emission characteristics are less susceptible to the defects. Also, the setting thyristors S can be laminated monolithically.

<Voltage reduction layer 89>
Further, in the light emitting chip C described above, the setting thyristor S is stacked on the laser diode LD via the tunnel junction layer 84. Therefore, the voltage used for the lighting signal φI is increased in absolute value. As described above, "L2" (-5 V) was used.
Therefore, in order to reduce the voltage used for the lighting signal φI in absolute value, a voltage reduction layer 89 that reduces the voltage applied to the setting thyristor S may be used.

FIG. 16 is an enlarged cross-sectional view of the island 301 or the like in which the laser diode LD and the setting thyristor S provided with the voltage reduction layer 89 are stacked. FIG. 16 shows the islands 301, 302, and 303 of FIG. 7 to which a voltage reduction layer 89 is added. Therefore, the same parts as those in FIG. 7 are denoted by the same reference numerals, and the description thereof will be omitted, and different parts will be described.
The voltage reduction layer 89 is provided between the p-anode layer 85 and the n-gate layer 86 of the setting thyristor S. By doing this, the transfer thyristor T has a similar configuration.
The voltage reduction layer 89 may be p-type with an impurity concentration similar to that of the p anode layer 85 as a part of the p anode layer 85, and an impurity similar to that of the n gate layer 86 as a part of the n gate layer 86. It may be n-type of concentration. Further, the voltage reduction layer 89 may be an i layer.

The role of the voltage reduction layer 89 in the setting thyristor S and the transfer thyristor T will be generalized and described as a thyristor.
FIG. 17 is a diagram for explaining the structure of a thyristor and the characteristics of the thyristor. 17 (a) is a cross-sectional view of the thyristor _{S A} with a voltage reduction layer 89, FIG. 17 (b), a cross-sectional view of the thyristor _{S B} without a voltage reduction layer 89, FIG. 17 (c) thyristor characteristics It is. FIGS. 17A and 17B correspond to, for example, the cross section of the setting thyristor S which is not stacked on the laser diode LD. Therefore, it is assumed that the back surface electrode 91 is provided on the back surface of the p anode layer 85.
As shown in FIG. 17 (a), the thyristor _{S A} is provided between the p anode layer 85 and the n gate layer 86 includes a voltage reduction layer 89. If the voltage reduction layer 89 is p-type with the same impurity concentration as the p-anode layer 85, it functions as part of the p-anode layer 85, and if it is n-type with the same impurity concentration as the n-gate layer 86, Act as part of the n gate layer 86. The voltage reduction layer 89 may be an i layer.
The thyristor S _B shown in FIG. 17B does not include the voltage reduction layer 89.

The rising voltage Vr (see FIG. 17C) in the thyristor is determined by the energy (band gap energy) of the smallest band gap in the semiconductor layer constituting the thyristor. The rising voltage Vr in the thyristor is a voltage when the current in the on state of the thyristor is extrapolated to the voltage axis.
As shown in FIG. 17 (c), the thyristors _{S A,} compared to the p anode layer 85, n gate layer 86, p gate layer 87, n cathode layer 88, the voltage reduction layer 89 band gap energy is small layer It is provided. Thus, the rise voltage Vr of the thyristor _{S A} (A) is lower than the rising voltage Vr of the thyristors _{S B} without a voltage reduction layer 89 (B). Furthermore, the voltage reduction layer 89 is, for example, a layer having a band gap smaller than the band gap of the light emitting layer 82.

A thyristor (setting thyristor S, transfer thyristor T) is not used as a light emitting element, and functions as a part of a drive unit 101 that drives a light emitting element such as a laser diode LD. Therefore, the band gap is determined regardless of the emission wavelength of the light emitting element that actually emits light. Therefore, by providing the voltage reduction layer 89 having a band gap smaller than the band gap of the light emitting layer 82, the rise voltage Vr of the thyristor is reduced.
Thereby, the voltage applied to the thyristor and the light emitting element is reduced while the thyristor and the light emitting element are turned on.

FIG. 18 is a diagram for explaining the band gap energy of the material forming the semiconductor layer.
The lattice constant of GaAs is about 5.65 Å. The lattice constant of AlAs is about 5.66 Å. Thus, materials close to this lattice constant can be epitaxially grown on a GaAs substrate. For example, AlGaAs or Ge, which is a compound of GaAs and AlAs, can be epitaxially grown on a GaAs substrate.
Also, the lattice constant of InP is about 5.87 Å. Materials close to this lattice constant can be epitaxially grown on an InP substrate.
The lattice constant of GaN differs depending on the growth surface, but the a-plane is 3.19 Å and the c-plane is 5.17 Å. Materials close to this lattice constant can be epitaxially grown on the GaN substrate.

And, with respect to GaAs, InP and GaN, the band gap energy in which the rise voltage Vr of the thyristor decreases is a material in the range shown by the halftone dots in FIG. That is, when a material in the range indicated by the halftone dots is used as a layer constituting the thyristor, the rise voltage Vr of the thyristor becomes the band gap energy of the material in the region indicated by the halftone dots.
For example, the band gap energy of GaAs is about 1.43 eV. Therefore, if the voltage reduction layer 89 is not used, the rise voltage Vr of the thyristor is about 1.43V. However, by using or including the material in the range indicated by the halftone dots as a layer constituting the thyristor, the rise voltage Vr of the thyristor can be more than 0 V and less than 1.43 V (0 V <Vr <1.43 V ).
This reduces power consumption when the thyristor is in the on state.

  A material in the range shown by halftone dots is Ge with a band gap energy of about 0.67 eV for GaAs. There is also InAs with a band gap energy of about 0.36 eV for InP. Alternatively, a material having a small band gap energy can be used for a compound of GaAs and InP, a compound of InN and InSb, a compound of InN and InAs, or the like with respect to a GaAs substrate or an InP substrate. In particular, mixed compounds based on GaInNAs are suitable. These may include Al, Ga, As, P, Sb and the like. In addition, GaNP can be the voltage reduction layer 89 for GaN. In addition, it corresponds to twice the lattice constant (a-plane) of (1) InN layer, InGaN layer, (2) InN, InGaN, InNAs, InNSb by metamorphic growth etc., and (3) GaN. Can be introduced as the voltage reduction layer 89. These may include Al, Ga, N, As, P, Sb, and the like.

  Although the rise voltage Vr of the thyristor is described here, the same applies to the holding voltage Vh which is the minimum voltage at which the thyristor maintains the on state and the voltage applied to the thyristor in the on state (see FIG. 17C). .

  On the other hand, the switching voltage Vs (see FIG. 17C) of the thyristor is determined by the depletion layer of the reverse biased semiconductor layer. Therefore, the voltage reduction layer 89 has less influence on the switching voltage Vs of the thyristor.

  That is, the voltage reduction layer 89 reduces the rising voltage Vr while maintaining the switching voltage Vs of the thyristor. As a result, the voltage applied to the on-state thyristor is reduced, and the power consumption is reduced. The switching voltage Vs of the thyristor is set to an arbitrary value by adjusting the material, impurity concentration, and the like of the p anode layer 85, the n gate layer 86, the p gate layer 87, and the n cathode layer 88. However, the switching voltage Vs changes depending on the insertion position of the voltage reduction layer 89.

  Moreover, although the example which provided one voltage reduction layer 89 is shown in FIG. 16, you may provide with two or more. For example, when a voltage reduction layer 89 is provided between the p anode layer 85 and the n gate layer 86 and between the p gate layer 87 and the n cathode layer 88, or one in the n gate layer 86, Another p gate layer 87 may be provided. Besides, two or three layers out of the p anode layer 85, the n gate layer 86, the p gate layer 87, and the n cathode layer 88 may be selected and provided in each layer. The conductivity type of these voltage reduction layers may be combined with the anode layer provided with the voltage reduction layer, the cathode layer, or the gate layer, or may be i-type.

The material used as the voltage reduction layer 89 is more difficult to grow and inferior in quality compared to GaAs, InP, and the like. Therefore, a defect is easily generated inside the voltage reduction layer 89, and the defect extends in a semiconductor such as GaAs which is grown thereon.
As described above, the light emission characteristics of the light emitting element such as the laser diode LD are susceptible to the defects contained in the semiconductor layer. On the other hand, the thyristor (setting thyristor S) may be turned on to supply current to the laser diode LD. Therefore, if the thyristor including the voltage reduction layer 89 is not used as a light emitting layer but is used for voltage reduction, a defect may be included in the semiconductor layer constituting the thyristor.

  Therefore, as in the case of the tunnel junction layer 84 and the metallic conductive III-V compound layer, the laser diode LD is provided on the substrate 80, and the setting thyristor S including the voltage reduction layer 89 is provided thereon. Just do it. As a result, the generation of defects in the laser diode LD is suppressed, and the light emission characteristics are less susceptible to the defects. Also, the setting thyristors S can be laminated monolithically.

  Hereinafter, modifications of the light emitting chip C according to the first embodiment will be described. In the modification shown below, it demonstrates by the part on which the laser diode LD and the setting thyristor S in the island 301 of the light-emitting chip C were laminated | stacked. Since the islands 302 and 303 have the same configuration as the setting salista S of the island 301, they are omitted. And the explanation of the part similar to the island 301 explained so far is omitted, and the different part is explained. The same applies to the other modifications and the other embodiments.

(Modified Example of Light-Emitting Chip C According to First Embodiment 1-1)
FIG. 19 is an enlarged cross-sectional view of the island 301 in which the laser diode LD and the setting thyristor S are stacked to explain the modification 1-1. The protective layer 90 is omitted. FIG. 19 is a cross-sectional view of the island 301 shown in FIG. 6, but viewed from the -y direction of FIG. In this state, the p-ohmic electrode 331 can not be seen. Therefore, the portion of the p-ohmic electrode 331 is viewed from the -x direction of FIG. The same applies to the following.

  In the modification 1-1, the current confinement layer (the current confinement layer 85b in the modification 1-1) is provided in the p-anode layer 85 of the setting thyristor S instead of the p-anode (cladding) layer 81 of the laser diode LD. ing. That is, the p-anode layer 85 is composed of the lower p-anode layer 85a, the current confinement layer 85b, and the upper p-anode layer 85c. The other configuration is the same as that of the light emitting chip C according to the first embodiment.

  The modification example 1-1 is manufactured by changing the method of manufacturing the light emitting chip C according to the first embodiment shown in FIGS. 10, 11, 12 and 13. That is, the current confinement layer 85 b may be oxidized from the side surface as the lower p anode layer 85 a, the current confinement layer 85 b, and the upper p anode layer 85 c. The current blocking portion β is also formed in the current confinement layer 85 b of the p-anode layer 85 of the island 302.

Also in the light emitting chip C of the modified example 1-1, since the flow of current is limited to the current passing portion α in the central portion of the laser diode LD, the power consumed for non-radiative recombination is suppressed to reduce power consumption. And the light extraction efficiency is improved.
The current confinement layer may be provided on the n cathode (cladding) layer 83 of the laser diode LD or the n cathode layer 88 of the setting thyristor S.

(Modification 1-2 of light-emitting chip C according to the first embodiment)
FIG. 20 is an enlarged cross-sectional view of the island 301 in which the laser diode LD and the setting thyristor S are stacked to explain the modification 1-2.
In the modification 1-2, a tunnel junction layer 84 is provided at a portion corresponding to the current passing portion α, instead of the current confinement layer 81b. The other configuration is the same as that of the light emitting chip C according to the first embodiment.
As described above, the tunnel junction layer 84 tends to flow current in the reverse bias state. However, in the junction between the n cathode (cladding) layer 83 and the p anode layer 85 which are not tunnel junctions, it is difficult for current to flow in a reverse bias state where no breakdown occurs.
Therefore, when the tunnel junction layer 84 is provided in the portion corresponding to the current passing portion α, the current flowing to the laser diode LD is limited to the central portion.

  The light emitting chip C of the modification 1-2 is manufactured by changing the method of manufacturing the light emitting chip C according to the first embodiment shown in FIGS. 10, 11, 12 and 13. That is, in FIG. 10A, the p anode (cladding) layer 81, the light emitting layer 82, the n cathode (cladding) layer 83, and the tunnel junction layer 84 are sequentially stacked on the substrate 80. Thereafter, the portion of the tunnel junction layer 84 to be the current blocking portion β is removed, and the portion of the tunnel junction layer 84 to be the current passing portion α is left. Thereafter, the p-anode layer 85p may be stacked on and around the remaining tunnel junction layer 84.

  The method of using the tunnel junction layer 84 in the light emitting chip C of the modification 1-2 for current confinement may be applied to the case of using a semiconductor material to which steam oxidation is difficult to apply.

(Modification 1-3 of light-emitting chip C according to the first embodiment)
FIG. 21 is an enlarged cross-sectional view of the island 301 in which the laser diode LD and the setting thyristor S are stacked, for explaining the modification 1-3.
In Modification Example 1-3, the n cathode (cladding) layer 83 is a Distributed Bragg Reflector (DBR) (hereinafter, referred to as a DBR layer). The DBR layer is configured by laminating a plurality of semiconductor layers provided with a refractive index difference. The DBR layer is configured to reflect the light emitted from the laser diode LD. The other configuration is the same as that of the light emitting chip C according to the first embodiment.

  When a semiconductor material whose band gap is smaller than the emission wavelength is used for the tunnel junction layer 84, the light reaching the tunnel junction layer 84 is absorbed at the band edge to become a loss. Therefore, in Modification Example 1-3, the DBR layer is provided between the light emitting layer 82 and the tunnel junction layer 84, and the tunnel junction layer 84 is provided at a position corresponding to the node of the standing wave generated in the DBR layer. In this way, band edge absorption by the semiconductor material used for the tunnel junction layer 84 is significantly suppressed.

The DBR layer is composed of, for example, a combination of a low refractive index layer of high Al composition of Al _0.9 Ga _0.1 As and a high refractive index layer of low Al composition of Al _0.2 Ga _0.8 As ing. The film thickness (optical path length) of each of the low refractive index layer and the high refractive index layer is set to, for example, 0.25 (1/4) of the center wavelength. The composition ratio of Al between the low refractive index layer and the high refractive index layer may be changed in the range of 0 to 1.

  Therefore, in the method of manufacturing the light emitting chip C according to the first embodiment shown in FIG. 10, FIG. 11, FIG. 12 and FIG. Manufactured by changing to DBR layer.

  In the light emitting chip C of the modified examples 1-1 to 1-3, a metallic conductive III-V group compound layer may be used instead of the tunnel junction layer 84, and the setting thyristor S and the transfer thyristor T may be used. A voltage reduction layer 89 may be added.

Second Embodiment
In the light emitting chip C according to the first embodiment, the light emitting element is a laser diode LD. In the light emitting chip C according to the second embodiment, the light emitting element is a light emitting diode LED.
The configuration other than the stacked configuration of the light emitting diode LED and the setting thyristor S in the light emitting chip C is the same as that of the first embodiment, and the laser diode LD may be replaced with the light emitting diode LED. Therefore, the description of similar parts is omitted, and different parts will be described.

FIG. 22 is an enlarged cross-sectional view of the island 301 in which the light emitting diode LED and the setting thyristor S are stacked in the light emitting chip C according to the second embodiment.
In the light emitting chip C according to the second embodiment, the p anode layer 81, the light emitting layer 82, and the n cathode layer 83 constituting the light emitting diode LED are stacked on the p type substrate 80, and the tunnel junction layer 84 is interposed. The p-anode layer 85, the n-gate layer 86, the p-gate layer 87, and the n-cathode layer 88 that constitute the setting thyristor S are stacked.
The p-anode layer 81 is composed of the lower p-anode layer 81a, the current confinement layer 81b, and the upper p-anode layer 81c.

The lower p anode layer 81a and the upper p anode layer 81c are, for example, p-type Al _0.9 GaAs with an impurity concentration of 1 × 10 ¹⁸ / cm ³ . Al composition may be changed in the range of 0-1. Note that GaInP may be used.
The n cathode layer 83 is, for example, n-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . Al composition may be changed in the range of 0-1. Note that GaInP may be used.
The other parts are the same as in the first embodiment.

The light emitting diode LED emits light in a direction orthogonal to the substrate 80 as indicated by an arrow. Therefore, it can be used when utilizing the light emitted in the direction orthogonal to the substrate 80. The central portion of the n ohmic electrode 321 is open.
In this case, light exits through the tunnel junction layer 84. The tunnel junction layer 84 may absorb light because it contains impurities at a high concentration. Even in this case, it can be used for applications where the amount of light may be small. For example, it may be used in applications where the light quantity may be nW or μW or the like in radiant energy. The same applies to other modifications and other embodiments.

  As described in the first embodiment, a metallic conductive III-V compound layer may be used instead of the tunnel junction layer 84. Further, a voltage reduction layer 89 may be added to the setting thyristor S and the transfer thyristor T. Similar to the tunnel junction layer 84, the metallic conductive III-V compound layer and the voltage reduction layer 89 may also absorb the light emitted by the light emitting diode LED.

  As a method of avoiding light absorption in the tunnel junction layer 84, the metallic conductive III-V compound layer, and the voltage reduction layer 89, the setting thyristor S is partially or entirely at the central opening of the n ohmic electrode 321. A part or all of the n cathode layer 88, the p gate layer 87, the n gate layer 86, the p anode layer 85, and the tunnel junction layer 84 in the thickness direction may be removed by etching. When a metallic conductive III-V compound layer is used instead of the tunnel junction layer 84, part or all of the metallic conductive III-V compound layer may be etched away in the thickness direction. Furthermore, when using the voltage reduction layer 89, it may be removed in the same manner.

  Also, as in the modification 1-1 of the first embodiment, the p-anode layer 85 of the setting thyristor S may be provided with a current confinement layer. A current confinement layer may be provided on the n cathode layer 83 of the light emitting diode LED and the n cathode layer 88 of the setting thyristor S.

  Furthermore, as in the modification 1-2 of the first embodiment, the tunnel junction layer 84 may be used as a current confinement layer instead of the current confinement by steam oxidation.

(Modified Example of Light-Emitting Chip C According to Second Embodiment 2-1)
FIG. 23 is an enlarged cross-sectional view of the island 301 in which the light emitting diode LED and the setting thyristor S are stacked for explaining the modification 2-1.
In the modification 2-1, the light emitting layer 82 is sandwiched by two DBR layers. That is, the p anode layer 81 and the n cathode layer 83 are configured as a DBR layer. The p-anode layer 81 includes a current confinement layer 81b. That is, the p-anode layer 81 is stacked in the order of the lower p-anode layer 81a, the current confinement layer 81b, and the upper p-anode layer 81c, and the lower p-anode layer 81a and the upper p-anode layer 81c are configured as a DBR layer. There is.
The lower p anode layer 81a, the upper p anode layer 81c, and the n cathode layer 83 are referred to as a lower p anode (DBR) layer 81a, an upper p anode (DBR) layer 81c, and an n cathode (DBR) layer 83. Sometimes.

  The configuration of the DBR layer is the same as that of modification 1-3 in the first embodiment. The film thickness (optical path length) of the current confinement layer 81 b in the p-anode (DBR) layer 81 is determined by the structure to be adopted. When importance is given to the extraction efficiency and the process reproducibility, it is preferable to be set to an integral multiple of the film thickness (optical path length) of the low refractive index layer and the high refractive index layer constituting the DBR layer. It is set to .75 (3/4). In the case of an odd multiple, the current confinement layer 81 b may be sandwiched between the high refractive index layer and the high refractive index layer. In the case of an even multiple, the current confinement layer 81b may be sandwiched between the high refractive index layer and the low refractive index layer. That is, the current confinement layer 81 b may be provided to suppress the disturbance of the refractive index period due to the DBR layer. Conversely, if it is desired to reduce the influence of the oxidized part (refractive index or strain), the film thickness of the current confinement layer 81b is preferably several tens of nm, and is inserted into the standing wave node part standing in the DBR layer. Is preferred.

The p anode (DBR) layer 81 and the n cathode (DBR) layer 83 are configured to reflect light emitted from the light emitting layer 82 of the light emitting diode LED. That is, the p anode (DBR) layer 81 and the n cathode (DBR) layer 83 constitute a resonator (cavity), and the light emitted from the light emitting layer 82 is enhanced by resonance and output. That is, in the modified example 2-1, the setting thyristor S is stacked on the resonant type light emitting diode LED.
Further, since the current confinement layer 81b is provided, the power consumed for non-radiative recombination is suppressed, and the reduction in power consumption and the light extraction efficiency are improved.

  The light emitting chip C of the modified example 2-1 is manufactured by partially changing the manufacturing method shown in FIG. 10, FIG. 11, FIG. 12 and FIG. 13 in the first embodiment. That is, in the first stacked semiconductor layer forming step of FIG. 10A, the lower p anode layer 81a, the upper p anode layer 81c, and the n cathode layer 83 of the p anode layer 81 may be formed as a DBR layer.

  The position where the current confinement layer is provided may be changed, the tunnel junction layer 84 or the metallic conductive III-V compound layer may be used as the current confinement layer, and the voltage reduction layer 89 may be provided. The light from the light emitting diode LED may be absorbed by the tunnel junction layer 84, the metallic conductive group III-V compound layer, the voltage reduction layer 89, etc., and the amount of emitted light may be reduced. Even in this case, it can be used for applications where the amount of light may be small.

  When the light from the light emitting diode LED is absorbed by the tunnel junction layer 84 and the amount of emitted light decreases, the n cathode of the setting thyristor S is partially or entirely at the central opening of the n ohmic electrode 321. A part or all of the layer 88, the p gate layer 87, the n gate layer 86, the p anode layer 85, and the tunnel junction layer 84 in the thickness direction may be removed by etching. When a metallic conductive III-V compound layer is used instead of the tunnel junction layer 84, part or all of the metallic conductive III-V compound layer may be etched away in the thickness direction. Furthermore, when using the voltage reduction layer 89, it may be removed in the same manner.

  With this configuration, absorption of light emitted from the light emitting diode LED by the tunnel junction layer 84 is suppressed. Even when the metallic conductive III-V compound layer or the voltage reducing layer 89 is used, light emitted from the light emitting diode LED is absorbed by the metallic conductive III-V compound layer or the voltage reducing layer 89 Is suppressed.

(Modification 2-2 of light emitting chip C according to the second embodiment)
FIG. 24 is an enlarged cross-sectional view of the island 301 in which the light emitting diode LED and the setting thyristor S are stacked for explaining the modification 2-2.
In the modification 2-2, the n cathode (DBR) layer 83 of the light emitting chip C shown in FIG. 23 is an n cathode layer 83 which is not a DBR layer, and instead an n cathode layer 88 is a DBR layer. Thus, the n cathode layer 88 is referred to as an n cathode (DBR) layer 88. The other configuration is the same as that of the light emitting chip C according to the first embodiment.

  In the modification 2-2, the n cathode (DBR) layer 83 and the p anode (DBR) layer 85 constitute a resonator (cavity), and the light emitted from the light emitting layer 82 is enhanced by resonance and output. .

  The light emitting chip C of the modified example 2-2 is manufactured by partially changing the method of manufacturing the light emitting chip C shown in FIGS. 10, 11, 12 and 13 in the first embodiment. That is, the p anode layer 81 is formed as the p anode (DBR) layer 81 in the first laminated semiconductor layer forming step of FIG. 10A, and the n anode is formed in the second laminated semiconductor layer forming step of FIG. Layer 88 may be an n anode (DBR) layer 88.

Further, the position at which the current confinement layer is provided may be changed, the tunnel junction layer 84 or the metallic conductive III-V compound layer may be used as the current confinement layer, and the voltage reduction layer 89 may be provided.
The light from the light emitting diode LED may be absorbed by the tunnel junction layer 84, the metallic conductive group III-V compound layer, the voltage reduction layer 89, etc., and the amount of emitted light may be reduced. Even in this case, it can be used for applications where the amount of light may be small.

(Modification 2-3 of light-emitting chip C according to the second embodiment)
FIG. 25 is an enlarged cross-sectional view of the island 301 in which the light emitting diode LED and the setting thyristor S are stacked, for explaining the modification 2-3.
In the modification 2-3, the n cathode (DBR) layer 83 of the light emitting chip C shown in FIG. 23 is an n cathode layer 83 which is not a DBR layer. The other configuration is the same as the light emitting chip C according to the first embodiment.

In the light emitting chip C of the modified example 2-3, the p-anode (DBR) layer 81 is provided under the light emitting layer 82 (substrate 80). In this case, since a reflectance of 30% is obtained at the interface between the n cathode layer 88 and air, the light emitted from the light emitting layer 82 is intensified by resonance and is output.
Further, among the light emitted from the light emitting layer 82, the light directed to the substrate 80 side is reflected and directed to the light exit side. Therefore, the light utilization efficiency is improved as compared with the case where the p anode layer 81 is not a DBR layer.

  The light emitting chip C of the modified example 2-3 is manufactured by partially changing the manufacturing method shown in FIG. 10, FIG. 11, FIG. 12 and FIG. 13 in the first embodiment. That is, in the step of forming the first stacked semiconductor layer body of FIG. 10A, the lower p anode layer 81a and the upper p anode layer 81c of the p anode layer 81 may be formed as a DBR layer.

  The position where the current confinement layer is provided may be changed, the tunnel junction layer 84 or the metallic conductive III-V compound layer may be used as the current confinement layer, and the voltage reduction layer 89 may be provided. The light from the light emitting diode LED may be absorbed by the tunnel junction layer 84, the metallic conductive group III-V compound layer, the voltage reduction layer 89, etc., and the amount of emitted light may be reduced. Therefore, it may be used for applications where the amount of light may be small.

Third Embodiment
In the light emitting chip C according to the first embodiment, the light emitting element is a laser diode LD, and in the light emitting chip C according to the second embodiment, the light emitting element is a light emitting diode LED. In the light emitting chip C according to the third embodiment, a vertical cavity surface emitting laser (VCSEL) is used as a light emitting element.
The configuration other than the stacked configuration of the vertical cavity surface emitting laser VCSEL and the setting thyristor S (including the transfer thyristor T) in the light emitting chip C is the same as that of the first embodiment, and the laser diode LD May be replaced with a vertical cavity surface emitting laser VCSEL. Therefore, the description of similar parts is omitted, and different parts will be described.

FIG. 26 is an enlarged sectional view of an island 301 in which the vertical cavity surface emitting laser VCSEL of the light emitting chip C according to the third embodiment and the setting thyristor S are stacked.
The vertical cavity surface emitting laser VCSEL and the setting thyristor S are stacked.
The basic configuration is the same as that of the light emitting chip C according to the second embodiment shown in FIG.
In a light emitting layer 82 sandwiched between two DBR layers (p anode (DBR) layer 81 and n cathode (DBR) layer 83), the vertical cavity surface emitting laser VCSEL resonates light to cause laser oscillation. . When the reflectance of two DBR layers (p anode (DBR) layer 81 and n cathode (DBR) layer 83) is, for example, 99% or more, laser oscillation occurs.

As described in the first embodiment, a metallic conductive III-V compound layer may be used instead of the tunnel junction layer 84. Further, a voltage reduction layer 89 may be added to the setting thyristor S and the transfer thyristor T. Similar to the tunnel junction layer 84, the metallic conductive III-V compound layer and the voltage reduction layer 89 may also absorb the light emitted by the light emitting diode LED.
Also, as in the modification 1-1 of the first embodiment, the p-anode layer 85 of the setting thyristor S may be provided with a current confinement layer. A current confinement layer may be provided on the n cathode layer 83 of the light emitting diode LED and the n cathode layer 88 of the setting thyristor S.

The light from the vertical cavity surface emitting laser VCSEL may be absorbed by the tunnel junction layer 84, the metallic conductive group III-V compound layer, the voltage reduction layer 89, and the like to reduce the amount of emitted light. Therefore, it may be used for applications where the amount of light may be small.
As a method of avoiding light absorption in the tunnel junction layer 84, the n cathode layer 88 of the setting thyristor S, the p gate layer 87, the n gate layer 86, p in part or all of the central opening of the n ohmic electrode 321 A part or all of the anode layer 85 and the tunnel junction layer 84 in the thickness direction may be removed by etching. When a metallic conductive III-V compound layer is used instead of the tunnel junction layer 84, part or all of the metallic conductive III-V compound layer may be etched away in the thickness direction. Furthermore, when using the voltage reduction layer 89, it may be removed in the same manner.

  Hereinafter, a modification of the light emitting chip C according to the third embodiment will be described. In the modified example described below, a portion of the island 301 of the light emitting chip C in which the vertical cavity surface emitting laser VCSEL and the setting thyristor S are stacked will be described. The other configuration is the same as that of the light emitting chip C described above, so different parts will be described, and description of similar parts will be omitted.

(Modification 3-1 of light-emitting chip C according to the third embodiment)
FIG. 27 is an enlarged cross-sectional view of the island 301 in which the vertical cavity surface emitting laser VCSEL and the setting thyristor S are stacked, for explaining the modification 3-1.
The basic configuration of the modification 3-1 is the same as that of the modification 2-2 of the light emitting chip C according to the second embodiment shown in FIG.
The vertical cavity surface emitting laser VCSEL causes light to resonate in the light emitting layer 82 sandwiched between two DBR layers (p anode (DBR) layer 81 and n cathode (DBR) layer 88) to cause laser oscillation. .

  The position where the current confinement layer is provided may be changed. Also, instead of the tunnel junction layer 84, a metallic conductive III-V compound layer may be used. A tunnel junction layer 84 or a metallic conductive III-V compound layer may be used as the current confinement layer. Furthermore, a voltage reduction layer 89 may be provided on the thyristor (setting thyristor S, transfer thyristor T).

  The light from the light emitting diode LED may be absorbed by the tunnel junction layer 84, the metallic conductive group III-V compound layer, the voltage reduction layer 89, etc., and the amount of emitted light may be reduced. Even in this case, it can be used for applications where the amount of light may be small.

(Modification 3-2 of light-emitting chip C according to the third embodiment)
FIG. 28 is an enlarged cross-sectional view of the island 301 in which the vertical cavity surface emitting laser VCSEL and the setting thyristor S are stacked for explaining the modified example 3-2.
The basic configuration of the modification 3-2 is that, in the modification 1-2 of the light-emitting chip C according to the first embodiment shown in FIG. 20, the p-anode layer 81 and the p-anode layer 85 are DBR layers. There is. The other configuration is the same as that of the modification 1-2, so the description will be omitted.
Vertical cavity surface emitting laser VCSEL emits light by resonating light in two DBR layers (p anode (DBR) layer 81 and p anode (DBR) layer 85) sandwiching a light emitting layer 82 and an n cathode layer 83 I am doing it.

In addition, since the modified example 3-2 does not use the current narrowing layer 81b, it can be easily applied to a semiconductor material on a substrate such as InP, GaN, or sapphire, which is difficult to apply steam oxidation.
Since the tunnel junction layer 84 is used for current confinement, the power consumed for non-radiative recombination is suppressed, and power consumption reduction and light extraction efficiency are improved.

  Also, instead of the tunnel junction layer 84, a metallic conductive III-V compound layer may be used. Furthermore, a voltage reduction layer 89 may be provided on the thyristor (setting thyristor S, transfer thyristor T).

  The light from the light emitting diode LED may be absorbed by the tunnel junction layer 84, the metallic conductive group III-V compound layer, the voltage reduction layer 89, etc., and the amount of emitted light may be reduced. Even in this case, it can be used for applications where the amount of light may be small.

  Although the laser diode LD, the light emitting diode LED, and the vertical cavity surface emitting laser VCSEL have been described as the light emitting element in the first to third embodiments, other light emitting elements such as a laser transistor may be used. You may use.

The self-scanning light emitting element array (SLED) in the first to third embodiments includes a light emitting unit 102 including a light emitting element (laser diode LD, light emitting diode LED, vertical cavity surface emitting laser VCSEL) Although the drive unit 101 includes the setting thyristor S, the transfer thyristor T, and the like, the drive unit 101 may include a control thyristor or the like between the setting thyristor S and the transfer thyristor T or the like. Furthermore, other members such as diodes and resistors may be included.
Although the transfer thyristors T are connected by the coupling diode D, they may be connected by a member such as a resistor capable of transmitting a change in potential.

  In addition, in the stacked light emitting elements (laser diode LD, light emitting diode LED, vertical cavity surface emitting laser VCSEL) and the setting thyristor S without using the transfer thyristor T, the first transfer signal φ1 supplied to the transfer thyristor T is used. A signal in which the lighting signal φI is superimposed may be supplied to the odd-numbered setting thyristors S, and a signal in which the lighting signal φI is superimposed on the second transfer signal φ2 may be supplied to the even-numbered setting thyristors S. By doing this, the number of elements used is reduced, and the size of the light emitting chip C is reduced. In this case, the setting thyristor S or the like excluding the light emitting element constitutes the driving unit 101.

  In the first to third embodiments, the conductivity types of the light emitting element (laser diode LD, light emitting diode LED, vertical cavity surface emitting laser VCSEL), setting thyristor S, and transfer thyristor T are reversed. The polarity of the circuit may be changed. That is, the anode common may be a cathode common and the cathode common may be an anode common.

  In order to suppress light emission delay and relaxation oscillation when the light emitting element (laser diode LD, light emitting diode LED, vertical cavity surface emitting laser VCSEL) is turned on, a minute current of a threshold current or more is injected into the light emitting element in advance. The light emission state or the oscillation state may be slightly set. That is, the light emitting element is made to slightly emit light before the setting thyristor S is turned on, and when the setting thyristor S is turned on, the amount of light emission of the light emitting element is increased to obtain a predetermined light amount. It is also good. As such a configuration, for example, an electrode is formed on the anode layer of a light emitting element (laser diode LD, light emitting diode LED, vertical cavity surface emitting laser VCSEL), and a voltage source or current source is connected to this electrode. The weak current may be injected from the voltage source or the current source to the light emitting element before the setting thyristor S is turned on.

  Moreover, as the structure of the transfer thyristor T and the setting thyristor S in each embodiment, even if it is a structure having the functions of the transfer thyristor T and the setting thyristor S in each embodiment, it may be other than pnpn four-layer structure Good. For example, a pinin structure having a thyristor characteristic, a pipin structure, an npip structure, or a pnin structure may be used. In this case, an i layer, an n layer, an i layer sandwiched between p and n of a pinin structure, and an n layer or i layer sandwiched between p and n of a pnin structure become a gate layer, and a gate layer The n-ohmic electrode provided above may be used as a terminal of the gate Gt (gate Gs). Alternatively, an i-layer, a p-layer, an i-layer sandwiched between n and p in an npip structure, or a p-layer or an i-layer sandwiched between n and p in an npip structure is a gate layer on the gate layer The p-ohmic electrode 332 provided on the gate Gt may be used as a terminal of the gate Gt (gate Gs).

  Furthermore, in each of the embodiments, the semiconductor structure in which a plurality of semiconductor layers constituting a thyristor and a plurality of semiconductor layers constituting a light emitting element are stacked via a semiconductor layer constituting a tunnel junction is a self-scanning type. It can be used for applications other than light emitting element arrays (SLEDs). For example, it is composed of one light emitting element (laser diode LD, light emitting diode LED, vertical cavity surface emitting laser VCSEL, etc.) and setting thyristor S stacked thereon, and is inputted by an external electric signal or optical signal. It can be used as a single light emitting component that lights up. In this case, the light emitting element constitutes the light emitting unit 102, and the setting thyristor S constitutes the driving unit 101.

  In the above, p-type GaAs is mainly described as an example of the substrate 80. In the case of using another substrate (the first stacked semiconductor layer (p anode layer 81, light emitting layer 82, n cathode layer 83, tunnel junction formed in the step of forming the first stacked semiconductor layer in FIG. 10A) Layer 84), and a second laminated semiconductor layer (p anode layer 85, n gate layer 86, p gate layer 87, n cathode layer 88) formed in the step of forming a second laminated semiconductor layer formed in FIG. An example of) will be described.

First, an example of the first stacked semiconductor layer and the second stacked semiconductor layer in the case of using a GaN substrate is as follows.
The p-anode layer 81 is, for example, p-type Al _0.9 GaN with an impurity concentration of 1 × 10 ¹⁸ / cm ³ , for example. Al composition may be changed in the range of 0-1.
Since it is difficult to use an oxidation confinement layer as a current confinement layer on a GaN substrate, a configuration using a tunnel junction layer for current confinement (FIGS. 20 and 28) and metallic conductive III-V compound layers The configuration in which the current confinement is used for current confinement is desirable. Alternatively, it is also effective to use ion implantation as a current confinement method.

  The light emitting layer 82 has a quantum well structure in which well layers and barrier layers are alternately stacked. The well layer is, for example, GaN, InGaN, AlGaN or the like, and the barrier layer is AlGaN, GaN or the like. The light emitting layer 82 may be a quantum wire (quantum wire) or a quantum box (quantum dot).

The n cathode layer 83 is, for example, n-type Al _0.9 GaN having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . Al composition may be changed in the range of 0-1.

The tunnel junction layer 84 is composed of a junction (see FIG. 10A) of an n ⁺⁺ layer 84 a heavily doped with n-type impurities and ap ⁺⁺ layer 84 b heavily doped with n-type impurities. ing. n ⁺⁺ layer 84a and ^{p ++} layer 84b is a high concentration of, for example an impurity concentration of 1 × ¹⁰ 20 / cm ^3. The impurity concentration of the normal junction is 10 ¹⁷ / cm ³ to 10 ¹⁸ / cm ³ . The combination ^{(hereinafter,} referred to with ^{n ++} layer 84a ^{/ p ++} layer 84b.) between the n ⁺⁺ layer 84a and the ^{p ++} layer 84b is, for example ^{n ++ GaN / p ++ GaN,} n ++ GaInN / p ++ GaInN, n ⁺⁺ AlGaN / p ⁺⁺ AlGaN. The combinations may be mutually changed.

The p anode layer 85 is, for example, p-type Al _0.9 GaN with an impurity concentration of 1 × 10 ¹⁸ / cm ³ . Al composition may be changed in the range of 0-1.
The n gate layer 86 is, for example, n-type Al _0.9 GaN having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . Al composition may be changed in the range of 0-1.
The p gate layer 87 is, for example, p-type Al _0.9 GaN with an impurity concentration of 1 × 10 ¹⁷ / cm ³ . Al composition may be changed in the range of 0-1.
The n cathode layer 88 is, for example, n-type Al _0.9 GaN with an impurity concentration of 1 × 10 ¹⁸ / cm ³ . Al composition may be changed in the range of 0-1.

Next, an example of the first stacked semiconductor layer and the second stacked semiconductor layer in the case of using an InP substrate is as follows.
The p-anode layer 81 is, for example, p-type InGaAsP having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . The Ga composition and the Al composition may be changed in the range of 0 to 1.
Since it is difficult to use an oxidation narrowing layer as a current narrowing layer on an InP substrate, a configuration using a tunnel junction layer for current narrowing (FIGS. 20 and 28) or a metallic conductive III-V compound layer The configuration in which the current confinement is used for current confinement is desirable. Alternatively, it is also effective to use ion implantation for current confinement.

  The light emitting layer 82 has a quantum well structure in which well layers and barrier layers are alternately stacked. The well layer is, for example, InAs, InGaAsP, AlGaInAs, GaInAsPSb or the like, and the barrier layer is InP, InAsP, InGaAsP, AlGaInAsP or the like. The light emitting layer 82 may be a quantum wire (quantum wire) or a quantum box (quantum dot).

The n cathode layer 83 is, for example, n-type InGaAsP having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . The Ga composition and the Al composition may be changed in the range of 0 to 1.

The tunnel junction layer 84 is formed of a junction (see FIG. 10B) of an n ⁺⁺ layer 84 a heavily doped with n-type impurities and ap ⁺⁺ layer 84 b heavily doped with n-type impurities. ing. n ⁺⁺ layer 84a and ^{p ++} layer 84b is a high concentration of, for example an impurity concentration of 1 × ¹⁰ 20 / cm ^3. The impurity concentration of the normal junction is 10 ¹⁷ / cm ³ to 10 ¹⁸ / cm ³ . The combination ^{(hereinafter,} referred to with ^{n ++} layer 84a ^{/ p ++} layer 84b.) between the n ⁺⁺ layer 84a and the ^{p ++} layer 84b is, for example ^{n ++ InP / p ++ InP,} n ++ InAsP / p ++ InAsP, n ⁺⁺ InGaAsP / p ⁺⁺ InGaAsP, n ⁺⁺ InGaAs PSb / p ⁺⁺ InGaAs PSb. The combinations may be mutually changed.

The p anode layer 85 is, for example, p-type InGaAsP having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . The Ga composition and the Al composition may be changed in the range of 0 to 1.
The n gate layer 86 is, for example, n-type InGaAsP having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . The Ga composition and the Al composition may be changed in the range of 0 to 1.
The p gate layer 87 is, for example, p-type InGaAsP having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . The Ga composition and the Al composition may be changed in the range of 0 to 1.
The n cathode layer 88 is, for example, n-type InGaAsP having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . The Ga composition and the Al composition may be changed in the range of 0 to 1.

  These semiconductor layers are stacked, for example, by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or the like.

Moreover, it is also possible to apply the embodiment described above to a p-type, n-type and i-type layer made of an organic material.
Furthermore, each embodiment may be used in combination with other embodiments.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... Image formation process part, 11 ... Image formation unit, 12 ... Photosensitive drum, 14 ... Print head, 30 ... Image output control part, 40 ... Image processing part, 62 ... Circuit board, 63 ... Light source section 64 rod lens array 65 light emitting device 80 substrate 81 anode p layer anode p (cladding) layer p anode (DBR) layer 81 b 85 b current confinement layer 82 light emitting layer 83 ... n cathode layer, n cathode (cladding) layer, n cathode (DBR) layer, 84 ... tunnel junction layer, 84 a ... n ⁺⁺ layer, 84 b ... p ⁺⁺ layer, 85 ... p anode layer, 86 ... n gate layer , 87: p gate layer, 88: n cathode layer, 89: voltage reduction layer, 90: protective layer, 91: back electrode, 101: driving unit, 102: light emitting unit, 110: signal generation circuit, 120: transfer No. generating part 140: lighting signal generating part 160: reference potential supply part 170: power supply potential supplying part 301 to 306 island: φ1 first transfer signal φ2 second transfer signal φI (φI1 to φI40 ) ... Lighting signal, α ... Current passing portion (region), β ... Current blocking portion (region), C (C1 to C40) ... Light emitting chip, D (D1 to D127) ... Coupling diode, LED (LED 1 to LED 128) ... Light emitting diode, LD (LD1 to LD128): laser diode, SD: start diode, T (T1 to T128), transfer thyristor, VCSEL (VCSEL1 to VCSEL128), vertical cavity surface emitting laser, Vga: power supply potential, Vsub: reference potential

Claims (11)

A substrate,
A plurality of light emitting elements provided on the substrate;
A plurality of setting thyristors that are stacked on each of the plurality of light emitting elements and set to emit light or increase the amount of light emission of the plurality of light emitting elements by being turned on;
The plurality of light emitting elements are provided on the substrate in the lateral direction, connected to each of the plurality of setting thyristors, and the on state is sequentially transferred to enable the connected setting thyristor to be transferred to the on state. A light emitting component comprising a plurality of transfer thyristors.   The light emitting component according to claim 1, wherein the setting thyristor and the transfer thyristor are formed of laminated semiconductor layers of the same layer configuration in which a plurality of semiconductor layers are laminated.   3. The light emitting component according to claim 2, wherein the laminated semiconductor layer constituting the setting thyristor and the transfer thyristor includes a voltage reduction layer which reduces a rising voltage of the setting thyristor and the transfer thyristor.   The light emitting element is composed of another laminated semiconductor layer in which a plurality of semiconductor layers are laminated, and the voltage reduction layer has a band gap energy smaller than that of any semiconductor layer constituting the other laminated semiconductor layer. The light emitting component according to claim 3, characterized in that   The light emitting component according to claim 4, wherein the voltage reduction layer has a band gap energy smaller than that of a semiconductor layer constituting a light emitting layer of the light emitting element.   The light emitting component according to claim 1, wherein the light emitting element and the setting thyristor are connected in series via a tunnel junction layer or a group III-V compound layer having metallic conductivity.   The setting thyristor is turned on by the voltage applied to the light emitting element and the setting thyristor connected in series, and the light emitting element is made to emit light or the amount of light emission is increased. Item 7. A light emitting component according to item 6.   The light emitting component according to claim 1, wherein a current path of the light emitting element is narrowed. A light emitting means comprising the light emitting component according to claim 1;
An optical means for forming an image of the light emitted from the light emitting means;
A print head comprising: An image carrier,
Charging means for charging the image carrier;
An exposure unit that includes the light emitting component according to claim 1 and exposes the image carrier via an optical unit;
Developing means for developing the electrostatic latent image formed on the image carrier by exposure by the exposure means;
A transfer unit configured to transfer the image developed on the image carrier to a transfer target;
An image forming apparatus comprising: A first stacked semiconductor layer forming step of forming a first stacked semiconductor layer in which a plurality of semiconductor layers are stacked to form a plurality of light emitting elements on a substrate;
A first stacked semiconductor layer etching step of etching the first stacked semiconductor layer on the substrate except a region where at least a plurality of the light emitting elements are formed;
A plurality of setting thyristors that set each of the plurality of light emitting elements to increase light emission or light emission amount by being turned on on the substrate and the first laminated semiconductor layer left on the substrate; A second on which a plurality of semiconductor layers are stacked to form a plurality of transfer thyristors for sequentially transferring the on state to the on state, and transferring the on state to the on state, respectively. And a second laminated semiconductor layer forming step of forming a laminated semiconductor layer.

Images