JP2018112694A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent occurrence of trouble in terms of video reproduction, and to synchronize and display images of a plurality of image display devices.SOLUTION: A slave-side image display circuit 100_1 includes: a horizontal counter 111 for generating a horizontal scanning period signal by dividing a dot clock; a vertical counter 113 for generating a vertical scanning period signal by dividing the horizontal scanning period signal; and a reset generation part 115 that receives a master vertical synchronization signal (Master_VSYNC) from a master-side image display circuit 100_0 and resets the vertical counter when a horizontal scanning period signal is outputted from the horizontal counter.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a gaming machine such as a pachinko machine or a pachislot machine provided with an image processing device that displays images on a plurality of display devices.

In a device that displays images, such as a car navigation system, a different image may be displayed on each of a plurality of displays, or a divided image may be displayed on each display to form a single screen on the plurality of displays. is there. In particular, pachinko machines use a plurality of sub-displays in addition to the main display to display various contents in order to increase the level of entertainment.
Conventionally, in order to display images on a plurality of displays in synchronization, a graphic display controller (GDC) is prepared for each display, and each GDC has RGB screen data and a synchronization signal for synchronizing display with other displays. In general, a reference clock signal serving as a reference for transferring screen data per scanning line is generated and output to a corresponding display.
In addition, as described in Patent Document 1, GDC and its memory (ROM / RAM) are reduced by controlling the screen display of two displays with a single GDC, thereby reducing the mounting cost. A two-screen display system has also been proposed. However, as shown in Table 1, since the dot clock, the horizontal scanning frequency, and the vertical scanning frequency are different depending on the display resolution, various problems arise when controlling a plurality of displays.

Table 1 shows the horizontal and vertical frequencies for each video standard.

Here, since playability is important for the production video of the gaming machine, frame dropping of the production video is not permitted, and smooth reproduction of the production video itself is also required (first request). Furthermore, if the content of the effect video displayed on each display is the same, as well as the content is different, each effect video is linked to an event (for example, jackpot), so the effect displayed on each display From the start to the end of the video, the video playback speeds are the same on all the displays and are required to be synchronized (second request).
In order to satisfy the first requirement, each display may decode the effect video using a vertical synchronization signal for each display output from the GDC as a trigger. However, as shown in Table 1, there is a problem that the production video gradually shifts because the generation timing of the vertical synchronization signal does not match between the displays having different resolutions. FIG. 8 is a diagram illustrating a state in which frame images of displays having different resolutions are shifted. As shown in the figure, the frame image is drawn every 16.58 ms on the SVGA display, and the frame image is drawn every 16.68 ms on the VGA display. Deviation of each occurs. In this way, when presentation video is displayed on displays with different resolutions with a single GDC, the video playback speeds do not match between the displays, resulting in deviation of the production video, and display the video as intended by the production designer. The problem that it is not possible arises.

  For the purpose of matching the playback speed of moving images, which is the second requirement, it may be possible to force the vertical sync signal to match between multiple displays with different resolutions. There is a problem that the timing of the vertical synchronizing signal input to the slave side display circuit that is forcibly matched is different from the original timing of the vertical synchronizing signal generated by the slave side display circuit.

FIG. 9 is a schematic diagram showing the relationship between the forcibly input vertical synchronization signal VS0 and the timing of the original vertical synchronization signal VS1 of the slave side display circuit. In the figure, for convenience of explanation, the active video period is shown in the upper left corner. As shown in the figure, since the forcibly input vertical synchronization signal is located in the middle of one horizontal line, the vertical blanking period is not a line unit (integer) but a fraction (a value including a decimal point). For this reason, when a display interface such as eDP (Embedded Display Port) that does not allow generation of a synchronization signal in the middle of one horizontal line is used, there is a problem that the video is disturbed or the video cannot be reproduced.
Moreover, if the dot clock of the slave side display circuit is changed according to the forced vertical synchronizing signal, the above-mentioned fractional problem can be avoided, but the accuracy of the clock generation source and the frequency divider in the GDC is limited. For this reason, there is a problem that the combination of displays is very limited.

JP 2010-169753 A

Thus, various problems occur when trying to synchronize the display of a plurality of displays.
The present invention has been made in view of the above circumstances, and an object of the present invention is to display images of a plurality of image display devices in a synchronized manner while preventing occurrence of problems in video reproduction.

In order to solve the above problems, the invention according to claim 1 is a master-side image display circuit that generates a master synchronization signal, and a master-side image display unit that displays a master image based on the master synchronization signal. A slave-side image display circuit for generating a slave synchronization signal, and a slave-side image display means for displaying a slave image based on the slave synchronization signal, wherein the slave-side image display The circuit includes a horizontal counter that divides the dot clock to generate a horizontal scanning cycle signal, a vertical counter that divides the horizontal scanning cycle signal to generate a vertical scanning cycle signal, and a master side image display circuit. Reset means for resetting the vertical counter when a vertical synchronizing signal is supplied and the horizontal scanning period signal is output from the horizontal counter , Characterized in that it comprises a.
The invention according to claim 2 is arranged between the plurality of slave-side image display means, the slave-side image display circuit and each slave-side image display means, and a plurality of image data for the image display means. Image distribution means for distributing image data to the respective slave-side image display means from the synthesized data obtained by alternately synthesizing the image data, and the slave-side image display circuit has a number of dots corresponding to the slave-side image display means. A cycle counter that outputs a cycle count signal each time the clock is counted, and the reset means is supplied with the master vertical synchronization signal from the master-side image display circuit, and outputs the cycle count signal from the cycle counter. The horizontal counter and the vertical counter are reset when they are set.

  According to the present invention, it is possible to display images of a plurality of image display devices in synchronization while preventing occurrence of problems in video reproduction.

It is a hardware block diagram which shows the schematic structural example of the game machine which concerns on 1st embodiment of this invention. It is a block diagram showing hardware constitutions around a display circuit concerning a first embodiment of the present invention. (A), (b) is a timing chart for demonstrating the output timing of VSYNC of a master side and a slave side. It is a schematic diagram which shows the example of arrangement | positioning of the image signal which comprises 1 frame. It is a hardware block diagram which shows the schematic structural example of the game machine which concerns on 2nd embodiment of this invention. It is the block diagram which showed the hardware constitutions around the display circuit which concerns on 2nd embodiment of this invention. (A), (b) is a timing chart for demonstrating the output timing of VSYNC of a master side and a slave side. It is a figure which shows a mode that the frame image of the display from which resolution differs differs. It is the schematic diagram which showed the relationship between the vertical synchronizing signal VS0 forcibly input and the timing of the original vertical synchronizing signal VS1 of a slave side display circuit. It is a schematic diagram explaining operation | movement of an image distributor. It is a schematic diagram explaining the conventional problem in the case of using an image distributor.

The present invention is based on the premise that a vertical synchronizing signal used in a display circuit for driving a master-side display is supplied to a display circuit for driving a slave-side display, and the two vertical synchronizing signals are synchronized. In particular, the present invention is characterized in that after the vertical synchronization signal is supplied from the master side, the generation of the vertical synchronization signal for the slave is delayed so that no trouble occurs in the image display of the display on the slave side. There is.
Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .

[First embodiment]
<Amusement machine>
FIG. 1 is a hardware configuration diagram showing a schematic configuration example of the gaming machine according to the first embodiment of the present invention.
The gaming machine 1 includes an image processing device 10, a plurality of display units 15_0, 15_1, and 12_2 connected to the image processing device 10, and a program ROM (Program Read Only Memory) connected to the image processing device 10 via the bus B. ) 16, an external memory 17, and a data ROM (Read Only Memory) 18. The image processing device 10 includes a control unit 11, a drawing unit 12, an internal memory 13, and a display circuit unit 14 including a plurality of image display circuits 100_0, 100_1, and 100_2.

The control unit 11 is means for controlling each unit of the image processing apparatus 10 and includes a CPU (Central Processing Unit), a RAM (Random Access Memory), and the like. The CPU of the control unit 11 executes various controls by reading out the program stored in the program ROM 16 and developing it in the RAM.
The drawing unit 12 is a circuit that reads and decodes image data stored in the data ROM 18 in accordance with the display list output from the control unit 11 and draws RGB image data. Here, the display list is a description in which a drawing control command group and setting data that can be interpreted by the drawing unit 12 are described in time series for an image of one frame to be drawn.
The internal memory 13 is volatile storage means such as SRAM (Static RAM) or eDRAM (Embedded Dynamic RAM) that can operate at high speed. The internal memory 13 has functions as a frame buffer 22 (FIG. 2) and a line buffer 101 (FIG. 2) that temporarily store image data (RGB image data) drawn by the drawing unit 12. The image data for the frame can be stored and the image data can be output for each line.
The display circuit unit 14 includes one image display circuit 100_0 (master side image display circuit) that functions as a master and at least one image display circuit 100_1, 100_2,... (Slave side image display circuit) that functions as a slave. Each image display circuit 100 (100_0, 100_1, 100_2) generates a horizontal synchronization signal (HSYNC), a vertical synchronization signal (VSYNC), and a DE (Data Enable) signal for each display unit 15.
The display units 15_0, 15_1, and 15_2 are connected to the image display circuits 100_0, 100_1, and 100_2 so as to correspond one-to-one. The display unit 15_0 is a master-side image display unit, and the display units 15_1 and 15_2 are slave-side image display units. Each display unit 15 (15_0, 15_1, 15_2) is a device that displays an image such as an LCD (Liquid Crystal Display). Each display unit 15 displays RGB image data (master image data, slave image data) output from each image display circuit 100 according to a synchronization signal (master synchronization signal, slave synchronization signal) output from each image display circuit 100. To do. The display units 15 may have the same resolution or may have different resolutions.

The program ROM 16 is a non-volatile memory that stores programs executed by the control unit 11, control data necessary for controlling the image processing apparatus 10, setting data, and the like.
The external memory 17 includes a volatile memory such as a DDR SDRAM (Double-Data-Rate Synchronous Dynamic RAM), and temporarily stores image data read from the data ROM 18. Note that the gaming machine 1 may have a configuration in which the external memory 17 is omitted.
The data ROM 18 is a nonvolatile storage unit configured by a NAND flash memory, a NOR flash memory, or the like. The data ROM 18 stores encoded content data such as images and sounds.

<Basic operation>
A basic operation of the gaming machine related to the image processing apparatus will be described.
First, the CPU of the control unit 11 reads the program and control data from the program ROM 16 and develops them in the RAM of the control unit 11. Subsequently, the control unit 11 generates a display list including setting data and a control command group for the image to be drawn, and outputs the display list to the drawing unit 12. Based on the display list, the drawing unit 12 outputs, for example, a read request for image data necessary for image formation for one frame to the data ROM 18 and reads out the image data from the data ROM 18. The drawing unit 12 performs a decoding process and a drawing process on the read image data, and writes the drawing data in the internal memory 13.
Each image display circuit 100 of the display circuit unit 14 reads drawing data from the internal memory 13 and outputs data as a display screen to each display unit 15. Each display unit 15 displays an image based on the data output from the image display circuit 100.

<Image processing device>
An image processing apparatus according to a first embodiment of the present invention will be described. FIG. 2 is a block diagram showing a hardware configuration around the display circuit according to the first embodiment of the present invention. The following description is based on a configuration example in which a set of image display circuits and a display unit is provided on the slave side.

In addition to the configuration shown in FIG. 1, the image processing apparatus 10 includes a master-side dot clock generation unit 21_0, a slave-side dot clock generation unit 21_1, and a frame buffer 22.
The dot clock generation unit 21_0 generates a dot clock (Dot_CLK0) to be supplied to the image display circuit 100_0 on the master side from the base clock CLK0 supplied from the clock oscillation circuit in the control unit 11. The dot clock generation unit 21_1 generates a dot clock (Dot_CLK1) to be supplied to the slave-side image display circuit 100_1 from the base clock CLK1 supplied from the clock oscillation circuit in the control unit 11. Both dot clock generation units 21 are configured by a PLL (Phase-Locked Loop). The base clocks CLK0 and CLK1 supplied to each dot clock generation unit 21 may be the same clock (clock supplied from the same supply source) or different clocks (clocks supplied from different supply sources). ). Each dot clock generation unit 21 may be arranged in the display circuit unit 14 (or the corresponding image display circuit 100).

  The frame buffer 22 stores image data (for example, RGB data) of one or more frames that have been decoded and rendered by the rendering unit 12. In this example, the frame buffer 22 is configured by the internal memory 13, but may be configured by the external memory 17, or may be configured by a VRAM (Video RAM) different from the above memories.

<Slave side image display circuit>
The slave-side image display circuit 100_1 that constitutes the image processing apparatus 10 includes a timing generation unit 110, a line buffer 101, and an RGB generation unit 102.
The timing generation unit 110 generates synchronization signals (horizontal synchronization signal HSYNC and vertical synchronization signal VSYNC) and outputs them to the display unit 15_1. A detailed configuration of the timing generation unit 110 will be described later.
The line buffer 101 stores the image data output from the frame buffer 22 for each line. The number of lines stored in the line buffer 101 can be arbitrarily designed, but 1, 2, 4, 8 lines, etc. are preferably used. In this example, the line buffer 101 is composed of the internal memory 13, but may be composed of the external memory 17.
The RGB generation unit 102 supplies the display unit 15_1 with image data (RGB data) input from the line buffer 101 and a data enable signal (DE) indicating whether the image data is in the active video period or the blanking period. Signal). In addition, the RGB generation unit 102 outputs a standby signal (wait) that causes the line buffer 101 to wait for output of image data in accordance with the state of the horizontal / vertical scanning cycle signal. The DE signal and the standby signal are generated based on the horizontal synchronization signal and the vertical synchronization signal.
Note that the configuration of the master-side image display circuit 100_0 may be the same as that of the slave-side image display circuit 100_1, or may be a configuration in which the reset generation unit 115 is omitted.

<Timing generator>
The timing generation unit will be described.
The timing generation unit 110 includes a horizontal counter 111, an HSYNC generation unit 112, a vertical counter 113, a VSYNC generation unit 114, and a reset generation unit 115 (reset means).

  The horizontal counter 111 divides the dot clock DOT_CLK1 input from the dot clock generation unit 21_1 by the total number of horizontal pixels (H_Total) according to the resolution of the display unit 15_1, thereby forming a horizontal scanning cycle signal composed of a plurality of bits. Is generated. The horizontal scanning cycle signal generated by the horizontal counter 111 is supplied to the RGB generation unit 102, the HSYNC generation unit 112, and the reset generation unit 115. The horizontal counter 111 sends a vertical count-up output to the vertical counter 113 every time the total number of horizontal pixels (H_Total) is counted. The horizontal counter 111 resets its count value to zero each time a vertical count-up output is sent.

  The HSYNC generation unit 112 generates a horizontal synchronization signal (Hsync) based on the output of the horizontal counter 111 and outputs it to the display unit 15_1.

  The vertical counter 113 divides the horizontal scanning cycle signal output from the horizontal counter 111 by the total number of vertical lines (V_Total) corresponding to the resolution of the display unit 15_1 to thereby generate a vertical scanning cycle signal composed of a plurality of bits. Generate. The vertical scanning cycle signal generated by the vertical counter 113 is supplied to the RGB generation unit 102, the HSYNC generation unit 112, and the reset generation unit 115. The vertical counter 113 resets its count value to zero every time it counts the total number of vertical lines (V_Total).

  The VSYNC generation unit 114 generates a vertical synchronization signal (Vsync) based on the output of the vertical counter 113 and outputs it to the display unit 15_1.

The reset generation unit 115 resets the counter values of the horizontal counter 111 and the vertical counter 113 to zero based on a vertical synchronization signal (Master_VSYNC: master vertical synchronization signal) input from the image display circuit 100_0. Is output. When Master_VSYNC is output from the image display circuit 100_0, the reset generation unit 115 waits for the input of the horizontal scanning cycle signal from the horizontal counter 111 and then outputs the reset signal. In other words, the reset generation unit 115 outputs a reset signal at the timing of the end of one horizontal line, thereby realizing image synchronization at a timing that does not adversely affect the image display of the display unit 15_1.
Here, when the image display circuit 100_1 does not require synchronization with the image display circuit 100_0, the horizontal counter 111 and the vertical counter 113 reset the count value to zero only by their outputs. On the other hand, when the image display circuit 100_1 functions as a slave of the image display circuit 100_0, the horizontal counter 111 and the vertical counter 113 count values when there is an output of the image display circuit 100_1 or when a reset signal is input from the reset generation unit 115. Reset to zero. Note that in the slave mode in which the image display circuit 100_1 is synchronized with the image display circuit 100_0, the vertical counter 113 is reset by a reset signal from the reset generation unit 115.

<Timing chart>
FIGS. 3A and 3B are timing charts for explaining the output timing of the VSYNC on the master side and the slave side. FIG. 3A is a diagram showing an output cycle of VSYNC, and FIG. 3B is a partially enlarged view of FIG. Hereinafter, an example in which the master side is SVGA and the slave side is VGA will be described. For convenience, the description will be made assuming that VSYNC is generated at the leading clock of the first horizontal line.

  Since SVGA has a dot clock period of 25 ns, VSYNC on the master side is output every 16.58 ms as shown in FIG. Similarly, since one period of the dot clock is 39.72 ns in the VGA, the VSYNC on the slave side is output every 16.68 ms. When the master side and the slave side VSYNC are asynchronous, the slave side VSYNC is delayed by 0.1 ms with respect to the master side. That is, if the slave is not synchronized with the master, the image on the slave side is delayed by 0.1 ms per frame with respect to the image on the master side.

  As shown in the enlarged view of FIG. 3B, when the VSYNC on the master side occurs, the horizontal counter on the slave side counts the 622nd clock on the 522th line. If a display interface that does not allow the generation of VSYNC in the middle of a line, such as eDP (Embeded Display Port), is used, the problem is that if VSYNC is generated in the middle of the line, the video is distorted or the video cannot be played back. Will occur.

  Therefore, in the present embodiment, the reset generation unit 115 delays the output of the reset signal until the horizontal scanning period signal is input from the horizontal counter 111 after the input of MASTER_VSYNC. By processing in this way, as shown in FIG. 3B, the count values of the horizontal counter 111 and the vertical counter 113 can be reset to zero after the end of one line. When a display interface that does not allow the generation of a synchronization signal in the middle is used, it is possible to prevent problems such as the video being distorted or the video being unable to be reproduced.

  Note that there is a gap between the VSYNC on the master side and the VSYNC on the slave side, but since this gap is 7080 ns at the maximum, it is not a gap that is recognized by the player and is synchronized for each frame. Since the processing is performed, the image display on the display unit is not shifted more than the maximum shift amount. Further, the decoding process in the rendering unit 12 is performed in synchronization with VSYNC, but the decoding process is also performed almost synchronously, so that it is possible to prevent dropped frames due to the decoding process not being in time.

  As described above, according to the present embodiment, it is possible to substantially synchronize the VSYNC on the master side and the VSYNC on the slave side while preventing occurrence of problems in video reproduction.

<Image signal arrangement example>
FIG. 4 is a schematic diagram showing an arrangement example of image signals constituting one frame. An image signal constituting one frame includes an active video period in which image data is output and a blanking period in which no image data is output.
The horizontal blanking period includes a horizontal front porch, a horizontal synchronization period (horizontal synchronization signal: HSYNC), and a horizontal back porch. When the image standard is VGA, the horizontal blanking period is 160 pixels (dot clock), the horizontal front porch can be set to 48 pixels, the HSYNC pulse width can be set to 32 pixels, and the horizontal back porch can be set to 80 pixels.
The vertical blanking period includes a vertical front porch, a vertical synchronization period (vertical synchronization signal: VSYNC), and a vertical back porch. When the image standard is VGA, the vertical blanking period is 45 pixels, the vertical front porch can be set to 31 + 3 pixels, the VSYNC pulse width can be set to 4 pixels, and the vertical back porch can be set to 7 pixels.
In the case of generating an image signal like the example shown in the figure, the HSYNC generation unit 112 inputs a reset signal from the reset generation unit 115 and then outputs HSYNC after 48 dot clocks as a count value, and the VSYNC generation unit 114 resets the reset generation unit 115. After the reset signal is input from, HSYNC is output after 3 lines as the count value.
Note that the number of pixels in each period included in the horizontal blanking period and the vertical blanking period can be freely designed.

[Second Embodiment]
A gaming machine according to the second embodiment of the present invention will be described. FIG. 5 is a hardware configuration diagram showing a schematic configuration example of the gaming machine according to the second embodiment of the present invention. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
The gaming machine 2 includes a plurality of display units 15_0 connected to the master-side image display circuit 100_0 and a plurality of slave-side image display circuits 100_1 via an image distributor 23 (image distribution unit). Display units 15_1 and 15_2 are provided. The resolutions of the display unit 15_1 and the display unit 15_2 that use the common image distributor 23 are the same.
For the connection between the image processing apparatus 10 and the display unit 15 in this embodiment, an LVDS (Low voltage differential signaling) interface, an RGB interface, or the like is used. Note that the number of display units connected to the image distributor 23 is limited to a range allowed by the image display circuit 100 and the image distributor 23.

<Operation of image distributor>
FIG. 10 is a schematic diagram for explaining the operation of the image distributor. This figure shows an example in which an image is distributed to two display units (display unit 1 and display unit 2) having the same resolution.
From the image display circuit 100_1, pixel data or control data for the display unit 15_1 and pixel data or control data for the display unit 15_2 are alternately synthesized by using a clock that is twice the slave dot clock (dot_CLK1). The combined data is output to the image distributor 23. The synthesized data for one cycle includes data that is processed synchronously in a plurality of display units.
The image distributor 23 divides the synthesized data using a clock that is twice the dot_CLK1, and outputs the respective data to the display units 15_1 and 15_2.

  In this way, by using a clock obtained by multiplying the dot clock by the number of display units connected to the image distributor 23, synthesis and distribution of the synthesized data are performed correctly.

<Conventional problems when using an image distributor>
FIG. 11 is a schematic diagram for explaining a conventional problem when the image distributor is used. This figure is a diagram for explaining a problem in image distribution that occurs when the slave-side VSYNC is forcibly synchronized with the master-side VSYNC.
Usually, the dot clock on the master side and the dot clock on the slave side are asynchronous with each other. Therefore, when the slave-side VSYNC is adjusted in synchronization with the master-side VSYNC, VSYNC is generated at a timing that does not match the phase of the clock used by the image distributor.
If VSYNC is input in the middle of the data as shown in FIG. 11, the data (D2_004_00 in the figure) disappears. The distribution destination of the data after the disappearance is shifted by one data, and as a result, the images to be displayed are exchanged with the display units 15_1 and 15_2 of the distribution destination.

<Image processing device>
An image processing apparatus according to the second embodiment of the present invention will be described. The image processing apparatus according to this embodiment is characterized in that a reset signal is output at a timing that is a multiple of the number of display units connected to the display circuit unit in order to prevent data disappearance and data replacement. is there.
FIG. 6 is a block diagram showing a hardware configuration around the display circuit according to the second embodiment of the present invention.
In the slave-side image display circuit 100_1 constituting the image processing apparatus 10, the RGB generation unit 102 converts the combined data to be displayed on the display units 1 and 2 created by the drawing unit 12 into RGB data and supplies the RGB data to the image distributor 23. Output.
The image display circuit 100_1 includes a cycle counter 116 in addition to the configuration shown in the first embodiment. The cycle counter 116 counts the dot clocks input from the dot clock generator 21_1, and when the count reaches a number corresponding to the number of display units connected to the image distributor 23, the cycle counter 116 In response to this, a cycle count signal is output. For example, the cycle counter 116 outputs a cycle count signal every two dot clocks when two display units are connected to the image distributor 23, and every three dot clocks when three display units are connected. Outputs cycle count signal.
The cycle counter 116 may be a counter that keeps counting up the dot clock. In this case, the cycle counter 116 outputs a cycle count signal when the count number is a multiple of the number corresponding to the number of display units. . The cycle counter 116 may be a counter that repeats outputting and resetting a cycle count signal for each number of cycles corresponding to the number of display units.

When the vertical generation signal (Master_VSYNC) is input from the image display circuit 100_0, the reset generation unit 115 waits for the input of the cycle counter signal from the cycle counter 116 and then outputs the reset signal. Note that when using an LVDS or RGB interface, VSYNC may occur in the middle of a line.
The configuration of the image display circuit 100_0 on the master side may be the same as that of the image display circuit 100_1 on the slave side, or one or both of the reset generation unit 115 and the cycle counter 116 are omitted. Also good.

<Timing chart>
FIGS. 7A and 7B are timing charts for explaining the output timing of the VSYNC on the master side and the slave side. FIG. 7A is a diagram showing an output cycle of VSYNC, and FIG. 7B is a partially enlarged view of FIG. FIG. 7A is a diagram similar to FIG. Hereinafter, an example in which the master side is SVGA and the slave side is VGA will be described. For convenience, the description will be made assuming that VSYNC is generated at the leading clock of the first horizontal line.

  As shown in the enlarged view of FIG. 7B, when the master-side VSYNC occurs, the slave-side horizontal counter counts the 622th clock of the 522th line. If an image for a plurality of display units is distributed using a distributor, there is a problem that if VSYNC occurs in the middle of a cycle, the image data cannot be distributed normally or the image is replaced due to the disappearance of the data. Occur.

  Therefore, in this embodiment, the reset generation unit 115 delays the output of the reset signal until the input of the cycle count signal from the cycle counter 116 after the input of MASTER_VSYNC. By processing in this way, the count values of the horizontal counter 111 and the vertical counter 113 can be reset to zero after the end of one cycle, as shown in FIG. Image data can be normally distributed.

Note that a deviation occurs between the VSYNC on the master side and the VSYNC on the slave side, but this deviation is a maximum of one cycle, that is, a maximum of 2 × 39.72 ns when there are two image distribution destinations. In the case of 79.44 ns and 3 image distribution destinations, the maximum is 3 × 39.72 ns = 119.16 ns, so that the shift is not enough to be recognized by the player, and synchronization processing is performed for each frame. Therefore, the image display on the display unit is not shifted more than the maximum shift amount. Further, the decoding process in the rendering unit 12 is performed in synchronization with VSYNC, but the decoding process is also performed almost synchronously, so that it is possible to prevent dropped frames due to the decoding process not being in time.
As described above, according to the present embodiment, it is possible to substantially synchronize the VSYNC on the master side and the VSYNC on the slave side while preventing occurrence of problems in video distribution.
Note that the operation of the reset generation unit 115 may be switched according to the display interface used. That is, the reset generation unit 115 operates so as to output a reset signal based on the input of the MASTER_VSYNC and the horizontal scanning cycle signal (first embodiment), or outputs the reset signal based on the input of the MASTER_VSYNC and the cycle count signal. It may be possible to switch whether to operate so as to output (second embodiment).

[Summary of Embodiments, Actions, and Effects of the Present Invention]
<First embodiment>
In this embodiment, a master-side image display circuit 100_0 that generates a master synchronization signal (HSYNC and VSYNC), a master-side image display means (display unit 15_0) that displays a master image based on the master synchronization signal, and a slave A gaming machine 1 including a slave-side image display circuit 100_1 that generates synchronization signals (HSYNC and VSYNC), and slave-side image display means (display unit 15_1) that displays a slave image based on the slave synchronization signal. The slave-side image display circuit includes a horizontal counter 111 that divides the dot clock to generate a horizontal scanning cycle signal, a vertical counter 113 that divides the horizontal scanning cycle signal to generate a vertical scanning cycle signal, and a master. The master vertical synchronization signal (Master_VSYNC) is supplied from the side image display circuit, and the horizontal counter And resetting means for resetting the vertical counter when Luo horizontal scanning period signal is output (reset generator 115), characterized in that it comprises a.
In this aspect, the reset generation means delays the output of the reset signal until the output of the horizontal scanning cycle signal from the horizontal counter after the input of MASTER_VSYNC. By processing in this way, the count value of the vertical counter can be reset to zero after the end of one line, and a display interface that does not allow generation of a synchronization signal in the middle of one horizontal line, such as eDP, is used. In addition, it is possible to prevent such problems that the video is disturbed or the video cannot be reproduced.

<Second embodiment>
The gaming machine 2 according to this aspect is arranged between a plurality of slave-side image display means (display units 15_1 and 15_2), the slave-side image display circuit 100_1, and each slave-side image display means, and a plurality of image display means Image distribution means (image distributor 23) for distributing image data to the respective slave side image display means from the synthesized data obtained by alternately synthesizing the image data for use, and the slave side image display circuit displays the slave side image display A cycle counter 116 that outputs a cycle count signal each time the number of dot clocks corresponding to the means is counted is provided. The reset means (reset generation unit 115) receives a master vertical synchronization signal (Master_VSYNC) from the master-side image display circuit 100_0. Is supplied and a cycle count signal is output from the cycle counter. Characterized by resetting the data 111 and vertical counter 113.
In this aspect, the reset generation means delays the output of the reset signal until the output of the cycle count signal from the cycle counter after the input of MASTER_VSYNC. By processing in this way, the count values of the horizontal counter and the vertical counter can be reset to zero after the end of one cycle, and the image data can be distributed normally without erasing the data. Become.

  DESCRIPTION OF SYMBOLS 1, 2 ... Game machine, 10 ... Image processing apparatus, 11 ... Control part, 12 ... Drawing part, 13 ... Internal memory, 14 ... Display circuit part, 15 ... Display part, 100 ... Image display circuit, 101 ... Line buffer, DESCRIPTION OF SYMBOLS 102 ... RGB production | generation part, 110 ... Timing production | generation part, 111 ... Horizontal counter, 112 ... HSYNC production | generation part, 113 ... Vertical counter, 114 ... VSYNC production | generation part, 115 ... Reset production | generation part (reset means), 116 ... Cycle counter, 15 Display unit 16 Program ROM 17 External memory 18 Data ROM 21 Dot clock generation unit 22 Frame buffer 23 Image distributor (image distribution unit)

Claims (2)

A master-side image display circuit for generating a master synchronization signal; and a master-side image display means for displaying a master image based on the master synchronization signal;
A gaming machine comprising: a slave-side image display circuit that generates a slave synchronization signal; and a slave-side image display means that displays a slave image based on the slave synchronization signal,
The slave image display circuit
A horizontal counter that divides the dot clock to generate a horizontal scanning cycle signal;
A vertical counter that divides the horizontal scanning cycle signal to generate a vertical scanning cycle signal;
And a reset means for resetting the vertical counter when the master vertical synchronizing signal is supplied from the master-side image display circuit and the horizontal scanning period signal is output from the horizontal counter. Machine. A plurality of slave side image display means;
Image data is arranged between the slave-side image display circuit and each slave-side image display means, and from the combined data obtained by alternately synthesizing the image data for the plurality of image display means to each slave-side image display means. And an image distribution means for distributing
The slave-side image display circuit includes a cycle counter that outputs a cycle count signal every time the number of dot clocks corresponding to the slave-side image display unit is counted.
The reset means resets the horizontal counter and the vertical counter when the master vertical synchronization signal is supplied from the master-side image display circuit and the cycle count signal is output from the cycle counter. The gaming machine according to claim 1.

Images