JP2018022812A - Electronic device and method for manufacturing the same - Google Patents

Electronic device and method for manufacturing the same Download PDF

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JP2018022812A
JP2018022812A JP2016154163A JP2016154163A JP2018022812A JP 2018022812 A JP2018022812 A JP 2018022812A JP 2016154163 A JP2016154163 A JP 2016154163A JP 2016154163 A JP2016154163 A JP 2016154163A JP 2018022812 A JP2018022812 A JP 2018022812A
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semiconductor circuit
circuit chip
substrate
wiring film
flexible
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JP6781983B2 (en
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小林 健
Takeshi Kobayashi
健 小林
俊弘 竹下
Toshihiro Takeshita
俊弘 竹下
亮平 武井
Ryohei Takei
亮平 武井
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National Institute of Advanced Industrial Science and Technology AIST
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Abstract

PROBLEM TO BE SOLVED: To largely reduce the transmission of a distortion from a flexible board to a semiconductor circuit chip mounted on the flexible board.SOLUTION: An electronic device comprises: a flexible board 11 having a flexible wiring film, a flexible sensor, a flexible battery, etc. formed on its surface; a semiconductor circuit chip 12 which is an IC chip containing a semiconductor integrated circuit (IC) of electronic circuits, such as a semiconductor signal processing circuit and a radio communication circuit; and distortion buffer structures 13a, 13b which elastically secure and support the semiconductor circuit chip 12 only by its opposing ends in the state of floating from the flexible board 11, and electrically connect between the semiconductor circuit chip 12 and the flexible board 11. Thus even if the flexible board 11 is bent, the distortion buffer structures 13a, 13b can largely reduce the transmission of bending as distortion to the semiconductor circuit chip 12.SELECTED DRAWING: Figure 1

Description

本発明は電子デバイス及びその製造方法に係り、特にフレキシブルで極薄の電子デバイス及びその製造方法に関する。   The present invention relates to an electronic device and a manufacturing method thereof, and more particularly to a flexible and ultrathin electronic device and a manufacturing method thereof.

近年、生体に装着して生体情報を検出するセンサデバイスが注目を集めており、中でも人体に装着する衣類型ウェアラブルデバイスが新たなエレクトロニクス市場を牽引していく電子デバイスとして期待されている。この種の衣類型ウェアラブルデバイスにとって重要視される点として、如何に違和感無く装着できるかという柔軟な構造を有したフレキシブル性があげられる。このフレキシブルな電子デバイスの作製技術として、従来より高伸縮配線やセンサなどをフレキシブル基板に印刷する印刷技術の開発が進められた。しかし、印刷技術では、センサから得られる信号を処理するマイクロコンピュータ(以下、「マイコン」と略す)や、数百MHz帯で無線通信を行うためのRF-IC(Radio Frequency Integrated Circuit)などは、作製が困難である(例えば、非特許文献1参照)。   2. Description of the Related Art In recent years, sensor devices that are attached to a living body and detect biological information have attracted attention. In particular, a clothing-type wearable device that is attached to a human body is expected as an electronic device that will drive a new electronics market. An important point for this type of garment-type wearable device is flexibility with a flexible structure of how it can be worn comfortably. As a technique for producing this flexible electronic device, development of a printing technique for printing a highly stretchable wiring, a sensor, or the like on a flexible substrate has been advanced. However, in printing technology, a microcomputer (hereinafter abbreviated as “microcomputer”) that processes signals obtained from sensors, an RF-IC (Radio Frequency Integrated Circuit) for wireless communication in the several hundred MHz band, It is difficult to manufacture (see Non-Patent Document 1, for example).

そのため、現在ではシリコン(Si)基板やSOI(Silicon On Insulation)基板の上にマイコンやRF-ICなどが集積回路化された半導体回路チップ(ICチップ)を作製して薄化した後(例えば、非特許文献2,3参照)、それをフレキシブル基板上に接着して電子デバイスを製造する方法が採用されている。また、フレキシブルな電子デバイスに柔軟性を持たせ、フレキシブル基板の十分な屈曲性を有しつつICチップの割れや剥離を防止するため、特許文献1にはICチップを、その中央領域のみで接着層を介してフレキシブル基板に固定することで、フレキシブル基板が屈曲しても実装されたICチップが殆ど追従しないようにした方法が開示されている。   Therefore, after manufacturing and thinning a semiconductor circuit chip (IC chip) in which a microcomputer, an RF-IC, etc. are integrated on a silicon (Si) substrate or SOI (Silicon On Insulation) substrate (for example, Non-Patent Documents 2 and 3), and a method of manufacturing an electronic device by adhering it to a flexible substrate is employed. In addition, in order to give flexibility to a flexible electronic device and prevent the IC chip from cracking or peeling while having sufficient flexibility of the flexible substrate, Patent Document 1 discloses that the IC chip is bonded only in the central region. A method is disclosed in which the mounted IC chip hardly follows even when the flexible substrate is bent, by fixing to the flexible substrate via a layer.

更に、特許文献2には基板上に作製した極薄化した電子デバイス構造体(機能性素子、電極及び電極パッドからなる)を基板から剥離してフレキシブル基板に接着して転写することでフレキシブルな電子デバイスを製造する方法が開示されている。この特許文献2に記載の電子デバイスは、電子デバイス全体がフレキシブルになるため、より柔軟なフレキシブルな電子デバイスを実現することができる。このような従来のシリコンを基板としたIC製造技術と印刷技術を組み合わせた電子デバイスは、フレキシブル・ハイブリッド・エレクトロニクスと呼ばれ近年注目を集めている(例えば、非特許文献4参照)。   Further, in Patent Document 2, a flexible electronic device structure (comprising a functional element, an electrode, and an electrode pad) manufactured on a substrate is peeled off from the substrate, adhered to a flexible substrate, and transferred. A method of manufacturing an electronic device is disclosed. In the electronic device described in Patent Document 2, since the entire electronic device is flexible, a more flexible and flexible electronic device can be realized. Such an electronic device that combines an IC manufacturing technique using a silicon substrate and a printing technique is called flexible hybrid electronics and has attracted attention in recent years (for example, see Non-Patent Document 4).

H.Fuketa,et ai.,“Organic-Transistor-Based 2kV ESD-Tolerant Flexible Wet Sensor Sheet for Biomedical Applications with Wireless Power and Data Transmission Using 13.56MHz Magnetic Resonance”,2014 International Solid-State Circuits Conference(ISSCC),(2014)pp.490-491H. Fuketa, et ai., “Organic-Transistor-Based 2kV ESD-Tolerant Flexible Wet Sensor Sheet for Biomedical Applications with Wireless Power and Data Transmission Using 13.56MHz Magnetic Resonance”, 2014 International Solid-State Circuits Conference (ISSCC), ( 2014) pp.490-491 Y.S.Kim.et al.,“Ultra Thinning of DRAM wafer for 3D WOW Application:Impact of Thinning on Retention Characteristic and Atomic Level Analysis of Backside Damage”,Proc.Advanced Metalization Conference(2014)and ADMETA 2014.,pp.1-2YSKim. Et al., “Ultra Thinning of DRAM wafer for 3D WOW Application: Impact of Thinning on Retention Characteristic and Atomic Level Analysis of Backside Damage”, Proc. Advanced Metalization Conference (2014) and ADMETA 2014., pp.1- 2 Y.S.Kim.et al.,“Hot Spt Co.etal.,oiling Evaluation using Closed-Channel Cooling System(C3S)for MPU 3DI Application”,IEEE symp.on VLSI Technol.,(2011)pp.140-145Y.S.Kim.et al., “Hot Spt Co. etal., Oiling Evaluation using Closed-Channel Cooling System (C3S) for MPU 3DI Application”, IEEE symp.on VLSI Technol., (2011) pp.140-145 大谷基之,“飛躍狙うフレキシブル・ハイブリッド・エレクトロニクス(FHE)技術”,日経テクノロジー,(2016)Motoyuki Otani, “Flexible Hybrid Electronics (FHE) Technology Aiming for Leaps”, Nikkei Technology, (2016)

特開2012−038921号公報JP 2012-038921 A 特開2016−039343号公報Japanese Patent Application Laid-Open No. 2006-039343

しかしながら、上記の非特許文献4に記載のフレキシブル・ハイブリッド・エレクトロニクスで作製された電子デバイスを衣類型ウェアラブルデバイスに使用する場合、衣類型ウェアラブルが伸長したり曲がったりすると、それが電子デバイスのフレキシブル基板を通して、電子デバイスの機能性素子である半導体回路チップ(例えば、マイコンやRF-ICなどの集積回路化された半導体信号処理回路や無線通信回路)に歪みとして伝達されてしまう。その結果、従来は半導体回路チップがフレキシブル基板の屈曲に左右されない正確な生体情報の検出及びそれに基づく所期の特性を得ることができず、あるいは極薄の半導体回路チップ自体が破断してしまい、電子デバイスの信頼性や長寿命化を阻害するという問題がある。   However, when the electronic device manufactured by the flexible hybrid electronics described in Non-Patent Document 4 is used for a clothing-type wearable device, if the clothing-type wearable expands or bends, it is a flexible substrate of the electronic device. Then, it is transmitted as distortion to a semiconductor circuit chip (for example, a semiconductor signal processing circuit or a wireless communication circuit integrated into a microcomputer or RF-IC) that is a functional element of the electronic device. As a result, the conventional semiconductor circuit chip cannot accurately detect biological information that is not affected by the bending of the flexible substrate and the expected characteristics based on it, or the ultra-thin semiconductor circuit chip itself breaks, There is a problem of hindering the reliability and longevity of electronic devices.

また、特許文献1に記載の方法は、パッケージされているICチップ(半導体回路チップ)の実装に関する方法であり、ICチップが極薄ではなく、また、フレキシブル基板の曲がりや伸長が接着層を介してICチップに歪みとして伝達されることは避けられず、衣類型ウェアラブルデバイスに使用することは困難である。更に、特許文献2記載の電子デバイスでは、フレキシブル基板上の極薄化した電子デバイス構造体に、フレキシブル基板の屈曲が伝達しないようにした対策はとられていないため、衣類型ウェアラブルデバイスに使用した場合、正確な人体情報の検出及びそれに基づく所期の特性を得ることができない。   Further, the method described in Patent Document 1 is a method related to mounting of a packaged IC chip (semiconductor circuit chip), and the IC chip is not extremely thin, and bending or stretching of the flexible substrate is performed via an adhesive layer. Therefore, it is inevitable that it is transmitted to the IC chip as strain, and it is difficult to use it for a clothing type wearable device. Furthermore, the electronic device described in Patent Document 2 is used for a clothing-type wearable device because no measures have been taken to prevent the bending of the flexible substrate from being transmitted to the ultra-thin electronic device structure on the flexible substrate. In this case, accurate human body information detection and desired characteristics based on the detection cannot be obtained.

本発明は以上の点に鑑みなされたもので、フレキシブル基板から当該フレキシブル基板に搭載された半導体回路チップへの歪みの伝達を大幅に低減した構造の電子デバイス及びその製造方法を提供することを目的とする。   The present invention has been made in view of the above points, and an object thereof is to provide an electronic device having a structure in which transmission of strain from a flexible substrate to a semiconductor circuit chip mounted on the flexible substrate is significantly reduced, and a method for manufacturing the electronic device. And

上記の目的を達成するため、第1の発明に係る電子デバイスは、表面に端子が形成された電子回路を内蔵する半導体回路チップと、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されたフレキシブル基板と、表面に配線膜が形成された構造であり、前記半導体回路チップの前記端子に前記配線膜の一端を接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続すると共に、前記半導体回路チップの端部を前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持する構造の歪み緩衝構造部とを備えることを特徴とする。   In order to achieve the above object, an electronic device according to a first invention includes a semiconductor circuit chip containing an electronic circuit having terminals formed on the surface, and a flexible substrate having at least a flexible wiring film and a flexible sensor formed on the surface. And having a wiring film formed on the surface, connecting one end of the wiring film to the terminal of the semiconductor circuit chip, and connecting the other end of the wiring film to the flexible wiring film, And a strain buffering structure having a structure in which an end portion of the semiconductor circuit chip is elastically fixed and supported in a state where the semiconductor circuit chip and the flexible substrate are separated from each other.

また、上記の目的を達成するため、第2の発明に係る電子デバイスは、第1の発明の歪み緩衝構造部が、前記フレキシブル基板とは異なる極薄の基板に形成された前記半導体回路チップの側縁部と、前記極薄の基板の端部との間を別々に接続する、平面が所定形状の複数の接続用基板部分の上に前記配線膜が形成されており、前記複数の接続用基板部分の各一方の端部の上の前記配線膜の一端を前記半導体回路チップの端子に電気的に接続し、前記複数の接続用基板部分の各他方の端部のみを前記フレキシブル基板にそれぞれ前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持すると共に前記配線膜の他端を前記フレキシブル配線膜に電気的に接続した構造であることを特徴とする。   In order to achieve the above object, an electronic device according to a second aspect of the present invention is the semiconductor circuit chip in which the strain buffering structure of the first aspect is formed on a very thin substrate different from the flexible substrate. The wiring film is formed on a plurality of connection substrate portions having a predetermined plane shape, which separately connect a side edge portion and an end portion of the ultra-thin substrate, and the plurality of connection connections One end of the wiring film on one end of each substrate portion is electrically connected to a terminal of the semiconductor circuit chip, and only the other end of each of the plurality of connection substrate portions is respectively connected to the flexible substrate. The semiconductor circuit chip and the flexible substrate are elastically fixed and supported in a separated state, and the other end of the wiring film is electrically connected to the flexible wiring film.

また、上記の目的を達成するため、第3の発明に係る電子デバイスは、第1の発明のフレキシブル基板が、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部と基板側縁部に沿う四角枠との間を平面が所定形状の複数の接続部でそれぞれ接続する形状の基板部分を残した開口部を有するとともに、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されており、第1の発明の歪み緩衝構造部が、前記フレキシブル基板の前記接続部の表面に前記配線膜が形成された構造であり、前記フレキシブル基板の前記矩形領域に搭載された前記半導体回路チップを前記接続部及び前記四角枠で弾性的に固定・支持すると共に、前記配線膜の一端を前記半導体回路チップの前記端子に接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続することを特徴とする。   In order to achieve the above object, according to a third aspect of the present invention, in the electronic device according to the first aspect, the flexible substrate includes a rectangular region for mounting the semiconductor circuit chip, a side edge of the rectangular region, and a substrate side. It has an opening that leaves a portion of the substrate that is connected to the rectangular frame along the edge by a plurality of connecting portions having a predetermined shape, and at least a flexible wiring film and a flexible sensor are formed on the surface. The strain buffering structure portion of the first invention is a structure in which the wiring film is formed on the surface of the connection portion of the flexible substrate, and the semiconductor circuit chip mounted in the rectangular region of the flexible substrate is It is elastically fixed and supported by the connecting portion and the square frame, one end of the wiring film is connected to the terminal of the semiconductor circuit chip, and the other end of the wiring film is connected to the front. Characterized by connecting the flexible wiring layer.

また、上記の目的を達成するため、第4の発明に係る電子デバイスは、第1の発明の歪み緩衝構造部が、前記フレキシブル基板、及び前記半導体回路チップが形成された極薄の基板とはそれぞれ異なる弾性体基板に形成されており、前記弾性体基板が前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部にそれぞれの一端が接続された平面が所定形状の複数の接続部とからなり、かつ、前記複数の接続部の表面に配線膜が形成された構造であり、前記配線膜の一端を前記弾性体基板の矩形領域に搭載された前記半導体回路チップの端子に電気的に接続し、かつ、前記複数の接続部の他端をスペーサを介して前記フレキシブル基板に前記半導体回路チップと離間させた状態で弾性的に固定・支持するとともに、前記2つの接続部の他端上の前記配線膜と前記フレキシブル配線膜とを前記スペーサを覆う導電性部材で電気的に接続することを特徴とする。   In order to achieve the above object, an electronic device according to a fourth aspect of the present invention is a strain buffer structure according to the first aspect, wherein the flexible substrate and the ultrathin substrate on which the semiconductor circuit chip is formed The elastic substrate is formed on different elastic substrates, and the elastic substrate is connected to a rectangular region for mounting the semiconductor circuit chip, and a plurality of connections having a predetermined shape in a plane in which one end is connected to a side edge of the rectangular region. And a wiring film is formed on the surfaces of the plurality of connecting portions, and one end of the wiring film is electrically connected to a terminal of the semiconductor circuit chip mounted on a rectangular region of the elastic substrate. And the other ends of the plurality of connection portions are elastically fixed and supported on the flexible substrate through a spacer while being spaced apart from the semiconductor circuit chip. Characterized by electrically connecting the said wiring film on the end flexible wiring film by a conductive member for covering the spacer.

ここで、第1乃至第4の発明における所定形状は、ジグザグ形状、S字形状又はメッシュ状である。   Here, the predetermined shape in the first to fourth inventions is a zigzag shape, an S shape, or a mesh shape.

上記の目的を達成するため、第6の発明に係る電子デバイスの製造方法は、表面に端子が形成された電子回路を内蔵する半導体回路チップを作製する工程と、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されたフレキシブル基板を作製する工程と、表面に配線膜が形成された構造の歪み緩衝構造部により、前記半導体回路チップの前記端子に前記配線膜の一端を接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続すると共に、前記半導体回路チップの端部を前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持する固定工程とを含むことを特徴とする。   In order to achieve the above object, a method for manufacturing an electronic device according to a sixth aspect of the invention includes a step of manufacturing a semiconductor circuit chip containing an electronic circuit having a terminal formed on the surface, and at least a flexible wiring film and a flexible on the surface. One end of the wiring film is connected to the terminal of the semiconductor circuit chip by a step of producing a flexible substrate on which a sensor is formed, and a strain buffer structure having a structure in which a wiring film is formed on the surface, and the wiring A fixing step of connecting the other end of the film to the flexible wiring film and elastically fixing and supporting the end of the semiconductor circuit chip in a state where the semiconductor circuit chip and the flexible substrate are separated from each other. It is characterized by.

また、上記の目的を達成するため、第7の発明に係る電子デバイスの製造方法は、第6の発明における半導体回路チップを作製する工程を、前記フレキシブル基板とは異なる極薄の基板に前記半導体回路チップを作製する工程とし、
第6の発明における前記固定工程を、平面が所定形状で、かつ、表面に配線膜が形成されており、前記配線膜の一端が前記半導体回路チップの前記端子にそれぞれの一端が別々に電気的に接続された複数の接続部を前記極薄の基板に形成する接続部形成工程と、前記複数の接続部のそれぞれの前記配線膜の他端を前記フレキシブル配線膜に電気的に接続すると共に、前記複数の接続部の前記配線膜の他端が形成されている前記極薄の基板部分で、前記半導体回路チップと前記フレキシブル基板とを離間させた状態で固定する工程とからなるようにしたことを特徴とする。
In order to achieve the above object, a method for manufacturing an electronic device according to a seventh aspect of the invention includes the step of producing a semiconductor circuit chip according to the sixth aspect of the invention on an ultrathin substrate different from the flexible substrate. As a process of making a circuit chip,
In the fixing step according to the sixth aspect of the invention, the plane has a predetermined shape and a wiring film is formed on the surface, one end of the wiring film is electrically connected to the terminal of the semiconductor circuit chip, and each one end is electrically A connecting portion forming step of forming a plurality of connecting portions connected to the ultra-thin substrate, electrically connecting the other end of each of the wiring films of the plurality of connecting portions to the flexible wiring film, A step of fixing the semiconductor circuit chip and the flexible substrate in a separated state at the ultra-thin substrate portion where the other ends of the wiring films of the plurality of connection portions are formed. It is characterized by.

また、上記の目的を達成するため、第8の発明に係る電子デバイスの製造方法は、第7の発明における接続部形成工程を、前記半導体回路チップの前記端子に一端が別々に接続され、他端が開放とされた平面形状が前記所定形状の複数の配線膜をシリコン基板上に形成する工程と、前記半導体回路チップ及び前記配線膜がそれぞれ形成された前記シリコン基板の裏側からエッチングにより、前記半導体回路チップを残し、かつ、前記複数の配線膜が形成されている前記シリコン基板部分を薄く残した凹部を形成する工程と、前記凹部が形成された前記シリコン基板から、前記半導体回路チップ及び前記複数の配線膜が表面に形成された薄い前記シリコン基板部分を剥離し、前記複数の配線膜が表面に形成された薄い前記シリコン基板部分を前記極薄の基板上の複数の接続部として得る工程とより構成し、
第7の発明における半導体回路チップと前記フレキシブル基板とを離間させた状態で固定する工程を、前記複数の配線膜の各端部の直下の前記極薄の基板部分のみを、前記フレキシブル基板の表面と離間させた状態でスペーサを介して固定する工程と、前記フレキシブル配線膜と前記複数の配線膜の各端部とを導電性部材で電気的に接続する工程とよりなるようにしたことを特徴とする。
In addition, in order to achieve the above object, an electronic device manufacturing method according to an eighth invention is the same as the connection part forming step according to the seventh invention except that one end is separately connected to the terminal of the semiconductor circuit chip. The step of forming a plurality of wiring films having a predetermined planar shape with an open end on the silicon substrate, and etching from the back side of the silicon substrate on which the semiconductor circuit chip and the wiring film are respectively formed, Forming a recess leaving a semiconductor circuit chip and thinly leaving the silicon substrate portion on which the plurality of wiring films are formed; and from the silicon substrate on which the recess is formed, the semiconductor circuit chip and the The thin silicon substrate portion having a plurality of wiring films formed on the surface is peeled off, and the thin silicon substrate portion having the plurality of wiring films formed on the surface is removed. More configuration and obtaining a plurality of connections on the substrate ultrathin,
The step of fixing the semiconductor circuit chip and the flexible substrate in a state of being separated from each other in the seventh invention is performed by using only the ultrathin substrate portion immediately below each end of the plurality of wiring films as the surface of the flexible substrate. A step of fixing via a spacer in a state of being separated from each other, and a step of electrically connecting the flexible wiring film and each end of the plurality of wiring films with a conductive member. And

また、上記の目的を達成するため、第9の発明に係る電子デバイスの製造方法は、第6の発明におけるフレキシブル基板を作製する工程を、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成された加工前のフレキシブル基板に対し、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部と基板側縁部に沿う四角枠との間を平面が所定形状で、かつ、表面に前記配線膜が形成されるとともに、前記配線膜の一端が前記フレキシブル配線膜にそれぞれ電気的に接続された形状の複数の接続部とを残した開口部を形成して加工処理したフレキシブル基板を作製する工程とし、
第6の発明における固定工程を、前記加工処理したフレキシブル基板の前記矩形領域に、前記半導体回路チップの端子が前記複数の接続部のそれぞれの配線膜の他端に電気的に接続されるように前記半導体回路チップを搭載する工程を有し、前記半導体回路チップを前記複数の接続部及び前記四角枠で弾性的に固定・支持するようにしたことを特徴とする。
In addition, in order to achieve the above object, an electronic device manufacturing method according to a ninth invention includes a step of manufacturing a flexible substrate according to the sixth invention, wherein at least a flexible wiring film and a flexible sensor are formed on the surface. With respect to the previous flexible substrate, the plane between the rectangular area for mounting the semiconductor circuit chip, and the rectangular frame along the side edge of the rectangular area and the side edge of the substrate has a predetermined shape, and the wiring is formed on the surface. Forming a film and forming an opening that leaves a plurality of connecting portions each having a shape in which one end of the wiring film is electrically connected to the flexible wiring film, and manufacturing a flexible substrate; age,
In the fixing step according to the sixth aspect of the invention, the terminal of the semiconductor circuit chip is electrically connected to the other end of each wiring film of the plurality of connection portions in the rectangular region of the processed flexible substrate. And a step of mounting the semiconductor circuit chip, wherein the semiconductor circuit chip is elastically fixed and supported by the plurality of connection portions and the rectangular frame.

また、上記の目的を達成するため、第10の発明に係る電子デバイスの製造方法は、第6の発明における前記固定工程を、前記フレキシブル基板、及び前記半導体回路チップが形成された極薄の基板とはそれぞれ異なる弾性体基板に対し、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部にそれぞれの一端が接続された平面が所定形状で、かつ、表面に配線膜が形成された複数の接続部とを形成する工程と、前記極薄の基板に形成された前記半導体回路チップの端子が、前記複数の接続部のそれぞれの配線膜の一端に電気的に接続されるように前記半導体回路チップを前記矩形領域に搭載する工程と、前記複数の接続部の他端をスペーサを介して前記フレキシブル基板に前記半導体回路チップと離間させた状態で弾性的に固定・支持するとともに、前記複数の接続部の他端上の前記配線膜と前記フレキシブル配線膜とを前記スペーサを覆う導電性部材で電気的に接続する工程とからなるようにしたことを特徴とする。   In order to achieve the above object, an electronic device manufacturing method according to a tenth aspect of the present invention is the ultrathin substrate on which the flexible substrate and the semiconductor circuit chip are formed in the fixing step according to the sixth aspect of the present invention. A rectangular area for mounting the semiconductor circuit chip, and a plane where one end of each of the rectangular areas is connected to a side edge of the rectangular area has a predetermined shape, and a wiring film is formed on the surface. Forming a plurality of connected portions, and terminals of the semiconductor circuit chip formed on the ultra-thin substrate are electrically connected to one end of each wiring film of the plurality of connected portions. Mounting the semiconductor circuit chip in the rectangular region, and elastically fixing the other end of the plurality of connecting portions to the flexible substrate with a spacer interposed therebetween. And a step of electrically connecting the wiring film on the other end of the plurality of connection portions and the flexible wiring film with a conductive member covering the spacer. .

ここで、第6乃至第10の発明における所定形状は、ジグザグ形状、S字形状又はメッシュ状である。   Here, the predetermined shape in the sixth to tenth inventions is a zigzag shape, an S shape, or a mesh shape.

本発明によれば、フレキシブル基板から当該フレキシブル基板に搭載された半導体回路チップへの歪みの伝達を大幅に低減することができる。   According to the present invention, transmission of strain from a flexible substrate to a semiconductor circuit chip mounted on the flexible substrate can be greatly reduced.

本発明に係る電子デバイスの第1の実施形態の概略模式的構成図である。1 is a schematic configuration diagram of a first embodiment of an electronic device according to the present invention. 本発明に係る電子デバイスの第1の実施形態の製造方法を説明する各製造工程時の素子平面図及び素子断面図である。It is the element top view at the time of each manufacturing process explaining the manufacturing method of 1st Embodiment of the electronic device which concerns on this invention, and element sectional drawing. 本発明に係る電子デバイスの第2の実施形態の製造方法(その1)を説明する各製造工程時の素子平面図及び素子断面図である。It is the element top view and element sectional drawing at the time of each manufacturing process explaining the manufacturing method (the 1) of 2nd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第2の実施形態の製造方法(その2)を説明する各製造工程時の素子平面図及び素子断面図である。It is the element top view at the time of each manufacturing process and element sectional drawing explaining the manufacturing method (the 2) of 2nd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第3の実施形態の製造方法(その1)を説明する各製造工程時の素子平面図及び素子断面図である。It is the element top view and element sectional drawing at the time of each manufacturing process explaining the manufacturing method (the 1) of 3rd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第3の実施形態の製造方法(その2)を説明する各製造工程時の素子平面図及び素子断面図である。It is the element top view and element sectional drawing at the time of each manufacturing process explaining the manufacturing method (the 2) of 3rd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第3の実施形態の製造方法(その3)を説明する各製造工程時の素子平面図及び素子断面図である。It is the element top view and element sectional drawing at the time of each manufacturing process explaining the manufacturing method (the 3) of 3rd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスを用いたウェアラブルデバイスの一例の全体構成図である。It is a whole block diagram of an example of the wearable device using the electronic device which concerns on this invention. 本発明に係る電子デバイスを用いたウェアラブルデバイスの一例の使用例を示す図である。It is a figure which shows the usage example of an example of the wearable device using the electronic device which concerns on this invention. 本発明の第1の実施形態の電子デバイスをウェアラブルデバイスに適用した場合の概略模式的構成図である。1 is a schematic schematic configuration diagram when an electronic device according to a first embodiment of the present invention is applied to a wearable device. 本発明の第1の実施形態の電子デバイスをウェアラブルデバイスに適用した場合の概略模式的構成図である。1 is a schematic schematic configuration diagram when an electronic device according to a first embodiment of the present invention is applied to a wearable device. 本発明の第1の実施形態の電子デバイスをウェアラブルデバイスに適用した場合の概略模式的構成図である。1 is a schematic schematic configuration diagram when an electronic device according to a first embodiment of the present invention is applied to a wearable device. 歪み緩衝構造部の平面形状の他の例の説明図である。It is explanatory drawing of the other example of the planar shape of a distortion buffer structure part. 半導体回路チップと歪み緩衝構造部との接続の他の例(その1)の説明図である。It is explanatory drawing of the other example (the 1) of a connection of a semiconductor circuit chip and a distortion buffer structure part. 半導体回路チップと歪み緩衝構造部との接続の他の例(その2)の説明図である。It is explanatory drawing of the other example (the 2) of a connection of a semiconductor circuit chip and a distortion buffer structure part. 半導体回路チップと歪み緩衝構造部との接続の他の例(その3)の説明図である。It is explanatory drawing of the other example (the 3) of a connection of a semiconductor circuit chip and a distortion buffer structure part.

次に、本発明の各実施形態について図面を参照して説明する。
(第1の実施形態)
図1は、本発明に係る電子デバイスの第1の実施形態の概略模式的構成図を示す。同図に模式的に示すように、本実施形態の電子デバイス10は、フレキシブル基板11と、極薄の半導体回路チップ12と、表面に配線膜が形成されている歪み緩衝構造部13a及び13bとより構成されている。フレキシブル基板11は、表面にフレキシブル配線膜、フレキシブルセンサ、フレキシブルバッテリなどが形成されており、その伸長率は例えば1%〜10%である。半導体回路チップ12は、半導体信号処理回路(マイコン含む)や無線通信回路などの電子回路の半導体集積回路(IC)を内蔵するICチップであり、その伸長率は例えば0.1%〜0.01%で、また極薄に形成されている。
Next, each embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows a schematic schematic configuration diagram of a first embodiment of an electronic device according to the present invention. As schematically shown in the figure, the electronic device 10 of the present embodiment includes a flexible substrate 11, an ultrathin semiconductor circuit chip 12, and strain buffer structures 13a and 13b having a wiring film formed on the surface. It is made up of. The flexible substrate 11 has a flexible wiring film, a flexible sensor, a flexible battery, and the like formed on the surface, and the elongation rate thereof is, for example, 1% to 10%. The semiconductor circuit chip 12 is an IC chip incorporating a semiconductor integrated circuit (IC) of an electronic circuit such as a semiconductor signal processing circuit (including a microcomputer) or a wireless communication circuit, and its expansion rate is, for example, 0.1% to 0.01. %, And it is very thin.

また、歪み緩衝構造部13a及び13bは、半導体回路チップ12の底面とフレキシブル基板11の上面との間に間隔dを設けた状態で、半導体回路チップ12の対向する2つの端部とフレキシブル基板11の対向する2つの端部との間を別々に固定している。したがって、半導体回路チップ12は、歪み緩衝構造部13a及び13bによりフレキシブル基板11に弾性的に固定されており、半導体回路チップ12は、フレキシブル基板11が屈曲しても、それに関係なく、緩衝構造部13a及び13bによりフレキシブル基板11から間隔dだけ浮いた状態でほぼ静止しているため、フレキシブル基板11の屈曲が半導体回路チップ12に歪みとして伝達されることを大幅に低減できる。   In addition, the strain buffering structures 13 a and 13 b have two opposing end portions of the semiconductor circuit chip 12 and the flexible substrate 11 with a gap d between the bottom surface of the semiconductor circuit chip 12 and the top surface of the flexible substrate 11. Are separately fixed between the two opposing ends. Therefore, the semiconductor circuit chip 12 is elastically fixed to the flexible substrate 11 by the strain buffering structures 13a and 13b, and the semiconductor circuit chip 12 is not affected by the bending of the flexible substrate 11, regardless of whether the flexible structure 11 is bent. 13a and 13b are substantially stationary with a distance d from the flexible substrate 11, and the bending of the flexible substrate 11 can be greatly reduced from being transmitted to the semiconductor circuit chip 12 as distortion.

また、歪み緩衝構造部13a及び13bは、表面に形成された配線膜の一端が半導体回路チップ12の固定した端部を介して半導体回路チップ12の端子に電気的に接続され、配線膜の他端がフレキシブル基板11の表面のフレキシブル配線膜に電気的に接続されている。すなわち、歪み緩衝構造部13a及び13bは、半導体回路チップ12の端部のみをフレキシブル基板11から浮いた状態で弾性的に固定支持すると共に、半導体回路チップ12とフレキシブル基板11との間を電気的に接続する。なお、歪み緩衝構造部13a及び13bにより端部が固定された半導体回路チップ12の底面とフレキシブル基板11の上面との間の間隔dの値は、使用用途などに応じて適宜決定される設計事項である。   In addition, the strain buffering structures 13a and 13b are configured such that one end of the wiring film formed on the surface is electrically connected to the terminal of the semiconductor circuit chip 12 via the fixed end of the semiconductor circuit chip 12, and the other of the wiring film The end is electrically connected to the flexible wiring film on the surface of the flexible substrate 11. That is, the strain buffering structures 13 a and 13 b elastically fix and support only the end of the semiconductor circuit chip 12 while floating from the flexible substrate 11, and electrically connect the semiconductor circuit chip 12 and the flexible substrate 11. Connect to. It should be noted that the value of the distance d between the bottom surface of the semiconductor circuit chip 12 whose ends are fixed by the strain buffer structure portions 13a and 13b and the top surface of the flexible substrate 11 is a design matter that is appropriately determined according to the use application. It is.

次に、本実施形態の電子デバイス10の製造方法について説明する。
図2(A1)〜(G1)及び(A2)〜(G2)は、本発明に係る電子デバイスの第1の実施形態の製造方法を説明する各製造工程時の素子平面図及び素子断面図を示す。同図中、図1と同一構成部分には同一符号を付してある。なお、図2(C2)〜(G2)は、図2(C1)〜(G1)の一点鎖線に沿う断面図を示す。本実施形態の製造方法は、SOI基板集積型の製造方法で、まず、図2(A1)の平面図及び同図(A2)の断面図に示すように、シリコン基板21、シリコン酸化膜層22及び表層シリコン層23が積層されたSOI基板20を用意する。表層シリコン層23はシリコン基板21に比し極薄の厚さである。続いて、図2(B1)の平面図及び(B2)の断面図に示すように、表層シリコン層23の中央位置に、公知の方法で半導体信号処理回路や無線通信回路などの電子回路を集積回路(IC)化した半導体回路チップ12を形成する。半導体回路チップ12の端子は表層シリコン層23の表面に形成される。
Next, a method for manufacturing the electronic device 10 of the present embodiment will be described.
2 (A1) to (G1) and (A2) to (G2) are an element plan view and an element cross-sectional view at each manufacturing step for explaining the manufacturing method of the first embodiment of the electronic device according to the present invention. Show. In the figure, the same components as those in FIG. 2C2 to 2G2 are cross-sectional views taken along one-dot chain lines in FIGS. 2C1 to 2G1. The manufacturing method of this embodiment is an SOI substrate integrated manufacturing method. First, as shown in the plan view of FIG. 2A1 and the cross-sectional view of FIG. 2A2, the silicon substrate 21 and the silicon oxide film layer 22 are manufactured. And an SOI substrate 20 on which the surface silicon layer 23 is laminated. The surface silicon layer 23 is extremely thin compared to the silicon substrate 21. Subsequently, as shown in the plan view of FIG. 2B1 and the cross-sectional view of FIG. 2B2, electronic circuits such as a semiconductor signal processing circuit and a wireless communication circuit are integrated at a central position of the surface silicon layer 23 by a known method. A semiconductor circuit chip 12 formed into a circuit (IC) is formed. The terminals of the semiconductor circuit chip 12 are formed on the surface of the surface silicon layer 23.

次に、図2(C1)の平面図及び(C2)の断面図に示すように、表層シリコン層23の表面に導電膜を成膜した後、その導電膜に対しフォトリソグラフィ及びエッチングなどの公知技術を適用して一端が半導体回路チップ12の端子に接続され、他端が表層シリコン層23の端部付近に位置するような平面形状がジグザグ状の配線膜24a及び24bをパターニング形成する。続いて、図2(D1)の平面図及び(D2)の断面図に示すように、シリコン基板21の裏側から深掘りRIE(DRIE;Deep Reactive Ion Etching)により、シリコン基板21及びシリコン酸化膜層22の長手方向の端部と半導体回路チップ12を残し、かつ、ジグザグ状の配線膜24a及び24bの下側の表層シリコン層23を極薄く残し、それ以外を除去する。   Next, as shown in the plan view of FIG. 2 (C1) and the cross-sectional view of (C2), after forming a conductive film on the surface of the surface silicon layer 23, photolithography, etching and the like are performed on the conductive film. By applying the technique, the wiring films 24a and 24b having a zigzag planar shape with one end connected to the terminal of the semiconductor circuit chip 12 and the other end located near the end of the surface silicon layer 23 are patterned. Next, as shown in the plan view of FIG. 2 (D1) and the cross-sectional view of (D2), the silicon substrate 21 and the silicon oxide film layer are formed by deep RIE (DRIE) from the back side of the silicon substrate 21. The end portion 22 in the longitudinal direction and the semiconductor circuit chip 12 are left, and the surface silicon layer 23 below the zigzag wiring films 24a and 24b is left extremely thin, and the others are removed.

このようにして、公知のMEMS(Micro Electro Mechanical Systems)デバイスの作製方法と同様の工程を経て、シリコン基板21が21’で、シリコン酸化膜層22が22’で、表層シリコン層23が23’でそれぞれ示すように大部分が除去され、一部のみが残された凹部25が形成されると共に、表層シリコン層23’上にジグザグ状の配線膜24a及び24bが形成され、かつ、半導体回路チップ12が極薄に形成された構造体が製造される。   In this way, through the same process as a known MEMS (Micro Electro Mechanical Systems) device manufacturing method, the silicon substrate 21 is 21 ', the silicon oxide film layer 22 is 22', and the surface silicon layer 23 is 23 '. As shown in FIG. 6, a recess 25 is formed in which most is removed and only a part is left, zigzag wiring films 24 a and 24 b are formed on the surface silicon layer 23 ′, and a semiconductor circuit chip A structure in which 12 is formed extremely thin is manufactured.

続いて、ポリジメチルシロキサン(PDMS)などの粘着材を上記構造体の上部に粘着し、その粘着状態を保ったまま粘着材を引き上げると、上記構造体は厚さが厚い長手方向の両端部分で切断されて、ジグザグ状の配線膜24a及び24bが表面に形成され、かつ、半導体回路チップ12が形成された表層シリコン層23’が粘着材と共に引き上げられる。すなわち、図2(E1)の平面図及び(E2)の断面図に示すように、上記構造体の両端部分以外のジグザグ状の配線膜24a及び24bが表面に形成され、かつ、半導体回路チップ12が形成された表層シリコン層23’が、シリコン基板21’及びシリコン酸化膜層22’から剥離される。なお、この剥離は粘着材ではなく、ピンセットを用いて行ってもよい。このようにして、図2(E1)の平面図及び(E2)の断面図に示すように、半導体回路チップ12の対向する両側に、表層シリコン層23’とジグザグ状の配線膜24a及び24bとからなり、一端が半導体回路チップ12の端子に接続された歪緩衝構造部13a及び13bが形成される。   Subsequently, when an adhesive material such as polydimethylsiloxane (PDMS) is adhered to the upper part of the structure, and the adhesive material is pulled up while maintaining the adhesive state, the structure has a thick thickness at both end portions in the longitudinal direction. By cutting, zigzag wiring films 24a and 24b are formed on the surface, and the surface silicon layer 23 ′ on which the semiconductor circuit chip 12 is formed is pulled up together with the adhesive. That is, as shown in the plan view of FIG. 2 (E1) and the cross-sectional view of (E2), zigzag wiring films 24a and 24b other than both end portions of the structure are formed on the surface, and the semiconductor circuit chip 12 is formed. The surface silicon layer 23 ′ on which is formed is peeled from the silicon substrate 21 ′ and the silicon oxide film layer 22 ′. In addition, you may perform this peeling not using an adhesive material but using tweezers. In this way, as shown in the plan view of FIG. 2 (E1) and the cross-sectional view of (E2), the surface silicon layer 23 ′ and the zigzag wiring films 24a and 24b are formed on the opposite sides of the semiconductor circuit chip 12. The strain buffering structure portions 13a and 13b having one end connected to the terminal of the semiconductor circuit chip 12 are formed.

次に、表面にフレキシブル配線膜26a、26bやフレキシブルセンサ及びフレキシブルバッテリなど(図示せず)が形成されると共に、表面の所定位置に所定高さのプラスチックなどの絶縁体製のスペーサ27a及び27bが離間して形成されたフレキシブル基板11が用意される。フレキシブル基板11の材質は、例えばポリウレタン系やポリエステル系の伸縮性を有する樹脂である。そして、図2(F1)の平面図及び(F2)の断面図に示すように、フレキシブル基板11上にスペーサ27a、27bを介して上記の半導体回路チップ12及び歪み緩衝構造部13a、13bからなる主構造体が実装される。   Next, flexible wiring films 26a and 26b, a flexible sensor, a flexible battery, and the like (not shown) are formed on the surface, and spacers 27a and 27b made of an insulator such as plastic having a predetermined height are formed at predetermined positions on the surface. A flexible substrate 11 formed separately is prepared. The material of the flexible substrate 11 is, for example, a polyurethane-based or polyester-based stretchable resin. As shown in the plan view of FIG. 2 (F1) and the cross-sectional view of (F2), the semiconductor circuit chip 12 and the strain buffer structure portions 13a and 13b are formed on the flexible substrate 11 via spacers 27a and 27b. The main structure is implemented.

ここで、スペーサ27a、27bは、表層シリコン層23’の長手方向の両端部の裏面位置に対応して設けられており、また、主構造体のフレキシブル基板12上への実装は、スペーサ27a、27bと表層シリコン層23’の長手方向の両端部の裏面との間でのみ公知の方法で固着される。したがって、それぞれ歪み緩衝構造部13a及び13bの長手方向の両端部の一方の端部に接続されている半導体回路チップ12は、歪み緩衝構造部13a及び13bの長手方向の両端部の他方の端部でのみスペーサ27a、27bを介してフレキシブル基板11に、スペーサ27a及び27bの高さ分だけ浮いた状態で固定される。すなわち、半導体回路チップ12は、歪み緩衝構造部13a及び13bによりフレキシブル基板11に対して浮いた状態で弾性的に固定・支持される。   Here, the spacers 27a and 27b are provided corresponding to the positions of the back surfaces of both end portions in the longitudinal direction of the surface silicon layer 23 ′, and the mounting of the main structure on the flexible substrate 12 is performed by using the spacers 27a and 27b. It adheres by a well-known method only between 27b and the back surface of the both ends of the longitudinal direction of surface layer silicon layer 23 '. Accordingly, the semiconductor circuit chip 12 connected to one end of both ends in the longitudinal direction of the strain buffering structures 13a and 13b is connected to the other end of both ends in the longitudinal direction of the strain buffering structures 13a and 13b. In this case, it is fixed to the flexible substrate 11 via the spacers 27a and 27b in a state where it floats by the height of the spacers 27a and 27b. That is, the semiconductor circuit chip 12 is elastically fixed and supported in a state where it is floated with respect to the flexible substrate 11 by the strain buffering structures 13a and 13b.

そして、最後に、図2(G1)の平面図及び(G2)の断面図に示すように、フレキシブル基板11に形成されているフレキシブル配線膜26a、26bの電極パッドとジグザグ状の配線膜24a、24bの端部との間を、スクリーン印刷などにより導電性ペースト28a、28bを塗布して電気的に接続し、電子デバイス10の製造が終了する。   Finally, as shown in the plan view of FIG. 2 (G1) and the cross-sectional view of (G2), the electrode pads of the flexible wiring films 26a and 26b formed on the flexible substrate 11 and the zigzag wiring film 24a, The conductive paste 28a, 28b is applied and electrically connected between the end portions of 24b by screen printing or the like, and the manufacture of the electronic device 10 is completed.

このようにして製造された本実施形態の電子デバイス10によれば、極薄の半導体回路チップ12をフレキシブル基板11に対して浮いた状態で固定する歪緩衝構造部13a及び13bは、半導体回路チップ12の両端部のみを固定するとともに、平面形状がジグザグ状であるため半導体回路チップ12を弾性的に固定する。このため、フレキシブル基板11が屈曲しても半導体回路チップ12はほぼ静止しており、半導体回路チップ12に歪みとして伝達されることは殆どない。その結果、本実施形態の電子デバイス10を例えば衣類型ウェアラブルデバイスに使用した場合、衣類型ウェアラブルが伸長したり曲がったりしても、半導体回路チップ12がフレキシブル基板11の屈曲に殆ど影響されることなく正確な生体情報の検出及びそれに基づく所期の特性を得ることができ、また極薄の半導体回路チップ12自体が破断することを防止できる。   According to the electronic device 10 of the present embodiment manufactured as described above, the strain buffer structure portions 13a and 13b for fixing the ultrathin semiconductor circuit chip 12 in a floating state with respect to the flexible substrate 11 include the semiconductor circuit chip. 12 is fixed at both ends, and the semiconductor circuit chip 12 is elastically fixed because the planar shape is a zigzag shape. For this reason, even if the flexible substrate 11 is bent, the semiconductor circuit chip 12 is almost stationary and is hardly transmitted as distortion to the semiconductor circuit chip 12. As a result, when the electronic device 10 of the present embodiment is used for, for example, a clothing-type wearable device, the semiconductor circuit chip 12 is almost affected by the bending of the flexible substrate 11 even if the clothing-type wearable is stretched or bent. In addition, accurate biological information detection and desired characteristics based thereon can be obtained, and the ultrathin semiconductor circuit chip 12 itself can be prevented from breaking.

(第2の実施形態)
次に、本発明に係る電子デバイスの第2の実施形態について図面と共に説明する。
図3(A1)〜(D1)及び(A2)〜(D2)は、本発明に係る電子デバイスの第2の実施形態の製造方法(その1)を説明する各製造工程時の素子平面図及び素子断面図、図4(A1)〜(D1)及び(A2)〜(D2)は、本発明に係る電子デバイスの第2の実施形態の製造方法(その2)を説明する各製造工程時の素子平面図及び素子断面図を示す。なお、図3(B2)〜(D2)は、同図(B1)〜(D1)中の一点鎖線に沿う断面図を示す。本実施形態の製造方法は、フレキシブル基板加工型の製造方法で、本実施形態の電子デバイス30は、図3及び図4の両方の製造工程により最終的に図3(D1)の平面図及び図3(D2)の断面図に示すように、配線膜32a及び32bが表面に形成された歪み緩衝構造部を有するように加工処理されたフレキシブル基板37と、極薄の半導体回路チップ40とよりなる構造に製造される。
(Second Embodiment)
Next, a second embodiment of the electronic device according to the present invention will be described with reference to the drawings.
3 (A1) to (D1) and (A2) to (D2) are element plan views at the time of each manufacturing process for explaining the manufacturing method (part 1) of the second embodiment of the electronic device according to the present invention. FIG. 4 (A1) to (D1) and (A2) to (D2) are cross-sectional views of the element, illustrating the manufacturing method (part 2) of the second embodiment of the electronic device according to the present invention. An element plan view and an element cross-sectional view are shown. 3 (B2) to (D2) are cross-sectional views taken along one-dot chain lines in FIGS. 3 (B1) to (D1). The manufacturing method of the present embodiment is a method for manufacturing a flexible substrate processing mold, and the electronic device 30 of the present embodiment is finally subjected to the manufacturing process of both FIG. 3 and FIG. 3 (D2), the wiring film 32a and 32b are formed of a flexible substrate 37 processed so as to have a strain buffer structure formed on the surface, and an ultrathin semiconductor circuit chip 40. Manufactured to structure.

まず、図3(A1)の平面図及び同図(A2)の断面図に示す加工処理前のフレキシブル基板31を用意する。ただし、このフレキシブル基板31の表面には、既にフレキシブル配線膜、フレキシブルセンサ、フレキシブルバッテリなどが形成されている。次に、このフレキシブル基板31の表面に導電膜を成膜した後、その導電膜に対しフォトリソグラフィ及びエッチングなどの公知技術を適用して、図3(B1)の平面図及び(B2)の断面図に示すように、中央の所定サイズの領域に対して、長手方向の各端部から平面がジグザグ形状の配線膜32a及び32bと、複数の電極パッド33a及び33bとをそれぞれパターニング形成する。配線膜32a及び32bのフレキシブル基板31の側縁部側の端部は、フレキシブル基板31のフレキシブル配線膜に接続されている。上記中央の所定サイズの領域は、後に半導体回路チップを搭載することを想定したサイズの領域であり、その領域内の複数の電極パッド33a、33bが配線膜32a、32bの端部に接続されている。   First, the flexible substrate 31 before processing shown in the plan view of FIG. 3A1 and the cross-sectional view of FIG. However, a flexible wiring film, a flexible sensor, a flexible battery, and the like are already formed on the surface of the flexible substrate 31. Next, after forming a conductive film on the surface of the flexible substrate 31, a known technique such as photolithography and etching is applied to the conductive film, and a plan view of FIG. 3 (B1) and a cross section of (B2). As shown in the figure, wiring films 32a and 32b having a zigzag plane from each end in the longitudinal direction and a plurality of electrode pads 33a and 33b are formed by patterning in a central area of a predetermined size. The ends of the wiring films 32 a and 32 b on the side edge side of the flexible substrate 31 are connected to the flexible wiring film of the flexible substrate 31. The central region having a predetermined size is a region assuming that a semiconductor circuit chip will be mounted later, and a plurality of electrode pads 33a and 33b in the region are connected to end portions of the wiring films 32a and 32b. Yes.

続いて、図3(C1)の平面図及び(C2)の断面図に示すように、上記中央の所定サイズの領域内に設けられた半導体回路チップの搭載用矩形領域34と、矩形領域34の対向する2つの辺の各中央部と、フレキシブル基板31の側縁部に沿う四角枠35との間を平面がジグザグ形状の2つの配線膜32a及び32bでそれぞれ接続する形状の基板部分を残した開口部36を、例えばレーザー加工装置を用いて開口する。このようにフレキシブル基板31は開口部36を有するように加工処理されてフレキシブル基板37となる。この加工処理後のフレキシブル基板37の、配線膜32a及び32bが表面に形成されたジグザグ状形成部分は歪み緩衝構造部を構成する。   Subsequently, as shown in the plan view of FIG. 3 (C1) and the cross-sectional view of (C2), the semiconductor circuit chip mounting rectangular area 34 provided in the central area of the predetermined size, and the rectangular area 34 A substrate portion having a shape in which two wiring films 32a and 32b whose planes are zigzag-shaped between the central portions of the two opposing sides and the rectangular frame 35 along the side edge portion of the flexible substrate 31 is left. The opening 36 is opened using, for example, a laser processing apparatus. Thus, the flexible substrate 31 is processed so as to have the opening 36 to become the flexible substrate 37. The zigzag-shaped portion of the flexible substrate 37 after the processing, on which the wiring films 32a and 32b are formed, constitutes a strain buffering structure.

一方、図3の製造工程とは別に、図4(A1)の平面図及び(A2)の断面図に示すシリコン基板39を用意し、そのシリコン基板39に図4(B1)の平面図及び(B2)の断面図に示すように、極薄の半導体回路チップ40を公知の方法で作製する。半導体回路チップ40は、半導体信号処理回路(マイコン含む)や無線通信回路などの電子回路の半導体集積回路(IC)を内蔵するICチップである。半導体回路チップ40の表面には、接続用端子である電極パッド41a及び41bが形成される。   On the other hand, a silicon substrate 39 shown in the plan view of FIG. 4 (A1) and the cross-sectional view of (A2) is prepared separately from the manufacturing process of FIG. 3, and the plan view of FIG. As shown in the sectional view of B2), an extremely thin semiconductor circuit chip 40 is manufactured by a known method. The semiconductor circuit chip 40 is an IC chip in which a semiconductor integrated circuit (IC) such as a semiconductor signal processing circuit (including a microcomputer) or a wireless communication circuit is built. On the surface of the semiconductor circuit chip 40, electrode pads 41a and 41b which are connection terminals are formed.

続いて、図4(C1)の平面図及び(C2)の断面図に39’で示すように、DRIEなどの公知のエッチング方法を適用してシリコン基板39の厚さを半導体回路チップ40を残して薄化処理する。続いて、図4(D1)の平面図及び(D2)の断面図に示すように、薄化処理したシリコン基板39’を更に半導体回路チップ40を残して、その周辺部分を除去するダイシング処理をレーザーを用いて行う。これにより、シリコン基板39’から極薄の半導体回路チップ40が切り出される。ダイシング処理後のシリコン基板42は半導体回路チップ40の側面のみを覆う。   Subsequently, as shown by 39 ′ in the plan view of FIG. 4 (C1) and the cross-sectional view of (C2), a known etching method such as DRIE is applied to leave the thickness of the silicon substrate 39 to leave the semiconductor circuit chip 40. And thinning. Subsequently, as shown in the plan view of FIG. 4D1 and the cross-sectional view of FIG. 4D2, a dicing process is performed to remove the peripheral portion of the thinned silicon substrate 39 ′ while leaving the semiconductor circuit chip 40. Perform using a laser. Thereby, an extremely thin semiconductor circuit chip 40 is cut out from the silicon substrate 39 '. The silicon substrate 42 after the dicing process covers only the side surface of the semiconductor circuit chip 40.

そして、図3(C1)の平面図及び(C2)の断面図に示したフレキシブル基板37の表面の矩形領域34に、図4の製造工程により得られた極薄の半導体回路チップ40が、図3(D1)の平面図及び(D2)の断面図に示すように、フェースダウンでボンディングされる。このボンディングは、フレキシブル基板37の表面の電極パッド33a、33bと半導体回路チップ40の端子である電極バッド41a、41bとが接合されるように、アライメントマークを設けて顕微鏡などで観察しながら微小な位置調整を行った後実行される。これにより、本実施形態の電子デバイス30が製造される。   Then, in the rectangular region 34 on the surface of the flexible substrate 37 shown in the plan view of FIG. 3 (C1) and the cross-sectional view of (C2), the ultrathin semiconductor circuit chip 40 obtained by the manufacturing process of FIG. 3 As shown in the plan view of (D1) and the sectional view of (D2), bonding is performed face down. This bonding is performed by providing an alignment mark and observing with a microscope or the like so that the electrode pads 33a and 33b on the surface of the flexible substrate 37 and the electrode pads 41a and 41b which are terminals of the semiconductor circuit chip 40 are bonded. Executed after position adjustment. Thereby, the electronic device 30 of this embodiment is manufactured.

このようにして製造された本実施形態の電子デバイス30によれば、フレキシブル基板37の配線膜32a及び32bが表面に形成されたジグザグ状形成部分は歪み緩衝構造部を構成し、一端が四角枠35上のフレキシブル配線膜に接続されると共に固定されており、他端が半導体回路チップ40の端部の電極パッドに接続されると共に、半導体回路チップ40をフレキシブル基板37の表面に接しないように浮いた状態で弾性的に固定する。このため、フレキシブル基板37が屈曲しても半導体回路チップ40はほぼ静止しており、半導体回路チップ40に歪みとして伝達されることは殆どない。その結果、本実施形態の電子デバイス30を例えば衣類型ウェアラブルデバイスに使用した場合、衣類型ウェアラブルが伸長したり曲がったりしても、半導体回路チップ40がフレキシブル基板37の屈曲に左右されない正確な生体情報の検出及びそれに基づく所期の特性を得ることができ、また極薄の半導体回路チップ40自体が破断することを防止できる。   According to the electronic device 30 of the present embodiment manufactured in this way, the zigzag-shaped formation portion on which the wiring films 32a and 32b of the flexible substrate 37 are formed constitutes a strain buffering structure portion, and one end is a square frame. The other end is connected to the electrode pad at the end of the semiconductor circuit chip 40, and the semiconductor circuit chip 40 is not in contact with the surface of the flexible substrate 37. Elastically fixed in a floating state. For this reason, even if the flexible substrate 37 is bent, the semiconductor circuit chip 40 is almost stationary and is hardly transmitted to the semiconductor circuit chip 40 as distortion. As a result, when the electronic device 30 of the present embodiment is used for, for example, a clothing-type wearable device, an accurate living body in which the semiconductor circuit chip 40 is not affected by the bending of the flexible substrate 37 even if the clothing-type wearable is stretched or bent. Information detection and desired characteristics based thereon can be obtained, and the ultrathin semiconductor circuit chip 40 itself can be prevented from breaking.

(第3の実施形態)
次に、本発明に係る電子デバイスの第3の実施形態について図面と共に説明する。
図5(A1)〜(D1)及び(A2)〜(D2)は、本発明に係る電子デバイスの第3の実施形態の製造方法(その1)を、図6(A1)〜(D1)及び(A2)〜(D2)は、本発明に係る電子デバイスの第3の実施形態の製造方法(その2)を、図7(A1)〜(C1)及び(A2)〜(C2)は、本発明に係る電子デバイスの第3の実施形態の製造方法(その3)を、それぞれ説明する各製造工程時の素子平面図及び素子断面図を示す。なお、図5(B2)〜(D2)は、図5(B1)〜(D1)中の一点鎖線に沿う断面図、図7(A2)〜(C2)は、図7(A1)〜(C1)中の一点鎖線に沿う断面図を示す。本実施形態の製造方法は、弾性体基板接合型の製造方法で、前述したSOI基板集積型とフレキシブル基板加工型の中間的な製造方法である。本実施形態で製造される電子デバイス50は、図5乃至図7の製造工程により最終的に図7(C1)の平面図及び図7(C2)の断面図に示すように、歪み緩衝構造部を有するように加工処理されたフレキシブル基板64と、極薄の半導体回路チップ60と、表面に配線膜52a及び52bが形成された歪み緩衝構造部とよりなる構造である。
(Third embodiment)
Next, a third embodiment of the electronic device according to the present invention will be described with reference to the drawings.
5 (A1) to (D1) and (A2) to (D2) show a manufacturing method (No. 1) of the third embodiment of the electronic device according to the present invention. (A2) to (D2) show the manufacturing method (No. 2) of the third embodiment of the electronic device according to the present invention. FIGS. 7 (A1) to (C1) and (A2) to (C2) show the present method. The manufacturing method (the 3) of 3rd Embodiment of the electronic device which concerns on invention is shown by the element top view at the time of each manufacturing process which each demonstrates, and element sectional drawing. 5 (B2) to (D2) are cross-sectional views taken along one-dot chain lines in FIGS. 5 (B1) to (D1), and FIGS. 7 (A2) to (C2) are FIGS. 7 (A1) to (C1). ) Is a cross-sectional view taken along one-dot chain line. The manufacturing method of the present embodiment is an elastic substrate bonding type manufacturing method, which is an intermediate manufacturing method between the above-described SOI substrate integrated type and flexible substrate processing type. As shown in the plan view of FIG. 7 (C1) and the cross-sectional view of FIG. 7 (C2), the electronic device 50 manufactured in the present embodiment is finally subjected to the strain buffering structure portion by the manufacturing process of FIGS. The structure includes a flexible substrate 64 processed so as to have an ultrathin semiconductor circuit chip 60, and a strain buffering structure portion on which wiring films 52a and 52b are formed.

次に、本実施形態の製造方法について図5乃至図7と共に説明する。まず、図5(A1)の平面図及び同図(A2)の断面図に示す弾性体基板51を用意する。弾性体基板51は、ポリウレタン系あるいはポリエステル系の柔軟性のある樹脂からなる第2のフレキシブル基板で、本実施形態の電子デバイス50を構成する後述する第1のフレキシブル基板64と材質及び伸長率は同様であるが、その伸長率は第1のフレキシブル基板64とやや大きくてもよい(若干剛性があってもよい)。ただし、弾性体基板51にはフレキシブル配線膜やフレキシブルバッテリなどは形成されていない。   Next, the manufacturing method of this embodiment is demonstrated with FIG. 5 thru | or FIG. First, an elastic substrate 51 shown in the plan view of FIG. 5A1 and the cross-sectional view of FIG. The elastic substrate 51 is a second flexible substrate made of a polyurethane-based or polyester-based flexible resin. The elastic substrate 51 is made up of a material and an elongation rate of the first flexible substrate 64, which will be described later, constituting the electronic device 50 of the present embodiment. Although the same, the elongation ratio may be slightly larger than the first flexible substrate 64 (may be slightly rigid). However, a flexible wiring film or a flexible battery is not formed on the elastic substrate 51.

続いて、弾性体基板51の表面に導電膜を成膜した後、その導電膜に対しフォトリソグラフィ及びエッチングなどの公知技術を適用して、図5(B1)の平面図及び(B2)の断面図に示すように、中央の所定サイズの領域に対して、長手方向の各端部から平面がジグザグ形状の配線膜52a及び52bと、複数の電極パッド53a及び53bとをそれぞれパターニング形成する。上記中央の所定サイズの領域は、後に半導体回路チップを搭載することを想定したサイズの領域であり、その領域内に複数の電極パッド53a、53bが形成され、配線膜52a、52bの端部に接続されている。   Subsequently, after a conductive film is formed on the surface of the elastic substrate 51, a known technique such as photolithography and etching is applied to the conductive film, and a plan view of FIG. 5B1 and a cross section of FIG. As shown in the figure, wiring films 52a and 52b having a zigzag plane from each end in the longitudinal direction and a plurality of electrode pads 53a and 53b are formed by patterning with respect to an area of a predetermined size in the center. The central region having a predetermined size is a region that is supposed to be mounted with a semiconductor circuit chip later. A plurality of electrode pads 53a and 53b are formed in the region, and the end portions of the wiring films 52a and 52b are formed. It is connected.

続いて、図5(C1)の平面図及び(C2)の断面図に示すように、上記中央の所定サイズの領域内に設けられた半導体回路チップの搭載用矩形領域54と、矩形領域54の対向する2つの辺の各中央部と、弾性体基板51の側縁部に沿う四角枠55との間を平面がジグザグ形状の2つの配線膜52a及び52bでそれぞれ接続する形状の基板部分を残した開口部56を、例えばレーザー加工装置を用いて開口する。このように弾性体基板51は開口部56を有するように加工処理されて弾性体基板57となる。この加工処理後の弾性体基板57の、配線膜52a及び52bが表面に形成されたジグザグ状形成部分は歪み緩衝構造部を構成する。   Subsequently, as shown in the plan view of FIG. 5 (C1) and the cross-sectional view of (C2), the semiconductor circuit chip mounting rectangular area 54 provided in the central area of the predetermined size, and the rectangular area 54 A substrate portion having a shape in which the two zigzag wiring planes 52a and 52b are respectively connected between the central portions of the two opposing sides and the rectangular frame 55 along the side edge portion of the elastic substrate 51 is left. The opened opening 56 is opened using, for example, a laser processing apparatus. Thus, the elastic substrate 51 is processed so as to have the opening 56 to become an elastic substrate 57. The zigzag-shaped formed portion of the processed elastic substrate 57 on which the wiring films 52a and 52b are formed constitutes a strain buffer structure.

続いて、図5(D1)の平面図及び(D2)の断面図に示すように、加工処理後の弾性体基板57の四角枠55から、粘着剤を用いてあるいはピンセットを用いて、矩形領域54を、配線膜52a及び52bが表面に形成された平面がジグザグ形状の2つの基板部分でそれぞれ接続する形状の構造体58が剥離される。   Subsequently, as shown in the plan view of FIG. 5 (D1) and the cross-sectional view of (D2), from the rectangular frame 55 of the elastic substrate 57 after the processing, a rectangular region using an adhesive or tweezers. 54, the structure 58 having a shape in which the plane on which the wiring films 52a and 52b are formed is connected by two zigzag substrate portions is peeled off.

一方、図5の製造工程とは別に、図6(A1)の平面図及び(A2)の断面図に示すシリコン基板59を用意し、そのシリコン基板59に図6(B1)の平面図及び(B2)の断面図に示すように、極薄の半導体回路チップ60を公知の方法で作製する。半導体回路チップ60は、半導体信号処理回路(マイコン含む)や無線通信回路などの電子回路の半導体集積回路(IC)を内蔵するICチップである。半導体回路チップ60の表面には、接続用端子である電極パッド61a及び61bが形成される。   On the other hand, separately from the manufacturing process of FIG. 5, a silicon substrate 59 shown in the plan view of FIG. 6A1 and the cross-sectional view of FIG. 6A2 is prepared, and the plan view of FIG. As shown in the sectional view of B2), an extremely thin semiconductor circuit chip 60 is manufactured by a known method. The semiconductor circuit chip 60 is an IC chip that incorporates a semiconductor integrated circuit (IC) of an electronic circuit such as a semiconductor signal processing circuit (including a microcomputer) or a wireless communication circuit. On the surface of the semiconductor circuit chip 60, electrode pads 61a and 61b which are connection terminals are formed.

続いて、図6(C1)の平面図及び(C2)の断面図に59’で示すように、DRIEなどの公知のエッチング方法を適用してシリコン基板59の厚さを半導体回路チップ60を残して薄化処理する。続いて、図6(D1)の平面図及び(D2)の断面図に示すように、薄化処理したシリコン基板59’を更に半導体回路チップ60を残して、その周辺部分を除去するダイシング処理をレーザーを用いて行う。これにより、シリコン基板59’から極薄の半導体回路チップ60が切り出される。ダイシング処理後のシリコン基板62は半導体回路チップ60の側面のみを覆う。   Subsequently, as shown by 59 ′ in the plan view of FIG. 6C1 and the cross-sectional view of FIG. 2C2, a known etching method such as DRIE is applied to leave the thickness of the silicon substrate 59 to leave the semiconductor circuit chip 60. And thinning. Subsequently, as shown in the plan view of FIG. 6D1 and the cross-sectional view of FIG. 6D2, a dicing process is performed to remove the peripheral portion of the thinned silicon substrate 59 ′ while leaving the semiconductor circuit chip 60. Perform using a laser. Thereby, an extremely thin semiconductor circuit chip 60 is cut out from the silicon substrate 59 '. The silicon substrate 62 after the dicing process covers only the side surface of the semiconductor circuit chip 60.

そして、図5(D1)の平面図及び(D2)の断面図に示した弾性体基板57の表面の矩形領域54に、図6の製造工程により得られた極薄の半導体回路チップ60がフェースダウンでボンディングされ、図7(A1)の平面図及び(A2)の断面図に示す主構造体が作製される。このボンディングは、弾性体基板57の表面の電極パッド53a、53bと半導体回路チップ60の端子である電極バッド61a、61bとが接合されるように、アライメントマークを設けて顕微鏡などで観察しながら微小な位置調整を行った後実行される。   Then, the ultrathin semiconductor circuit chip 60 obtained by the manufacturing process of FIG. 6 is faced to the rectangular region 54 on the surface of the elastic substrate 57 shown in the plan view of FIG. 5 (D1) and the cross-sectional view of (D2). The main structure shown in the plan view of FIG. 7A1 and the cross-sectional view of FIG. This bonding is performed by providing an alignment mark and observing with a microscope or the like so that the electrode pads 53a and 53b on the surface of the elastic substrate 57 and the electrode pads 61a and 61b which are terminals of the semiconductor circuit chip 60 are bonded. It is executed after the correct position adjustment.

続いて、矩形領域54にボンディングされた半導体回路チップ60を配線膜52a及び52bが表面に形成された平面がジグザグ形状の2つの基板部分でそれぞれ接続する形状の主構造体が、図7(B1)の平面図及び(B2)の断面図に示すように、所定高さのプラスチックなどの絶縁体製のスペーサ65a及び65bを介してフレキシブル基板64に実装される。フレキシブル基板64は、表面にフレキシブル配線膜やフレキシブルセンサ及びフレキシブルバッテリなど(図示せず)が形成されると共に、表面の所定位置にスペーサ65a及び65bが離間して形成されており、その材質は例えばポリウレタン系やポリエステル系の伸縮性を有する樹脂である。   Subsequently, a main structure having a shape in which the semiconductor circuit chip 60 bonded to the rectangular region 54 is connected to each other by two substrate portions each having a zigzag shape on which the wiring films 52a and 52b are formed is illustrated in FIG. ) And a cross-sectional view of (B2), it is mounted on the flexible substrate 64 via spacers 65a and 65b made of an insulator such as plastic having a predetermined height. The flexible substrate 64 has a flexible wiring film, a flexible sensor, a flexible battery, and the like (not shown) formed on the surface, and spacers 65a and 65b are formed at predetermined positions on the surface, and the material is, for example, It is a polyurethane-based or polyester-based stretchable resin.

ここで、スペーサ65a及び65bは、主構造体の長手方向の両端部の裏面位置に対応して設けられており、また、主構造体のフレキシブル基板64上への実装は、スペーサ65a、65bとの間でのみ公知の方法で固着される。したがって、半導体回路チップ60は、配線膜52a及び52bが表面に形成された平面がジグザグ形状の2つの基板部分をそれぞれ歪み緩衝構造部とし、その2つの歪み緩衝構造部の両端部及び2つのスペーサ27a、27bのみを介して、フレキシブル基板64の表面に対してスペーサ65a及び65bの高さ分だけ浮いた状態で固定される。すなわち、半導体回路チップ60は、2つの歪み緩衝構造部によりフレキシブル基板64に対して浮いた状態で弾性的に固定・支持される。   Here, the spacers 65a and 65b are provided corresponding to the positions of the back surfaces of both ends in the longitudinal direction of the main structure, and the mounting of the main structure on the flexible substrate 64 is performed with the spacers 65a and 65b. It is fixed in a known manner only between the two. Therefore, in the semiconductor circuit chip 60, the two substrate portions each having the zigzag shape on the surface on which the wiring films 52a and 52b are formed are used as the strain buffer structure portions, respectively, and both end portions of the two strain buffer structure portions and the two spacers. It is fixed in a state where it floats by the height of the spacers 65a and 65b with respect to the surface of the flexible substrate 64 only through 27a and 27b. In other words, the semiconductor circuit chip 60 is elastically fixed and supported in a state of floating with respect to the flexible substrate 64 by the two strain buffering structures.

そして、最後に、図7(C1)の平面図及び(C2)の断面図に示すように、フレキシブル基板64に形成されているフレキシブル配線膜63a、63bとジグザグ状の配線膜52a、52bの端部との間を、スクリーン印刷などにより導電性ペースト66a、66bを塗布して電気的に接続し、電子デバイス50の製造が終了する。   Finally, as shown in the plan view of FIG. 7 (C1) and the sectional view of (C2), the ends of the flexible wiring films 63a and 63b and the zigzag wiring films 52a and 52b formed on the flexible substrate 64 are shown. The conductive pastes 66a and 66b are applied and electrically connected to each other by screen printing or the like, and the manufacture of the electronic device 50 is completed.

このようにして製造された本実施形態の電子デバイス50によれば、半導体回路チップ60をフレキシブル基板64に対して浮いた状態で固定する2つの歪緩衝構造部(構造体58中の配線膜52a、52bが表面に形成された平面ジグザグ形状基板部分)は、半導体回路チップ60の両端部のみを固定するとともに、平面形状がジグザグ状であるため半導体回路チップ60を弾性的に固定する。このため、フレキシブル基板64が屈曲しても半導体回路チップ60はほぼ静止しており、半導体回路チップ60に歪みとして伝達されることを大幅に低減できる。その結果、本実施形態の電子デバイス50を例えば衣類型ウェアラブルデバイスに使用した場合、衣類型ウェアラブルが伸長したり曲がったりしても、半導体回路チップ60がフレキシブル基板64の屈曲に殆ど影響されることなく正確な生体情報の検出及びそれに基づく所期の特性を得ることができ、また極薄の半導体回路チップ60自体が破断することを防止できる。   According to the electronic device 50 of the present embodiment manufactured as described above, the two strain buffering structures (the wiring film 52a in the structure 58) that fixes the semiconductor circuit chip 60 in a floating state with respect to the flexible substrate 64. , 52b formed on the surface of the flat zigzag substrate portion) fixes only both ends of the semiconductor circuit chip 60, and the plane shape is zigzag, so that the semiconductor circuit chip 60 is elastically fixed. For this reason, even if the flexible substrate 64 is bent, the semiconductor circuit chip 60 is substantially stationary, and transmission to the semiconductor circuit chip 60 as strain can be greatly reduced. As a result, when the electronic device 50 of the present embodiment is used for, for example, a clothing-type wearable device, the semiconductor circuit chip 60 is almost affected by the bending of the flexible substrate 64 even if the clothing-type wearable is stretched or bent. In addition, accurate biological information detection and desired characteristics based thereon can be obtained, and the ultrathin semiconductor circuit chip 60 itself can be prevented from breaking.

以上説明した第1乃至第3の実施形態の製造方法によれば、製造プロセス及び歪み緩衝構造部の材質などの違いはあるが、いずれも極薄の半導体回路チップ12、40、60の端部のみが歪み緩衝構造部により弾性的に固定されているという点、及び極薄の半導体回路チップ12、40、60が直接フレキシブル基板11、37、64と接していないという点で共通する。これにより、いずれの製造方法で作成した電子デバイス10、30、50も前述した所期の効果を得ることができる。なお、第1の実施形態のSOI基板集積型の製造方法は、半導体回路チップと歪み緩衝構造部とを同じ基板に集積化するため、一枚のウェハ(基板)に作製できる半導体回路チップの数が少ないのに対し、第2の実施形態及び第3の実施形態の製造方法では半導体回路チップを歪み緩衝構造部と異なる基板に作製するため一枚のウェハ(基板)に作製できる半導体回路チップの数を多くでき、単価を安価にできるという効果もある。半導体回路チップの単価はウェハ一枚にどれだけ組み込めるかで決まるからである。   According to the manufacturing methods of the first to third embodiments described above, although there are differences in the manufacturing process and the material of the strain buffer structure, the end portions of the ultra-thin semiconductor circuit chips 12, 40, 60 are all used. Only in that they are elastically fixed by the strain buffering structure, and that the ultrathin semiconductor circuit chips 12, 40, 60 are not in direct contact with the flexible substrates 11, 37, 64. Thereby, the electronic device 10, 30, and 50 created by any manufacturing method can obtain the expected effect mentioned above. In the SOI substrate integrated manufacturing method of the first embodiment, the number of semiconductor circuit chips that can be manufactured on a single wafer (substrate) is obtained because the semiconductor circuit chip and the strain buffer structure are integrated on the same substrate. On the other hand, in the manufacturing methods of the second embodiment and the third embodiment, the semiconductor circuit chip is manufactured on a different substrate from the strain buffer structure portion, so that the semiconductor circuit chip that can be manufactured on one wafer (substrate) is produced. There is also an effect that the number can be increased and the unit price can be reduced. This is because the unit price of the semiconductor circuit chip is determined by how much can be incorporated into one wafer.

次に、本発明に係る電子デバイスを用いたウェアラブルデバイスについて説明する。図8は、本発明に係る電子デバイスを用いたウェアラブルデバイスの一例の全体構成図を示す。同図において、ウェアラブルデバイス100は、本発明に係る電子デバイスの半導体回路チップ及び歪み緩衝構造部からなる主構造体101がフレキシブル基板102上に形成されている。主構造体101を構成する平面形状がジグザグ状の歪み緩衝構造部の一方の端部は、同じ主構造体101を構成する半導体回路チップの端部の端子に電気的に接続されるとともにフレキシブル基板102の表面に接しないように離間した状態で弾性的に固定し、他方の端部がフレキシブル基板102の表面に形成されているフレキシブル配線膜103に電気的に接続されている。また、フレキシブル基板102には、フレキシブルセンサ・バッテリ等104が形成されている。ウェアラブルデバイス100は、フレキシブル基板102上に実装された主構造体101の上面を、ポリエチレンナフタレート(PEN)やポリエチレンテレフタレート(PET)などの樹脂からなるカバーフィルム105で被覆した構造である。カバーフィルム105は保護膜として機能する。   Next, a wearable device using the electronic device according to the present invention will be described. FIG. 8 shows an overall configuration diagram of an example of a wearable device using the electronic device according to the present invention. In the figure, a wearable device 100 has a main structure 101 formed of a semiconductor circuit chip and a strain buffer structure of an electronic device according to the present invention formed on a flexible substrate 102. One end portion of the strain buffering structure portion having a zigzag planar shape constituting the main structure 101 is electrically connected to a terminal at an end portion of the semiconductor circuit chip constituting the same main structure 101 and a flexible substrate. It is elastically fixed in a separated state so as not to contact the surface of 102, and the other end is electrically connected to the flexible wiring film 103 formed on the surface of the flexible substrate 102. In addition, a flexible sensor / battery 104 or the like is formed on the flexible substrate 102. The wearable device 100 has a structure in which the upper surface of the main structure 101 mounted on the flexible substrate 102 is covered with a cover film 105 made of a resin such as polyethylene naphthalate (PEN) or polyethylene terephthalate (PET). The cover film 105 functions as a protective film.

次に、本発明に係る電子デバイスを用いたウェアラブルデバイスの使用例について説明する。図9は、本発明に係る電子デバイスを用いたウェアラブルデバイスの一例の使用例を示す図である。図9において、図8の構成の電子デバイス100は、例えばシャツ150の設定位置に装着され、シャツ150を着た人体の心拍数、呼吸その他必要な人体情報をフレキシブルセンサにより収集する衣類型ウェアラブルデバイスを構成している。このような衣類型ウェアラブルデバイスに本発明に係る電子デバイス100を用いた場合、シャツ150の伸縮に伴いフレキシブル基板(図8の102)が伸縮しても、半導体回路チップにはフレキシブル基板の伸縮が歪みとして殆ど伝達されないため、人体情報の検出が正確にできる。   Next, a usage example of a wearable device using the electronic device according to the present invention will be described. FIG. 9 is a diagram showing a usage example of an example of a wearable device using the electronic device according to the present invention. In FIG. 9, an electronic device 100 configured as shown in FIG. 8 is worn at a set position of a shirt 150, for example, and wearable wearable devices that collect heart rate, breathing and other necessary human body information of the human body wearing the shirt 150 using a flexible sensor. Is configured. When the electronic device 100 according to the present invention is used for such a wearable wearable device, even if the flexible substrate (102 in FIG. 8) expands and contracts with the expansion and contraction of the shirt 150, the semiconductor circuit chip does not expand and contract the flexible substrate. Since it is hardly transmitted as distortion, human body information can be detected accurately.

次に、前述した実施形態の電子デバイスをウェアラブルデバイスに適用した場合の概略について説明する。図10は、第1の実施形態をウェアラブルデバイスに適用した場合の概略模式的構成図、図11は、第2の実施形態をウェアラブルデバイスに適用した場合の概略模式的構成図、図12は、第3の実施形態をウェアラブルデバイスに適用した場合の概略模式的構成図を示す。図10、図11及び図12中、図2、図3及び図7と同一構成部分には同一符号を付し、その説明を省略する。第1の実施形態の電子デバイスは、図10に模式的に示すようにフレキシブル基板11の下面全面が衣料のテキスタイル160に接着されている。第2の実施形態の電子デバイスは、図11に模式的に示すようにフレキシブル基板37の端部が衣料のテキスタイル160に接着されている。ただし、フレキシブル基板37の中央の半導体回路チップ40が搭載されている領域は、テキスタイル160の表面に接着されておらず離間している。また、第3の実施形態の電子デバイスは、図12に模式的に示すようにフレキシブル基板64の下面全面が衣料のテキスタイル160に接着されている。なお、テキスタイル160は例えば伸長率1%〜10%である。   Next, an outline when the electronic device of the above-described embodiment is applied to a wearable device will be described. FIG. 10 is a schematic schematic configuration diagram when the first embodiment is applied to a wearable device, FIG. 11 is a schematic schematic configuration diagram when the second embodiment is applied to a wearable device, and FIG. The schematic model block diagram at the time of applying 3rd Embodiment to a wearable device is shown. 10, FIG. 11 and FIG. 12, the same components as those in FIG. 2, FIG. 3 and FIG. In the electronic device of the first embodiment, as shown schematically in FIG. 10, the entire lower surface of the flexible substrate 11 is bonded to a textile 160 of clothing. In the electronic device of the second embodiment, as schematically shown in FIG. 11, the end of the flexible substrate 37 is bonded to a textile 160 of clothing. However, the area where the semiconductor circuit chip 40 at the center of the flexible substrate 37 is mounted is not bonded to the surface of the textile 160 and is separated. In the electronic device of the third embodiment, the entire lower surface of the flexible substrate 64 is bonded to a clothing textile 160 as schematically shown in FIG. The textile 160 has, for example, an elongation rate of 1% to 10%.

なお、本発明は以上の実施形態に限定されるものではなく、例えば歪み緩衝構造部13a、13b等の平面形状はジグザグ状に限定されるものではなく、半導体回路チップ12、36の端部のみを弾性的に支持できる他の形状、例えば図13の(A)に示すS字状や同図(B)に示すメッシュ状であってもよい。なお、S字型の歪み緩衝構造で電子回路を保持し、フレキシブル基板で覆うことでフレキシブルな生体センサを作製する研究報告が文献(C.H.Lee,et al.,”Soft Core/Shell Packages for Stretchable Electronics”,Advanced Matrerials,(2015) pp.3698-3704)に記載されている。しかし、この手法は半導体回路チップがパッケージ化されている点と、半導体回路チップが直接フレキシブル基板に接している点とで本発明における歪み緩衝構造部とは異なる。   The present invention is not limited to the above embodiment. For example, the planar shapes of the strain buffering structures 13a and 13b are not limited to the zigzag shape, and only the end portions of the semiconductor circuit chips 12 and 36 are used. May be in other shapes, for example, an S shape shown in FIG. 13A or a mesh shape shown in FIG. In addition, there is a research report (CHLee, et al., “Soft Core / Shell Packages for Stretchable Electronics” that manufactures a flexible biosensor by holding an electronic circuit with an S-shaped strain buffer structure and covering it with a flexible substrate. "Advanced Matrerials, (2015) pp. 3698-3704). However, this method is different from the strain buffer structure portion of the present invention in that the semiconductor circuit chip is packaged and the semiconductor circuit chip is in direct contact with the flexible substrate.

また、半導体回路チップの端部を直接的に又は間接的に固定・保持する歪み緩衝構造部は2つに限定されるものではなく、複数あればよい。例えば図14に模式的に示すように半導体回路チップ170の3か所の端部をそれぞれ固定・保持する3つの歪み緩衝構造部170を有するようにしてもよい。また、図15に模式的に示すように半導体回路チップ180の4か所の端部をそれぞれ固定・保持する4つの歪み緩衝構造部190を有するようにしてもよい。更に、図16に模式的に示すように半導体回路チップ170の各辺3か所の端部をそれぞれ別々に固定・保持するメッシュ状の9つの歪み緩衝構造部200を有するようにしてもよい。   Further, the number of strain buffering structures that directly or indirectly fix and hold the end of the semiconductor circuit chip is not limited to two, and there may be a plurality of strain buffering structures. For example, as schematically shown in FIG. 14, three strain buffering structures 170 for fixing and holding the three end portions of the semiconductor circuit chip 170 may be provided. Further, as schematically shown in FIG. 15, there may be provided four strain buffering structures 190 for fixing and holding the four end portions of the semiconductor circuit chip 180. Further, as schematically shown in FIG. 16, nine mesh-shaped strain buffering structures 200 for separately fixing and holding the three end portions of each side of the semiconductor circuit chip 170 may be provided.

人間や動物などの健康モニタリングを目的とした衣類型ウェアラブルデバイスなど、フレキシブルな電子デバイスの使用可能な分野に広く応用可能である。   It can be widely applied to fields where flexible electronic devices can be used, such as clothing-type wearable devices for health monitoring of humans and animals.

10、30、50 電子デバイス
11、64、102 フレキシブル基板
12、40、60、170 半導体回路チップ
13a、13b、180、190、200 歪み緩衝構造部
20 SOI基板
21、21’、39、39’、42、59、59’ シリコン基板
22、22’ シリコン酸化膜層
23、23’ 表層シリコン層
24a、24b、32a、32b、52a、52b 配線膜
25 凹部
26a、26b、63a、63b、103 フレキシブル配線膜
27a、27b、65a、65b スペーサ
28a、28b、66a、66b 導電性ペースト
31 加工処理前のフレキシブル基板
33a、33b、41a、41b、53a、53b、61a、61b 電極パッド
34、54 矩形領域
35、55 四角枠
36、56 開口部
37 加工処理後のフレキシブル基板
51 弾性体基板(第2のフレキシブル基板)
57 加工処理後の弾性体基板
58 構造体
100 ウェアラブルデバイス
101 主構造体
104 フレキシブルセンサ・バッテリ等
150 シャツ



10, 30, 50 Electronic device 11, 64, 102 Flexible substrate 12, 40, 60, 170 Semiconductor circuit chip 13a, 13b, 180, 190, 200 Strain buffer structure 20 SOI substrate 21, 21 ′, 39, 39 ′, 42, 59, 59 'Silicon substrate 22, 22' Silicon oxide film layer 23, 23 'Surface silicon layer 24a, 24b, 32a, 32b, 52a, 52b Wiring film 25 Recess 26a, 26b, 63a, 63b, 103 Flexible wiring film 27a, 27b, 65a, 65b Spacers 28a, 28b, 66a, 66b Conductive paste 31 Flexible substrates 33a, 33b, 41a, 41b, 53a, 53b, 61a, 61b Electrode pads 34, 54 Rectangular regions 35, 55 before processing Square frame 36, 56 Opening 37 Flexible after processing Plate 51 elastic substrate (second flexible substrate)
57 Elastic substrate 58 after processing 58 Structure 100 Wearable device 101 Main structure 104 Flexible sensor, battery, etc. 150 Shirt



Claims (11)

表面に端子が形成された電子回路を内蔵する半導体回路チップと、
表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されたフレキシブル基板と、
表面に配線膜が形成された構造であり、前記半導体回路チップの前記端子に前記配線膜の一端を接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続すると共に、前記半導体回路チップの端部を前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持する構造の歪み緩衝構造部と
を備えることを特徴とする電子デバイス。
A semiconductor circuit chip containing an electronic circuit having terminals formed on the surface;
A flexible substrate having at least a flexible wiring film and a flexible sensor formed on the surface;
A wiring film is formed on the surface, one end of the wiring film is connected to the terminal of the semiconductor circuit chip, and the other end of the wiring film is connected to the flexible wiring film, and the semiconductor circuit An electronic device comprising: a strain buffering structure having a structure in which an end portion of a chip is elastically fixed and supported in a state where the semiconductor circuit chip and the flexible substrate are separated from each other.
前記歪み緩衝構造部は、
前記フレキシブル基板とは異なる極薄の基板に形成された前記半導体回路チップの側縁部と、前記極薄の基板の端部との間を別々に接続する、平面が所定形状の複数の接続用基板部分の上に前記配線膜が形成されており、前記複数の接続用基板部分の各一方の端部の上の前記配線膜の一端を前記半導体回路チップの端子に電気的に接続し、前記複数の接続用基板部分の各他方の端部のみを前記フレキシブル基板にそれぞれ前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持すると共に前記配線膜の他端を前記フレキシブル配線膜に電気的に接続した構造であることを特徴とする請求項1記載の電子デバイス。
The strain buffer structure is
A plurality of connection planes each having a predetermined shape, wherein a side edge portion of the semiconductor circuit chip formed on an ultrathin substrate different from the flexible substrate and an end portion of the ultrathin substrate are separately connected. The wiring film is formed on the substrate portion, and one end of the wiring film on one end of each of the plurality of connection substrate portions is electrically connected to a terminal of the semiconductor circuit chip, Only the other end of each of the plurality of connection substrate portions is elastically fixed and supported on the flexible substrate in a state where the semiconductor circuit chip and the flexible substrate are separated from each other, and the other end of the wiring film is connected to the flexible substrate. The electronic device according to claim 1, wherein the electronic device has a structure electrically connected to the flexible wiring film.
前記フレキシブル基板は、
前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部と基板側縁部に沿う四角枠との間を平面が所定形状の複数の接続部でそれぞれ接続する形状の基板部分を残した開口部を有するとともに、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されており、
前記歪み緩衝構造部は、
前記フレキシブル基板の前記接続部の表面に前記配線膜が形成された構造であり、前記フレキシブル基板の前記矩形領域に搭載された前記半導体回路チップを前記接続部及び前記四角枠で弾性的に固定・支持すると共に、前記配線膜の一端を前記半導体回路チップの前記端子に接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続することを特徴とする請求項1記載の電子デバイス。
The flexible substrate is
A substrate portion having a shape in which a plane is connected by a plurality of connection portions each having a predetermined shape between a rectangular region for mounting the semiconductor circuit chip and a rectangular frame along a side edge portion of the rectangular region and a substrate side edge portion is left. And at least a flexible wiring film and a flexible sensor are formed on the surface,
The strain buffer structure is
The wiring film is formed on the surface of the connection portion of the flexible substrate, and the semiconductor circuit chip mounted on the rectangular region of the flexible substrate is elastically fixed by the connection portion and the square frame. 2. The electronic device according to claim 1, wherein one end of the wiring film is connected to the terminal of the semiconductor circuit chip and the other end of the wiring film is connected to the flexible wiring film.
前記歪み緩衝構造部は、
前記フレキシブル基板、及び前記半導体回路チップが形成された極薄の基板とはそれぞれ異なる弾性体基板に形成されており、前記弾性体基板が前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部にそれぞれの一端が接続された平面が所定形状の複数の接続部とからなり、かつ、前記複数の接続部の表面に配線膜が形成された構造であり、前記配線膜の一端を前記弾性体基板の矩形領域に搭載された前記半導体回路チップの端子に電気的に接続し、かつ、前記複数の接続部の他端をスペーサを介して前記フレキシブル基板に前記半導体回路チップと離間させた状態で弾性的に固定・支持するとともに、前記2つの接続部の他端上の前記配線膜と前記フレキシブル配線膜とを前記スペーサを覆う導電性部材で電気的に接続することを特徴とする請求項1記載の電子デバイス。
The strain buffer structure is
The flexible substrate and the ultra-thin substrate on which the semiconductor circuit chip is formed are formed on different elastic substrates, and the elastic substrate has a rectangular area for mounting the semiconductor circuit chip and the rectangular area. A plane in which one end is connected to each side edge portion is composed of a plurality of connecting portions having a predetermined shape, and a wiring film is formed on the surface of the plurality of connecting portions, and one end of the wiring film is formed The semiconductor circuit chip is electrically connected to a terminal of the semiconductor circuit chip mounted on the rectangular area of the elastic substrate, and the other ends of the plurality of connection portions are separated from the semiconductor circuit chip on the flexible substrate via a spacer. The wiring film on the other end of the two connection portions and the flexible wiring film are electrically connected by a conductive member that covers the spacer. The electronic device of claim 1, wherein.
前記所定形状は、ジグザグ形状、S字形状又はメッシュ状であることを特徴とする請求項1乃至4のうちいずれか一項記載の電子デバイス。   The electronic device according to claim 1, wherein the predetermined shape is a zigzag shape, an S shape, or a mesh shape. 表面に端子が形成された電子回路を内蔵する半導体回路チップを作製する工程と、
表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されたフレキシブル基板を作製する工程と、
表面に配線膜が形成された構造の歪み緩衝構造部により、前記半導体回路チップの前記端子に前記配線膜の一端を接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続すると共に、前記半導体回路チップの端部を前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持する固定工程と
を含むことを特徴とする電子デバイスの製造方法。
Producing a semiconductor circuit chip containing an electronic circuit having terminals formed on the surface;
Producing a flexible substrate having at least a flexible wiring film and a flexible sensor formed on the surface;
The strain buffer structure having a structure in which a wiring film is formed on the surface connects one end of the wiring film to the terminal of the semiconductor circuit chip and connects the other end of the wiring film to the flexible wiring film. And a fixing step of elastically fixing and supporting an end portion of the semiconductor circuit chip in a state where the semiconductor circuit chip and the flexible substrate are separated from each other.
前記半導体回路チップを作製する工程は、前記フレキシブル基板とは異なる極薄の基板に前記半導体回路チップを作製する工程であり、
前記固定工程は、
平面が所定形状で、かつ、表面に配線膜が形成されており、前記配線膜の一端が前記半導体回路チップの前記端子にそれぞれの一端が別々に電気的に接続された複数の接続部を前記極薄の基板に形成する接続部形成工程と、
前記複数の接続部のそれぞれの前記配線膜の他端を前記フレキシブル配線膜に電気的に接続すると共に、前記複数の接続部の前記配線膜の他端が形成されている前記極薄の基板部分で、前記半導体回路チップと前記フレキシブル基板とを離間させた状態で固定する工程とからなることを特徴とする請求項6記載の電子デバイスの製造方法。
The step of producing the semiconductor circuit chip is a step of producing the semiconductor circuit chip on a very thin substrate different from the flexible substrate,
The fixing step includes
The plane is a predetermined shape, and a wiring film is formed on the surface, and a plurality of connecting portions in which one end of the wiring film is electrically connected to the terminal of the semiconductor circuit chip separately. A connecting portion forming step to be formed on an extremely thin substrate;
The ultrathin substrate portion in which the other end of the wiring film of each of the plurality of connecting portions is electrically connected to the flexible wiring film and the other end of the wiring film of the plurality of connecting portions is formed. The method of manufacturing an electronic device according to claim 6, further comprising a step of fixing the semiconductor circuit chip and the flexible substrate in a separated state.
前記接続部形成工程は、
前記半導体回路チップの前記端子に一端が別々に接続され、他端が開放とされた平面形状が前記所定形状の複数の配線膜をシリコン基板上に形成する工程と、
前記半導体回路チップ及び前記配線膜がそれぞれ形成された前記シリコン基板の裏側からエッチングにより、前記半導体回路チップを残し、かつ、前記複数の配線膜が形成されている前記シリコン基板部分を薄く残した凹部を形成する工程と、
前記凹部が形成された前記シリコン基板から、前記半導体回路チップ及び前記複数の配線膜が表面に形成された薄い前記シリコン基板部分を剥離し、前記複数の配線膜が表面に形成された薄い前記シリコン基板部分を前記極薄の基板上の複数の接続部として得る工程とよりなり、
前記半導体回路チップと前記フレキシブル基板とを離間させた状態で固定する工程は、
前記複数の配線膜の各端部の直下の前記極薄の基板部分のみを、前記フレキシブル基板の表面と離間させた状態でスペーサを介して固定する工程と、
前記フレキシブル配線膜と前記複数の配線膜の各端部とを導電性部材で電気的に接続する工程とよりなることを特徴とする請求項7記載の電子デバイスの製造方法。
The connecting portion forming step includes
Forming a plurality of wiring films having a predetermined shape on a silicon substrate, one end of which is separately connected to the terminal of the semiconductor circuit chip and the other end of which is open;
Etching from the back side of the silicon substrate on which the semiconductor circuit chip and the wiring film are formed, respectively, to leave the semiconductor circuit chip, and to form a recess in which the silicon substrate portion on which the plurality of wiring films are formed remains thin Forming a step;
The thin silicon substrate having the semiconductor circuit chip and the plurality of wiring films formed on the surface is peeled from the silicon substrate having the recesses formed thereon, and the thin silicon having the plurality of wiring films formed on the surface And a step of obtaining a substrate portion as a plurality of connecting portions on the ultra-thin substrate,
The step of fixing the semiconductor circuit chip and the flexible substrate in a separated state,
Fixing only the ultrathin substrate portion directly below each end of the plurality of wiring films via a spacer in a state of being separated from the surface of the flexible substrate;
The method of manufacturing an electronic device according to claim 7, further comprising a step of electrically connecting the flexible wiring film and each end of the plurality of wiring films with a conductive member.
前記フレキシブル基板を作製する工程は、
表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成された加工前のフレキシブル基板に対し、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部と基板側縁部に沿う四角枠との間を平面が所定形状で、かつ、表面に前記配線膜が形成されるとともに、前記配線膜の一端が前記フレキシブル配線膜にそれぞれ電気的に接続された形状の複数の接続部とを残した開口部を形成して加工処理したフレキシブル基板を作製する工程であり、
前記固定工程は、
前記加工処理したフレキシブル基板の前記矩形領域に、前記半導体回路チップの端子が前記複数の接続部のそれぞれの配線膜の他端に電気的に接続されるように前記半導体回路チップを搭載する工程を有し、前記半導体回路チップを前記複数の接続部及び前記四角枠で弾性的に固定・支持することを特徴とする請求項6記載の電子デバイスの製造方法。
The step of producing the flexible substrate includes:
With respect to the unprocessed flexible substrate having at least a flexible wiring film and a flexible sensor formed on the surface, a rectangular region for mounting the semiconductor circuit chip, a side edge of the rectangular region, and a square frame along the substrate side edge An opening that leaves a plurality of connecting portions in a shape in which the plane is a predetermined shape and the wiring film is formed on the surface, and one end of the wiring film is electrically connected to the flexible wiring film. Forming a flexible substrate processed by forming a portion,
The fixing step includes
Mounting the semiconductor circuit chip in the rectangular region of the processed flexible substrate so that a terminal of the semiconductor circuit chip is electrically connected to the other end of each wiring film of the plurality of connection portions; 7. The method of manufacturing an electronic device according to claim 6, wherein the semiconductor circuit chip is elastically fixed and supported by the plurality of connection portions and the square frame.
前記固定工程は、
前記フレキシブル基板、及び前記半導体回路チップが形成された極薄の基板とはそれぞれ異なる弾性体基板に対し、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部にそれぞれの一端が接続された平面が所定形状で、かつ、表面に配線膜が形成された複数の接続部とを形成する工程と、
前記極薄の基板に形成された前記半導体回路チップの端子が、前記複数の接続部のそれぞれの配線膜の一端に電気的に接続されるように前記半導体回路チップを前記矩形領域に搭載する工程と、
前記複数の接続部の他端をスペーサを介して前記フレキシブル基板に前記半導体回路チップと離間させた状態で弾性的に固定・支持するとともに、前記複数の接続部の他端上の前記配線膜と前記フレキシブル配線膜とを前記スペーサを覆う導電性部材で電気的に接続する工程とからなることを特徴とする請求項6記載の電子デバイスの製造方法。
The fixing step includes
The flexible substrate and the elastic substrate different from the ultra-thin substrate on which the semiconductor circuit chip is formed have a rectangular region for mounting the semiconductor circuit chip, and one end at each side edge of the rectangular region. A step of forming a plurality of connecting portions in which the connected plane has a predetermined shape and a wiring film is formed on the surface;
Mounting the semiconductor circuit chip in the rectangular region so that terminals of the semiconductor circuit chip formed on the ultra-thin substrate are electrically connected to one end of each wiring film of the plurality of connecting portions. When,
The other end of the plurality of connection portions is elastically fixed and supported in a state separated from the semiconductor circuit chip on the flexible substrate via a spacer, and the wiring film on the other end of the plurality of connection portions; The method of manufacturing an electronic device according to claim 6, further comprising a step of electrically connecting the flexible wiring film with a conductive member covering the spacer.
前記所定形状は、ジグザグ形状、S字形状又はメッシュ状であることを特徴とする請求項6乃至10のうちいずれか一項記載の電子デバイスの製造方法。
The method of manufacturing an electronic device according to claim 6, wherein the predetermined shape is a zigzag shape, an S shape, or a mesh shape.
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