JP2017142501A - Liquid crystal display device and inspection method of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device achieving reduction in size of a pixel constituting the device and allowing accurate inspection of pixels, and a pixel inspection method of the liquid crystal display device.SOLUTION: In a pixel 12A, a data output to a column data line d1 is sampled by a switch SW11 and written in SM121. Data are stored in SM121 (holding means) of all pixels 12A constituting an image display part. Then a switch SW12 in all pixels 12A is turned on by a trigger pulse, and the data in SM121 is transferred at the same time to a capacitor C11 constituting DM122 (DRAM) and held, as well as is applied to a reflective electrode PE. By effectively arranging SM 121, DM 122 and the reflective electrode PE in a height direction of the element, reduction in size of the pixel can be achieved. By use of a sense amplifier connected to the pixel 12A and a pixel 12B, these pixels are appropriately inspected.SELECTED DRAWING: Figure 2

Description

The present invention relates to a liquid crystal display device and a liquid crystal display device inspection method, and more particularly, to a liquid crystal display device and a liquid crystal inspection method that enable downsizing of constituent pixels and enable accurate pixel inspection.

Conventionally, a sub-frame driving method is known as one of halftone display methods in a liquid crystal display device. In the subframe driving method, which is a type of time axis modulation method, a predetermined period (
For example, in the case of a moving image, each frame is divided into a plurality of subframes, and the subframes are combined in accordance with the gradation to be displayed to drive each pixel. Do. The gradation to be displayed is determined by the ratio of the pixel driving period occupying within a predetermined period. The ratio of the pixel driving period within the predetermined period is determined by the combination of the divided subframes.

As a liquid crystal display device adopting the sub-frame driving method as described above, for example, Patent Document 1
Each pixel has a master latch, a slave latch, a liquid crystal display element,
And what is comprised from a total of three switching transistors of the 1st-3rd is known.

In this case, in each pixel, the master latch applies one bit of first data through the first switching transistor to one of the two input terminals, and applies to the other input terminal. On the other hand, 1-bit second data having a complementary relationship with the first data is applied through the second switching transistor. When a target pixel is selected based on application of a row selection signal through the row scanning line, the first switching transistor and the second switching transistor are turned on, and the first data is written. When the first data has a logical value “1” and the second data has a logical value “0”, the pixel performs display based on the data.

After each data is written to all the pixels by the above-described operation within a certain subframe period, the third switching transistors of all the pixels are turned on within the subframe period. The data written in the master latch is simultaneously read out to the slave latch. The slave latched data is applied to the pixel electrode of the liquid crystal display element.
Data latched by the slave latch is applied. The series of operations described above is repeated for each subframe, and a desired gradation display is performed based on a combination of all subframes within one frame period.

That is, in the liquid crystal display device adopting the subframe driving method, the same or different predetermined display period is assigned to each subframe for all the subframes existing in one frame period. Each pixel performs white display (displayed) in all subframes during maximum gradation display, and does not perform white display (not displayed) in all subframes during minimum gradation display. In other words, the display is black. In cases other than the maximum gradation display and the minimum gradation display, the subframe to be displayed is selected according to the displayed gradation. In addition,
In this conventional liquid crystal display device, input data is digital data indicating gradation, and a digital driving system having a two-stage latch configuration is used.

JP-T-2001-523847

However, in the conventional liquid crystal display device described above, the two latches in each pixel are respectively
Since it is composed of a so-called SRAM (Static Random Access Memory), the number of transistors constituting the circuit increases. Therefore, there is a problem that it is difficult to reduce the size of the pixel.

In addition, each pixel of the above-described conventional liquid crystal display device usually uses a silicon backplane that constitutes a circuit including a shift register, which is a large-scale semiconductor integrated circuit (LSI: Lar).
ge Scale Integrated circuit) process. In the probe inspection after the wafer is created, there is a problem that the pixel inspection cannot be normally performed. The problem is that when pixel inspection is performed, data is input from the column data line to the SRAM in order to check whether the data has been normally written after the data is input to the column data line and the input data is written to the SRAM. This occurs because data is read out, but the SRAM may be rewritten by the charge accumulated in the column data line at this time.

In addition to the discussion so far, the liquid crystal display device described in Patent Document 1 described above is a two-switch type SRAM having two complementary bit lines. However, as a related art, one bit line and one 1 A problem when a one-switch type SRAM composed of two switches is employed will also be described.

For example, in the case of a liquid crystal display device having a so-called full high definition (FHD) resolution,
The number of pixels in the vertical direction of the screen is 1080 pixels, and the capacity of each column data line is about 1 pF. For example, the column data line is set to 0 V at the “L” level. For example, the SRAM and the switching transistor connected to the column data line constitute the SRAM. The input terminals of the first inverter are connected to the output terminal of the second inverter, and the input terminal of the second inverter is the first.
The voltage of the input terminal of the inverter connected to the switching transistor among the two inverters connected to the input terminal of the inverter is 3.3 V at the “H” level.
In this case, when the switching transistor is turned on for the purpose of reading the data written in the SRAM for pixel inspection from the column data line, the other inverter whose output terminal is connected to the switching transistor is connected to the switching transistor. A charge capacity of about 1 pF is charged from a power source through a P-channel MOS (Metal Oxide Semiconductor) type field effect transistor (hereinafter referred to as a PMOS transistor).

At this time, since the driving force of the transistor constituting the other inverter is smaller than the driving force of the transistor constituting the one inverter, the charging time tends to be longer. For this reason, the voltage at the input terminal of the one of the inverters tends to be lower than the inverted voltage without the necessary charging being performed completely. Then, the voltage at the input terminal of the one inverter, that is, the data to be written in the SRAM is rewritten. For this reason, there is a problem that the data of the SRAM cannot be output to the column data line, and the accurate pixel inspection cannot be performed.

The present invention has been made in view of the above points, and enables downsizing of the constituent pixels,
An object of the present invention is to provide a liquid crystal display device and a pixel inspection method thereof capable of accurately performing pixel inspection.

In order to solve the above-described problem, the present invention provides a liquid crystal display device including a plurality of pixels provided at each intersection where a plurality of column data lines and a plurality of row scanning lines intersect, wherein the pixels The display element in which liquid crystal is filled and sealed between the opposing pixel electrode and the common electrode, and each frame data of the input video signal is displayed using a plurality of subframes whose display period is shorter than one frame period. A first switching unit that performs sampling for the first data through the column data line; and a first switching unit that configures an SRAM together with the first switching unit, and the first switching unit holds the sampled subframe data. A holding unit, a second switching unit for outputting the subframe data held by the first holding unit, and a DRAM together with the second switching unit. And a second holding unit that rewrites the stored content by the subframe data held in the first holding unit input through the second switching unit and applies output data to the pixel electrode; The sub-frame data is repeatedly written to the first holding unit in units of rows in the plurality of pixels, and after the sub-frame data is written to all of the plurality of pixels, the plurality of pixels are generated by a trigger pulse. An operation of turning on all the second switching units and rewriting the storage contents of the second holding unit of the plurality of pixels by the subframe data held in the first holding unit for each subframe. And a first control unit connected to the first pixel for each pair of the first pixel and the second pixel. And data lines, the second and the second data lines connected to the pixels, to provide a liquid crystal display device, characterized in that it comprises a sense amplifier connected respectively.

In order to achieve the above object, the present invention provides the above-described inspection method for a liquid crystal display device, wherein a 1-bit inspection signal is input to the first data line connected to the first pixel. And a step of inputting an inverted signal of the inputted inspection signal to the second data line connected to the second pixel, and latching the inspection signal in the SRAM of the first pixel. And latching the inverted signal in the SRAM of the second pixel;
Supplying the latched test signal to the first data line and supplying the latched inverted signal to the second data line; and the supplied test signal; And amplifying a potential difference based on the supplied inverted signal by the sense amplifier. A method for inspecting a liquid crystal display device is provided.

According to the present invention, it is possible to provide a liquid crystal display device and a pixel inspection method thereof capable of downsizing the constituent pixels and enabling accurate pixel inspection.

1 is an overall configuration diagram of a liquid crystal display device 1 according to an embodiment of the present invention. 1 is a circuit diagram according to a first embodiment of the present invention. It is a circuit diagram of an example of an inverter concerning an embodiment of the invention. It is an example of the cross-section figure of the pixel which concerns on embodiment of this invention. 4 is a timing chart for explaining pixel writing / reading operations in the liquid crystal display device 1 according to the embodiment of the present invention. It is explanatory drawing which multiplexes the saturation voltage and threshold voltage of a liquid crystal of the liquid crystal display device 1 which concerns on embodiment of this invention as binary weighted pulse width modulation data. It is a block diagram of the sense amplifier circuit which concerns on embodiment of this invention. 6 is a timing chart for explaining operations of pixel inspection according to the embodiment of the present invention. FIG. 3 is a pixel circuit schematic diagram illustrating when the DRAM of the liquid crystal display device 1 according to the embodiment of the present invention is turned on and off.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device 1 according to an embodiment of the present invention. The liquid crystal display device 1 includes an image display unit in which a plurality of pixels 12A and pixels 12B are regularly arranged, a timing generator, a vertical shift register, a data latch circuit, a horizontal driver, a sense amplifier, and a pixel read-out device. And a shift register.

The horizontal driver includes a horizontal shift register, a latch circuit, and a level shifter / pixel driver. The pixel readout shift register is a shift register having a number of stages corresponding to half the number of pixels for one row.

The image display unit has one end connected to the vertical shift register and extends in the row direction (X direction).
One (m is a natural number of 2 or more) row scanning lines g1 to gm, and n (n is a natural number of 2 or more) columns that have one end connected to the level shifter / pixel driver and extend in the column direction (Y direction). Data line d1
~ Dn are provided at each intersection where they intersect and are arranged in a two-dimensional matrix, respectively (
m × n) / 2 pixels 12A and 12B are formed (in FIG. 1, the image display unit is indicated by a block surrounded by a broken line). The pixel 12A and the pixel 12B are two adjacent pixels connected to the same row scanning line. All the pixels 12A and 12B in the image display unit are commonly connected to trigger pulse trigger lines trig and trigb, one end of which is connected to the timing generator.

The forward trigger pulse transmitted by the forward trigger pulse trigger line trig and the inverted trigger pulse transmitted by the inverted trigger pulse trigger line trigb are always in an inverse logical value relationship (complementary relationship).

The timing generator receives a vertical synchronization signal Vst, a horizontal synchronization signal Hst,
An external signal such as a basic clock CLK is received as an input signal. The timing generator then generates an AC signal FR, V start pulse VST, H based on these external signals.
Start pulse HST, clock signal VCK and clock signal HCK, latch pulse LT
, Trigger pulse trig / trigb, pixel readout shift register clock signal TC
Various internal signals such as K / TCKb are generated.

Among the internal signals, the AC signal FR is a signal whose polarity is inverted every subframe. The AC signal FR is supplied as a common electrode voltage Vcom, which will be described later, to the common electrodes of the liquid crystal display elements in the pixels 12A and 12B constituting the image display unit. Start pulse VS
T is a pulse signal output at the start timing of each subframe described later. Subframe switching is controlled by this start pulse VST.

The start pulse HST is a pulse signal output at the start timing input to the horizontal shift register. The clock signal VCK is a shift clock that defines one horizontal scanning period (1H) in the vertical shift register, and the vertical shift register performs a shift operation in accordance with the timing of the clock signal VCK. The clock signal HCK is a shift clock in the horizontal shift register, and is a signal for shifting data with a 32-bit width. The latch pulse LT is a pulse signal that is output at a timing when the horizontal shift register has finished shifting data corresponding to the number of pixels in one row in the horizontal direction.

Further, the timing generator supplies the normal trigger pulse to the all pixels 12A and 12B in the image display unit through the normal trigger pulse trigger line trig and the reverse trigger pulse to the reverse trigger pulse trigger line trigger. The forward trigger pulse and the reverse trigger pulse are sequentially written to the first signal holding means (not shown in FIG. 1) provided in each of the pixels 12A and 12B in the image display unit. Output immediately after. Then, within the sub-frame period, the data of the first signal holding means of all the pixels 12A and 12B in the image display unit are transferred to the second signal holding means in the same pixel (not shown in FIG. 1) at a time. Transferred. For the first signal holding means and the second signal holding means,
This will be described in detail later.

The vertical shift register transfers the V start pulse VST supplied at the beginning of each subframe in accordance with the clock signal VCK. The vertical shift register sequentially supplies row scanning signals to the row scanning lines g1 to gm sequentially in 1H units. The vertical shift register supplies row scanning lines to all the row scanning lines g1 to gm in one frame period. As a result, in one frame period, the row scanning lines are sequentially selected in units of 1H from the uppermost row scanning line g1 to the lowermost row scanning line gm in the image display unit.

The data latch circuit latches 32-bit width data divided for each subframe supplied from an external circuit (not shown) based on the basic signal CLK from the host device, and then synchronizes with the basic signal CLK. Output to the shift register.

In this embodiment, one frame of a video signal is divided into a plurality of subframes having a display period shorter than one frame period of the video signal, and gradation display is performed by a combination of the subframes. In the above-described pixel and a higher-order component circuit outside the peripheral circuit, the gradation data indicating the gradation for each pixel of the video signal is displayed for each gradation for displaying the gradation of each pixel in the entire plurality of subframes. It is converted into 1-bit subframe data in units of subframes. Then, in the upper configuration circuit outside these pixels and peripheral circuits, the sub-frame data for 32 pixels in the same sub-frame is further supplied to the data latch circuit as the 32-bit width data.

When viewed in the processing system of 1-bit serial data, the horizontal shift register starts shifting by the H start pulse HST supplied first from the timing generator and clocks the 32-bit width data supplied from the data latch circuit. Shift in synchronization with the signal HCK. The latch circuit has a horizontal shift register n equal to the number n of pixels for one row of the image display unit.
At the time when the data for bits has been shifted, the data for n bits supplied in parallel from the horizontal shift register in accordance with the latch pulse LT supplied from the timing generator (that is, subframe data for n pixels in the same row) Are latched and output to the level shifter of the level shifter / pixel driver.

When the data transfer to the latch circuit is completed, the H start pulse is output again from the timing generator, and the horizontal shift register resumes shifting the 32-bit width data from the data latch circuit in accordance with the clock signal HCK.

A level shifter provided in the level shifter / pixel driver shifts the signal level of n subframe data corresponding to n pixels in one row supplied by being latched by the latch circuit to the liquid crystal driving voltage. A pixel driver provided in the level shifter / pixel driver outputs n subframe data corresponding to n pixels in one row after the level shift to n column data lines d1 to dn in parallel.

The horizontal shift register, the latch circuit, and the level shifter / pixel driver that constitute the horizontal driver output data for the pixel row in which data is written this time within 1H,
Shifting of data relating to pixel rows in which data is written in H is performed in parallel. In a certain horizontal scanning period, the latched n subframe data for one row are simultaneously output in parallel to the n column data lines d1 to dn as data signals.

Here, the column data lines d1 to dn are used in units of two adjacent column data lines at the time of pixel inspection. Two adjacent data lines are connected to a sense amplifier, and a weak potential signal difference is amplified and converted into a VDD and GND signal (here, VDD is a power supply voltage and GND is a reference voltage). Then, the converted pixel inspection signals are stored in the pixel readout shift register all at once for the number of pixels that is half of 1H by turning on the TEST. Thereafter, TEST is turned off, and a pixel inspection signal is latched in the pixel readout shift register. The pixel readout shift register clock signal TCK is a clock for transferring a signal input from a sense amplifier arranged for every two column data lines. Signals subjected to pixel inspection in accordance with the pixel readout shift register clock signal TCK / TCKb are sequentially read out serially from the output terminal TOUT.

Of the plurality of pixels 12A and 12B constituting the image display unit, n / 2 pixels 12A and pixels 12B in one row selected by the row scanning signal from the vertical shift register are simultaneously transmitted from the level shifter / pixel driver. The output n sub-frame data for one row is sampled through n data lines d1 to dn, and a first to be described later in each pixel 12A and pixel 12B (not shown in FIG. 1). Write to the signal holding means.

Next, each embodiment of the pixel 12A and the pixel 12B as the main part of the liquid crystal display device of the present invention will be described in detail.
(First embodiment)
One of the many aspects of the present invention is shown in FIG. 2 as a first embodiment and will be described below. FIG. 2 is a diagram showing each pixel of the liquid crystal display device 1 together with its peripheral circuits. In FIG. 2, a pixel 12A (indicated by a broken line in FIG. 2) and a pixel 12B (indicated by a broken line in FIG. 2) are connected to any one of the same row scanning lines g in FIG. Two pixels adjacent in the column direction, the pixel 12A is provided at the intersection of any one column data line d1 and one row scanning line g, and the pixel 12B is adjacent to the column data line d1. It is provided at the intersection of the column data line d2 and the row scanning line g. The column data line d1 and the column data line d2 are connected to a sense amplifier. The sense amplifier is a circuit that amplifies a weak potential difference input from d1 and d2.

The pixel 12A includes a switch SW11 that is a first switching unit, a first holding unit SM121 that holds a signal (data) according to on / off of the switch SW11, a switch SW12 that is a second switching unit, and a switch SW12. The capacitor C11 is a second holding unit that holds a signal according to ON / OFF, the reflective electrode PE1 and the liquid crystal LC1 that are pixel electrodes, and the CE that is a common electrode. The first holding means SM121 includes an inverter INV11
And an inverter INV12. Switch SW11 and first holding means SM1
21 constitutes an SRAM (Static Random Access Memory) (SRAM 1 in FIG. 2).
). The switch SW12 and the capacitor C11 are DRAM (Dynamic Random Access Memory).
(DM122 in FIG. 2).

The pixel 12B includes a switch SW21 that is a first switching unit, a first holding unit SM123 that holds a signal (data) according to on / off of the switch SW21, a switch SW22 that is a second switching unit, and a switch SW22. The capacitor C21 is a second holding unit that holds a signal according to on / off, the reflection electrode PE2 and the liquid crystal LC2 that are pixel electrodes, and CE that is a common electrode. The first holding means SM123 includes an inverter INV21.
And an inverter INV22. Switch SW21 and first holding means SM1
23 constitutes an SRAM (Static Random Access Memory) (SRAM 2 in FIG. 2).
). The switch SW22 and the capacitor C21 are DRAM (Dynamic Random Access Memory).
(DM124 in FIG. 2).

The liquid crystal display element LMC1 and the liquid crystal display element LMC2 are arranged in a space between the reflective electrode PE1 and the reflective electrode PE2, which are pixel electrodes having light reflection characteristics, which are spaced apart from each other, and the common electrode CE having light transmittance. The LC1 and the liquid crystal LC2 are filled and sealed.

The switches SW11 and SW21 have gates commonly connected to the row scanning line g, drains separately connected to the column data lines d1 and d2, and sources connected to SM121 and SM123.
Each of the N-channel MOS transistors (hereinafter referred to as “N-channel MOS transistors”) connected to the input terminals of
NMOS transistor). The SM 121 is a self-holding memory composed of two inverters INV11 and INV12 having one output terminal connected to the other input terminal. Similarly, the SM 123 is a self-holding memory composed of two inverters INV21 and INV22 having one output terminal connected to the other input terminal.

The input terminal of the inverter INV11 is connected to the output terminal of the inverter INV12 and the source of the NMOS transistor constituting the switch SW11. Inverter IN
The input terminal of V12 is connected to the switch SW12 and the output terminal of the inverter INV11. Similarly, the inverter INV21 has its input terminal connected to the output terminal of the inverter INV22 and the source of the NMOS transistor constituting the switch SW21. The input terminal of the inverter INV22 is the switch SW22 and the inverter INV21.
Connected to the output terminal.

The inverter INV11, the inverter INV12, the inverter INV21, and the inverter INV22 are all P-channel MOS transistors (hereinafter referred to as PMOS transistors) PT in which the gates and drains are connected as shown in FIG.
Although it is a configuration of a CMOS inverter composed of r and NMOS transistor NTr, each is designed to have different driving power.

The transistors in the input-side inverter INV11 and inverter INV21 constituting SM121 and SM123 when viewed from the switch SW11 and the switch SW21, respectively,
Compared with the transistors in the inverters INV12 and INV22 on the output side that constitute the SM121 and SM123 when viewed from the switches SW11 and SW21, transistors having higher driving power are used. Further, the driving power of the NMOS transistors constituting the switches SW11 and SW21 is the inverter INV12 and the inverter INV2.
2 is configured by a transistor having a larger driving force than that of the NMOS transistor constituting the circuit 2.

This is because the current that flows in the switch SW11 and the switch SW21 is greater than the voltage at which the transistors on the input side of the inverter INV11 and the inverter INV21 are inverted when the voltage on the input side of the switch SW11 and the switch SW21 is “H” level. NMO constituting the transistors of the inverters INV12 and INV22 on the output side
This is because it needs to be larger than the current flowing through the S transistor.

Accordingly, since the driving power of the NMOS transistors constituting the switch SW11 and the switch SW21 is configured to be larger than the driving power of the NMOS transistors constituting the inverter INV12 and the inverter INV22, the switch SW11 and the switch SW21 are taken into consideration. It is necessary to determine the transistor size of the NMOS transistors constituting the inverters and the transistor sizes of the NMOS transistors constituting the inverters INV12 and INV22.

The switches SW12 and SW22 have their drains connected to each other,
The transmission gate is composed of an NMOS transistor and a PMOS transistor whose sources are connected to each other. The gate of the NMOS transistor is connected to the normal trigger pulse trigger line trigger, and the gate of the PMOS transistor is connected to the inverted trigger pulse trigger line trigger.

In addition, the switch SW12 and the switch SW22 have one terminal SM121 and SM12.
3 and the other terminal are connected to the capacitors C11 and C21 and the liquid crystal display element LCM1.
And the reflective electrode PE1 and the reflective electrode PE2 of the liquid crystal display element LCM2. Accordingly, in the switches SW12 and SW22, the normal rotation trigger pulse supplied via the trigger line trig is “H” level (in this case, the reverse trigger pulse supplied via the trigger line trigb is “L” level). When it is turned on, SM121 and SM
The stored data 123 is read out and transferred to the capacitors C11 and C21, the reflective electrode PE1, and the reflective electrode PE2.

Further, the switch SW12 and the switch SW22 have the normal rotation trigger pulse supplied via the trigger line trig at the “L” level (in this case, the reverse trigger pulse supplied via the trigger line trigb is at the “H” level). When it is off, SM121 and SM123
The stored data is not read out.

Since the switch SW12 and the switch SW22 are configured as transmission gates, the voltage in the range from GND to VDD shown in FIG. 3 can be turned on / off.
That is, when the signal applied to the gates of the NMOS transistor and the PMOS transistor constituting the transmission gate is the GND side potential ("L" level), the PMOS
Instead of the transistor not conducting, the NMOS transistor can conduct with low resistance. On the other hand, when the gate input signal is at the VDD side potential ("H" level), N
Instead of MOS transistors cannot conduct, PMOS transistors can conduct with low resistance.

Therefore, the normal rotation trigger pulse supplied via the trigger line trig and the trigger line trig
switch SW12 and switch SW2 by the inversion trigger pulse supplied via b.
By controlling on / off of the transmission gate that constitutes 2, the voltage range from GND to VDD can be switched with low resistance / high resistance.

The capacitor C11 and the switch SW12 form a DM122 DRAM, and the capacitor C2
1 constitutes a DRAM of the DM 124 together with the switch SW22. Here, SM121
When the storage data of the capacitors C11 and C21 are different from the stored data of the capacitors C11 and C21, the switches SW12 and SW22 are turned on, and the SM121 and SM123 are stored.
When the stored data is transferred to the capacity C11 and the capacity C21.
The data held in 21 needs to be replaced with the data stored in SM121 and SM123.

When the retained data of the capacitor C11 and the capacitor C21 is rewritten, the retained data is changed by charging or discharging, charging / discharging of the capacitor C11 is performed by an output signal of the inverter INV11, and charging / discharging of the capacitor C21 is performed by an output signal of the inverter INV21. Respectively. When the data held in the capacitors C11 and C21 is rewritten from “L” level to “H” level by charging, the output signals of the inverters INV11 and INV21 are “
H ", and at this time, the PMO constituting the inverter INV11 and the inverter INV21
S transistor (PTr in FIG. 3) is on, NMOS transistor (NTr in FIG. 3 to be described later)
) Is turned off, the capacitors C11 and C21 are charged by the power supply voltage VDD connected to the sources of the PMOS transistors of the inverters INV11 and INV21.

On the other hand, when the data held in the capacitors C11 and C21 is rewritten from “H” level to “L” level by discharging, the output signals of the inverters INV11 and INV21 are “
At this time, the NMOS transistors (NTr in FIG. 3 to be described later) constituting the inverter INV11 and the inverter INV21 are turned on, and the PMOS transistor (PTr in FIG. 3) is turned off. Therefore, the accumulated charges in the capacitors C11 and C21 Is inverter INV11
And through the NMOS transistor (NTr in FIG. 3 described later) of the inverter INV21
Discharged to ND. Since the switch SW12 and the switch SW22 have the configuration of the analog switch using the transmission gate described above, the capacitors C11 and C2 described above are used.
1 can be charged and discharged at high speed.

Furthermore, in this embodiment, the driving power of the inverter INV11 and the inverter INV21 is
Since the driving power of the inverters INV12 and INV22 is set larger than that of the inverters INV12 and INV22, the capacitors C11 and C21 can be charged and discharged at high speed. When the switch SW12 and the switch SW22 are turned on, the charges stored in the capacitor C11 and the capacitor C21 also affect the input gates of the inverter INV12 and the inverter INV22. However, the inverter INV11 and the inverter INV22 are compared with the inverter INV12 and the inverter INV22. By setting the driving force of INV21 large, inverter INV12
In addition, the charging / discharging of the capacitor C11 and the capacitor C21 by the inverter INV11 and the inverter INV21 is prioritized over the data input inversion of the inverter INV22, and SM121, SM123
The stored data is never rewritten.

According to the pixel 12A and the pixel 12B of the present embodiment shown in FIG. 2, the applied voltage of the liquid crystal display elements LCM1 and LCM2 can be set high as described above, and the dynamic range can be increased. The effect that becomes.

Furthermore, the remarkable effect that the pixel can be reduced in size can be obtained. These two pixels 12
As shown in FIG. 2, the miniaturization of A and 12B is a total of 14 transistors and two capacitors C1.
1 and a capacitor C21, and in addition to the reason that the pixel can be configured by a smaller number of components than the two conventional pixels, as described below, SM121, SM12
3, DM122, DM124, reflective electrode PE1, and reflective electrode PE2 because it can be effectively arranged in the height direction of the element.

FIG. 4 is a cross-sectional configuration diagram of a pixel according to an embodiment of the present invention. The capacitor C11 and the capacitor C21 shown in FIG. 2 include an MIM (Metal-Insulator-Metal) capacitor that forms a capacitor between wires,
A diffusion capacitor that forms a capacitor between the substrate and polysilicon, a PIP (Poly-Insulator-Poly) capacitor that forms a capacitor between two layers of polysilicon, or the like can be used. FIG. 4 shows a cross-sectional configuration diagram of the liquid crystal display device when the capacitor C11 is configured by the MIM. FIG. 4 is a sectional view showing a part of the pixel 12A.

In FIG. 4, the PMOS transistor P of the inverter INV11 in which the drains are connected to each other by sharing a diffusion layer serving as the drain on the N well formed on the silicon substrate.
Tr11 and a PMOS transistor Tr2 of the switch SW12 are formed. Further, on the P-well formed on the silicon substrate, the NMOS transistor NTr12 of the inverter INV12 and the NMOS transistor Tr1 of the switch SW12, in which the drains are connected by sharing the diffusion layer serving as the drain, are formed. . FIG. 4 shows the NMOS transistor constituting the inverter INV11 and the P constituting the inverter INV12.
The MOS transistor is not shown.

Further, above each of the transistors PTr11, Tr2, Tr1, and NTr12, an interlayer insulating film is interposed between the metals, and the first metal, the second metal, the third metal, the electrode, the fourth metal, and the fifth metal. Are stacked. The fifth metal constitutes the reflective electrode PE formed for each pixel. Each diffusion layer constituting each source of the NMOS transistor Tr1 and the PMOS transistor Tr2 constituting the switch SW12 is electrically connected to the first metal by a contact, and further, through the through hole, the second metal, the third metal, It is electrically connected to the 4th metal and the 5th metal. That is, the sources of the NMOS transistor Tr1 and the PMOS transistor Tr2 constituting the switch SW12 are connected to the reflective electrode P.
E is electrically connected.

Furthermore, a passivation film (PSV) is provided as a protective film on the reflective electrode PE (fifth metal).
Are formed and spaced apart from the common electrode CE, which is a transparent electrode. These pixel electrodes P
A liquid crystal LC1 is filled and sealed between E1 and the common electrode CE to form a liquid crystal display element LCM1.

Here, an MIM electrode is formed on the third metal via an interlayer insulating film. This MI
The M electrode has a capacitor C11 together with the third metal and an interlayer insulating film between the third metal and the MIM electrode.
Is configured. When the capacitor C11 is configured by the MIM, the SM 121 and the switch SW11
, Switch SW12 is a transistor and wiring of each layer of the first metal and second metal, DM12
2 can be formed by MIM wiring using the third metal above the transistor. Since the MIM electrode is electrically connected to the fourth metal via the through hole, and the fourth metal is electrically connected to the reflective electrode PE1 via the through hole, the capacitor C11 is electrically connected to the reflective electrode PE1. Connected.

The light emitted from the light source (not shown in FIG. 4) is transmitted through the common electrode CE and the liquid crystal LC1, is incident on the reflective electrode PE1 (fifth metal), is reflected, and travels backward through the original incident path. Electrode C
Injected through E.

According to the present embodiment, as shown in FIG. 4, the fifth metal, which is a five-layer wiring, is connected to the reflective electrode PE.
By assigning it to 1, it becomes possible to effectively arrange the capacitor portions of the SM 121 and DM 122 and the reflective electrode PE1 in the height direction, thereby realizing pixel miniaturization. Thus, for example, 3
Pixels with a pitch of μm or less can be configured with transistors having a power supply voltage of 3.3V. With this 3 μm pitch pixel, a liquid crystal display panel with a diagonal length of 0.55 inches and a horizontal direction of 4000 pixels and a vertical direction of 2000 pixels can be realized.

Next, data writing and reading operations of the liquid crystal display device 1 of FIG. 1 using the pixel 12A and the pixel 12B of this embodiment will be described with reference to the timing chart of FIG. As described above, in the liquid crystal display device 1, the row scanning lines are sequentially selected in units of 1H from the row scanning line g1 to the row scanning line gm by the row scanning signal from the vertical shift register. The plurality of pixels 12A and pixels 12B constituting the image display unit perform data writing in units of n pixels in one row that are commonly connected to the selected row scanning line. Then, after writing is completed for all of the plurality of pixels 12A and 12B constituting the image display unit, reading is performed on all the pixels at the same time based on the trigger pulse.

FIG. 5A schematically shows a writing period and a reading period of one pixel of 1-bit subframe data output from the horizontal driver to the column data lines d1 to dn. A slanting line on the left indicates the writing period. In FIG. 5A, B0b, B1b, and B2b are bits B
Indicates that the data is inverted data of O, B1, and B2.

FIG. 5B shows a trigger line tri for forward rotation trigger pulse from the timing generator.
The trigger pulse output to g is shown. This trigger pulse is output every subframe. Since the inversion trigger pulse output to the inversion trigger pulse trigger line trigb always has a reverse logic value with respect to the normal rotation trigger pulse, its illustration is omitted.

First, among the plurality of pixels 12A and 12B in one row selected by the row scanning signal, the pixel 1
2A is a state in which the switch SW11 is turned on, and is then output to the column data line d1 in FIG.
The normal subframe data of bit B0 in A) is sampled by the switch SW11 and written into the SM 121. In the pixel 12B, the switch SW21 is turned on, and the normal subframe data of the bit B0 of FIG. 5A output to the column data line d2 at that time is sampled by the switch SW21 and written to the SM123. Less than,
Similarly, bit B0 is set in SM121 and SM123 of all pixels constituting the image display unit.
At time T1 shown in FIG. 5 after the writing of the subframe data is completed and the writing operation is finished, a normal rotation trigger pulse of “H” level is displayed on the image display unit 11 as shown in FIG.
Are simultaneously supplied to all the pixels 12A and 12B.

As a result, the switches SW12 and SW22 of all the pixels 12A and 12B are turned on, so that the normal subframe data of bit B0 stored in the SM121 and SM123 is simultaneously transferred to the capacitors C11 and C21 through the switch SW12. And is applied to the reflective electrodes PE1 and PE2. The holding period for normal subframe data of bit B0 by the capacitors C11 and C21 is from time T1 to time T2 when the next "H" level normal rotation trigger pulse is input as shown in FIG. 5B. One subframe period. FIG. 5C schematically shows bits of subframe data applied to the reflective electrodes PE1 and PE2.

Here, when the bit value of the sub-frame data is “1”, that is, “H” level, the power supply voltage VDD (in this example, 3.3 V) is applied to the reflective electrode PE1 and the reflective electrode PE2, and the bit value is “0”. ", That is, at the" L "level, the reflective electrode PE1 and the reflective electrode P
0V is applied to E2. On the other hand, a free voltage can be applied to the common electrode CE as the common electrode voltage Vcom without being limited to GND and VDD.
The voltage is switched to the specified voltage at the same time as when the level normal rotation trigger pulse is input. Here, the common electrode voltage Vcom is lower than 0V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the normal rotation subframe data is applied to the reflective electrode PE1 and the reflective electrode PE2, as shown in FIG. Set to voltage.

The liquid crystal LC1 and the liquid crystal LC2 shown in FIG. 2 are gradations corresponding to the applied voltages of the liquid crystal LC1 and the liquid crystal LC2, which are absolute values of the difference voltage between the applied voltage of the reflective electrode PE1 and the reflective electrode PE2 and the common electrode voltage Vcom. Display. Therefore, in one subframe period from time T1 to time T2 when the normal subframe data of bit B0 is applied to the reflective electrode PE1 and the reflective electrode PE2, the applied voltages of the liquid crystal LC1 and the liquid crystal LC2 are shown in FIG. Thus, when the bit value of the subframe data is “1”, it becomes 3.3 V + Vtt (= 3.3 V − (− Vtt)), and when the bit value of the subframe data is “0”, + Vtt (= 0 V− (−Vtt)).

FIG. 6 shows the relationship between the applied voltage (RMS voltage) of the liquid crystal and the gray scale value of the liquid crystal. As shown in FIG. 6, the gray scale value curve indicates that the black gray scale value is the threshold voltage Vtt of the liquid crystal.
The gray scale value of white corresponds to the RMS voltage of the liquid crystal, and the saturation voltage Vsat of the liquid crystal (= 3.3V +
Vtt) is shifted to correspond to the RMS voltage. It is possible to match the gray scale value to the effective part of the liquid crystal response curve. Therefore, the liquid crystal LC is liquid crystal LCM as described above.
When the applied voltage is (3.3V + Vtt), white is displayed, and when it is + Vtt, black is displayed.

Subsequently, within the subframe period in which the normal subframe data of the bit B0 is displayed, the SM121 of the pixel 12A and the pixel 12B of the inverted subframe data of the bit B0 as shown by B0b in FIG. And writing to SM123 is started in order.
Then, the inverted subframe data of bit B0 is written into SM121 and SM123 of all the pixels of the image display unit 11, and at time T2 after the completion of the writing, as shown in FIG.
A normal rotation trigger pulse of H ″ level is simultaneously supplied to all the pixels constituting the image display unit 11.

Thereby, the switches SW12 and SW2 of all the pixels 12A and 12B are set.
2 is turned on, the inverted subframe data of bit B0 stored in SM121 and SM123 is transferred to and held in the capacitors C11 and C21 through the switches SW12 and SW22, and the reflection electrode PE1 and the reflection electrode Applied to PE2.
The holding period of the inverted subframe data of bit B0 by the capacitors C11 and C21 is from time T2 to time T3 when the next “H” normal rotation trigger pulse is input as shown in FIG. 5B. One subframe period. Here, since the inverted subframe data of bit B0 is always in an inverse logical value relationship with the normal subframe data of bit B0,
It is “0” when the normal rotation subframe data of 0 is “1”, and “1” when the normal rotation subframe data of bit B 0 is “0”.

On the other hand, the common electrode voltage Vcom is higher than the 3.3V threshold voltage Vtt as shown in FIG. 5D during the subframe period in which the inverted subframe data is applied to the reflective electrode PE1 and the reflective electrode PE2. Set to voltage. Therefore, in one subframe period from time T2 to time T3 when the inverted subframe data of the bit B0 is applied to the reflective electrode PE1 and the reflective electrode PE2, the applied voltage of the liquid crystal LC1 and the liquid crystal LC2 has the bit value of the subframe data “
When it is “1”, it is −Vtt (= 3.3 V− (3.3 V + Vtt)), and when the bit value of the subframe data is “0”, it is −3.3 V−Vtt (= 0 V− (3.3 V + Vtt)). It becomes.

Accordingly, when the bit value of the normal subframe data of bit B0 is “1”, the bit value of the inverted subframe data of bit B0 that is subsequently input is “0”, so the liquid crystal L
The applied voltage of C1 and the liquid crystal LC2 is − (3.3V + Vtt), and the direction of the potential applied to the liquid crystal LC1 and the liquid crystal LC2 is opposite to that of the normal subframe data of the bit B0, but the absolute value is the same. Therefore, the pixels 12A and 12B display the same white as when the normal rotation subframe data of the bit B0 is displayed. Similarly, when the bit value of the normal subframe data of bit B0 is “0”, the bit value of the inverted subframe data of bit B0 that is subsequently input is “1”. The applied voltage of LC2 becomes −Vtt, and the liquid crystal L
The directions of the potentials applied to C1 and the liquid crystal LC2 are opposite to those in the normal subframe data of the bit B0, but the absolute values are the same, so the pixels 12A and 12B display black.

Accordingly, as shown in FIG. 5E, the pixel 12A and the pixel 12B display the same gradation in the bit B0 and the complementary bit B0b of the bit B0 in the two subframe periods from the time T1 to the time T3, Since AC driving in which the potential directions of the liquid crystal LC1 and the liquid crystal LC2 are inverted every subframe is performed, it is possible to prevent the liquid crystal LC1 and the liquid crystal LC2 from being burned.

Subsequently, within the subframe period in which the inverted subframe data of the complementary bit B0b is displayed, as shown by B1 in FIG. 5A, the pixels 12A and 12B of the normal subframe data of the bit B1 are displayed. Writing to the SM 121 and SM 123 is started in order. Then, SM121 and SM123 of all the pixels 12A and 12B of the image display unit 11 are displayed.
The normal rotation sub-frame data of bit B1 is written to the pixel, and at time T3 after the completion of the writing, as shown in FIG. Are supplied at the same time.

As a result, since the switches SW12 and SW22 of all the pixels are turned on, SM1
21 and the normal subframe data of bit B1 stored in SM123 are stored in the switch S
It is transferred to and held by the capacitors C11 and C21 through W12 and the switch SW22, and is applied to the reflective electrodes PE1 and PE2. Bit B by this capacity C11 and capacity C21
As shown in FIG. 5B, the normal subframe data 1 is held from the time T3 as shown in FIG.
This is one subframe period until time T4 when a normal rotation trigger pulse of H ″ level is input.

On the other hand, the common electrode voltage Vcom is a voltage lower than 0V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the normal rotation subframe data is applied to the reflective electrode PE1 and the reflective electrode PE2, as shown in FIG. Set to Therefore, in one subframe period from time T3 to time T4 when the normal subframe data of bit B1 is applied to the reflective electrode PE1 and the reflective electrode PE2, the applied voltages of the liquid crystal LC1 and the liquid crystal LC2 are shown in FIG. Thus, when the bit value of the subframe data is “1”, it becomes 3.3V + Vtt (= 3.3V − (− Vtt)),
When the bit value of the subframe data is “0”, it is + Vtt (= 0V − (− Vtt)).

Subsequently, within the subframe period in which the normal subframe data of the bit B1 is displayed, the SM121 of the pixel 12A and the pixel 12B of the inverted subframe data of the bit B1, as indicated by B1b in FIG. And writing to SM123 is started in order.
Then, the inverted subframe data of bit B1 is written into SM121 and SM123 of all the pixels of the image display unit 11, and at time T4 after the completion of the writing, as shown in FIG.
A normal rotation trigger pulse of H ″ level is simultaneously supplied to all the pixels constituting the image display unit 11.

Thereby, the switches SW12 and SW2 of all the pixels 12A and 12B are set.
2 is turned on, so that the inverted subframe data of bit B1 stored in SM121 and SM123 is transferred to and held in capacitors C11 and C21 through switches SW12 and SW22, and reflection electrode PE1 and reflection electrode Applied to PE2. The holding period of the inverted subframe data of bit B0 by the capacitors C11 and C21 is from time T4 to time T5 when the next “H” level normal rotation trigger pulse is input as shown in FIG. 5B. One subframe period. Here, the inverted subframe data of bit B1 is always in the relationship of the inverse logical value with the normal subframe data of bit B1.

On the other hand, the common electrode voltage Vcom is higher than the 3.3V threshold voltage Vtt as shown in FIG. 5D during the subframe period in which the inverted subframe data is applied to the reflective electrode PE1 and the reflective electrode PE2. Set to voltage. Therefore, in one subframe period from time T4 to time T5 when the inverted subframe data of bit B1 is applied to the reflective electrode PE1 and the reflective electrode PE2, the bit value of the subframe data is “1”. Is −Vtt (= 3.3V− (3.3V + Vtt)), and when the bit value of the subframe data is “0”, −3.3V−Vtt (= 0V− (3.3V + Vtt)). .

Thereby, the pixel 12A and the pixel 12B are time T3 to time T3 as shown in FIG.
During the two subframe periods up to 5, the same gradation is displayed by the bit B1 and the complementary bit B1b of the bit B1, and the AC driving is performed in which the potential direction of the liquid crystal display element LCM is inverted every subframe. Can be prevented.

Thereafter, the same operation as described above is repeated, and according to the liquid crystal display device having the pixels 12A and 12B of the present embodiment, gradation display can be performed by a combination of a plurality of subframes.

The display periods of bit B0 and complementary bit B0b are the same first subframe period, and the display periods of bit B1 and complementary bit B1b are also the same second subframe period. The subframe period and the second subframe period are not necessarily the same. Here, as an example, the second subframe period is set to be twice the first subframe period. As shown in FIG. 5E, the third subframe period, which is the display period of the bit B2 and the complementary bit B2b, is set to be twice the second subframe period.
The same applies to the other subframe periods. The length of each subframe period is determined to be a predetermined length according to the system, and the number of subframes is also determined to be an arbitrary number.

Next, the basic operation of the pixel inspection of the liquid crystal display device 1 according to the embodiment of the present invention will be described with reference to FIG. First, a row scanning signal of “H” level is supplied to a specific row scanning line g at the start of pixel inspection to turn on the switch SW11 and the switch SW21. In addition, the trigger lines trig and trigb have “H” level trigger pulses and “L” respectively.
The “level inversion trigger pulse is supplied, and the switches SW12 and SW22 are also turned on.

Next, “L” level data is supplied to the column data line d1 as a 1-bit inspection signal.
As a result, “L” level data is written at the point “a”, which is the connection point between the input terminal of the inverter INV11 and the output terminal of the inverter INV12 constituting the SM 121 of the pixel 12A, and the output terminal of the inverter INV11 and the inverter INV12 "H" level data is written at a point b, which is a connection point where the input terminal is connected to the capacitor C11 via the switch SW12. At this time, in SM121 of the pixel 12A, the driving force of the transistor constituting the inverter INV11 is larger than the driving force of the transistor constituting the inverter INV12, so that the point a is the input of the SM121 and the point b is the output of the SM121. Function. Here, the switch SW12 is in an ON state, and C11 is also in a state in which “H” level data is written.

On the other hand, "H" level data is supplied to the column data line d2 as a 1-bit inspection signal.
As a result, “H” level data is written at a point c, which is a connection point between the input terminal of the inverter INV21 and the output terminal of the inverter INV22 that constitutes the SM123 of the pixel 12B, and the output terminal of the inverter INV21 and the inverter INV22 "L" level data is written at point d, which is a connection point where the input terminal is connected to the capacitor C21 via the switch SW22. At this time, in SM123 of the pixel 12B, since the driving force of the transistor constituting the inverter INV21 is larger than the driving force of the transistor constituting the inverter INV22, the point c is used as the input of the switch SM123, and the point d is used as the output of the switch SM123. Each functions. Here, since the switch SW22 is on, C21 is also “L”.
"Level data has been written.

Next, when the row scanning line g is set to the “L” level, the reflective electrode PE1 and the pixel 12B of the pixel 12A.
Each of the reflective electrodes PE2 is in a state in which "H" level data and "L" level data obtained by inverting the input data are latched.

After the data writing is finished, the input of the sense amplifier connected to d1 and d2 is connected to the mid supplied with the intermediate voltage by turning on nut. As a result, the inputs d1 and d2 of the sense amplifier are precharged to an intermediate voltage of 1.65V. Then, nu is turned off. Since d1 and d2 have the capacity of the signal line, a voltage of 1.65 V is held.

Next, when the row scanning line g is set to the “H” level, the data written in the pixels 12A and 12B are output to the signal line d1 and the signal line d2, respectively. Since the pixels 12A and 12B are SRAMs whose inputs and outputs are determined in advance, the pixels 12A and 12B are held on the signal lines d1 and d2.
5V is written to the pixel 12A and the pixel 12B, but the data written to the pixel 12A and the pixel 12B is also output to the signal line d1 and the signal line d2, respectively, and the signal line d1 and the signal line d2 are The level of the signal line changes under the influence of the data written in the pixel 12A and the pixel 12B.

That is, the signal line d1 is driven to “L” level by the inverter INV12 by data written to the pixel 12A, and the signal line d2 is driven to “H” level by the inverter INV22 by data written to the pixel 12B. The drive power of the inverter INV12 and the inverter INV22 is very small and the signal line capacity is large.
It takes time to drive to the “level” and “H” level. However, if a slight potential difference occurs between the signal line d1 and the signal line d2, the sense amplifiers input from the signal line d1 and the signal line d2 can reduce the potential difference. Amplified and output to the “L” level.

The signal extracted by the sense amplifier is shaped in a signal waveform by a buffer and input to a predetermined location of a pixel readout shift register. Thereafter, a signal is serially extracted from the output terminal TOUT in accordance with the TCK / TCKb signal sent from the timing generator.

In the above pixel inspection, “L” level data is input from the column data line d1 to the two pixels 12A and 12B, and “H” level data is input from the column data line d2, and the respective signals are output. First inspection method for reading, and second inspection method for inputting “H” level data from the column data line d1, and inputting “L” level data from the column data line d2, and reading the respective signals Are executed twice at different timings.

As a result, the “L” level voltage and the “H” level voltage can be read from the pixel 12A and the pixel 12B, so that the pixel function test of logic as a memory can be performed. At this time, for example, if the capacitor C11 or the capacitor C21 is short-circuited to a wiring connected to GND or VDD by a process, it is impossible to read arbitrary data in the pixel inspection. Further, even when the SM 121 and SM 123 are short-circuited or disconnected, it is impossible to read arbitrary data in the pixel inspection according to the present invention. When the above data reading is impossible, it is determined that the liquid crystal display device has a defective pixel, and it is possible to take a business appropriate measure.

Subsequently, FIG. 7 shows a configuration diagram of the sense amplifier circuit. The sense amplifier circuit amplifies and outputs the difference voltage between the two gate inputs of +/− within the circuit. The voltage source circuit forms an analog voltage supplied to the sense amplifier by resistance division. Note that the sense amplifier circuit is not necessarily configured as shown in FIG. Furthermore, a high-performance sense amplifier with a high gain may be used.

Next, the pixel inspection operation corresponding to the above-described malfunction in this embodiment will be described in more detail with reference to the timing charts of FIGS. 1, 2, and 8.

At the time of pixel inspection, first, even-numbered column data lines dev (d2, d4, d6,...
, Dn) is the pixel 12B connected to the H data write side, and the odd-numbered column data line dod
The pixel 12A connected to (d1, d3, d5,..., Dn−1) is assumed to be the L data writing side. In this case, at the first time t1 at the time of pixel inspection, trig is “H”.
Level, trigb is set to “L” level, SW12 of the pixel 12A, and SW of the pixel 12B
22 is controlled to be on.

Next, from time t2 to time t3, LT is controlled to the “H” level, and the column data lines d1 to d1 are controlled.
Predetermined data is written to dn. At this time, as described above, the even-numbered column data line de
“H” level data is written to v (d2, d4, d6,..., dn), and “L” is written to odd-numbered column data lines dod (d1, d3, d5,..., dn−1). Write level data. From time t2 to time t4, one row scanning line g1 of the image display unit is controlled to the “H” level, and data written to the column data lines d1 to dn from the level shifter / pixel driver is equivalent to one row. Write to pixel 12A and pixel 12B.

Next, the data written in the pixel is read out. Tlat at time t4.5
Is set to “L” level to open all column data lines. As a result, the column data lines d1 to dn are in a state where the voltage is determined only by the capacitance.

At time t5, the odd-numbered column data line dod and the even-numbered column data line dev are short-circuited to the mid signal (1.65 V) by setting the control signal nu to the “H” level. As a result, the column data lines d1 and d2 become 1.65V. After that, the control signal nut
Is set to the “L” level, all the column data lines are opened. As a result, the column data lines d1 to dn are in a state where a voltage of 1.65 V is determined only by the capacitance.

By controlling the row scanning line g1 to the “H” level at time t6, the pixel 12A and the pixel 1
Read the data written to 2B. At the timing of T6, the inverter IN of the pixel 12A
The column data line d1 is driven by V12, and the column data line d2 is driven by the inverter INV22 of the pixel 12B. Since the driving forces of the inverter INV12 and the inverter INV22 are very small, the potential of the column data line slightly fluctuates at first, but the data becomes “L” level and “H” level over time. Thereby, the column data line d1
Is driven in the "L" level direction, and the column data line d2 is driven in the "H" level direction.

The slight voltage difference between d1 and d2 is amplified by the sense amplifier and input to a buffer connected to the output of the sense amplifier. Data is shaped to VDD (power supply voltage) and GND (reference voltage) levels by the buffer. By controlling TEST to the “H” level at time t6, the outputs e1 to en of the buffers connected to the output of the sense amplifier are simultaneously latched in the pixel readout shift register. At time t7, TEST is set to “L” level to complete the latch of the pixel readout shift register.

From time t7, the clock signal TCKb and the clock signal TCK shown in FIG. 8 that are supplied to the pixel readout shift register and in opposite phases are alternately turned on and off alternately. As a result, among the readout signals stored in the pixel readout shift register, the readout signals from the column sense amplifier buffer output en to the readout signals from the column sense amplifier buffer output e1 are sequentially output to the output terminal TOUT. . The clock signal TCKb and the clock signal TCK are repeatedly turned on / off by half the number of pixels for one row, thereby reading all data and completing the inspection for one row. A pixel inspection can be performed by comparing the readout signal of the pixels for one row with the input inspection signal and determining whether or not they are the same.

After the above operation is completed, this time, by controlling the vertical shift register, a set of each pixel 12A and pixel 12B in the next pixel row is selected, and pixel inspection is performed in the same manner as described above. These are repeated, the inspection for the number of pixels in the vertical direction is executed, and the inspection is performed for all the pixels constituting the image display unit. As described above, the input inspection signal does not need to be set to the “L” level on the column data line d1 and to the “H” level on the column data line d2, and the opposite data may be written and inspected.

Thus, according to the present embodiment, the pixel inspection can be performed accurately. According to the present embodiment, the inspection can be performed without increasing the number of inspection transistors in the pixel 12A and the pixel 12B for the pixel inspection, and thus compared with a conventional liquid crystal display device using two SRAMs in the pixel. Pixels can be downsized and pixel inspection can be performed accurately.

The above is the pixel inspection when the DRAM is controlled to be turned on, but the present invention can also perform the pixel inspection when the DRAM is turned off. At this time, in FIG. 9, trig is set to “L” level, t
By controlling irgb to “H” level, the inspection with the DRAM turned off can also be performed. The other timing charts are the same as described above, and will be omitted.

In this case, it is possible to perform an open inspection of the DRAM by performing two types of pixel inspections when the DRAM is turned on and when the DRAM is turned off, and comparing the inspection results.

FIGS. 9A and 9B show schematic diagrams of the case with and without DRAM, respectively. When the DRAM is present, the switch SW12 and the switch SW22 in FIG. 2 are turned on. When there is no DRAM, the wiring is cut due to a process failure at the points b and d, and C11 and C21 are not connected. Show. In other words, in FIG.
The difference between (A) and (B) is whether or not the capacitors C11 and C21 are connected to the inverter INV12 and the inverter INV22 in the pixel circuit, respectively.

At this time, when the capacitor C11 is connected to the inverter INV12 and the capacitor C21 is connected to the inverter INV22 (A), the driving force of the inverter is strong, and the inverter INV
When the capacitor C11 is not connected to the capacitor 12 and the capacitor C21 is not connected to the inverter INV22 (B), the driving force of the inverter is weak. The gate voltage constituting the inverter INV12 is determined by the capacitance of the liquid crystal LC1 and the capacitor C11, but is determined by charging with the output voltage of the inverter INV11 (not shown in FIG. 9) (shown in FIG. 2). The output voltage of the inverter INV11 is determined by the input voltage level of the inverter INV11. The input voltage of the inverter INV11 is determined to be about 1.65V by the d1 voltage written to 1.65V.

That is, when the “L” level voltage is written at the point b in FIG. 2, when reading, the inverter INV11 tries to rewrite the voltage at the point b to 1.65V. However, when the capacitances of the liquid crystal LC1 and the capacitor C11 at the point b are large, it takes time to rewrite to 1.65 V, and as a result, a slight “H” level inversion voltage is output to the point a. By slightly increasing the point a to the “H” level, the inverter INV11 becomes slightly “
Trying to output the L ″ level. By repeating these, the column data line d is little by little.
1 goes to “H” level.

This is the case of the pixel 12A, but since the inverted voltage of the pixel 12A is written into the pixel 12B, the voltage at the point c is slightly outputted as the “L” level voltage, and the column data line d2 gradually becomes “L”.
As a result, a potential difference that can be determined by the sense amplifier is output to d1 and d2, and an "H" level (VDD) voltage is output to the output of the sense amplifier, so that pixel inspection can be performed.

At this time, when the DRAM is disconnected and not connected, the liquid crystal LC1 is displayed at the point b.
This capacity is rewritten to 1.65V by the inverter INV11.
If the capacitance at point b is small, it will be rewritten to 1.65 V in a short time, so inverter IN
The input voltage of V12 becomes 1.65V, and the voltage at point a becomes 1.65V.
Also in the pixel 12B, the voltage at the point c is 1.65 V, there is almost no potential difference between the connected d1 and d2, the sense amplifier becomes insensitive, and a normal determination voltage cannot be output.

For this reason, in FIG. 8, the time during which d1 and d2 change to a predetermined voltage from time t6 (
(B) is longer than A). Since the potential difference at which the sense amplifier starts to operate normally is determined, by adjusting the time from time t6 to time t7 to a certain time (X), (A
) Can be normally inspected, but (B) can be prevented from being inspected normally.

By adopting (A) in which the DRAM is connected and inspected during this X time, the DRAM portion in the pixel cannot be normally inspected if it is open (disconnected). As a result, an open inspection of the DRAM can be performed. Normally, open inspection requires pixel electrodes to be inspected in series via through holes. However, according to the method according to the present invention, the pixel configuration is not changed, so that the pixel pitch can be increased. It is possible to perform an open inspection of the DRAM.

Note that the specific numerical values and the like shown in the respective embodiments described above are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified.

1 liquid crystal display device 12A, 12B pixel CE common electrode LC1, LC2 liquid crystal PE1, PE2 reflective electrode LCM1, LCM2 liquid crystal display element C11, C21 capacitance SW11, SW12, SW21, SW22 switch INV11, INV12, INV21, INV22 inverter d1, d2 column Data line g Row scan line

Claims (2)

A liquid crystal display device comprising a plurality of pixels provided at each intersection where a plurality of column data lines and a plurality of row scanning lines intersect,
The pixel is
A display element in which liquid crystal is filled and sealed between the opposing pixel electrode and the common electrode;
For each frame data of the input video signal, a first switching unit that performs sampling for displaying using a plurality of subframes whose display period is shorter than one frame period via the column data line;
A first holding unit that constitutes an SRAM together with the first switching unit, and in which the first switching unit holds the sampled subframe data;
A second switching unit for outputting the subframe data held by the first holding unit;
The DRAM is configured together with the second switching unit, and the storage content is rewritten by the subframe data held in the first holding unit inputted through the second switching unit, and output data is transferred to the pixel electrode. A second holding unit to be applied;
The sub-frame data is repeatedly written to the first holding unit in units of rows in the plurality of pixels, and after the sub-frame data is written to all of the plurality of pixels, the plurality of pixels are generated by a trigger pulse. An operation of turning on all the second switching units and rewriting the storage contents of the second holding unit of the plurality of pixels by the subframe data held in the first holding unit for each subframe. A pixel control unit for
For each of the plurality of pixels, a first column data line connected to the first switching unit of the first pixel and the second pixel for each pair of the first pixel and the second pixel And a second column data line connected to the first switching unit, and a sense amplifier connected to each of the second column data lines,
A signal written to the pixel electrode through the DRAM is read from the DRAM through the SRAM with the second switching unit turned on, and from the first switching unit through the column data line, and the sense amplifier is A liquid crystal display device characterized by using the pixel inspection. An inspection method for a liquid crystal display device according to claim 1,
A 1-bit inspection signal is input to the first column data line connected to the first switching unit of the first pixel, and connected to the first switching unit of the second pixel. Inputting an inversion signal of the inspection signal to the second column data line,
Latching the test signal in the SRAM of the first pixel and latching the inverted signal in the SRAM of the second pixel;
Turning on the second switching unit of the first pixel and latching the inspection signal latched in the SRAM of the first pixel in the DRAM of the first pixel;
Turning on the second switching unit of the second pixel and latching the inverted signal latched in the SRAM of the second pixel in the DRAM of the second pixel;
Turning on the second switching unit of the first pixel and reading out the inspection signal latched in the DRAM of the first pixel to the SRAM of the first pixel;
Turning on the second switching unit of the second pixel and reading the inverted signal latched in the DRAM of the second pixel into the SRAM of the second pixel;
Supplying the latched test signal to the first column data line and supplying the latched inverted signal to the second column data line;
A method for inspecting a liquid crystal display device, comprising: amplifying a potential difference based on the supplied inspection signal and the supplied inverted signal by the sense amplifier.

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