JP2016218639A - Output circuit, linear regulator using the same, audio amplifier, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit capable of suppressing steep current increase such as inrush current and ground fault current.SOLUTION: An output transistor 102 is a P-channel MOSFET having a drain connected via an output line 206 to a load. A first resistor R1 is provided between an input line 204 and a source of the output transistor 102. A first transistor M1 is a P-channel MOSFET that is provided between the input line 204 and a gate of the output transistor 102, the gate to which a voltage Vof a connection node N1 between the output transistor 102 and the first resistor R1 is inputted.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an output circuit, and more particularly to an overcurrent protection technique thereof.

  The output circuit that supplies a large current to the load monitors the current (output current) that flows through the output transistor, which is a power transistor. When the output current exceeds the threshold, the output transistor is turned off or between the gate and source An overcurrent protection function is provided that reduces the voltage to increase the channel resistance and limit the current.

FIG. 1 is a circuit diagram of an output circuit 100r having an overcurrent protection function studied by the present inventors. The output circuit 100r includes an overcurrent detection circuit 110r and an overcurrent suppression circuit 120r in addition to the output transistor 102. The gate voltage V _G of the output transistor 102 is controlled by the main control circuit 202.

Overcurrent detection circuit 110, the output current _{I OUT} flowing through the output transistor 102 is compared with a predetermined threshold current _{I TH1,} when detecting the overcurrent state of the I _{OUT> I TH1,} it asserts an overcurrent detection signal S1 To do. For example, the overcurrent detection circuit 110 includes a transistor 112 whose gate and source are connected in common with the output transistor 102. The transistor 112, the detected current _{I S} flows in proportion to the current of the output current _{I OUT.} Sense resistor _{R S} is detected current provided on a path of _{I S,} to generate a voltage drop (detection voltage) _{V S} proportional to the output current _{I OUT.} The comparator 114 compares the detection voltage V _S with the threshold voltage V _TH1 corresponding to the threshold current I _TH1 , and when V _S > V _TH1 , in other words, when I _OUT > I _TH1 , The current detection signal S1 is output.

When the overcurrent detection signal S1 is asserted, the overcurrent suppression circuit 120r supplies current to the gate of the output transistor 102 to pull up the gate voltage V _G and increase the resistance of the channel of the output transistor 102. The overcurrent suppression circuit 120 includes a switch 122 that is turned on when the overcurrent detection signal S1 is asserted, and a current mirror circuit 124 that pulls up the gate of the output transistor 102 when the switch 122 is turned on.

According to the output circuit 100r of FIG. 1, in an overcurrent state where I _OUT > I _TH1 , the gate voltage V _G of the output transistor 102 is increased, the resistance of the channel is increased, and the output current I _OUT can be suppressed.

Japanese Patent Laid-Open No. 5-315852 JP 2002-304225 A

As a result of studying the output circuit 100r of FIG. 1, the present inventor has recognized the following problems. Comparator 114 has a finite response speed and therefore some detection delay occurs. There is also a delay from when the overcurrent suppression circuit 120 detects the assertion of the overcurrent detection signal S1 to when the gate voltage V _G of the output transistor 102 rises.

Here, an inrush current may flow from the output transistor 102 immediately after the circuit is started. Alternatively, when the OUT terminal is short-circuited (for example, a ground fault), the output current I _OUT increases. In these situations, since the output current I _OUT changes sharply, the overcurrent protection by the overcurrent detection circuit 110 and the overcurrent suppression circuit 120 in FIG. 1 causes a problem that overcurrent flows due to a response delay. There is.

  The present invention has been made in view of such a problem, and one of exemplary purposes of an aspect thereof is to provide an output circuit capable of suppressing a steep current rise such as an inrush current or a ground fault current.

  One embodiment of the present invention relates to an output circuit. The output circuit includes an output transistor that is a P-channel MOSFET having a load connected to a drain via an output line, a first resistor provided between the input line and the source of the output transistor, and a gate of the input line and the output transistor. And a first transistor which is a P-channel MOSFET whose gate is supplied with the output transistor and the voltage of the connection node of the first resistor.

As the output current flowing through the output transistor increases, the voltage drop across the first resistor increases, thereby reducing the channel resistance of the first transistor. As a result, the gate voltage of the output transistor increases, the gate-source voltage decreases, the channel resistance increases, and the output current is suppressed. In other words, since the first transistor has both an overcurrent detection function and an overcurrent suppression function, the responsiveness can be improved compared to a circuit in which these functions are assigned to individual circuits, and a steep current such as an inrush current can be obtained. The rise can be suppressed.
Further, when the resistance value of the first resistor increases due to variations, the output current is thereby reduced. However, since the voltage drop of the first resistor is reduced at this time, the degree of protection (current suppression amount) is weakened. On the other hand, if the resistance value of the first resistor decreases due to variations, the output current increases, but the voltage drop of the first resistor increases, so the degree of protection increases. Therefore, high stability (robustness) can be realized against fluctuations in the resistance value of the first resistor.

In one embodiment, the output circuit may further include a second resistor provided in series with the first transistor between the input line and the gate of the output transistor.
The amount of current suppression can be adjusted according to the resistance value of the second resistor.

In one aspect, the first resistor may be configured with a wiring resistance.
As described above, since the stability against variations in the first resistance is high, a wiring resistance can be used, and a minute resistance can be formed.

The output circuit of an aspect may further include a second transistor provided in series with the first transistor between the input line and the gate of the output transistor.
In this case, the suppression of overcurrent by the first transistor can be validated / invalidated according to on / off of the second transistor.

In one aspect, the output circuit includes an overcurrent detection circuit that generates an overcurrent detection signal that is asserted when a current flowing through the output transistor exceeds a first threshold current, and an output transistor when the overcurrent detection signal is asserted. And an overcurrent suppression circuit that increases the gate voltage of the first and second gates.
When the overcurrent suppression by the first transistor is insufficient, reliable protection can be realized by adding an overcurrent detection circuit and an overcurrent suppression circuit.

In one embodiment, the output circuit may further include a second transistor that is provided in series with the first transistor between the input line and the gate of the output transistor and is turned on when the overcurrent detection signal is asserted.
As a result, while the normal overcurrent protection is performed by the overcurrent suppression circuit, the second transistor suppresses the output current exceeding the first threshold current in the case of an inrush current or an output line short-circuit (especially a ground fault). It can be carried out.

In one aspect, the output circuit includes an overcurrent detection circuit that generates an overcurrent detection signal that is asserted when a current flowing through the output transistor exceeds a first threshold current, and an output circuit between the input line and the gate of the output transistor. And a second transistor that is provided in series with one transistor and is turned on when the overcurrent detection signal is asserted.
Thereby, suppression by the first transistor can be limited to a region where the output current is higher than the first threshold current.

  The first threshold current may be smaller than a second threshold current at which the first transistor begins to turn on. Thereby, a normal overcurrent state can be suppressed by the overcurrent suppression circuit, and a steep and large current can be suppressed by the first transistor.

  The first threshold current may be greater than a second threshold current at which the first transistor begins to turn on.

  The overcurrent detection circuit includes a third transistor having a common gate and source connected to the output transistor, a third resistor provided between the drain of the third transistor and the ground line, and a voltage drop across the third resistor. A comparator that generates an overcurrent detection signal by comparing with a first threshold voltage corresponding to one threshold current.

  In one aspect, the first threshold voltage may be a predetermined voltage. The first threshold voltage may be generated by dividing the voltage of the input line.

  In one aspect, the first threshold voltage may be a voltage corresponding to the output voltage of the output line. The first threshold voltage may be generated by dividing the output voltage. As a result, it is possible to realize a U-shaped characteristic, a drooping characteristic, and an inverted L-shaped characteristic.

  The overcurrent suppression circuit includes a fourth transistor in which an overcurrent detection signal is input to the gate / base and the source / emitter is grounded, a current mirror circuit that folds the current flowing through the fourth transistor and supplies the current to the gate of the output transistor , May be included.

The overcurrent suppression circuit may further include a fourth resistor provided between the current mirror circuit and the fourth transistor.
The amount of current suppression by the overcurrent suppression circuit can be adjusted according to the resistance value of the fourth resistor.

The output circuit may be integrated on a single semiconductor substrate.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Another aspect of the present invention relates to a linear regulator. The linear regulator includes any one of the output circuits described above and an error amplifier that adjusts the gate voltage of the output transistor of the output circuit so that the feedback voltage according to the voltage of the output line of the output circuit approaches the reference voltage. May be.

  Another embodiment of the present invention relates to an audio amplifier circuit. This audio amplifier circuit may include any of the output circuits described above.

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to suppress a steep current increase such as an inrush current or a ground fault current.

It is a circuit diagram of an output circuit provided with the overcurrent protection function which this inventor examined. 1 is a circuit diagram of a semiconductor device including an output circuit according to a first embodiment. FIG. 3 is an operation waveform diagram when the semiconductor device of FIG. 2 is activated. It is a circuit diagram of the semiconductor device concerning a comparison technique. It is a circuit diagram of a semiconductor device provided with the output circuit concerning a 2nd embodiment. It is a circuit diagram of a linear regulator provided with a semiconductor device. It is a circuit diagram of an audio output circuit provided with a semiconductor device.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

(First embodiment)
FIG. 2 is a circuit diagram of the semiconductor device 200 including the output circuit 100 according to the first embodiment. The semiconductor device 200 is a functional IC integrated on a semiconductor substrate. A DC voltage _VIN is supplied from the outside to the input terminal (IN). The semiconductor device 200 supplies the generated output voltage _VOUT to a load (not shown) connected to the output terminal (OUT).

The semiconductor device 200 includes an output circuit 100 and a control circuit 202. The output transistor 102 of the output circuit 100 is provided between the input line 204 and the output line 206. The control circuit 202 controls the gate voltage V _G of the output transistor 102 so that a desired output voltage V _OUT is obtained.

In addition to the output transistor 102, the output circuit 100 includes a first resistor R1, a first transistor M1, and a second resistor R2. The output transistor 102 is a P-channel MOSFET, and a load (not shown) is connected to its drain via an output line 206. The first resistor R <b> 1 is provided between the input line 204 and the source of the output transistor 102. The resistance value of the first resistor R1 is denoted as r. The first transistor M1 is a P-channel MOSFET, and is provided between the input line 204 and the gate of the output transistor 102. The voltage V _N1 of the connection node N1 between the output transistor 102 and the first resistor R1 is input to the gate of the first transistor M1.

  The second resistor R2 is provided in series with the first transistor M1 between the input line 204 and the gate of the output transistor 102.

  The above is the configuration of the semiconductor device 200 including the output circuit 100. Next, the operation will be described.

  FIG. 3 is an operation waveform diagram at the time of startup of the semiconductor device 200 of FIG. The vertical axis and horizontal axis of the waveform diagrams and time charts in this specification are appropriately expanded and reduced for easy understanding, and each waveform shown is also simplified for easy understanding. Or it is exaggerated or emphasized.

  In FIG. 3, the operation when overcurrent suppression is not performed is indicated by a broken line, and the inrush current suppression operation is indicated by a solid line. First, generation of an inrush current will be described with reference to a broken line.

A large capacity capacitor is connected to the OUT terminal. At time t0, the input voltage V _IN is supplied to the IN terminal, the semiconductor device 200 is activated, and the gate voltage V _G is controlled so that the output voltage V _OUT at the OUT terminal becomes a desired voltage level. Immediately after startup, the charge of the capacitor connected to the OUT terminal is zero, and a large output current _IOUT flows to charge the capacitor. This is the inrush current.

Subsequently, an inrush current suppressing operation will be described with reference to a solid line.
At time t0, the semiconductor device 200 is activated, and the output current I _OUT increases sharply. When the output current I _OUT increases, the voltage drop r × I _{OUT of} the first resistor R1 increases, and thus the gate-source voltage V _{GS1 of} the first transistor M1 increases. When the voltage drop r × I _{OUT of} the first resistor R1 exceeds the gate-source threshold voltage V _{GS (TH)} of the first transistor M1, the first transistor M1 is turned on, and the output current I _OUT further increases. The resistance value of the channel decreases.

That is, the threshold current I _TH2 for overcurrent protection in the semiconductor device 200 is given by the following equation (1).
I _TH2 = V _{GS (TH)} / r (1)

As the channel resistance value decreases, a current is supplied to the gate of the output transistor 102 via the second resistor R2 and the first transistor M1, and the gate voltage V _G becomes higher than that of the one-dot chain line. As a result, the gate-source voltage V _{GS of} the output transistor 102 decreases, and an increase in the output current I _OUT is suppressed.

  In the normal operation state, even when the OUT terminal is grounded, overcurrent is prevented by the same operation.

  The above is the operation of the semiconductor device 200. In the output circuit 100, since the first transistor M1 has both an overcurrent detection function and an overcurrent suppression function, the responsiveness can be improved compared to the circuit of FIG. 1 in which these functions are assigned to individual circuits. A steep current rise such as an inrush current at start-up and a ground fault current at output short-circuit can be suppressed.

Further, when the resistance value r of the first resistor R1 is increased by the variation, since thereby the output current _{I OUT} decreases, the voltage drop r × _{I OUT} of the first resistor R1 at this time is decreased, the first transistor M1 channel resistance is increased, the degree of lost small, rise of the gate voltage V _G protection (current suppression amount) is weakened. When the resistance value r of the first resistor R1 is reduced by the variation in the opposite, but the output current I _OUT is it increases, the voltage drop r × I _OUT of the first resistor R1 is increased, the channel of the first transistor M1 resistance decreases, increasing the width of the gate voltage V _G is increased, the degree of protection becomes strong. Therefore, the stability (robustness) is high with respect to variations and fluctuations in the resistance value r of the first resistor R1.

The robustness with respect to the variation of the resistance value r of the first resistor R1 becomes clear by comparison with the comparison technique of FIG. FIG. 4 is a circuit diagram of the semiconductor device 200s according to the comparative technique. FIG. 4 is a circuit diagram of a semiconductor device 200s including the overcurrent detection circuit 110s according to the comparison technique. The overcurrent detection circuit 110s includes a resistor R11, a current source CS1, and a comparator 114. The current source CS1 generates a constant current I _C1 and generates a voltage drop R × I _C1 at the resistor R11. R is the resistance value of the resistor R11. The comparator 114, the voltage _{V N2} at the connection node N2 of the resistor R11 and the current source CS1, and compared with the voltage _{V N1} at the connection node _N1, asserts an overcurrent detection signal S1 when the V N1 _{<V N2.}
The voltages V _N1 and V _N2 of the connection nodes N1 and N2 are given by equations (2) and (3), respectively.
V _N1 = V _IN −I _OUT × r (2)
V _N2 = V _IN −I _C1 × R (3)
Therefore, overcurrent suppression by the overcurrent suppression circuit 120 is performed with reference to the threshold current _ITH1 of the equation (4).
I _TH1 = I _C1 × R / r (4)

In this comparative technique, if the resistance value of the first resistor R1 varies, the threshold current _ITH1 varies while the degree of protection by the overcurrent suppressing circuit 120 remains constant, and thus the resistance value r of the first resistor R1. Variations and fluctuations greatly affect circuit operation. On the other hand, in the output circuit 100 according to the embodiment, the threshold current I _{TH2 in} the equation (1) varies according to the resistance value of the first resistor R1, and accordingly, the degree of overcurrent suppression is also increased. Since it changes, the robustness can be improved.

As described above, since the robustness against variations in the first resistance R1 is high, the first resistance R1 can be configured by a wiring resistance. The wiring resistance can be formed using aluminum wiring, copper wiring, bonding wire, via hole (through hole), or the like. The first resistor R1, the output at generating heat loss by the product of the current I _OUT, can be hundreds mΩ~ several Ω and the minute value the resistance value of the first resistor R1 by the wiring resistance, Circuit loss can be reduced.

  By providing the second resistor R2 provided in series with the first transistor M1 between the input line 204 and the gate of the output transistor 102, the amount of current suppression can be adjusted according to the resistance value. That is, if the resistance value of the second resistor R2 is increased, the amount of current supplied to the gate of the output transistor 102 via the second resistor R2 and the first transistor M1 in the overcurrent state can be reduced, and thus the suppression effect. Becomes smaller. On the contrary, if the resistance value of the second resistor R2 is lowered, the amount of current supplied to the gate of the output transistor 102 via the second resistor R2 and the first transistor M1 can be increased in the overcurrent state, and thus suppressed. The effect can be enhanced.

(Second Embodiment)
FIG. 5 is a circuit diagram of a semiconductor device 200a including the output circuit 100a according to the second embodiment. The semiconductor device 200a includes an overcurrent detection suppression circuit 130, an overcurrent detection circuit 110, and an overcurrent suppression circuit 120 in addition to the output transistor 102 and a control circuit (not shown).

The overcurrent detection suppression circuit 130 includes a first resistor R1, a first transistor M1, and a second resistor R2. Its configuration and operation are as described in the first embodiment. The overcurrent detection suppression circuit 130 further includes a second transistor M2 provided in series with the first transistor M1. The second transistor M2 is provided to switch the overcurrent detection suppression circuit 130 on (enable) and off (disable). In the state where the second transistor M2 is off, the suppression operation by the overcurrent detection suppression circuit 130 does not occur regardless of the voltage V _N1 of the connection node N1.

When the output current I _OUT flowing through the output transistor 102 exceeds the first threshold current I _TH1 , the overcurrent detection circuit 110 asserts the overcurrent detection signal S1 (for example, high level). The overcurrent suppression circuit 120 increases the gate voltage V _G of the output transistor 102 when the overcurrent detection signal S1 is asserted.

The first threshold current I _TH1 in the overcurrent detection circuit 110 is set smaller than the second threshold current I _{TH2 at} which the first transistor M1 starts to turn on.

When the overcurrent suppression by the first transistor M1 is insufficient, reliable protection can be realized by adding the overcurrent detection circuit 110 and the overcurrent suppression circuit 120. In particular, in the output circuit 100 of FIG. 2, when the resistance value r of the first resistor R1 is smaller than the combined resistance value of 1 / gm (gm is transconductance) of the output transistor 102 and the output load resistor _RLOAD , the current The effect of suppression is diminished. Such a configuration of FIG. 5 is suitable for an application.

  An inverted signal of the overcurrent detection signal S1 may be input to the gate of the second transistor M2. As a result, in the state where the overcurrent detection signal S1 is asserted, the second transistor M2 is turned on, and the suppression operation by the overcurrent detection suppression circuit 130 becomes effective.

That is, the second threshold value in which the output current I _OUT is larger than the first threshold current I _TH1 when the inrush current or the output line is short-circuited (especially ground fault) while performing the normal overcurrent protection by the overcurrent suppression circuit 120. In a state where the current _ITH2 is exceeded, suppression by the first transistor M1 can be performed.

  The overcurrent detection circuit 110 includes a third transistor M3, a third resistor R3, a comparator 114, and resistors R21 and R22. The third transistor M3 is a P-channel MOSFET of the same type as the output transistor 102, and the output transistor 102, the gate and the source are connected in common. The third resistor R3 is provided between the drain of the third transistor M3 and the ground line 208.

The comparator 114 compares the voltage drop of the third resistor R3 with the first threshold voltage V _TH1 corresponding to the first threshold current I _TH1 and generates an overcurrent detection signal S1. The resistors R21 and R22 divide the voltage _VIN of the input line 204 to generate a threshold voltage _VTH1 .

  The overcurrent suppression circuit 120 includes a fourth transistor M4, a fourth resistor R4, and a current mirror circuit 124.

  The fourth transistor M4 is an N-channel MOSFET (or NPN bipolar transistor), and an overcurrent detection signal S1 is input to the gate / base, and the source / emitter is grounded. The current mirror circuit 124 turns back the current flowing through the fourth transistor M4 and supplies it to the gate of the output transistor 102. The fourth resistor R4 is provided between the input of the overcurrent suppressing circuit 120 and the fourth transistor M4.

When the overcurrent detection signal S1 is asserted, the fourth transistor M4 is turned on. At this time, the current mirror circuit 124 supplies a current proportional to the current flowing through the fourth resistor R4 and the fourth transistor M4 to the gate of the output transistor 102, and pulls up the gate voltage V _G of the output transistor 102. The pull-up amount can be set according to the resistance value of the fourth resistor R4.

Next, the application of the semiconductor device 200 will be described.
1. Linear Regulator FIG. 6 is a circuit diagram of a linear regulator 300 including the semiconductor device 200b. An output capacitor C31 is connected to the OUT terminal. The output voltage _VOUT of the linear regulator is divided by resistors R31 and R32 and input to a feedback (FB) terminal. The control circuit 202b includes an error amplifier 210. The error amplifier 210 receives the feedback voltage V _FB corresponding to the reference voltage V _REF and the output voltage V _OUT , and adjusts the gate voltage V _G of the output transistor 102 so that the error approaches zero.

  The configuration of the output circuit 100 is the same as that in FIG. Or you may combine with the output circuit 100a of FIG. According to the linear regulator 300 of FIG. 6, the inrush current to the output capacitor C31 at the time of start-up can be suppressed, and / or the overcurrent at the time of a ground fault of the OUT terminal can be suppressed.

2. Audio Amplifier Circuit FIG. 7 is a circuit diagram of an audio output circuit including the semiconductor device 200c. The semiconductor device 200c is an audio amplifier circuit, and forms an audio output circuit 400 together with an external filter 402 and an electroacoustic transducer 404 such as a speaker or headphones. The output circuit 100c is a push-pull type output stage of the audio amplifier circuit. The output circuit 100c includes a low-side output transistor 104 in addition to the output circuit 100 of FIG. 2 or the output circuit 100a of FIG. The control circuit 202 receives the analog audio signal S2 and controls the gate voltages V _GH and _VGL of the output transistors 102 and 104 so that the voltage _VOUT corresponding to the analog audio signal S2 is generated at the OUT terminal. The audio amplifier circuit may be a class A or class AB linear amplifier or a class D amplifier (switching amplifier).

  According to the audio amplifier circuit 200c of FIG. 7, the inrush current to the capacitor C41 of the filter at the time of activation can be suppressed, and / or the overcurrent at the time of grounding of the OUT terminal can be suppressed.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
As shown in FIG. 5, in the configuration in which the overcurrent detection suppression circuit 130 and the overcurrent detection circuit 110 are used together, the first threshold current I _TH1 is the second threshold current I _{TH2 at which} the first transistor M1 starts to turn on. It may be larger. In this case, the second transistor M2 may be omitted.

(Second modification)
In FIG. 5, the first threshold voltage V _TH1 may be a variable voltage corresponding to the voltage V _OUT of the output line 206, and may be generated by, for example, dividing the output voltage V _OUT . Thereby, the overcurrent protection of the U-shaped characteristic and the drooping characteristic can be realized.

(Third Modification)
The application of the semiconductor device 200 is not limited to a linear regulator or an audio amplifier. For example, the semiconductor device 200 can be applied to various applications having a power transistor in the output stage, such as a motor driver or a control circuit for a switching regulator.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Output circuit, 102, 104 ... Output transistor, M1 ... 1st transistor, M2 ... 2nd transistor, M3 ... 3rd transistor, M4 ... 4th transistor, R1 ... 1st resistance, R2 ... 2nd resistance, R3 ... third resistor, R4 ... fourth resistor, 110 ... overcurrent detection circuit, 112 ... transistor, 114 ... comparator, R S _... sense resistor, 120 ... overcurrent suppressing circuit, 122 ... switch, 124 ... current mirror circuit, 130 ... Overcurrent detection suppression circuit, S1 ... Overcurrent detection signal, 200 ... Semiconductor device, 202 ... Control circuit, 204 ... Input line, 206 ... Output line, 208 ... Ground line, 210 ... Error amplifier, 300 ... Linear regulator, 400 ... Audio output circuit 402 ... filter 404 ... electroacoustic transducer.

Claims (18)

An output transistor that is a P-channel MOSFET with a load connected to the drain via an output line;
A first resistor provided between an input line and the source of the output transistor;
A first transistor which is provided between the input line and the gate of the output transistor, and is a P-channel MOSFET into which the voltage of the connection node between the output transistor and the first resistor is input;
An output circuit comprising:   The output circuit according to claim 1, further comprising a second resistor provided in series with the first transistor between the input line and the gate of the output transistor.   The output circuit according to claim 1, wherein the first resistor includes a wiring resistor.   4. The output circuit according to claim 1, further comprising a second transistor provided in series with the first transistor between the input line and the gate of the output transistor. 5. An overcurrent detection circuit that generates an overcurrent detection signal that is asserted when a current flowing through the output transistor exceeds a first threshold current;
When the overcurrent detection signal is asserted, an overcurrent suppression circuit that increases the gate voltage of the output transistor;
The output circuit according to claim 1, further comprising:   The apparatus further comprises a second transistor provided in series with the first transistor between the input line and the gate of the output transistor, and turned on when the overcurrent detection signal is asserted. 5. The output circuit according to 5. An overcurrent detection circuit that generates an overcurrent detection signal that is asserted when a current flowing through the output transistor exceeds a first threshold current;
A second transistor provided in series with the first transistor between the input line and the gate of the output transistor, and turned on when the overcurrent detection signal is asserted;
The output circuit according to claim 1, further comprising:   8. The output circuit according to claim 6, wherein the first threshold current is smaller than a second threshold current at which the first transistor starts to turn on.   6. The output circuit according to claim 5, wherein the first threshold current is larger than a second threshold current at which the first transistor starts to turn on. The overcurrent detection circuit includes:
A third transistor having a gate and a source connected in common to the output transistor;
A third resistor provided between the drain of the third transistor and a ground line;
A comparator that compares the voltage drop of the third resistor with a first threshold voltage corresponding to the first threshold current to generate the overcurrent detection signal;
The output circuit according to claim 5, further comprising:   The output circuit according to claim 10, wherein the first threshold voltage is a predetermined voltage.   The output circuit according to claim 10, wherein the first threshold voltage is a voltage corresponding to a voltage of the output line. The overcurrent suppression circuit is
A fourth transistor in which the overcurrent detection signal is input to the gate / base and the source / emitter is grounded;
A current mirror circuit that folds the current flowing through the fourth transistor and supplies it to the gate of the output transistor;
The output circuit according to claim 5, further comprising:   The output circuit according to claim 13, wherein the overcurrent suppression circuit further includes a fourth resistor provided between the current mirror circuit and the fourth transistor.   15. The output circuit according to claim 1, wherein the output circuit is monolithically integrated on a single semiconductor substrate. An output circuit according to any one of claims 1 to 15,
An error amplifier that adjusts a gate voltage of the output transistor of the output circuit so that a feedback voltage according to a voltage of the output line of the output circuit approaches a reference voltage;
A linear regulator comprising:   An audio amplifier comprising the output circuit according to claim 1.   A semiconductor device comprising the output circuit according to claim 1.

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