JP2016115979A - Image processing apparatus, control method and program thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mechanism for confining power consumption of a device in a predetermined range, when partially reconstituting other region while one region is operating, in a system using dynamic partial reconstitution.SOLUTION: An image processing apparatus has a reconstitution circuit including a plurality of partial reconstitution parts, and capable of reconstituting the circuitry dynamically and partially. Furthermore, the image processing apparatus calculates the total value of the value of power consumption of the partial reconstitution parts under operation, and the value of additional power required for reconstitution, when reconstituting the partial reconstitution parts of a part of the reconstitution circuit, determines whether or not the total value thus calculated is confined in the value of allowable power, and performs reconstitution of the reconstitution circuit when a determination is made that the total value thus calculated is confined in the value of allowable power.SELECTED DRAWING: Figure 7

Description

  The present invention relates to an image processing apparatus that handles image data, a control method thereof, and a program.

  Reconfigurable circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) capable of changing the configuration of an internal logic circuit are well known. Generally, PLD and FPGA logic circuit changes are realized by writing circuit configuration information stored in non-volatile memory such as ROM into configuration memory, which is volatile memory inside PLD or FPGA, at startup. Is done. Since the information in the configuration memory is cleared when the power is turned off, it is necessary to write the circuit configuration information stored in the ROM again in the configuration memory when the power is turned on. In this way, a method of configuring a PLD or FPGA logic circuit only once while power is supplied is called static reconfiguration. On the other hand, an FPGA or the like that can dynamically change the configuration of a logic circuit while the logic circuit is operating has been developed, and such a method of dynamically changing a logic circuit is called dynamic reconfiguration.

  Some FPGAs can rewrite only the circuit configuration of a specific area, not the circuit configuration of the entire FPGA chip, and such rewriting is called partial reconfiguration. In particular, changing other circuit configurations without stopping the operation of the circuit in operation is called dynamic partial reconfiguration. In dynamic partial reconfiguration, it is possible to partially reconfigure the FPGA logic circuit by rewriting only a partial area of the configuration memory instead of rewriting the entire configuration memory at the time of dynamic reconfiguration. it can. By using such dynamic partial reconfiguration, for example, a plurality of logic circuits can be switched and mounted in a certain area of the FPGA in a time division manner. As a result, with a small amount of hardware resources, various functions can be flexibly realized while maintaining high-speed computing performance by hardware.

  In addition, an image processing apparatus such as an MFP (Multi Function Printer) can select a plurality of processes (copy job, print job, SEND job, etc.) according to a request from the user. It is realized by hardware or software. When a part of the image processing function in the MFP is processed by an FPGA that can be dynamically reconfigured, generally, the execution timing for the dynamic reconfiguration to the FPGA is the timing at which the processing content is determined by a request from the user. . After the logic circuit information corresponding to the processing content is written in the configuration memory, a series of processing according to the request from the user can be performed.

  By the way, the logic circuit of the FPGA consumes power depending on the operating state, the scale of the operating logic circuit, and the operating frequency. However, a large amount of power is required in the process of reconfiguring the logic circuit in the FPGA. In general, in a logic circuit such as LSI or FPGA, if a large amount of power is consumed rapidly, a voltage drop occurs in the voltage used in the circuit, and if a voltage fluctuation exceeding a predetermined range occurs during circuit operation, The inside circuit may malfunction. As a method for dealing with the power consumption at the time of reconfiguration, in Patent Document 1, the reconfiguration processing is time-divided from the time until the next use of the circuit, and the reconfiguration processing is sequentially executed for each divided portion. It is described to do. This makes it possible to level the power consumption peak in the reconstruction process.

JP 2010-79726 A

  However, the above prior art has the following problems. For example, in the above prior art, since control including the power state other than the circuit to be reconfigured is not performed, a large amount of power is consumed outside the circuit to be reconfigured. A malfunction of the circuit during operation due to power consumption cannot be avoided. In other words, although the power required for the reconstruction process is small, the power consumed by other processes executed in parallel is large, and thus voltage fluctuations exceeding a predetermined range may occur during the reconstruction process. . In order to achieve a hardware configuration corresponding to such a case, it is necessary to reinforce the power supply IC and change the FPGA package, resulting in an increase in cost.

  The present invention has been made in view of the above-described problems, and in a system using dynamic partial reconfiguration, when a part of a region partially operates while another part is in operation, an apparatus is provided. An object is to provide a mechanism for keeping the power consumption within a predetermined range.

  The present invention is an image processing apparatus including a plurality of partial reconfiguration units and having a reconfiguration circuit capable of dynamically and partially reconfiguring a circuit configuration, wherein the image processing apparatus includes a part of the reconfiguration circuit. A calculating means for calculating a total value of a power consumption value of the partial reconfiguring section in operation and a value of additional power necessary for reconfiguration when reconfiguring the partial reconfiguring section; And a power determination unit that determines whether or not the total value calculated by the method falls within an allowable power value, and the power determination unit determines that the total value falls within the allowable power value. Reconfiguration means for executing reconfiguration.

  According to the present invention, in a system using dynamic partial reconfiguration, the power consumption of an apparatus is kept within a predetermined range when a part of a region is partially reconfigured while another region is operating. Can do.

1 is a block diagram illustrating an example of a configuration of an image processing apparatus according to a first embodiment. The block diagram which shows an example of a structure of the dynamic reconstruction part which concerns on 1st Embodiment. The block diagram which shows an example of the block diagram comprised by the dynamic reconstruction part in the use case 1 which concerns on 1st Embodiment. The figure which shows an example of the operating power management table which concerns on 1st Embodiment. The figure which shows an example of the power management table at the time of partial reconstruction which concerns on 1st Embodiment. The flowchart which shows the dynamic reconfiguration control flow which concerns on 1st Embodiment. The slow chart which shows the reconstruction sequence determination flow which concerns on 1st Embodiment. The flowchart which shows the control decision flow to the circuit in operation | movement which concerns on 1st Embodiment. The flowchart which shows the control decision flow of the reconstruction process which concerns on 1st Embodiment. The figure which shows the power consumption at the time of applying based on 1st Embodiment. The block diagram which shows an example of the block diagram comprised by the dynamic reconstruction part in the use case 2 which concerns on 1st Embodiment. The slow chart which shows the reconstruction sequence determination flow which concerns on 2nd Embodiment. The figure which shows the power consumption at the time of applying based on 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the present embodiments are not necessarily essential to the solution means of the present invention. .

<First Embodiment>
<Configuration of image processing apparatus>
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. First, the configuration of an image processing apparatus according to an embodiment of the present invention will be described with reference to FIG. In the present embodiment, a multifunction device (multifunctional processing device) having a scanner unit and a printer unit will be described as an example of the image processing device 100. The image processing apparatus 100 is realized by, for example, a multi-function processing apparatus (MFP) that is a multifunction machine that realizes a plurality of types of functions.

  The image processing apparatus 100 according to the present embodiment displays an operation unit 104 for a user using the image processing apparatus 100 to perform various operations, the state of the image processing apparatus 100, and operation buttons operated by the user. And a display unit 102. Note that the operation unit 104 and the display unit 102 may be provided integrally using a touch panel method. The image processing apparatus 100 further includes a reader unit 105 that reads image information from a document in accordance with an instruction from the operation unit 104, and a printer unit 107 that prints image data on paper. The reader unit 105 includes a CPU for controlling the reader unit 105, an illumination lamp for scanning a document, a scanning mirror, and the like. The printer unit 107 includes a CPU that controls the printer unit 107, and a photosensitive drum and a fixing device that perform image formation and fixing. The image processing apparatus 100 further includes a dynamic reconfiguration unit (reconfiguration circuit) 120 that can change the function using the logic circuit configuration information and is implemented by an FPGA or the like.

  The image processing apparatus 100 also includes a controller unit 101 that comprehensively controls the operation of the image processing apparatus 100. The controller unit 101 includes a CPU 111, and the CPU 111 executes control software for controlling each unit of the image processing apparatus. The controller unit 101 and the dynamic reconfiguration unit 120 can be connected via an interconnect 112 implemented by PCI-Express or the like to exchange various data. Furthermore, the dynamic reconfiguration unit 120 can receive image data obtained by reading a document from the reader unit 105 via the video bus 113.

  The image processing apparatus 100 includes a ROM 109 that stores a boot program executed by the CPU 111. The image processing apparatus 100 includes a RAM 110 that is a system work memory for the CPU 101 to operate and is also an image memory for temporarily storing image data. The RAM 111 is also a memory for copying, storing, and reading out the logic circuit configuration information stored in the storage unit 106 at high speed. Furthermore, the image processing apparatus 100 includes a storage unit 106 that stores a plurality of pieces of logic circuit configuration information for configuring the dynamic reconfiguration unit 120 implemented by an FPGA or the like. The storage unit 106 is realized by, for example, an HDD or an SD card. The controller unit 101 can perform image processing on the image data read by the reader unit 105 and store the image data in the storage unit 106, and can further store operation history data and user information data of the image processing apparatus 100. The controller unit 101 further performs various data processing such as correction, processing, editing, and analysis on the various data stored in the storage unit 105. The image processing apparatus 100 is connected to a network via the network I / F unit 108, and using this network, image data, various information, and logic circuit configuration information are exchanged with external devices connected to the network. Can be exchanged.

  The image processing apparatus 100 also includes a ROM 121, a RAM 122, and a camera unit 123 that are connected to the dynamic reconfiguration unit 120. The ROM 121 stores logic circuit configuration information for configuring the dynamic reconfiguration unit 120. The RAM 122 is a temporary storage area for various data used by the dynamic reconfiguration unit 120, and is a memory that stores logic circuit configuration information used for dynamic and partial reconfiguration processing described later. The camera unit 123 is connected to the dynamic reconfiguration unit 120 via a bus implemented by USB or the like, has a CCD and various sensors, and obtains image data and sensor output in accordance with instructions from the dynamic reconfiguration unit 120. Can do.

<Dynamic reconfiguration unit>
Next, a detailed configuration of the dynamic reconfiguration unit 120 will be described with reference to FIG. The dynamic reconfiguration unit 120 is a PR (partial reconfiguration area reconfigured by the communication I / F 211, the memory controller 207, the reader I / F 209, the USB I / F 208, the reconfiguration control unit 212, and the reconfiguration control unit 212. (Partial Reconfigurable Area) 201, 202, 203, 204, 205, 206, and a clock control unit 213.

  The communication I / F 211 constitutes an input / output unit for signals and communication packets transmitted / received to / from the controller unit 101 and controls communication with the controller unit 101. The communication I / F 211 is implemented by a standard such as PCI-Express, for example. The memory controller 207 controls writing and reading operations to the RAM 122 performed via the system bus 210. A reader I / F 209 is connected to the reader unit 105 that reads image data from a document via the video bus 113, receives the image data from the reader unit 105, and transfers the image data via the system bus 210.

  The USB I / F 208 is an I / F unit for the dynamic reconfiguration unit 120 to communicate with other devices such as a camera via the USB. According to the present embodiment, the USB I / F 208 is connected to the camera unit 123 and performs control of the camera unit 123 and control of receiving image data and sensor information from the camera unit 123.

  The reconfiguration control unit 212 uses the logic circuit configuration information stored in the ROM 121 or the RAM 122 or the logic circuit configuration information transferred from the controller unit 101 via the communication I / F 211 to configure each PR configuration (circuit configuration). Control). The clock control unit 213 controls various clocks supplied by the dynamic reconfiguration unit 120. Various clocks to be supplied include a transfer clock used in each I / F unit, an operation clock used in each PR, a reconfiguration clock used when the reconfiguration control unit 212 and each PR are reconfigured, etc. 213 can change the frequency or cut off.

  Partial reconfiguration areas PR201, 202, 203, 204, 205, and 206 are reconfigured into logic circuits in which some PRs are reconfigured to perform other functions while some PRs are operating. Is possible. The reconfigured logic circuit depends on the logic circuit configuration information, and the logic circuit configuration information is selected by the control of the controller unit 101 via the reconfiguration control unit 212. According to this embodiment, circuits other than the partial reconfiguration regions PR201, 202, 203, 204, 205, and 206 are configured only once when power is turned on, and are not dynamically reconfigured.

<Configuration Example of Logic Circuit Configured in Dynamic Reconfiguration Unit 120>
Next, an example of a logic circuit configured in the dynamic reconfiguration unit 120 in the image processing apparatus 100 according to the present embodiment will be described with reference to FIG.

  The image processing apparatus 100 performs necessary processing mainly in the controller unit 101 in accordance with the function selected by the user via the operation unit 104. When using a function that the controller unit 101 does not have or a function for reducing the software load of the controller unit, configure necessary circuits in the PRs 201, 202, 203, 204, 205, and 206 in the dynamic reconfiguration unit 120. Can be processed.

  Reference numeral 301 denotes a case where the dynamic reconfiguration unit 120 includes an AFC (affine transformation) in PR 205, a FILA (affine transformation filter) in PR 206, and a SENS (sensor input periodic checker) in PR 201. In this configuration, the controller unit 101 performs image processing on image data transferred from the storage unit 106 to the RAM 122 connected to the dynamic reconfiguration unit 120 and transferred via the communication I / F 211. Specifically, the rotation processing is performed by AFC, the target filter calculation processing such as edge enhancement is performed by FILA, and the image data after the image processing is written back to the RAM 122. The controller unit 101 that has detected the completion of processing transfers the image data in the RAM 122 to the storage unit 106. On the other hand, the SENS periodically checks data input via the USB I / F 208, and performs processing to notify the controller unit 101 via the communication I / F when detecting an input of a predetermined pattern.

  Reference numeral 302 denotes a case where ZS (image area separation) is configured in PR202, PR203, and PR204 in addition to the circuit configuration of 301. Since ZS has a large logic circuit scale, a plurality of regions PR202, PR203, and PR204 are used to form circuits as ZS1, ZS2, and ZS3, respectively. The ZS detects whether each pixel included in the image data read by the reader unit 105 is a character or a photograph, and stores the detected result in the RAM 122 as image area data, and then the controller unit 101 stores the storage unit 106. Forward to. By performing subsequent image processing using the image area data, it is possible to perform image processing that is suitable for the characteristics of the image data.

  Each PR has a register unit that can receive an instruction from the controller unit 101, and can perform each process based on a set value that is instructed and stored in the register unit. In the present embodiment, AFC, FILA, SENS, ZS, and the like are given as the logic circuit to be reconfigured. However, the logic circuit may be any type of processing. Even with the same function, logic circuits with different processing parameters may be configured, or different logic circuits may be configured for RGB image data or monochrome images.

<Reconfiguration control flow to the dynamic reconfiguration unit 120>
A reconfiguration control flow to the dynamic reconfiguration unit 120 in the image processing apparatus 100 according to the present embodiment will be described with reference to FIGS. 6 and 7 are diagrams for explaining the procedure of the dynamic reconfiguration control performed by the CPU 111 of the controller unit 101. FIG. First, a processing flow performed by the CPU 111 of the controller unit 101 in order to shift from the circuit configuration illustrated in 301 to the circuit configuration illustrated in 302 will be described with reference to FIG. Note that the processing described below is realized by the CPU 111 reading a control program stored in the ROM 109 or the storage unit 106 into the RAM 110 and executing it. In 301, PR201, PR205, and PR206 are operating as described above. At this time, in order to perform scanning according to a request from the user, the circuit configuration is shifted to a circuit configuration including ZS indicated by 302. This transition of the circuit configuration state is referred to as use case 1.

  In step S <b> 601, the CPU 111 confirms the current use area in the partial reconfiguration area PR of the dynamic reconfiguration unit 120. At the time of 301, PR201, PR205, and PR206 are in use, and PR202, PR203, and PR204 are unused. Subsequently, in S602, the CPU 111 determines whether or not an area where the ZS can be configured is usable. For example, if it cannot be used for another process, the process returns to S601 and waits until it can be used. On the other hand, if it is determined that PR can be used, the process proceeds to S603. At this time, the CPU 111 determines the logic circuit configuration information suitable for the PR to be used and the PR necessary for the reconfiguration process. Here, it is assumed that PR203, PR202, and PR204 are determined to be used as ZS1, ZS2, and ZS3, respectively, and necessary logic circuit configuration information is stored in the storage unit 106.

  In step S603, the CPU 111 determines a sequence for performing reconfiguration processing. When the reconfiguration sequence is determined, in S604, the CPU 111 can execute the reconfiguration process based on the reconfiguration sequence determined in S603 and shift to the state of 302.

  Here, referring to FIG. 7, the processing flow in which the CPU 111 of the controller unit 101 determines the reconfiguration sequence for use case 1 in S <b> 603 for shifting from the circuit configuration shown in 301 to the circuit configuration shown in 302. Will be described. Note that the processing described below is realized by the CPU 111 reading a control program stored in the ROM 109 or the storage unit 106 into the RAM 110 and executing it.

  In step S <b> 701, the CPU 111 acquires power information of the operating circuit using the operating power management table 401. FIG. 4 shows an example of the operating power management table 401 used by the CPU 111 in S701. In the present embodiment, the operating power management table 401 defines PR-ID, function, frequency, and power correlation information for each PR. The PR-ID represents an ID for distinguishing a partial reconstruction area having a plurality of areas. function represents the function of the configured circuit. The frequency represents the operating frequency of the circuit to be configured, and its unit is MHz. “power” represents the operating power of the configured circuit, and its unit is mW. For example, by referring to the operating power management table 401, when the AFC operates with an operation clock of 200 MHz in the PR 205, a numerical value of 120 mW is obtained as the operating power.

  Returning to the description of FIG. In use case 1, at the time of S701, PR201, PR205, and PR206 are operating, and operating power information can be obtained from each operating state / function as follows. That is, it can be calculated as PR201 + PR205 + PR206 = 40 + 120 + 160 = 320 [mW].

  Next, in step S <b> 702, the CPU 111 acquires additional power necessary for partial reconfiguration to be performed in the future using the partial reconfiguration power management table 501. FIG. 5 shows an example of the partial reconfiguration power management table 501 used by the CPU 111 in S702. Defines correlation information between PR-ID indicating which PR, function indicating the circuit configuration to be configured, frequency indicating the frequency of the reconfiguration clock used for the partial reconfiguration processing, and power indicating the power information required for reconfiguration doing. In this embodiment, the unit of frequency is MHz and the unit of power is mW.

  Returning to the description of FIG. Since PR203, PR202, and PR204 are reconfigured as ZS1, ZS2, and ZS3, respectively, in use case 1, additional power information is obtained as follows. That is, it can be calculated as PR202 + PR203 + PR204 = 200 + 190 + 240 = 630 [mW].

  Next, in S <b> 703, the CPU 111 functions as a power determination unit, and the total value of the in-use power (power consumption) and the additional power obtained in S <b> 701 and S <b> 702 is an allowable power for the dynamic reconfiguration unit 120. Whether or not reconfiguration is possible is determined based on whether or not the value is within the range (predetermined power range). The power allowable by the dynamic reconfiguration unit 120 is determined by the characteristics of the dynamic reconfiguration unit as a device, and is 850 [mw] in the present embodiment. That is, here, an upper limit of allowable power is defined in advance. If it is determined in S703 that reconfiguration is possible, the process proceeds to S704. If it is determined that reconfiguration is not possible, the process proceeds to S705.

  In step S704, the CPU 111 determines a reconfiguration sequence as a sequence for reconfiguring all the PRs to be used. That is, PR203, PR202, and PR204 perform reconfiguration processing in parallel as ZS1, ZS2, and ZS3 in S604 of FIG. For example, when there is no circuit in operation, it is assumed that the process often proceeds to S704.

  In use case 1 in the present embodiment, the total value (320 + 630 = 950 [mw]) of the in-use power and the additional power exceeds the allowable power value (850 [mw]). It is determined that there is not, and the process proceeds to S705. Note that, from S705 to S709, an example of steps performed to keep the power during operation and the additional power during reconfiguration within allowable power is described.

  In S705, the CPU 111 functions as a priority determination unit, and determines whether the priority of the circuit (ZS) to be reconfigured is higher than the priority of the circuit (AFC, FLTA, SENS) being executed. judge. If the function to be reconfigured has a higher priority than the function being executed, the process advances to step S706, and the CPU 111 adds a control sequence for suppressing power consumption to the operating circuit. Thereby, the logic circuit constituted by reconfiguration can be executed quickly. On the other hand, when the priority of the function being operated is lower than or equal to the function scheduled to be reconfigured, the process proceeds to S708, and the CPU 111 adds a control sequence for suppressing power consumption in the reconfiguration. . As a result, it is possible to perform the reconfiguration process without interfering with a process having a high priority or a process having the same priority but already being executed.

  Since ZS used for the scanning process instructed by the user from the operation unit 104 is defined as having a high priority for AFC and FLTA, in use case 1, the process proceeds to S706. In step S <b> 706, the CPU 111 determines control for suppressing power consumption for the circuit in operation. Controls that can be selected for the circuit in operation include control for stopping the operation clock and control for reducing the frequency of the operation clock. The CPU 111 selects these controls according to the function of the circuit in operation.

  In S707, the CPU 111 adds control to the operating circuit in S706 to the reconfiguration sequence, and the total value of the power in use and the additional power falls within the power allowable by the dynamic reconfiguration unit 120. Whether or not reconfiguration is possible is determined in the same manner as in S703. As a result of the determination, if the power is not within the allowable power, the process proceeds to S708, and the control of the reconstruction process which is the other control is further added. On the other hand, if the allowable power is sufficient, the flow for determining the reconstruction sequence is completed. In use case 1 in the present embodiment, even if control for stopping the operation clock is added in S706, the power does not fall within the allowable power, so the process proceeds to S708.

  In step S708, the CPU 111 determines control for reducing power consumption in the reconfiguration process. As control that can be selected for the reconfiguration processing, there are control for sequentially reconfiguring a plurality of partial reconfiguration units PR, control for reducing the frequency of the reconfiguration clock, and the like. The CPU 111 selects these controls according to the logic circuit information to be reconfigured.

  In step S709, the CPU 111 adds control to the reconfiguration process to the reconfiguration sequence in step S708, and determines whether the power in use and the additional power are within the power allowable by the dynamic reconfiguration unit 120. By determining, whether or not reconfiguration is possible is determined in the same manner as in S703. As a result of the determination, if the power is not within the allowable power, the process proceeds to S706, and the control to the operating circuit as the other control is further added. On the other hand, if the allowable power is sufficient, the flow for determining the reconstruction sequence is completed. In use case 1 in the present embodiment, in addition to the control for stopping the operation clock in S706, the order reconfiguration control that is the other control is further added in S708. Complete the flow. If both controls are added but the power does not fall within the allowable power, the degree of power reduction by each control may be increased, or an error may be terminated.

  Next, with reference to FIG. 8, a processing flow in which the CPU 111 determines a control for suppressing power consumption for an active circuit in S706 will be described. Note that the processing described below is realized by the CPU 111 reading a control program stored in the ROM 109 or the storage unit 106 into the RAM 110 and executing it.

  In step S801, the CPU 111 determines whether the operating circuit is a real-time process. If the circuit is a non-real-time process, the process proceeds to step S802. If the real-time process is performed, the process proceeds to step S803. Here, a process that cannot be stopped depending on the operating speed of the hard device, such as a video image process, is defined as a real-time process, and a process that can tolerate a certain amount of delay or stop is defined as a non-real-time process. AFC and FLTA are image processing on the image data stored in the storage unit 106, and are non-real time processing.

  If the circuit under operation is non-real time processing, in S802, control for stopping the operation clock is added to the reconfiguration sequence. When the CPU 111 selects this sequence and refers to the operating power management table 401, the power consumed by the AFC of the PR 205 is changed from 170 [mw] to 30 [mw].

  On the other hand, if the operating circuit is a real-time process, it is determined in S803 whether or not the processing speed can be reduced. For example, even if the processing rate or the processing resolution is halved and the operation clock is halved, the pattern recognition processing circuit that is established as a function may determine that the processing speed may be reduced in this determination. At this time, in S804, control for lowering the operation clock is added to the reconfiguration sequence. For example, in the case where the PR 205 is configured with FDT 2 that performs a part of face recognition processing, the power consumption can be reduced by 60 [mW] when the frequency of the operation clock is changed from 200 MHz to 100 MHz. If it is determined in S803 that the processing speed cannot be reduced, the control decision for the operating circuit is terminated.

  Next, with reference to FIG. 9, a processing flow in which the CPU 111 determines a control for suppressing power consumption with respect to the reconfiguration processing in S708 will be described. Note that the processing described below is realized by the CPU 111 reading a control program stored in the ROM 109 or the storage unit 106 into the RAM 110 and executing it.

  In step S901, the CPU 111 determines whether there are a plurality of areas to be reconfigured. If the logic circuit has a function composed of a plurality of PRs, the process proceeds to S902. If the logic circuit has a function composed of only one PR, the process proceeds to S903. In use case 1, since three regions PR202, PR203, and PR204 are used, the process proceeds to S902.

  In step S <b> 902, the CPU 111 determines to use, as a reconfiguration sequence, a control (order reconfiguration) for reconfiguring all PRs used for reconfiguration in order, not in parallel, for PRs that are a plurality of dynamic reconfiguration regions. . In use case 1 in the present embodiment, when the reconfiguration process is executed in parallel, 630 [mw] of additional power is required. However, if the reconfiguration process is executed for each 1 PR, the reconfiguration process can be executed with a maximum of 240 [mw] of additional power.

  On the other hand, in step S903, the CPU 111 determines to use control for reducing the frequency of the reconfiguration clock used for the reconfiguration processing as the reconfiguration sequence. For example, when the AF 204 circuit that performs affine transformation and filtering is reconfigured in the PR 204, the power consumption can be suppressed to 80 [mw] by reducing the reconfiguration clock from 160 MHz to 80 MHz.

<Power consumption>
Next, with reference to FIG. 10, the power consumption when applying the reconfiguration control flow to the dynamic reconfiguration unit 120 in the image processing apparatus 100 according to the present embodiment will be described.

  1001 represents time on the horizontal axis and power consumption on the vertical axis. Th on the vertical axis is a threshold value of power consumption that can be allowed by the dynamic reconfiguration unit 120 serving as a reference for voltage fluctuations to fall within a predetermined range. The solid line indicates the power consumption to which the present embodiment is applied, and the broken line Indicates power consumption when this embodiment is not applied. On the other hand, 1002 represents time on the horizontal axis and the voltage of the dynamic reconfiguration unit 120 on the vertical axis. If the voltage is within a predetermined range, the circuit is guaranteed to operate normally. A solid line indicates a case where the present embodiment is applied, and a broken line indicates a case where the present embodiment is not applied.

  Time Ta is the time when the circuit shown in 301 is configured. At this time, there is a request for reconfiguration of the circuit ZS that performs image area separation, and the CPU 111 executes the determination flow of the reconfiguration sequence according to the present embodiment, and further executes reconfiguration processing. The CPU 111 connects the logic circuit configuration information for configuring the ZS1, ZS2, and ZS3 stored in the storage unit 106 to PR202, PR203, and PR204 to the dynamic reconfiguration unit 120 via the communication I / F 211. To the RAM 122. Further, the CPU 111 first cuts off supply of the operation clocks of the PR 205 and PR 206 to the clock control unit 213 immediately before the time Tc based on the flow of the reconstruction sequence determination.

  Reference numeral 1003 represents a breakdown of power consumption of the operating circuit before the supply of the operation clock is cut off. Reference numeral 1004 represents a breakdown of power consumption of the operating circuit after the supply of the operation clock is cut off. This shows that power other than static power such as leakage power is reduced because the operation clocks of AFC and FLTA that are operating using PR205 and PR206 are cut off.

  Next, at times Tc, Tc2, and Tc3, the reconfiguration control unit 212 is instructed to reconfigure PR204, PR203, and PR202 using the logic circuit configuration information stored in the RAM 122. Perform configuration processing. Reference numeral 1005 represents a breakdown of power consumption when the determination flow of the reconfiguration control sequence according to the present embodiment is not applied. In addition to operating power in PR201, PR205, and PR206, power consumption associated with reconfiguration processing in PR202, PR203, and PR204 indicates that power consumption exceeding Th occurs, resulting in malfunction of the circuit. May cause. Reference numeral 1006 indicates a breakdown of power consumption when the reconfiguration control flow according to the present embodiment is applied. In S708, it is determined that the reconfiguration processing is performed in order, so that PR204 is reconfigured at time Tc, PR202 at Tc2, and PR203 at Tc3. As a result, the power consumption associated with the reconfiguration process indicated by 1005 is distributed, and the reconfiguration process can be performed with the power consumption below Th.

  Furthermore, after receiving the completion notification from the reconfiguration processing unit 212, the CPU 111 instructs the clock control unit to resume the operation clocks of the PR 205 and PR 206. At this point, the dynamic reconfiguration unit 120 has shifted to the state indicated by 302, and at time Tb, the PR 202, PR 203, and PR 204 process image data from the reader unit 105 as a circuit that performs image area separation. It is carried out.

  In this embodiment, all the power is used as a direct value of mW, but it may be used as a normalized value when the sharable power is 100, or an abstract such as Hi, Mid, or Lo. The determination may be made using the value. In the present embodiment, all the circuits that operate are described as dynamic partial reconfiguration in PR, but the dynamic reconfiguration unit 120 may include a statically configured circuit. In that case, control may be performed in consideration of operating power using power information corresponding to the function and operating frequency of the statically configured circuit. In this embodiment, the CPU 111 controls the operation of the reconfiguration control unit 212. However, the reconfiguration control unit 212 may perform control, or the dynamic reconfiguration unit 120 includes a CPU, which is controlled by the CPU. May be.

  As described above, according to the present embodiment, power consumption when performing dynamic partial reconfiguration is predetermined based on power information of an operating circuit and additional power information accompanying dynamic partial reconfiguration. The reconfiguration method and the control method for the operating circuit are selected so as to be within the allowable power. As a result, the dynamic reconfiguration unit 120 implemented by an FPGA or the like can keep the voltage fluctuation within a predetermined range even when there is a circuit in operation, and can avoid malfunction of the circuit. it can.

<Another use case>
Another use case will be described with reference to FIG. In the above-described embodiment, the use case for shifting to the circuit configuration indicated by reference numerals 301 to 302 has been described. However, the present invention can be applied to another use case. Reference numeral 1101 denotes LRCT (low-resolution image correction), FDTP (face recognition preprocessing), FDT1 (face recognition 1), and FDT (face recognition 2), which are configured as PR203, PR201, PR202, and PR205, respectively. Reference numeral 1102 denotes a case where an AFCF circuit that performs affine transformation and filtering is configured in the PR 204 in addition to the circuit configuration of 1101. The transition from the circuit configuration 1101 to the circuit configuration 1102 is referred to as use case 2.

  The operation in the flowchart of FIG. 7 for use case 2 will be described. In S701 to S703, as a result of the determination similar to the use case 1, it is not possible to reconfigure, so the process proceeds to S705. In S <b> 705, the CPU 111 has determined that the priorities are the same as a result of comparing the priority of the circuit being operated and the circuit to be reconfigured. Therefore, the CPU 111 proceeds to S <b> 708 and determines control of the reconfiguration process. According to the control determination procedure of the reconfiguration process described with reference to FIG. 9, since the AFCF is a dynamic partial reconfiguration process including one area, the control that can be selected by the CPU 111 reduces the frequency of the reconfiguration clock. That is. Subsequently, in S709, the CPU 111 adds control to the reconfiguration process to the reconfiguration sequence again, and whether the power in use and the additional power are within the power allowable by the dynamic reconfiguration unit 120. By determining whether or not reconfiguration is possible, it is determined in the same manner as in S703. As a result, since reconfiguration is possible, the reconfiguration sequence determination procedure ends.

  In use case 1, control for reducing power consumption was added to the reconfiguration processing control as well as control to the operating circuit. However, in use case 2, only the procedure is added to the reconfiguration processing, and the allowable power It was possible to control so that it was settled in. Further, depending on the state of the circuit in operation and the configuration of the circuit to be reconfigured, it may be possible to control the power to be within the allowable power only by performing additional control on the circuit in operation. In other words, in order to reduce power consumption, it is possible to select an appropriate control by giving priority to whether to add control to the operating circuit or to add processing to the reconfiguration processing. Thus, processing with high priority can be executed quickly.

<Second Embodiment>
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 12 and 13. In the first embodiment, whether to control the operating circuit by determining whether the priority of the circuit to be reconfigured is higher than the priority of the circuit being executed, Decided whether to control in the reconstruction process. However, there is a case where control for suppressing power more than necessary is added. For example, in the case of the first embodiment, the process control to the operating circuit is selected with priority. However, the control of the operating circuit alone cannot satisfy the allowable power, and the reconfiguration process is also performed. Control to reduce power consumption was added.

  Therefore, in the present embodiment, in consideration of the above-described contents, the selection of the control performed when the operating power and the power accompanying the partial reconfiguration are not within the allowable power is selected from the one having a high effect of suppressing the power consumption. Control to select in order. Note that the configuration of the image processing apparatus 100 and the configuration of the dynamic reconfiguration unit 120 are the same as those in the first embodiment, and a description thereof will be omitted.

<Processing flow>
First, referring to FIG. 12, in the second embodiment, the reconfiguration sequence for use case 1 for shifting from the circuit configuration shown in 301 to the circuit configuration shown in 302 in S603 is performed by the controller unit 101. A flow determined by the CPU 111 will be described. Since S701 to S703 and S704 described in the first embodiment are the same as those in the first embodiment, description thereof is omitted and only S1201 is described. The processing described below is realized by the CPU 111 reading a control program stored in the ROM 109 or the storage unit 106 into the RAM 110 and executing it.

  In step S <b> 1201, the CPU 111 extracts selectable controls using the operating power management table 401 and the partial power reconfiguration power management table 501. In the state 301, the PR 201, PR 205, and PR 206 are operating, and the control of shutting down the operating clock or reducing the frequency can be selected for the PR 205 and PR 206 for which a plurality of frequencies are prepared. Furthermore, in the reconfiguration processing of PR202, PR203, and PR204, it is possible to select a processing that lowers the frequency of the reconfiguration clock or performs reconfiguration in order. In the operating power management table 401, the meaning of frequency = 0 means that the operation clock is cut off, and if the value corresponding to frequency = 0 does not exist in the table, the operating clock is changed for reasons such as real-time processing. Indicates that the function cannot be cut off.

  Next, in S1202, the CPU 111 preferentially selects a control with a large power reduction amount from the selectable controls extracted in S1201. Here, there is an effect of 280 mW, which has the highest power reduction effect, by reducing the frequency of the reconfiguration clock from 160 MHz to 80 MHz. Therefore, the CPU 111 adds control for reducing the frequency of the operation clock to the reconfiguration sequence. To decide.

  Subsequently, in step S1203, the CPU 111 adds control to the operating circuit in step S1202 to the reconfiguration sequence, and whether the in-use power and the additional power are within the power allowable by the dynamic reconfiguration unit 120. By determining whether or not reconfiguration is possible, it is determined in the same manner as in S703. As a result of the determination, if it does not fit, the process proceeds to S1202, and the CPU 111 selects again the control to be added. When it is sufficiently within the allowable power, the determination flow of the reconstruction sequence is completed.

<Power consumption>
Next, with reference to FIG. 13, the power consumption when the reconfiguration control flow to the dynamic reconfiguration unit 120 in the image processing apparatus 100 according to the present embodiment is applied will be described. Reference numerals 1301 and 1302 denote time on the horizontal axis and power consumption on the vertical axis. Th on the vertical axis is a threshold value of power consumption that can be allowed by the dynamic reconfiguration unit 120 serving as a reference for voltage fluctuations to fall within a predetermined range, and indicates the power consumption to which the present embodiment is applied by a solid line, and is a broken line. Indicates power consumption when this embodiment is not applied.

  Reference numeral 1301 represents a breakdown of power consumption when the reconfiguration control sequence determination flow according to the present embodiment is not applied. In addition to operating power in PR201, PR205, and PR206, power consumption associated with reconfiguration processing in PR202, PR203, and PR204 indicates that power consumption exceeding Th occurs, resulting in malfunction of the circuit. May cause. Reference numeral 1302 indicates a breakdown of power consumption when the reconfiguration control flow according to the present embodiment is applied. By determining in step S708 that the process for reducing the reconfiguration clock is performed, the power consumption associated with the reconfiguration process indicated by 1301 is reduced, and the reconfiguration process can be performed with the power consumption below Th.

  As described above, according to the present embodiment, the selection of the control performed when the operating power and the power associated with the partial reconfiguration do not fall within the allowable power is selected in descending order of the effect of suppressing the power consumption. Control. By determining the reconfiguration sequence of the present embodiment, it is possible to perform dynamic reconfiguration processing without applying unnecessary power reduction control.

<Other embodiments>
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

  100: Image processing apparatus 104: Operation unit 102: Display unit 105: Reader unit 107: Printer unit 120: Dynamic reconfiguration unit

Claims (12)

An image processing apparatus having a reconfiguration circuit, including a plurality of partial reconfiguration units, and capable of dynamically and partially reconfiguring a circuit configuration,
When reconfiguring the partial reconfiguration unit of a part of the reconfiguration circuit, the total value of the power consumption value of the partial reconfiguration unit in operation and the additional power value necessary for reconfiguration is calculated. A calculating means for calculating;
Power determining means for determining whether or not the total value calculated by the calculating means falls within the allowable power value;
An image processing apparatus comprising: a reconfiguration unit configured to reconfigure the reconfiguration circuit when the power determination unit determines that the total value falls within an allowable power value.   When the power determination unit determines that the total value does not fall within the allowable power value, the power determination unit further includes a determination unit that determines a sequence for controlling the total value to fall within the allowable power value. The image processing apparatus according to claim 1. The determining means includes
The image according to claim 2, wherein a sequence for performing at least one of control for suppressing power consumption of the partial reconfiguration unit during operation and control for suppressing additional power for reconfiguration is determined. Processing equipment. The determining means includes
Priority determining means for determining which function of the function in the partial reconfiguration unit in operation and the function scheduled to be reconfigured in the partial reconfiguration unit is prioritized,
When the priority determination unit determines that the function scheduled to be reconfigured in the partial reconfiguration unit is higher in priority, it determines to perform control to reduce power consumption of the partial reconfiguration unit in operation. And
4. The control according to claim 3, wherein when the priority determination unit determines that the function of the partial reconfiguration unit in operation is higher in priority, control for suppressing additional power for reconfiguration is performed. 5. Image processing apparatus. The determining means includes
The calculation means calculates the total value when performing either one of control for suppressing power consumption of the partial reconfiguration unit during operation or control for suppressing additional power for reconfiguration,
The image processing apparatus according to claim 4, wherein when the calculated total value does not fall within an allowable power value, the sequence is determined so as to further add the other control.   The control for suppressing the additional power for reconfiguration is control for sequentially reconfiguring the plurality of partial reconfiguration units to be reconfigured, or control for reducing the frequency of the clock. Item 4. The image processing apparatus according to Item 3.   The image processing according to claim 3, wherein the control for suppressing the power consumption is a control for reducing a frequency of a clock to the corresponding partial reconfiguration unit or blocking a supply of the clock. apparatus.   The determining means determines the control to lower the frequency of the clock if the partial reconfiguration unit in operation is performing real-time processing as the control for suppressing the power consumption, or the partial reconfiguration in operation The image processing apparatus according to claim 7, wherein if the unit is not performing real-time processing, control for cutting off the supply of the clock is determined.   The determining means preferentially selects from among controls that suppress power consumption of the partial reconfiguration unit in operation or controls that suppress additional power for reconfiguration from a control with a high power reduction amount. The image processing apparatus according to any one of claims 2 to 8.   The calculation means defines the operating frequency and power consumption for each function configured in the partial reconfiguration unit, the power consumption value from each of the operation table and the reconfiguration table, and The image processing apparatus according to claim 1, wherein the value of the additional power is used. A method for controlling an image processing apparatus having a reconfiguration circuit, including a plurality of partial reconfiguration units and capable of dynamically and partially reconfiguring a circuit configuration,
When the calculating means reconfigures the partial reconfiguration unit of a part of the reconfiguration circuit, the power consumption value of the partial reconfiguration unit in operation and the value of additional power necessary for reconfiguration A calculation step of calculating the total value of
A power determination step for determining whether or not the total value calculated by the calculation means falls within a value of allowable power;
An image processing comprising: a reconfiguration unit that executes a reconfiguration step of reconfiguring the reconfiguration circuit when the power determination unit determines that the total value falls within an allowable power value. Control method of the device.   The program for making a computer perform each process in the control method of the image processing apparatus of Claim 11.

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