JP2016026345A - Temporary stop of memory operation for shortening reading standby time in memory array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for shortening a reading standby time in a memory array.SOLUTION: A memory controller receives a writing multi-block command from a host, and shifts a transfer state 12 to a data reception state 16 in which corresponding data are received from a host, and receives a stop command from the host, and shifts the data reception state to a programming state 18 in which writing control to a memory is performed. The memory controller receives a suspend command from the host during the programming state, and stores the corresponding data, and interrupts the writing control to the memory, and shifts the programming state to the transfer state 12. The memory controller receives a resumption command from the host after interruption, and shifts the transfer state to the programming state 18 without passing through the data reception state, and resumes the writing control to the memory by using the stored write data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a memory controller control method and apparatus.

  Currently, the most common interfaces used for both external and internal flash memory are the multimedia card (MMC) and the corresponding embedded MMC (e-MMC). New standards have also been developed, such as Universal Flash Storage (UFS), where internal and external flash memory share a single bus. These standards are intended to accommodate other types of memory, including magnetic, optical, and phase change.

  As a conventional technique, a NAND chip control method as described in Patent Document 1 is known.

International Publication No. 2007/110716

  In order to simplify the MMC or e-MMC interface, the memory card controller adapts the physical memory interface (eg, NAND interface) to the MMC bus interface, and further manages tasks specific to physical memory technology. These tasks in NAND memory may include defragmentation, bad block management, error correction and detection, algorithms for uniform wear, safety management, and logical versus physical block relocation. This reduces the complexity of other parts of the system, but all of these additional memory controller tasks take time to execute, and memory may be temporarily unavailable during this time.

  This may cause the memory card controller to take longer than hundreds of milliseconds to execute a host command due to the latest running data management routine such as data defragmentation or garbage collection, for example. During this time, the card is busy and cannot manage other host commands until the previous host command is completed. As a result, the response to the read command is delayed. This increased waiting time may prevent proper host operation.

  In order to solve the above problems, an apparatus according to the present invention includes a host that issues a command, a memory, and a memory that changes its own state according to the command and controls the memory according to the changed state. A memory controller that receives a write multiplex block command from the host and transitions from a transfer state to a data reception state in which the corresponding data is received from the host, and subsequently from the host. In response to a stop command, a transition is made to a programming state in which write control to the memory is performed, and during the programming state, a corresponding suspend command is received from the host to save the corresponding data and control to write to the memory. Interrupts and transitions to the transfer state, and then resumes from the host after the interruption. In response to command, characterized in that to resume control of writing to the memory with the write data stored in the transition to the programming state without going through the data reception state.

  Also, the memory controller control method of the present invention issues a write multiplex block command to transition from the transfer state to the data reception state, and issues a stop command after the write multiplex block command to change from the data reception state to the programming state. And transition to the transfer state from the programming state by issuing a suspend command during the programming state, and issue a resume command after the suspend command from the transfer state. A transition is made to the programming state without passing through the data reception state.

  The subject matter relating to the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, in addition to the objects, features and advantages of the present invention, both its construction and method of operation may be best understood by reading the following detailed description, taken in conjunction with the accompanying drawings.

FIG. 3 is a state diagram illustrating a portion of an e-MMC flash memory card controller suitable for illustrating aspects of an embodiment. FIG. 4 is a state diagram illustrating a portion of a memory controller, according to an embodiment. 6 is a timing chart showing suspend and resume of a write operation according to an embodiment. 6 is a timing chart showing interruption of a write operation according to the embodiment. FIG. 6 is a process flow diagram illustrating suspending and resuming a write operation according to an embodiment. FIG. 6 is a process flow diagram illustrating interruption of a write operation according to an embodiment. It is a block diagram which shows the management memory which has a host interface which can implement | achieve the process and apparatus relevant to another figure. FIG. 10 is a block diagram illustrating a mobile device capable of implementing processes and devices related to other figures.

  It is understood that the components shown in the figures are not necessarily drawn to scale for the sake of brevity and clarity of explanation. For example, the dimensions of some components may be expanded relative to other components for purposes of clarity. Moreover, the same reference numerals are used repeatedly in the figures to indicate corresponding or equivalent components, when considered properly.

  For logistics management systems and many other strategic demands, as well as business applications, memory read operations are preferably fast enough and are available immediately after writing the same data. Therefore, as described below, the host can access the management memory regardless of the state of the memory controller. For example, while a write operation is in progress, the host can suspend the write operation that is in progress and can perform a read operation and then resume the suspended write.

  For example, such a suspend operation can be beneficial if the host has each firmware stored in management memory and the memory controller needs to load a portion of it at a runtime that is busy storing data. In one embodiment, a new command sequence allows the host to suspend and resume a long write operation to perform a quick read operation.

  The write suspend command following the write resume command can be used by the host to ensure a read access time of a few milliseconds even in the worst case. This allows the host to execute the page in response to a strategic request, for example, by freezing the write operation for a short time. Any other long-term memory management operation can freeze in the same way.

  For ease of explanation, the following description is described in the context of the JESD84-A44 standard specification (published by the American Electronics Industry Association) of e-MMC 4.4JEDEC (Council for Electronic Device Technology). However, the same concept can be applied to other memory management protocols and memory interfaces.

  Either the built-in NAND flash memory or the NAND flash memory in an individual removable card can easily achieve the standard read speed required for any system. However, latency is longer due to memory management and write algorithms. Memory management is provided to the memory card controller according to the e-MMC specification, so that the host does not recognize whatever specific processing is being performed. Therefore, in order to always achieve high-speed memory performance, several methods that adapt to memory management tasks are required.

  When the e-MMC is a management NAND flash memory card, the internal memory card controller manages all executions in the internal NAND memory management operation. Of these, defragmentation and garbage collection are unpredictable and time consuming. These algorithms are typically executed during a write / erase command, and their duration depends on the occupancy of the NAND flash block and hence how an external host application accesses the memory system. Other types of physical memory require other memory management operations that can hinder rapid read cycles.

  Execution of an arbitrary management algorithm may increase the execution time of a write command due to an unpredictable technique. As a result, subsequent high-priority read operations may be delayed for a longer time than allowed by the specifications. This can inter alia interrupt the operation of the host.

  The description herein is described in the context of a flash memory card that is coupled to a host, such as a computer, smart phone, media player, or similar device via an e-MMC interface. However, the present invention is not limited to these. Many types of memory require background management tasks. Whether these tasks are similar to or significantly different from those required for flash memory, the present invention can reduce the latency of these tasks. The present invention is not limited to a specific memory hardware configuration. The memory may be built into a distinguishable card, a distinguishable chip, or built into some other device. If the memory is packaged as a memory card, memory management operations can be performed by the memory card controller. However, controllers involved in memory management may have different names in other types of memory. Accordingly, the present invention is described in the context of a memory or management memory, with a memory controller coupled between the memory and the host.

  Embodiments of the present invention can be more easily understood by providing a simple illustration. In this example, the host system processes a write multiple block command to the memory controller. The exemplary management memory has a memory cell array and is classified into a plurality of blocks. The memory controller is located at the center of the linked management memory array, performs data defragmentation, and may actually be part of the memory. In a conventional flash memory card, the memory card controller receives the data in the buffer and then returns to the defragmentation operation. This operation is followed by writing new data. Until these operations are complete, the host does not send any additional data or read any data. Furthermore, the data just transmitted is not read until the defragmentation process is completed. As an example of this, defragmentation is used. There are several other processes performed by the memory controller that can temporarily make the memory unavailable.

  This example can be more fully understood with reference to a conventional state diagram for standard e-MMC. This state diagram is shown as FIG. Some details not related to the operations described herein are removed from the standard drawing.

  As shown in FIG. 1, there are several states of the memory controller. These include a standby state (stby) 10, a transfer state (tran) 12, a data transmission state (data) 14, a data reception state (rcv) 16, a programming state (prg) 18, and a disconnected state (dis) 20. Other states may also be defined, but are not shown here for the sake of simplicity. Writing a memory cell to a nonvolatile memory device in flash memory is called programming. In other types of memory, programming states such as write or store may have different names. The specific states shown here are directly referenced from the e-MMC standard and are particularly well adapted to NAND flash. However, the present invention can be applied to other types of memory and other types of state machines.

  The controller transitions from one state to another based on the receipt or generation of a command, or based on the occurrence of an “operation complete” event, but not many. All commands are defined numerically as CMDxx where xx is a number. Each command has a numerical definition and arguments. However, in many commands, the argument is an element argument, which means it can be used to convey any information.

  The transition between stby and tran is controlled by the host using CMD7, a select / unselect command. Similarly, the transition between prg and dis and the transition from data to stby are controlled by CMD7. The effect of the command depends on the current state of the memory controller when the command is received. A transition from dis to stby occurs upon completion of the operation.

  In the simple example described above, the host addresses the write multiple block command to the memory card. This is CMD25. As shown in FIG. 1, in tran 12, CMD25 may be received by the host controller. In this example, the controller state is tran, and after receiving the write command (CMD25) in block 22, the memory controller state changes from tran to rcv to receive data. After receiving all data from the host for storage ("transfer end") or after receiving a stop command (CMD12) in block 24, the memory controller state transitions to prg.

  In accordance with the standard specification, the memory controller returns from prg to tran only when the previous write command is complete (“operation complete” in block 26). When the host is busy, it does not send any other command to the memory controller. If the controller is performing a complex operation such as defragmentation, it may remain “programmed” for milliseconds.

  Lists various standard read requests. These are shown in block 28 as CMD8, 11, 17, 18, 30, 56 (r). These commands can only be executed while the memory controller is in the transfer state. Thus, the memory controller quickly transitions from the current state to the transfer state in order to quickly validate the read request. In the standby state, this can be easily performed using CMD7. In the data transmission state, the memory controller can transmit more data as soon as the current request is followed. In an unconnected state, the host may wait until the operation in block 36 is complete, and then issue a CMD7 to the standby state or issue a command to use the CMD7 to put the memory controller into a programming state. The programming state transitions back to the transfer state after the operation in block 26 is complete.

  A fast “out-of-busy” method may be provided to the host to allow quick read requests to be provided in the data receive or program state. Such methods may provide a means for the host to freeze the current defragmentation, garbage collection, or other operations in progress on the e-MMC, thereby performing a higher priority read operation. Free the memory controller. The stopped operation can be resumed later. As described above, memory management operations are frequently triggered by write multiple block commands (CMD25).

  Briefly, the write suspend command can be used to suspend any micro-activity, which sends the DAT0 line (busy signal) and speeds up reading from the device. The write resume command can then cause the memory controller to enter the programmed state, completing the previously suspended write operation. A small amount of data can be saved for later resuming microactivity and completing the write operation. After a write suspend, all these data blocks already entered into the device from the host side can be saved for later resumption. There are several different ways to provide “out of busy” or “suspend and resume” methods.

  In one example, a standard stop command (CMD12) using a specific argument such as 0xF0F0F0F0 (hexadecimal number) is used. A standard stop command is always sent with an element argument and commands the standard STOP_TRANSMISION. By changing the argument to a specific unique argument, the operation and function of the command can be changed. This new command can also be considered as a “write suspend” command.

  According to this example, after receiving the write suspend command, the controller shifts to prg 18 and then shifts to “operation complete” 26 as soon as possible without completing all the steps. Instead, all controller background write operations are suspended. The controller may be configured to retain or save all the information and data necessary to resume and complete subsequent write operations.

  After “operation completed”, the memory controller returns to tran12. In this state, the host can send a read command 28 to the management memory, and the memory controller then goes to data 14 and sends the command. A read operation is performed in the data state 14. When the read operation reaches “operation complete” in block 30, the memory controller then transitions from rev16 to prg18 to return to the tran state 12 where the previous write command can be resumed.

  If the previous write command is not resumed, then all data transmitted to the host in the previous write command is erased. Any command sequence other than the resume sequence may cause the previous write command to be stopped forever. Various methods can be used to resume the write operation and transition from tran to prg. In one example, the following command sequence may be generated by the host:

CMD16 (0x00000004)
CMD56 (0x00000000)
write 4Byte 0xF0F0F0F0
In block 32, the set block length command CMD16 may be sent with the argument “0x00000004”. The argument indicates the data transfer length of the next command CMD56. This follows an industry standard write command (CMD 56) in block 22, which puts the memory controller in the rev state. The argument “0x00000000” is a stuff bit other than the first bit (bit 0) indicating the data transfer direction toward the memory array in this case. After receiving the data, in order to write the data block, “end of transfer” which sets it to the prg state is transmitted to the memory controller. Once in this state, the memory controller then completes the previously suspended write operation.

  In another example, a new command can be used for an additional purpose of placing the memory controller directly in a “programming” state, or an existing command can be given additional purposes. As shown in block 34, CMD6, 28, 29, 38 causes the memory controller to prg directly from tran. These commands can be used for specific purposes. In either case, a command may be sent to put the device directly into the prg state, completing the previously suspended write operation. In this example, CMD22 is used. This command is not currently in applications specified in the e-MMC standard specification. Instead of CMD 22, any other stored or unused command can be used or this command can be modified depending on the desired processing.

  If the host is in the write suspend or busy state described above and the host sends a read or resume command after suspend, then the maintenance operation can be resumed. However, if another command is issued, the memory controller can erase all the resume information. As a result, the interrupted write command is completed. Another risk is that there is a risk that the read data is undefined if a suspend operation is in progress and another read command is issued to the address involved in the suspended write. is there.

  In a third example, a write abort command sequence can be used. An interrupt command can be used that can abruptly interrupt all ongoing memory maintenance operations initiated by the e-MMC controller during the write command. An interrupt causes the host to issue a high priority read command that can be executed quickly.

  In response to a write abort command, the recopy operation of all data in memory can be abandoned. In this case, the physical block involved in the NAND memory is considered invalid. Therefore, even in this case, the physical block involved in the memory is erased in advance before it is written in the new data write operation. In order to avoid loss of all data related to the recopy operation, the write command interrupted by the write abort command can then be reissued by the host. This completes the high priority write operation after the high priority read.

  If the write operation is interrupted before completion, the memory controller may issue an error signal indicating that the operation did not complete successfully. In response, the host can then reissue the corresponding write command. If a suspend command is issued by the host as in the previous example, then the host can be configured to automatically repeat the last write request. In this case, since the host recognizes that the write operation has stopped, an error signal from the memory controller is not required.

  Alternatively, a write interrupt command may be issued by the memory controller in response to a read request with a high priority from the host. When a read request is provided to return an interrupted write operation to a normal state, the memory controller stores the interrupted operation and can automatically resume. Alternatively, the memory controller may simply issue an error signal regarding the interrupted operation. Upon receiving an error signal, the host may reissue the last write operation.

  The suspend command can be implemented in various ways. In one embodiment, similar to the first illustration, the stop command (CMD12) may be modified using a new argument format such as “0xF0F0F0F0”. Since the entire argument of the stop command is composed of stuff bits, other arguments can be used to add further functionality to the command.

  The foregoing method can be implemented in a memory controller or host. If the host is involved in a write suspend or write abort operation, the memory controller can then indicate to the host how such a command can be supported. In the e-MMC standard, each MMC card includes an EXT_CSD (increased card specific data) register. This register contains information about card performance and the selected mode. This information includes start address, storage capacity, partition, boot code, valid command set, timing and speed specifications, erased protection mode, and so on. When the card is activated, the register of the card is read by the host.

  In one embodiment, a dedicated field in the extended CSD register characteristics area may be set to communicate with a host platform where a write suspend / resume or write suspend command, or both, is available on the device. For example, the segment area of the extended CSD register can be used, allowing the host to select whether to validate these commands. In one embodiment, there may be bytes in the segment area set by the host. Once the host has set the byte, then the suspend and suspend / resume function in the device is available.

  The bytes in the segment area may have the structure shown in Table 1 as an example.

The WRITE_PRE_EMPTION_SUPPORT field may have the structure shown in Table 2 as an example.

In bit 1-WRITE_PRE_EMPTION_RESUME_EN, two different values may be used that indicate whether the write priority resume command is valid. In one example, these values can be selected from: That is, 0b0 indicates that the write suspend / resume command is not supported, and 0b1 indicates that the write suspend / resume command is supported.

  Similarly, in bit 0-WRITE_PRE_EMPTION_ABORT_EN, two different values indicating whether the write priority abort command is valid can be used. In one example, these values can be selected from: That is, 0b0 indicates that the write interruption command is not supported, and 0b1 indicates that the write interruption command is supported.

  Similarly, the WRITE_PRE_EMPTION_MGMT field may have the structure shown in Table 3 by way of example.

Bit 0-WRITE_PRE_EMPTION_ACT may have two different values that indicate whether write priority actions are supported. These values may be as follows: That is, 0b0 indicates that the write interruption command is not activated by the host, and 0b1 indicates that the write interruption command is activated by the host.

  The e-MMC standard EXT CSD register is a convenient way for communication performance with the host, and the above table is a specific example of how it is implemented. However, other registers and other control mechanisms may be used to perform the same communication function. Other types of memory devices and memory protocols may be used in the same or different ways. Alternatively, specific commands can be used by the host and card without any kind of configuration or specific data or registers used.

  FIG. 2 is a simplified state diagram illustrating how suspend and resume operations can be added to the operation of the memory system. FIG. 2 includes the transfer state 12, the data reception state 16, and the programming state 18 shown in FIG. Other states and their transitions are not shown to simplify the figure. As shown in FIG. 1, upon receipt of a command at block 22, the memory controller may transition from a transfer state to a data reception state. After receiving the data in block 24, the memory controller enters a programming state to write data to the memory. When the write operation is completed in block 26, the transfer state is restored. Other operations and commands also function as described in FIG. If the memory controller is in a programmed state and the read command needs to be valid quickly, a suspend command may be received at block 38 of FIG. This command can also be used to interrupt the receive data state 16. The suspend command causes the memory controller to quickly return to a transfer state that can validate the read request (not shown). In this state, a resume command may be received at block 40, and the memory controller returns to the programming state and completes the suspended operation. FIG. 3 is a transaction timing chart regarding the suspend / resume method as shown in FIG. In FIG. 3, the horizontal axis is the time that elapses from left to right. At the left end of the horizontal axis, the memory controller starts writing the multiple block 52. At the same time, garbage collection or other memory maintenance task 54 is performed. These tasks are typically performed in programming state 18 in a NAND flash memory card.

  The suspend command 56 is received at any time during writing. This is a command for stopping the write operation of the memory controller in order to supply a read command with a high priority. After receiving this suspend command, a non-stop busy time 58 continues. This is the time required to finish the write operation, save its state and any required operands and data values, and transition to the data state 14. At the end of this busy time, the read command becomes valid 60. After the high priority read command has been processed, a resume command 62 is issued that the memory controller can return to a write operation (not shown) that includes suspended garbage collection.

  FIG. 4 shows another method in which an interrupt command 64 is issued instead of the suspend command. In the example shown in FIG. 4, when the memory controller receives an interruption command, it executes a write 52 and a garbage collection 54.

  The time corresponding to these is the busy time 66, and then the reading 60 is executed. In this example, the read is valid more quickly because the busy time is shorter. This is because the resume command does not follow the suspend command. As a result, the memory controller need not store anything regarding the write operation. When another write command is received, the write operation is restarted from the beginning. Alternatively, a stop command or any other command that yields similar results may be utilized.

  Suspend / resume commands can reduce system downtime and reduce host attention. Stopping or interrupting makes the read valid more quickly, but any changes during the write operation are lost and need to be started from the beginning. Various other changes can be made by the methods described above, and specific choices can be determined depending on the memory, the nature of the controller, and the needs of the host system.

  The present invention can also be described using the flowchart shown in FIG. In FIG. 5, the memory and its host are in operation, and the host determines to request a high priority read command to be issued to the memory at block 111. First, in block 113, the host determines whether or not the memory is in a write state. If not, then the operation proceeds normally. In block 115, the host issues a read request, and subsequently receives read data in block 117. Processing then returns to the start.

  If the priority of the read request is low, the same processing may continue. If the memory is in a write operation and a read request is issued, then the memory completes the write operation and then validates the request. In the e-MMC context shown in FIG. 1, the memory transitions to the transfer state upon completion of the write operation. Next, it transitions to the data state in response to the read command and sends the requested data. No operation is interrupted, but the response to the read request is delayed.

  In FIG. 5, if the memory is currently in a write state, then at block 119, the host may issue a suspend command. This is a command that suspends the memory write operation, so that the memory can respond to read requests. In block 121, the suspend command is followed by a read request. In block 123, the host waits until the requested data is received. After receipt, the host issues a resume command at block 127. This allows the memory to resume the interrupted write operation. Thereafter, the host returns to the start.

  FIG. 6 shows another process flow. As shown in FIG. 6, the memory and its host are in operation, and the host determines to request a high priority read command to be issued to the memory at block 131. First, in block 133, the host determines whether or not the memory is in a write state. If not, then the operation proceeds normally. In block 135, the host issues a read request and subsequently receives read data in block 137. Processing then returns to the start. However, unlike FIG. 5, in FIG. 6, if the memory is currently in a write state, then in block 139, the host issues a stop or abort command. There is no resume command corresponding to the suspend command. An interrupt command is a command that still frees the memory to respond to a read request. After the abort command, processing returns to block 135. The host issues a read request. The host then receives data at block 137 and returns to the start. The process flow shown in FIG. 6 has some optional operations not shown. The host can track the last write command issued before the stop command. After receiving the read data, the host can reissue the write command. As a result, the memory returns to the write state and retrieves all data lost when the write process is stopped. Alternatively, after issuing a stop command, the host can wait for an error signal from the memory. The error signal can track the corresponding command, and after the read request becomes valid, the corresponding command can be reissued to memory by the host. In this method, the memory reacts to an error when a write is interrupted by a stop command.

  In an example different from the flowcharts shown in both FIGS. 5 and 6, the operation of determining the memory state may be ignored. Normally, even when a suspend or stop command is issued when the memory is in a standby state or a transfer state, this command does not affect the operation of the memory. In some examples, this can result in an error signal, which the host can interpret as an indication from the memory in its operational state. The system may be further configured to disable the suspend or stop command even when the memory is in a data transmission state or a disconnected state. This change simplifies host operations, but makes memory operations somewhat uncertain.

  FIG. 7 shows a management flash memory 223 in the form of an eMMC card. This is just one example of a memory product to which the present invention can be applied. However, this applies well to the specific embodiments described above. The components shown may be part of a single die or may consist of several dies. The components may be included in a single package, housing, or removable card, and may be included in several separate packages. The memory card includes a nonvolatile memory unit 201 such as a flash memory, but any other type of memory including a volatile memory may be used. The memory has various partitioning schemes and may be of various sizes. In some examples, this has multiple blocks and each block has multiple pages. However, other configurations may be used. The memory is coupled to a memory card controller or core logic 202 via a non-volatile memory interface 203.

  The interface typically has a control bus and a data bus, allowing physical layer communication between the controller and memory cells. The controller further includes an MMC interface 204 where the card 223 is coupled to the host memory control unit 205. The external MMC interface may have a management NAND interface, which communicates with MMC, eMMC, UFS, or other NAND-based memory interfaces. The interface has a bus connection 206 for communicating data, commands, and clock timing. However, various interfaces adapted for communication using various external protocols can be used instead. The memory card controller 202 converts the external interface into a physical interface having the memory 201. The controller or external MMC interface may include a data buffer that stores provisional values and adapts to latency in the internal and external buses. The controller performs various functions including, for example, the aforementioned data processing, memory maintenance, safety management, and error detection and correction.

  FIG. 8 illustrates an exemplary system 211 that may be applied to embodiments of the present invention. In the example shown, the system is a mobile, handheld mobile phone, but can be a wide variety of different devices with some modifications. The system is driven by a central processing unit (CPU) 213 that may or may not include a chipset. The CPU has an application unit 215 that executes a program using an operating system, and a baseband unit 217 that operates a telephone function. Both parts are coupled to a memory interface 219, which communicates with the system's memory via a bus.

  In the example shown, the system memory includes a volatile unit 221 that can be implemented as a random access memory (RAM) for high-speed access, and a nonvolatile unit 223 that can be implemented as a flash that does not lose data even when power is lost. Typically, RAM is used as a short-term storage for rapidly accessing data and instructions, while flash is used to store operating systems, system parameters, and applications. Alternatively, the memory can be implemented as a complete single memory in flash, the flash part being a PCM (phase change memory), MRM (magnetoresistance memory), FRAM (ferroelectric random access memory). May be implemented with other types of non-volatile memory, such as some of these combinations, or any other memory type. The operations described above in connection with FIGS. 5 and 6 can also be applied to non-volatile memories. In the case of power loss, all data stored in the volatile memory is erased.

  The baseband unit of the CPU is connected to the user interface. In the example shown, the user interface is a keypad 225 and a headset 227 with a speaker and microphone. Various other interfaces may be used such as touch screens, Bluetooth devices, accelerometers, proximity sensors, and other interfaces depending on the particular application. The baseband unit is also connected to an RF (Radio Frequency) circuit 229, and the system and an external device communicate with each other using a wireless connection. The wireless connection may be a cell phone, data, wireless network, or any other interface as required.

  The CPU may also be coupled to any of various peripheral devices 231 such as cameras, position measurement systems, displays, printers, Bluetooth devices, and other peripheral devices to assist in any additional functions of the system 211. . FIG. 8 further illustrates a power management system 233 that may include a power supply such as a battery that controls the power consumption of various components. The device may be software driven and controlled by a CPU, autonomous device, or a combination of both.

  In the previous description, many operations were described without specifying which hardware entity performs the operation. Many of these operations can be performed by various hardware units or modules, depending on the particular memory configuration. As described above, in the currently configured eMMC, the host controls read, write, and logical addresses, while the memory controller maps logical addresses to physical addresses to perform maintenance, error detection, and correction. Thus, the state diagram refers to the actual state of the memory controller, which is determined by a command from the host.

  In other systems, the memory is more autonomous and some of the aforementioned commands issued by the host are issued by internal processing of the memory controller. On the other hand, in other systems such as system memory, the host controls all aspects of memory usage. In this case, the state diagram more accurately shows the state of the host that directly controls the memory. The exact distribution of operations, commands, and responses can be modified to suit different industry standards and different memory utilizations, and the invention is not limited to any particular distribution. The term “computer-readable medium” may be any suitable medium that participates in providing program instructions to a processor, memory controller, or other suitable device for execution. Such media can have a variety of structures, including but not limited to, non-volatile media and volatile media. Non-volatile media may include, for example, optical or magnetic disks, semiconductor storage devices and other memories, ROM (read only memory), and the like. Volatile media can include dynamic memory, such as system memory, DRAM (dynamic RAM), SRAM (static RAM), and other types of volatile storage. Common types of computer readable media include, for example, magnetic media (eg, floppy disks, flexible disks, hard disks, magnetic tapes, and other magnetic media), optical media (eg, compact disk read-only memory ( CD-ROM) and other optical media), physical media with patterns (eg punch cards, punched tape, any other physical media), memory chips or cartridges (eg RAM, programmable read only memory (PROM), Erasable programmable read-only memory (EPROM, flash memory, and other memory chips or cartridges), and any other computer readable medium.

  In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, one of ordinary skill in the art appreciates that the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.

  Some portions of the detailed description are directed to algorithms and symbolic representations of operations on data bits or binary digital signals within a computer memory. These algorithmic descriptions and representations may be data processing techniques used by those skilled in the art to convey their work to others skilled in the art.

  The algorithm here is usually considered as a self-consistent sequence of actions or operations that lead to the desired result. These include physical treatments related to physical quantities. These quantities are typically in the form of electrical or magnetic signals that can be stored, transferred, integrated, compared, and otherwise manipulated, but are not limited to this. It may prove convenient to refer to these signals for bits, numeric data, elements, symbols, digits, terms, numbers, etc. mainly for common use. It should be understood, however, that all of these and similar terms are to be understood as being associated with the appropriate physical quantities and merely being convenient labels applied to these quantities.

  Unless otherwise stated, terms such as “processing”, “operation”, “calculation”, “decision”, etc. throughout the description of this specification refer to the amount in the registers and / or memory of the arithmetic system, Computers that process and / or convert into memory, registers or other such information storage devices in computing systems, other similar data representing physical quantities in transmission or display devices, ie data physically represented, such as by electronic calculations Reference to the actions and / or processes of a computing system, or similar electronic computing device will be apparent from the following description.

  Embodiments of the present invention may include an apparatus for performing the operations herein. The apparatus may be specially configured for the desired purpose, and may comprise a general purpose computer apparatus that is selectively activated or reconfigured by a program stored on the device. Such programs include, but are not limited to, floppy (registered trademark) disk, optical disk, compact disk read only memory (CD-ROM), magneto-optical disk, read only memory (ROM), random access memory (RAM), Electrically programmable read-only memory (EPROM), electrically erasable and programmable read-only memory (EEPROM), magnetic or optical card, or any other type suitable for electronic instruction storage It can be stored on a storage device medium such as any type of disk that can be coupled to the system bus of a computer device.

  The processes and displays described herein are not inherently related to any particular computing device or other device. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized device to perform the desired method. The desired structure for a variety of these systems will appear from the description below. In addition, embodiments of the present invention are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein. Further, it will be appreciated that the operations, performance, and features described herein can be realized by any combination of hardware (discrete or integrated circuit) and software.

  It will be understood that the terms “linked”, “connected” and their derivatives are used and these terms are not considered synonymous with each other. Rather, in particular embodiments, “connected” is intended that two or more elements are in direct physical or electrical contact with each other. “Coupled” means that two or more elements are in direct or indirect physical contact or electrical contact with each other (with other intervening elements between them) and / or two or more elements Are intended to work together or interact with each other (eg, to associate effects). While specific embodiments of the invention have been described, the invention is not limited to the details of such embodiments, but only by the following claims and their reasonable equivalents.

DESCRIPTION OF SYMBOLS 10 Standby state 12 Transfer state 14 Data transmission state 16 Data reception state 18 Programming state 20 Non-connection state 201 Non-volatile memory part 202 Memory card controller (core logic)
203 Non-volatile memory interface 204 MMC interface 205 Host memory control unit 206 Bus connection 211 System 213 Central processing unit (CPU)
215 Application unit 217 Baseband unit 219 Memory interface 221 Volatile unit 223 eMMC card (management flash memory, non-volatile unit)
225 Keypad 227 Headset 229 RF circuit 231 Peripheral device 233 Power management

Claims (9)

The host issuing the command,
Memory,
A memory controller that transitions its own state in response to the command and controls the memory in accordance with the transitioned state,
The memory controller receives a write multiple block command from the host and transitions from a transfer state to a data reception state in which the corresponding data is received from the host, and subsequently receives a stop command from the host and writes to the memory. A transition is made to a programming state in which control is performed, and during the programming state, a corresponding suspend command is received from the host to store the corresponding data and write control to the memory is interrupted to transition to the transfer state. Further, after the interruption, a resume command is received from the host, and the write control to the memory is resumed by using the write data stored in the programming state without passing through the data reception state. Equipment.   The memory controller receives a read command from the host in the transfer state after receiving the suspend command, performs read control to the memory, and then receives a resume command from the host. The apparatus of claim 1.   The apparatus according to claim 1, wherein the memory controller performs garbage collection control simultaneously with the write multiple block command.   The apparatus according to claim 1, wherein the memory controller performs defragmentation control simultaneously with the write multiple block command.   The apparatus according to claim 1, wherein the memory is a NAND flash memory. Issue a write multiple block command to transition from the transfer state to the data receive state,
Issue a stop command after the write multiple block command to transition from the data reception state to the programming state,
Issue a suspend command during the programming state to save data used for programming and transition from the programming state to the transfer state;
A method for controlling a memory controller, wherein a resume command is issued after the suspend command to transition from the transfer state to the programming state without passing through the data reception state.   7. The method of controlling a memory controller according to claim 6, wherein a read command is issued to make a transition to a data transmission state before issuing the resume command in the transfer state after issuing the suspend command.   8. The method of controlling a memory controller according to claim 6, wherein garbage collection control is performed simultaneously with the write multiple block command. 8. The memory controller control method according to claim 6, wherein defragmentation control is performed simultaneously with the write multiple block command.