JP2015002329A - Epitaxial wafer, method for manufacturing the same, and nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer capable of reducing warpage of the epitaxial wafer and reducing the parasitic capacitance generated on the nitride semiconductor layer side in an interface between an Si substrate and the nitride semiconductor layer, a method for manufacturing the same, and a nitride semiconductor device.SOLUTION: A p-type Si layer (1b) is formed on a p-type Si substrate (1a). A plurality of nitride semiconductor layers (2, 3, 4, 5, 6, and 7) are laminated on the p-type Si layer (1b). The p-type Si substrate (1a) is a p-type Si single crystal substrate whose resistivity is not more than 0.01 Ω cm. The p-type Si layer (1b)is a p-type Si layer (1b) whose resistivity is not less than 10 Ω cm and less than 1000 Ω cm. Parasitic capacitance is newly added by depleting the p-type Si layer (1b).

Description

  The present invention relates to an epitaxial wafer having a nitride semiconductor layer, a manufacturing method thereof, and a nitride semiconductor device.

  Conventionally, an epitaxial wafer is one in which boron is doped at a high concentration in an Si substrate so that the resistivity of the Si substrate is 0.01 Ω · cm or less and a nitride semiconductor layer is epitaxially grown on the Si substrate ( For example, refer to Unexamined-Japanese-Patent No. 2010-153817 (patent document 1)). In the above epitaxial wafer, the Si substrate is doped with boron at a high concentration to increase the impurity concentration of the Si substrate, making it harder than a high-purity Si substrate to which no impurities are added. In the epitaxial wafer in which the nitride semiconductor is epitaxially grown on the Si substrate, the warpage of the epitaxial wafer caused by the difference in thermal expansion coefficient between Si and the nitride semiconductor is reduced.

JP 2010-153817 A

  However, since the epitaxial wafer uses only a Si substrate with a high impurity concentration and a low resistivity, the parasitic capacitance generated on the nitride semiconductor layer side at the interface between the Si substrate and the nitride semiconductor layer is reduced. There is a problem that you can not.

  Accordingly, an object of the present invention is to reduce an epitaxial wafer warp and to reduce a parasitic capacitance generated on the nitride semiconductor layer side at the interface between the Si substrate and the nitride semiconductor layer, a method for manufacturing the same, and a nitride It is to provide a semiconductor device.

In order to solve the above problems, the epitaxial wafer of the present invention is
A Si substrate;
A Si layer formed on the Si substrate or on the Si substrate surface;
A plurality of nitride semiconductor layers formed on the Si layer,
The resistivity of the Si substrate is 0.1 Ω · cm or less,
The Si layer has a resistivity of 10 Ω · cm or more and less than 1000 Ω · cm.

In the epitaxial wafer of one embodiment,
The layer thickness of the Si layer is not less than 5 μm and not more than 25 μm.

Moreover, the manufacturing method of the epitaxial wafer of the present invention includes:
A step of ion-implanting an n-type dopant into the surface of a p-type Si substrate having a resistivity of 0.1 Ω · cm or less to form a Si layer having a resistivity of 10 Ω · cm or more and less than 1000 Ω · cm;
And a step of forming a plurality of nitride semiconductor layers on the Si layer.

The nitride semiconductor device of the present invention is
A Si substrate;
A Si layer formed on the Si substrate or on the Si substrate surface;
A plurality of nitride semiconductor layers formed on the Si layer;
A source electrode, a drain electrode and a gate electrode formed on the plurality of nitride semiconductor layers;
The resistivity of the Si substrate is 0.1 Ω · cm or less,
The Si layer has a resistivity of 10 Ω · cm or more and less than 1000 Ω · cm.

  According to the epitaxial wafer of the present invention, the resistivity of the Si substrate is 0.1 Ω · cm or less, and the resistivity of the Si layer formed on the Si substrate or on the Si substrate surface is 10 Ω · cm or more and less than 1000 Ω · cm. By doing so, the warpage of the epitaxial wafer can be reduced, and the parasitic capacitance generated on the nitride semiconductor layer side at the interface between the Si substrate and the nitride semiconductor layer can be reduced.

  Moreover, according to the epitaxial wafer manufacturing method of the present invention, an n-type dopant is ion-implanted into the surface of a p-type Si substrate having a resistivity of 0.1 Ω · cm or less, and the resistivity is 10 Ω · cm or more and less than 1000 Ω · cm. Therefore, the warpage of the epitaxial wafer can be reduced, and the parasitic capacitance generated on the nitride semiconductor layer side at the interface between the Si substrate and the nitride semiconductor layer can be reduced.

  Further, according to the nitride semiconductor device of the present invention, the resistivity of the Si substrate is 0.1 Ω · cm or less, and the resistivity of the Si layer formed on the Si substrate or on the Si substrate surface is 10 Ω · cm or more and 1000 Ω. By making it less than cm, it is possible to reduce the parasitic capacitance generated on the nitride semiconductor layer side at the interface between the Si substrate and the nitride semiconductor layer while reducing the warpage of the epitaxial wafer, and to reduce the switching energy loss.

FIG. 1 is a schematic cross-sectional view showing the configuration of the nitride semiconductor device according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining the distribution of parasitic capacitance in the nitride semiconductor device. FIG. 3 is a diagram for explaining the distribution of parasitic capacitance in a comparative example of the nitride semiconductor device.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a schematic cross-sectional view showing the structure of a field effect transistor as an example of a nitride semiconductor device according to the first embodiment of the present invention. The field effect transistor of the first embodiment is an HFET (Hetero-junction Field Effect Transistor).

  As shown in FIG. 1, the field effect transistor includes a p-type Si substrate 1a, a p-type Si layer 1b formed on the p-type Si substrate 1a, and a plurality of layers stacked on the p-type Si layer 1b. Nitride semiconductor layers (2, 3, 4, 5, 6, 7) and sources formed on the plurality of nitride semiconductor layers (2, 3, 4, 5, 6, 7) at intervals An electrode 11, a drain electrode 12, and a gate electrode 13 formed on the plurality of nitride semiconductor layers (2, 3, 4, 5, 6, 7) and between the source electrode 11 and the drain electrode 12. Yes.

The p-type Si substrate 1a is a p ⁺ -type Si single crystal substrate having a resistivity of 0.01 Ω · cm doped with boron at a high concentration (carrier concentration 1 × 10 ¹⁹ cm ⁻³ ). p-type Si layer 1b has a carrier concentration of 1 × ¹⁰ 13 ^{cm -3,} resistivity of a 1000 [Omega] · cm, layer thickness p of 10 [mu] m ^- is the type Si layer. Here, in general, the concentration of the semiconductor impurity is inversely proportional to the resistivity of the semiconductor, and the width of the semiconductor depletion layer is proportional to the square root of the impurity concentration. The parasitic capacitance due to the depletion layer is inversely proportional to the width of the depletion layer.

The plurality of nitride semiconductor layers (2, 3, 4, 5, 6, 7) include an AlN initial growth layer 2, an Al _0.2 Ga _0.8 N layer 3, a superlattice buffer layer 4, and a GaN channel layer 5. AlN intermediate layer 6 and Al _0.2 Ga _0.8 N barrier layer 7. The AlN initial growth layer 2, the Al _0.2 Ga _0.8 N layer 3, the superlattice buffer layer 4, the GaN channel layer 5, the AlN intermediate layer 6, and the Al _0.2 Ga _0.8 N barrier layer 7 are p-type. The layers are sequentially stacked on the Si layer 1b by epitaxial growth.

  The source electrode 11 and the drain electrode 12 are ohmic electrodes made of Ti / Al / Mo / Au. The gate electrode 13 is a Schottky electrode made of WN / W.

  Next, a method for manufacturing the field effect transistor having the above configuration will be described.

First, a p-type Si layer 1b having a carrier concentration of 1 × 10 ¹³ cm ⁻³ and a layer thickness of 10 μm is epitaxially grown on the p-type Si substrate 1a using a CVD (Chemical Vapor Deposition) method. As growth conditions, for example, SiH ₄ gas is used, and the temperature of the p-type Si substrate 1a is in the range of 1000 ° C. to 1200 ° C. Since the p-type Si layer 1b has a thickness of 10 μm, carriers present in the p-type Si substrate 1a are inductive or capacitive with carriers in the plurality of nitride semiconductor layers (2, 3, 4, 5, 6, 7). Prevents sexual interaction. Moreover, the p-type Si layer 1b can be depleted reliably.

  Next, the surface oxide film of the p-type Si layer 1b is removed with a hydrofluoric acid-based etchant, and the substrate 1 composed of the p-type Si substrate 1a and the p-type Si layer 1b is MOCVD (Metal Organic Chemical Vapor Deposition). Set on the growth) equipment.

  The substrate temperature of the substrate 1 is set to 1100 ° C., the chamber pressure is set to 13.3 kPa, and the surface of the substrate 1 is cleaned.

Next, the surface of the p-type Si layer 1b is nitrided by flowing NH ₃ (ammonia) at a constant substrate temperature and chamber pressure (substrate temperature 1100 ° C., chamber pressure 13.3 kPa) and a flow rate of 12.5 slm. I do.

Next, the substrate temperature and the chamber pressure are kept constant (substrate temperature 1100 ° C., chamber pressure 13.3 kPa), and the AlN initial growth layer 2 is grown to a film thickness of 100 nm. Here, TMA (trimethylaluminum) with a flow rate of 117 μmol / min and NH ₃ with a flow rate of 12.5 slm are supplied as a raw material for AlN that is the AlN initial growth layer 2.

Next, the substrate temperature is set to 1150 ° C., the chamber pressure is set to 13.3 kPa, and the Al _0.2 Ga _0.8 N layer 3 is grown to a film thickness of 40 nm. Here, TMG (trimethylgallium) with a flow rate of 100 μmol / min and a flow rate of 30 μmol / min were used as the raw material for Al _0.2 Ga _0.8 N, which is the Al _0.2 Ga _0.8 N layer 3. TMA and NH ₃ with a flow rate of 12.5 slm are supplied. The film thicknesses of the AlN initial growth layer 2 and the Al _0.2 Ga _0.8 N layer 3 may be 20 to 200 nm.

Next, an AlN layer (TMA flow rate = 117 μmol / min, NH ₃ flow rate = 12.5 slm) and an Al _0.15 Ga _0.85 N layer (TMG flow rate = 137 μmol / min, TMA flow rate = 18 μmol / min, NH ₃ flow rate) = 12.5 slm), the superlattice buffer layer 4 alternately stacked is grown 100 cycles. The superlattice buffer layer 4 has a carbon concentration of 1 × 10 ¹⁹ cm ⁻³ . The Al composition of the AlGaN layer of the superlattice buffer layer 4 is preferably about 0.05 to 0.3. The thickness of each layer of the superlattice buffer layer 4 is preferably about 5 to 25 nm. Further, the number of periods can be changed according to the required film thickness.

Next, the GaN (TMG flow rate = 50 μmol / min, NH ₃ flow rate = 12.5 slm) channel layer 5 to a film thickness of 1 μm, and the AlN (TMA flow rate = 10 μmol / min, NH ₃ flow rate = 12.5 slm) intermediate layer 6 are formed. Al _0.2 Ga _0.8 N (TMG flow rate = 33 μmol / min, TMA flow rate = 10 μmol / min, NH ₃ flow rate = 12.5 slm) barrier layers 7 are sequentially grown up to a film thickness of 30 nm. .

Next, an ohmic region is formed on the Al _0.2 Ga _0.8 N barrier layer 7 using photolithography, and Ti / Al / Mo / Au (Ti / Al / Mo / Au thickness) is formed in the ohmic region. Each deposit 10/60/15/60 nm). Thereafter, heat treatment at 800 ° C. is performed in a nitrogen atmosphere after lift-off for 30 seconds, thereby making ohmic contact between the Al _0.2 Ga _0.8 N barrier layer 7 and the source electrode 11 and Al _0.2 Ga _0.8 N. An ohmic contact between the barrier layer 7 and the drain electrode 12 is obtained.

Next, a gate region is formed on the Al _0.2 Ga _0.8 N barrier layer 7 using photolithography, and WN / W (WN / W thickness is 20/100 nm, respectively) is deposited on the gate region. To do. Thereafter, the gate electrode 13 is formed by lift-off. Further, a surface passivation film made of a SiN _x film is formed on the surface of the field effect transistor, so that the field effect transistor is formed.

  FIG. 2 is a diagram for explaining the distribution of parasitic capacitance in the field effect transistor.

As shown in FIG. 2, C _ds indicates three parasitic capacitances surrounded by a broken line between the source electrode 11 and the drain electrode 12. C _gd represents the parasitic capacitance between the gate electrode 13 and the drain electrode 12, C _GaN represents the parasitic capacitance of the nitride semiconductor layers 4 and 5, and C _sub represents the parasitic capacitance of the p-type Si layer 1b.

  FIG. 3 is a diagram illustrating the distribution of parasitic capacitance in the comparative example of the field effect transistor.

As shown in FIG. 3, in this comparative example, the entire substrate 101 is formed by doping boron at a high concentration (doping concentration 1 × 10 ¹⁹ cm ⁻³ ) as compared with the field effect transistor. Is different. C _db indicates a parasitic capacitance between the drain electrode 12 and the substrate (substrate) 101, that is, a parasitic capacitance generated on the nitride semiconductor layer side at the interface between the substrate 101 and the nitride semiconductor layers 104 and 105. The drain output capacitance Coss of the field effect transistor on the substrate 101 of the comparative example is
Coss = C _ds + C _db + C _gd (1)
It is represented by

ここで、Ｖｄｄは電源電圧を示している。 Based on the drain output capacitance Coss, the switching energy loss Eoss of the field effect transistor is expressed by the following equation (2).

Here, Vdd indicates a power supply voltage.

In order to reduce the switching energy loss Eoss, it is necessary to reduce Coss, that is, to reduce C _ds , C _db , and C _gd , respectively. However, the reduction of C _db in particular is a trade-off with characteristics due to the layer structure such as a withstand voltage, so it is difficult to cope with structural changes.

Therefore, as shown in FIG. 2, in the field effect transistor of the present invention, a p-type Si layer 1b is formed on a p-type Si substrate 1a, and the p-type Si layer 1b is depleted to newly add p-type Si. A parasitic capacitance C _sub is added to the layer 1b. The relationship between C _db and C _GaN and C _sub is expressed by the following equation (3).

From the above formula (3), C _db can be reduced by C _sub newly added in the p-type Si layer 1b. For this reason, Coss can be reduced and the switching energy loss Eoss of the field effect transistor can be reduced.

The approximate value of the specific improvement effect is estimated below. Here, it is assumed that the thickness from the substrate to the channel layer (d _T = d _GaN + d _BF ) in the nitride semiconductor formed on the Si substrate is 4 μm.

Assuming that 4 μm is depleted by voltage application, the capacitance C _GaN can be estimated to be about 30 pF (assuming an area of 1.2 mm × 1.2 mm).

１０μｍの空乏層幅を得るためには、

概ね１×１０^１３cm^−３のキャリア濃度が必要となる。 Here, in order to improve C _{db to} be 10 pF, it is necessary to add 15 pF as C _sub .

To obtain a depletion layer width of 10 μm,

A carrier concentration of approximately 1 × 10 ¹³ cm ⁻³ is required.

The above calculation example is an extremely improved numerical value, but in reality, even when the improvement is about 20%, the loss reduction is effective, and when trying to improve to C _db = 25 pF, 1 × 10 ¹⁵ cm ⁻³ This can be realized with a carrier concentration (resistivity 10 Ω · cm).

  Obtaining the same effect by increasing the thickness of the nitride semiconductor layer is undesirable from the viewpoint of increasing warpage due to stress.

(Second Embodiment)
Next, a field effect transistor as an example of the nitride semiconductor device according to the second embodiment of the present invention will be described.

In the field effect transistor according to the second embodiment, phosphorus (P) as an n-type dopant is ion-implanted into a region 20 μm from the surface of the p-type Si substrate 1a with respect to the p-type Si substrate 1a. This is different from the p-type Si layer 1b of the first embodiment in that a p-type Si layer 1b is formed in a region having a concentration of 1 × 10 ¹² cm ⁻³ , that is, on the surface of the p-type Si substrate 1a. In the structure of the second embodiment, the structure of the nitride semiconductor layer (2, 3, 4, 5, 6, 7) formed on the p-type Si layer 1b is the same as the structure of the first embodiment. The same.

  For this reason, the resistivity and thickness of the p-type Si layer 1b can be strictly controlled as compared with the case where the p-type Si layer 1b is formed by diffusing phosphorus on the surface of the p-type Si substrate 1a.

The switching energy loss Eoss of the field effect transistor manufactured as described above was further improved as compared with the first embodiment. This is because C _sub can be further reduced by lowering the carrier concentration of the p-type Si layer, and C _db can be further reduced.

In addition, this invention is not limited to the above-mentioned embodiment. For example, in the first and second embodiments, the superlattice buffer layer 4 is used. In the present invention, instead of the superlattice buffer layer, a composition gradient buffer layer in which the Al composition is gradually reduced, The buffer layer may be a combination of a composition gradient buffer layer and a superlattice buffer layer. The film thickness and composition of the Al _0.2 Ga _0.8 N barrier layer 7 may be changed depending on the required two-dimensional electron gas concentration and threshold voltage.

Further, in the first and second embodiment, using _{photolithography,} the ohmic contact and _Al 0.2 _{Ga 0.8} N barrier between Al 0.2 _{Ga 0.8} N barrier layer 7 and the source electrode 11 The ohmic contact between the layer 7 and the drain electrode 12 was obtained. However, in the present invention, the ohmic contact between the barrier layer and the source and drain electrodes may be obtained by using, for example, a recess ohmic method or by forming a metal in the barrier layer and annealing.

Moreover, in the said 1st, 2nd embodiment, although the layer thickness of the p-type Si layer 1b was 10 micrometers as an example, you may set in the range of 5 micrometers-25 micrometers. When the thickness of the Si layer is 5 μm to 25 μm, the Si layer can be depleted more reliably, and the parasitic capacitance C _db can be more reliably reduced at the interface.

  The nitride semiconductor device of the present invention is not limited to the HFET of the first and second embodiments, and may be a field effect transistor having another configuration.

  Although specific embodiments of the present invention have been described, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

The epitaxial wafer of the present invention is
A Si substrate 1a;
A Si layer 1b formed on the Si substrate 1a or on the surface of the Si substrate 1a;
A plurality of nitride semiconductor layers 2, 3, 4, 5, 6, 7 formed on the Si layer 1b;
The resistivity of the Si substrate 1a is 0.1 Ω · cm or less,
The resistivity of the Si layer 1b is 10 Ω · cm or more and less than 1000 Ω · cm.

  According to the epitaxial wafer of the present invention, the resistivity of the Si substrate 1a is 0.1 Ω · cm or less, which is realized, for example, by adding a p-type impurity element. Since the substrate to which the impurity element is added is harder than the high-purity substrate to which no impurity is added, the Si layer 1b and the nitride semiconductor layers 2, 3, 4, 5, 6, and 7 are formed on the Si substrate 1a. In the formed epitaxial wafer, warpage of the epitaxial wafer caused by the difference in thermal expansion coefficient between Si and the nitride semiconductor can be reduced.

The resistivity of the Si layer 1b is 10 Ω · cm or more and less than 1000 Ω · cm, and is realized by, for example, reducing the impurity concentration. Here, in general, the concentration of the semiconductor impurity is inversely proportional to the resistivity of the semiconductor, and the width of the semiconductor depletion layer is proportional to the square root of the impurity concentration. The parasitic capacitance due to the depletion layer is inversely proportional to the width of the depletion layer. The parasitic capacitance of the Si layer 1b can reduce the parasitic capacitance _{C db} at the interface between the Si substrate 1a and the nitride semiconductor layer 2,3,4,5,6,7.

In the epitaxial wafer of one embodiment,
The layer thickness of the Si layer 1b is not less than 5 μm and not more than 25 μm.

According to the embodiment, by setting the thickness of the Si layer 1b to 5 μm or more and 25 μm or less, the Si layer 1b can be depleted more reliably, and the parasitic capacitance C _db can be more reliably reduced at the interface.

Moreover, the manufacturing method of the epitaxial wafer of the present invention includes:
A step of ion-implanting an n-type dopant into the surface of a p-type Si substrate 1a having a resistivity of 0.1 Ω · cm or less to form a Si layer having a resistivity of 10 Ω · cm or more and less than 1000 Ω · cm;
And a step of forming a plurality of nitride semiconductor layers 2, 3, 4, 5, 6, and 7 on the Si layer.

According to the epitaxial wafer manufacturing method of the present invention, an n-type dopant is ion-implanted into the surface of a p-type Si substrate 1a having a resistivity of 0.1Ω · cm or less, and the resistivity is 10Ω · cm or more and less than 1000Ω · cm. A step of forming a certain Si layer, and a step of forming a plurality of nitride semiconductor layers 2, 3, 4, 5, 6, and 7 on the Si layer. The resistivity of the p-type Si substrate 1a is 0.1 Ω · cm or less, and is realized by adding a p-type impurity element. Since the substrate to which the impurity element is added is harder than the high-purity substrate to which no impurity is added, the Si layer and the nitride semiconductor layers 2, 3, 4, 5, 6, and 7 are formed on the p-type Si substrate 1a. In the formed epitaxial wafer, the warpage of the nitride semiconductor device caused by the difference in thermal expansion coefficient between Si and the nitride semiconductor can be reduced. Further, by depleting the Si layer formed by ion implantation of the n-type dopant on the surface of the p-type Si substrate 1a, a parasitic capacitance is newly added to the Si layer, and the added parasitic capacitance causes the p-type Si substrate 1a. And the parasitic capacitance C _db can be reduced at the interface between the nitride semiconductor layers 2, 3, 4, 5, 6, and 7. Further, the resistivity and thickness of the Si layer 1b can be strictly controlled as compared with the case where the Si layer 1b is formed by diffusing phosphorus on the surface of the p-type Si substrate 1a.

The nitride semiconductor device of the present invention is
A Si substrate 1a;
A Si layer 1b formed on the Si substrate 1a or on the surface of the Si substrate 1a;
A plurality of nitride semiconductor layers 2, 3, 4, 5, 6, 7 formed on the Si layer 1b;
A source electrode 11, a drain electrode 12 and a gate electrode 13 formed on the plurality of nitride semiconductor layers 2, 3, 4, 5, 6, 7;
The resistivity of the Si substrate 1a is 0.1 Ω · cm or less,
The resistivity of the Si layer 1b is 10 Ω · cm or more and less than 1000 Ω · cm.

  According to the nitride semiconductor device of the present invention, the resistivity of the Si substrate 1a is 0.1 Ω · cm or less, which is realized, for example, by adding a p-type impurity element. Since the substrate to which the impurity element is added is harder than the high-purity substrate to which no impurity is added, the Si layer 1b and the nitride semiconductor layers 2, 3, 4, 5, 6, and 7 are formed on the Si substrate 1a. In the formed epitaxial wafer, the warpage of the nitride semiconductor device caused by the difference in thermal expansion coefficient between Si and the nitride semiconductor can be reduced.

The resistivity of the Si layer 1b is 10 Ω · cm or more and less than 1000 Ω · cm, and is realized by, for example, reducing the impurity concentration. Here, in general, the concentration of the semiconductor impurity is inversely proportional to the resistivity of the semiconductor, and the width of the semiconductor depletion layer is proportional to the square root of the impurity concentration. The parasitic capacitance due to the depletion layer is inversely proportional to the width of the depletion layer. Since the resistivity of the Si layer 1b is 100 times or more of the resistivity of the Si substrate 1a, the parasitic capacitance of the Si layer 1b is at least 10 times or more of the parasitic capacitance of the Si substrate 1a. The parasitic capacitance of the Si layer 1b, thereby reducing the parasitic capacitance _{C db} at the interface between the Si substrate 1a and the nitride semiconductor layer 2,3,4,5,6,7.

1a p-type Si substrate 1b p-type Si layer 2 AlN initial growth layer 3 Al _0.2 Ga _0.8 N layer 4 superlattice buffer layer 5 GaN channel layer 6 AlN intermediate layer 7 Al _0.2 Ga _0.8 N barrier Layer 11 Source electrode 12 Drain electrode 13 Gate electrode

Claims (4)

A Si substrate;
A Si layer formed on the Si substrate or on the Si substrate surface;
A plurality of nitride semiconductor layers formed on the Si layer,
The resistivity of the Si substrate is 0.1 Ω · cm or less,
An epitaxial wafer characterized in that the resistivity of the Si layer is 10 Ω · cm or more and less than 1000 Ω · cm. The epitaxial wafer according to claim 1,
An epitaxial wafer characterized in that the thickness of the Si layer is not less than 5 μm and not more than 25 μm. A step of ion-implanting an n-type dopant into the surface of a p-type Si substrate having a resistivity of 0.1 Ω · cm or less to form a Si layer having a resistivity of 10 Ω · cm or more and less than 1000 Ω · cm;
And a step of forming a plurality of nitride semiconductor layers on the Si layer. A Si substrate;
A Si layer formed on the Si substrate or on the Si substrate surface;
A plurality of nitride semiconductor layers formed on the Si layer;
A source electrode, a drain electrode and a gate electrode formed on the plurality of nitride semiconductor layers,
The resistivity of the Si substrate is 0.1 Ω · cm or less,
The nitride semiconductor device, wherein the resistivity of the Si layer is 10 Ω · cm or more and less than 1000 Ω · cm.

Images