KR20150091706A - Nitride semiconductor and method thereof - Google Patents

Nitride semiconductor and method thereof Download PDF

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KR20150091706A
KR20150091706A KR1020140012239A KR20140012239A KR20150091706A KR 20150091706 A KR20150091706 A KR 20150091706A KR 1020140012239 A KR1020140012239 A KR 1020140012239A KR 20140012239 A KR20140012239 A KR 20140012239A KR 20150091706 A KR20150091706 A KR 20150091706A
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layer
buffer layer
gan
thin film
algan
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KR1020140012239A
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Korean (ko)
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조성무
김준호
김재무
장태훈
황의진
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엘지전자 주식회사
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Publication of KR20150091706A publication Critical patent/KR20150091706A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The present specification relates to a nitride semiconductor device and a manufacturing method thereof. The present invention provides the nitride semiconductor device and the manufacturing method thereof, capable of obtaining a normally-off property by using a p-GaN gate layer, minimizing a leakage current due to an acceptor trap of MgxNy, and improving the crystallization of a GaN channel by using a MgxNy/GaN super-lattices buffer (SLs buffer). For this, the semiconductor device according to one embodiment of the present invention includes a buffer layer, a supper lattice buffer layer which is formed on the buffer layer, a GaN channel layer which is formed on the super lattice buffer layer, an AlGaN barrier layer which is formed on the GaN channel layer, and a p-GaN gate layer which is formed on the AlGaN barrier layer. The super lattice buffer layer is formed by laminating a plurality of dual thin film layers on which the first thin film layer and the second thin film layer are laminated. Wherein, the first thin film layer is different from the second thin film layer.

Description

[0001] NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING [0002]

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

With the emphasis on green energy, the importance of power semiconductors is growing. Power semiconductors used in inverters such as electric vehicles, air conditioners and refrigerators are currently being manufactured by Silicon. However, nitride semiconductors of new materials are attracting attention as high critical electric field, low on resistance, high temperature and high frequency operation characteristics as compared with silicon and are being studied as materials of next generation power semiconductor devices.

Recently, mainstream power MOSFETs and IGBTs have been widely used in high output power devices, and devices such as HEMTs, HFETs, and MOSFETs have been studied in GaN series.

In the case of HEMTs, high-electron mobility is used for communication devices having high-frequency characteristics.

In addition, HEMTs have been used for power semiconductor devices and communication devices with high frequency characteristics. In recent years, hybrid / fuel cell vehicles are being developed, and hybrid cars are being launched by many overseas companies. A voltage booster converter that connects a motor and a generator in a hybrid vehicle and a semiconductor switch in the inverter require reliable operation at high temperatures due to the heat generated by the engine. The wide bandgap of GaN enables reliable high temperature operation and is suitable as a next-generation semiconductor switch in hybrid vehicles.

Among them, Furukawa Electric of Japan has announced the discrete high-electron-mobility transistor (HEMT) of AlGaN / GaN. It has high breakdown voltage of 750 V and low on-resistance of 6.3 mΩ-cm2, , Si superjunction MOSFET and SiC MESFET. In addition, GaN discrete was stable at a high temperature of 225 ℃.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET).

Referring to FIG. 1, a general HFET can switch a 2DEG current flowing from a drain electrode to a source electrode through a schottky gate electrode.

A general HFET 10 includes a substrate (not shown), a first GaN layer 11 formed on the substrate, an AlGaN layer 12 formed on the first GaN layer, a second GaN layer 12 formed on the AlGaN layer, A layer 13, a gate electrode 14, a source electrode 15 and a drain electrode 16 formed on the second GaN layer.

On the other hand, this kind of HFET device is excellent in voltage and current characteristics and many attempts have been made to use it as a high output power device. However, unlike other devices such as MOSFET and IGBT, a disadvantage .

The technique taught in the present specification relates to a nitride semiconductor device and a manufacturing method, by using the Mg x N y / GaN superlattice buffer layer (SLs buffer, Super-lattices buffer) to improve the crystallinity of the GaN channel, Mg x N a nitride semiconductor device having a normally-off characteristic by using a p-GaN gate layer and a manufacturing method thereof are manufactured by minimizing a leakage current due to an acceptor trap of y It has its purpose.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a buffer layer; A superlattice buffer layer formed on the buffer layer; A GaN channel layer formed on the superlattice buffer layer; An AlGaN barrier layer formed on the GaN channel layer; And a p-GaN gate layer formed on the AlGaN barrier layer. The superlattice buffer layer may be formed by stacking a plurality of first thin film layers and a second thin film layer stacked on the first thin film layer and the second thin film layer.

As an example related to the present specification, the thickness of the buffer layer may be 1 nm to 7 um.

As an example related to the present specification, the buffer layer may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

As an example related to the present specification, the AlN buffer layer may include a plurality of layers made of AlN grown at different temperatures.

As an example related to the present specification, the number of the plurality of layers made of AlN grown at the different temperatures may be 2 to 5.

As one example related to the present specification, the AlN buffer layer includes a first AlN layer grown at a low temperature; And a second AlN layer formed on the first AlN layer and grown at a high temperature.

As one example related to the present specification, the AlGaN buffer layer may include a plurality of layers made of AlGaN having different Al compositions.

As an example related to the present specification, the number of the plurality of layers made of AlGaN having different compositions of Al may be 2 to 5.

As one example related to the present specification, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be continuously decreased with a specific slope in the stacking direction.

As one example related to the present specification, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be discontinuously decreased in the stacking direction.

In one embodiment of the present invention, the thickness of at least one of the first thin film layer and the second thin film layer may be 1 nm to 100 nm.

As an example related to the present specification, the first thin film layer may be made of Mg x N y (0? X , y? 1), and the second thin film layer may be made of GaN.

As an example related to the present specification, the number of the double thin film layers to be stacked may be 2 to 500.

As an example related to the present specification, the superlattice buffer layer may be doped with a p-type dopant.

As one example related to the present specification, the p-type dopant may be at least one of Mg, C and Fe.

As an example related to the present specification, the concentration of the p-type dopant may be 3e 17 / cm 3 to 1e 20 / cm 3 .

As an example related to the present specification, the concentration of the p-type dopant may be decreased along the stacking direction of the superlattice buffer layer.

As an example related to the present specification, the thickness of the GaN channel layer may be 1 um to 3 um.

As an example related to the present specification, the GaN channel layer may be doped with at least one dopant of Mg, C and Fe.

As an example related to the present specification, the at least one dopant concentration may be 3e 17 / cm 3 to 1e 20 / cm 3 .

As an example related to the present specification, the thickness of the AlGaN barrier layer may be 10 nm to 30 nm.

As one example related to the present specification, the AlN layer may be formed on a substrate.

As one example related to the present specification, the substrate may be made of at least one of Si, SiC, Sapphire, and GaN.

As an example related to the present specification, the semiconductor device may further include a gate electrode formed on the p-GaN gate layer.

As an example related to the present specification, the semiconductor device may further include a drain electrode and a source electrode formed on a part of the AlGaN barrier layer.

As an example related to the present specification, the semiconductor device may further include an oxide film layer formed on the AlGaN barrier layer, the source electrode, the drain electrode, and a part of the gate electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a buffer layer on a substrate; Forming a superlattice buffer layer on the buffer layer; Forming a GaN channel layer on the superlattice buffer layer; Forming an AlGaN barrier layer on the GaN channel layer; And forming a p-GaN gate layer on the AlGaN barrier layer, wherein the superlattice buffer layer is formed by stacking a plurality of first thin film layers and a second thin film layer stacked on the first thin film layer and the second thin film layer.

As an example related to the present specification, the method of manufacturing a semiconductor device may further include forming a gate electrode on the p-GaN gate layer.

As an example related to the present specification, the method of manufacturing a semiconductor device may further include forming a drain electrode and a source electrode on a part of the AlGaN barrier layer.

As an example related to the present specification, the manufacturing method of the semiconductor device may further include forming an oxide film layer on the AlGaN barrier layer, the source electrode, the drain electrode, and a part of the gate electrode.

At least one of the buffer layer, the superlattice buffer layer, the GaN channel layer, the AlGaN barrier layer, and the oxide layer may be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) , HILP vapor deposition (HVPE), plasma enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

As an example related to the present specification, the buffer layer may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

In one embodiment of the present invention, the thickness of at least one of the first thin film layer and the second thin film layer may be 1 nm to 100 nm.

As an example related to the present specification, the first thin film layer may be made of Mg x N y (0? X , y? 1), and the second thin film layer may be made of GaN.

As an example related to the present specification, the number of the double thin film layers to be stacked may be 2 to 500.

As an example related to the present specification, the superlattice buffer layer may be doped with a p-type dopant.

As one example related to the present specification, the p-type dopant may be at least one of Mg, C and Fe.

As an example related to the present specification, the concentration of the p-type dopant may be 3e 17 / cm 3 to 1e 20 / cm 3 .

As an example related to the present specification, the concentration of the p-type dopant may be decreased along the stacking direction of the superlattice buffer layer.

According to one embodiment of the present invention, a nitride semiconductor device and a method of fabricating the same are provided. The Mg x N y / GaN super lattice buffer (SLs buffer) A nitride semiconductor device having a normally-off characteristic using a p-GaN gate layer and minimizing a leakage current due to an acceptor trap of Mg x N y , and a method of manufacturing the same to provide.

Particularly, according to the semiconductor device disclosed in this specification, the leakage current of the epi is reduced through the Mg x N y / GaN superlattice buffer layer which can block vertical leakage current, and the AlGaN barrier layer (AlGaN active layer or AlGaN barrier The on-off operation of the current by the 2DEG of the p-GaN gate layer is controlled by the pn-junction characteristic of the p-GaN gate layer, thereby providing a semiconductor device having high efficiency switching characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET).
2 is an exemplary view showing a structure of a semiconductor device according to an embodiment disclosed herein.
3 is a graph illustrating the doping profile of an Fe dopant according to one embodiment disclosed herein.
4 is a graph depicting the doping profile of an Fe dopant according to another embodiment disclosed herein.
5 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment disclosed herein.
6A to 6F are views showing an example of a method of manufacturing a semiconductor device according to an embodiment disclosed herein.

The techniques disclosed herein can be applied to a heterojunction field effect transistor and a manufacturing method thereof. However, the technique disclosed in this specification is not limited thereto, and can be applied to all nitride-based semiconductor devices to which the technical idea of the above-described technique can be applied and a manufacturing method thereof.

In recent years, according to the growth technology of a nitride semiconductor, the development of a light emitting diode and a blue-violet laser diode covering a red wavelength band in ultraviolet rays has been completed and has already been widely used in traffic lights, electric sign boards, mobile phones and the like.

Compared with Si-based devices, power-supply devices using nitride semiconductors have superior switching speed and withstand voltage characteristics, and have high current saturation rates, which is advantageous over Si-based devices for high-power, high-voltage applications.

That is, since GaN, which is a typical nitride semiconductor, has a large band gap energy and can form a two-dimensional 2DEG channel through heterojunction, the threshold voltage is large and high-speed operation can be performed.

These high power, high speed characteristics are attracting attention as a next generation power semiconductor material because they are well suited for power semiconductors that require high operating voltage and low energy loss on switching.

In order to fabricate such a nitride-based HFET, an epitaxial layer having a 2DEG structure must be grown. In general, substrates such as sapphire, Si, SiC and AlN are used.

Here, Si substrates have many merits as substrates for nitride power semiconductors because they can be mass-produced and have a low cost. However, the thermal expansion coefficient of Si is lower than that of GaN, and the probability of cracking is increased due to the tensile stress of the GaN layer at the time of cooling down after growth.

That is, since compound semiconductors are generally used on different types of substrates, stress and defects due to difference in lattice constant may occur. It is difficult to grow a high-quality epilayer due to crystal defects caused by incomplete bonding of compounds, There may be a disadvantage in that there is.

The technique disclosed herein improves the crystallinity of a GaN channel by using a Mg x N y / GaN super lattice buffer (SLs buffer) and improves the crystallinity of an Mg x N y acceptor trap And a method of manufacturing the nitride semiconductor device, which has a normally-off characteristic by using a p-GaN gate layer.

In the case of the Mg x N y layer, it is difficult to grow a uniform single layer and the island type layer is likely to grow.

However, when the GaN layer is grown on the GaN layer, the GaN layer can be grown laterally and the GaN layer can be prevented from propagating in the growth direction. Therefore, when the GaN layer is repeatedly grown with the superlattice, a high quality GaN channel can be grown thereon.

Thus, the technique disclosed herein reduces the leakage current of an epi through a Mg x N y / GaN superlattice buffer layer that can block vertical leakage currents and reduces the leakage current of the 2DEG of the AlGaN barrier layer (AlGaN active layer or AlGaN barrier) The on-off operation of the current by the p-GaN gate layer is controlled by the pn-junction characteristic of the p-GaN gate layer, thereby providing a semiconductor device having high efficiency switching characteristics.

It is noted that the technical terms used herein are used only to describe specific embodiments and are not intended to limit the scope of the technology disclosed herein. Also, the technical terms used herein should be interpreted as being generally understood by those skilled in the art to which the presently disclosed subject matter belongs, unless the context clearly dictates otherwise in this specification, Should not be construed in a broader sense, or interpreted in an oversimplified sense. In addition, when a technical term used in this specification is an erroneous technical term that does not accurately express the concept of the technology disclosed in this specification, it should be understood that technical terms which can be understood by a person skilled in the art are replaced. Also, the general terms used in the present specification should be interpreted in accordance with the predefined or prior context, and should not be construed as being excessively reduced in meaning.

Also, the singular forms "as used herein include plural referents unless the context clearly dictates otherwise. In this specification, the terms "comprising ", or" comprising ", etc. should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps.

Furthermore, terms including ordinals such as first, second, etc. used in this specification can be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals denote like or similar elements, and redundant description thereof will be omitted.

Further, in the description of the technology disclosed in this specification, a detailed description of related arts will be omitted if it is determined that the gist of the technology disclosed in this specification may be obscured. It is to be noted that the attached drawings are only for the purpose of easily understanding the concept of the technology disclosed in the present specification, and should not be construed as limiting the spirit of the technology by the attached drawings.

In the nitride-based semiconductor device, In the buffer layer  Explanation for

In power semiconductors, nitride semiconductors (GaN) are attracting attention as devices with high breakdown voltage and low on-resistance.

However, it is difficult to grow the device because the cost of the substrate is high and it is difficult to grow the device to maintain the lattice mismatch without defective GaN.

In addition, sapphire and SiC can not be processed by conventional semiconductor processes in post-growth process, so new process processes may need to be developed.

For this reason, we will use Silicon, which is a low-cost, low-cost substrate for semiconductor processing. In the case of Silicon, lattice mismatch with GaN, which is a nitride semiconductor, If the device is fabricated, the leakage current of the device can be increased by acting as a leakage path.

Therefore, when a buffer layer such as AlGaN is inserted between the GaN and the silicon substrate, the defect density can be reduced by reducing the lattice mismatch, and the Epi stress due to the difference in the lattice constant between the GaN and the silicon is reduced , even if the thicker GaN is grown, the generation of cracks can be prevented.

In the case of the device using Grade AlGaN buffer, the AlGaN layer having 1 to 5 Al compositions is grown on the AlN nucleation layer, thereby reducing the latitude mismatch between the silicon and the GaN buffer layer and growing the thick GaN buffer layer There may be advantages to grow.

Hereinafter, the buffer layer in the nitride semiconductor device according to the embodiment disclosed in this specification will be described in more detail.

II-V compound semiconductors are advantageous for high-speed and high-power devices because they can produce devices with high mobility and high current density by using 2-dimentional electron gas (2DEG) due to heterojunction have.

However, due to the 2DEG generated by the structural characteristics, the device has a normally-on characteristic, and since the additional voltage is applied for the off state, the standby state of the device also consumes power.

Compound semiconductors such as GaN have a weak n-type doping effect without intentional doping due to N-vacancy occurring in the bonding process such as Gallium and Nitride, and donors derived from impurities existing in the reaction chamber .

This defects and impurities act to lower the resistivity of GaN, which may cause leakage current problems to the outside region of the active layer.

The MOCVD process is known to typically form GaN with an electron concentration of 1 x 10 16 cm -3 .

In addition, since they are grown on different substrates such as sapphire, SiC, and Si, defects due to the difference in lattice constant with the substrate are generated. Therefore, when a conductive substrate such as Si is used, it is vulnerable to leakage current. Therefore, there is a need for a method for suppressing the leakage current and the leakage current through the buffer layer (or the buffer layer) and the normally off-off characteristic of the device.

There are several ways to reduce the leakage current from the epilayers in a nitride semiconductor power device with a heterojunction structure.

In particular, there may be a method of growing at least one buffer layer between the substrate and the GaN layer (or GaN channel layer) to reduce the leakage current.

In addition, in order to efficiently reduce the leakage current through the buffer layer, not only the semi-insulating function of the GaN channel needs to be strengthened, but also the crystal defects of the buffer layer for growing the buffer layer are minimized and the semi-insulating property is also increased, It may be necessary to minimize the vertical and lateral leakage currents.

This is a particularly necessary part of the operation of a high power device.

The technique disclosed in this specification proposes an effective epitaxial structure that reduces the leakage current of the buffer layer for GaN growth.

According to one embodiment disclosed herein, there may be various kinds of buffer layers for growing GaN on a substrate (for example, a Si substrate). For example, the buffer layer may have a structure including at least one of an AlN layer (AlN buffer layer or AlN nucleation layer), an AlGaN layer (or an AlGaN buffer layer), and a multi-buffer layer.

In the description of a semiconductor device according to an embodiment disclosed herein below with reference to FIG. 2, the buffer layer may be a buffer layer and a superlattice buffer layer .

That is, the buffer layer in FIG. 2 refers to a layer including at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN, and the superlattice buffer layer has a structure in which a first thin film layer and a second thin film layer, It may mean that a plurality of double thin film layers are stacked and formed.

According to one embodiment, the AlN layer (AlN buffer layer or AlN nucleation layer) may comprise a plurality of layers of AlN grown at different temperatures.

For example, the number of the plurality of layers made of AlN grown at the different temperatures may be 2 to 5.

Also, for example, an AlN buffer can be used in combination of low temperature and high temperature. That is, the lower portion of the AlN buffer may be formed by low temperature growth, and the upper portion of the AlN buffer may be formed by high temperature growth. In this case, the AlN layer may include a first AlN layer grown at a low temperature and a second AlN layer grown on the first AlN layer and grown at a high temperature.

Also, according to one embodiment, the AlGaN buffer layer may include a plurality of layers made of AlGaN having different Al compositions.

For example, the number of the plurality of layers made of AlGaN having different Al compositions may be 2 to 5.

Also, for example, a continuous graded or graded buffer having a high Al content in the lower layer of the AlGaN buffer and a low Al composition in the upper layer may be used.

That is, according to one embodiment, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be continuously decreased with a specific slope in the stacking direction.

According to another embodiment, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be discontinuously decreased in the stacking direction.

A semiconductor device according to an embodiment may include a superlattice buffer layer.

Here, the superlattice buffer layer includes

The first thin film layer and the second thin film layer may be stacked on one another.

Accordingly, the superlattice buffer layer may be a superlattice structure.

According to one embodiment, the first thin film layer may be made of Mg x N y (0? X , y? 1), and the second thin film layer may be made of GaN.

That is, the superlattice buffer layer may have a Mg x N y / GaN structure.

Therefore, when the buffer layer has a multiple buffer structure (or a multiple superlattice layer), the multiple buffer structure (or the superlattice buffer layer) may be formed by alternately stacking two different thin film layers.

According to the embodiment disclosed herein, the various types of buffer layers may be used as a single buffer layer, but may be combined with each other to be provided in one semiconductor element.

For example, the semiconductor device according to one embodiment may have a structure in which the AlN buffer (or AlN buffer layer) is formed on a substrate, and the superlattice buffer layer is formed on the AlN buffer layer.

In this case, the AlN buffer layer is a seed layer for growing GaN on the substrate, and may be referred to as a nucleation layer.

In general, the type of the substrate may be Si, SiC, an insulating substrate (e.g., sapphire substrate), a GaN substrate, or the like.

For example, when the substrate is a Si substrate, when the GaN layer is grown (or deposited or laminated) directly on the Si substrate, the crystallinity of the GaN layer is lowered due to the difference in lattice constant between Si and GaN, There may be a problem that the leakage current increases and the breakdown voltage characteristic deteriorates.

Therefore, as described above, by growing at least one buffer layer in the middle instead of growing the GaN layer directly on the Si substrate, it is possible to improve the crystallinity of the GaN layer and improve the leakage current characteristic and the breakdown voltage characteristic have.

In summary, the technique disclosed in this specification is a technique to which a new Mg x N y / GaN superlattice structure is applied to a nitride semiconductor device, and a nitride semiconductor having a leakage current reducing effect by an Mg acceptor trap Device.

According to the Mg x N y / GaN superlattice structure (or superlattice buffer layer) according to the technique disclosed in the present specification, the lateral growth of GaN can be induced through the 3D growth of the island to block the potential propagation in the growth direction as much as possible, It has the advantage of blocking the flow of leakage current by generating two point defects of Mg acceptor trap of MgN and C acceptor trap of GaN.

Hereinafter, a structure of a semiconductor device and a manufacturing method thereof according to an embodiment disclosed herein will be described with reference to FIGS. 2 to 4. FIG.

The work disclosed herein In the embodiment  Description of the semiconductor device according to

A semiconductor device according to an embodiment disclosed herein includes a buffer layer; A superlattice buffer layer formed on the buffer layer; A GaN channel layer formed on the superlattice buffer layer; An AlGaN barrier layer formed on the GaN channel layer; And a p-GaN gate layer formed on the AlGaN barrier layer.

Here, the superlattice buffer layer may be formed by stacking a plurality of first thin film layers and second thin film layers stacked on each other.

According to one embodiment, the thickness of the buffer layer may be 1 nm to 7 μm.

According to an embodiment, the buffer layer may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

According to one embodiment, the AlN buffer layer may include a plurality of layers made of AlN grown at different temperatures.

Also, according to an embodiment, the number of the plurality of layers made of AlN grown at different temperatures may be 2 to 5.

According to an embodiment, the AlN buffer layer may include a first AlN layer grown at a low temperature; And a second AlN layer formed on the first AlN layer and grown at a high temperature.

According to an embodiment, the AlGaN buffer layer may include a plurality of layers made of AlGaN having different Al compositions.

According to an embodiment, the number of the plurality of AlGaN layers having different compositions of Al may be 2 to 5.

Also, according to one embodiment, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be continuously decreased with a specific slope in the stacking direction.

According to an embodiment, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be discontinuously decreased in the stacking direction.

Also, according to one embodiment, the thickness of at least one of the first thin film layer and the second thin film layer may be 1 nm to 100 nm.

According to an embodiment, the first thin film layer may be made of Mg x N y (0? X , y? 1), and the second thin film layer may be made of GaN.

According to one embodiment, the number of the stacked double-layer layers may be 2 to 500.

According to one embodiment, the superlattice buffer layer may be doped with a p-type dopant.

According to one embodiment, the p-type dopant may be at least one of Mg, C, and Fe.

According to one embodiment, the concentration of the p-type dopant may be 3e 17 / cm 3 to 1e 20 / cm 3 .

Also, according to one embodiment, the concentration of the p-type dopant may be decreased along the stacking direction of the superlattice buffer layer.

According to one embodiment, the thickness of the GaN channel layer may be 1 um to 3 um.

According to one embodiment, the GaN channel layer may be doped with at least one dopant of Mg, C, and Fe.

According to one embodiment, the at least one dopant concentration may be 3e 17 / cm 3 to 1e 20 / cm 3 .

Also, according to one embodiment, the thickness of the AlGaN barrier layer may be 10 nm to 30 nm.

According to one embodiment, the AlN layer may be formed on a substrate.

According to one embodiment, the substrate may be made of at least one of Si, SiC, Sapphire, and GaN.

The semiconductor device according to an embodiment may further include a gate electrode formed on the p-GaN gate layer.

In addition, the semiconductor device according to an embodiment may further include a drain electrode and a source electrode formed on a part of the AlGaN barrier layer.

The semiconductor device according to an embodiment may further include an oxide layer formed on the AlGaN barrier layer, the source electrode, the drain electrode, and a part of the gate electrode.

2 is an exemplary view showing a structure of a semiconductor device according to an embodiment disclosed herein.

2, a semiconductor device 100 according to one embodiment disclosed herein may include a buffer layer 110, a superlattice buffer layer 120, a GaN channel layer 130, and an AlGaN barrier layer 140 have.

The semiconductor device 100 may further include a cap layer (not shown) made of GaN (or nitride or nitride) formed on the AlGaN barrier layer 140.

In addition, the semiconductor device 100 may further include an oxide layer 190 for preventing surface leakage current.

The semiconductor device 100 may further include a gate electrode 160 formed on the p-GaN gate layer.

The semiconductor device 100 may further include a source electrode 170 and a drain electrode 180 formed on a part of the AlGaN barrier layer 140.

The semiconductor device 100 according to an embodiment disclosed herein may switch a 2DEG (CDEG) current flowing from the drain electrode 180 to the source electrode 170 through a schottky gate electrode 160 ) Operation can be performed.

Here, the buffer layer 110 may be formed on a substrate (not shown).

According to one embodiment, the substrate may be n-type, p-type, or various types of materials. For example, the substrate may be at least one of an insulating substrate, a sapphire substrate, a GaN substrate, a SiC substrate, an AlN substrate, and a Si substrate. It will be apparent to those skilled in the art that various types of substrates may be applied to the semiconductor devices disclosed herein.

Further, the substrate can be removed after fabrication of the semiconductor device 100. [ Thus, the final structure of the semiconductor device may be a structure without the substrate.

The buffer layer 110 may be a seed layer for growing GaN on a substrate and may be referred to as a nucleation layer.

Here, the thickness of the buffer layer 110 may be 1 nm to 7 μm.

According to one embodiment, the buffer layer 110 may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

The AlN buffer layer may include a plurality of layers made of AlN grown at different temperatures.

In this case, the number of the plurality of layers made of AlN grown at different temperatures may be 2 to 5.

That is, the AlN buffer layer can be grown under various conditions. For example, the AlN buffer layer may include a first AlN layer grown at a low temperature and a second AlN layer grown at a high temperature formed on the first AlN layer.

The AlGaN buffer layer may include a plurality of layers made of AlGaN having different Al compositions.

Here, the number of the plurality of layers made of AlGaN having different compositions of Al may be 2 to 5.

The Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may vary in various directions depending on the stacking direction.

For example, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be continuously decreased with a specific slope in the stacking direction.

Also, for example, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be discontinuously reduced (for example, a discontinuous decrease in the stacking direction) in the stacking direction.

Specifically, the Al compositional change pattern of at least one of the AlN buffer layer and the AlGaN buffer layer may be similar to the Fe doping concentration profile of the superlattice buffer layer 120 described in FIGS. 3 to 4, which will be described later (FIGS. 4).

2, the superlattice buffer layer 120 includes a first thin film layer p121, p121 ', p121', p121 '' 'and a second thin film layer p122, p122', p122 ' (p120, p120 ', p120' ', p120' '') in which a plurality of thin film layers p122 '' 'are stacked.

Accordingly, the superlattice buffer layer 120 may denote a superlattice layer or a superlattice layer.

According to one embodiment, the number of the plurality of double thin film layers (for example, p120) to be laminated may be 2 to 500. In particular, the number of the plurality of double-layer thin film layers to be laminated may be 20 to 100.

That is, the superlattice buffer layer 120 may include 2 to 500 double thin film layers. Particularly (or preferably), the superlattice buffer layer 120 may comprise 20 to 100 double-layered layers.

In other words, the superlattice buffer layer 120 may have 2 to 500 pairs of the two different thin film layers (for example, p121 and p122). Particularly (or preferably), the superlattice buffer layer 120 may comprise 20 to 100 pairs of the two different thin film layers (for example, p121 and p122).

FIG. 2 shows a case where the superlattice buffer layer 120 includes four thin film layers (p120, p120 ', p120 ", p120' '').

Here, each of the four thin film layers p120, p120 ', p120' 'may include a first thin film layer p121, p121', p121 ', p121' '' and a second thin film layer p122, p122 ' '', p122 '' ') may be stacked.

According to one embodiment, the thickness of each of the first thin film layer p121, p121 ', p121' ', p121' '' and the second thin film layer p122, p122 ', p122' May be 1 nm to 100 nm. In particular (or preferably), the thickness of each of the first thin film layer (p121, p121 ', p121' ', p121' '') and the second thin film layer (p122, p122 ', p122' May range from 5 nm to 35 nm.

According to one embodiment, the first thin film layer p121, p121 ', p121 ", p121''' is made of Mg x N y (0? X , y? 1) , p122 ', p122'',p122''') may be made of GaN.

That is, in this case, the superlattice buffer layer 120 may be a layer having a Mg x N y / GaN structure.

The superlattice buffer layer 120 may be formed by various methods (or methods).

For example, the superlattice buffer layer 120 may be formed by selectively growing a nitride semiconductor crystal. The superlattice buffer layer 120 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxial growth method (MBE) (HVPE). ≪ / RTI > However, considering the crystallinity of the multi-buffer layer 120, MOCVD may be used for device fabrication.

According to one embodiment disclosed herein, the superlattice buffer layer 120 may be formed by doping a specific dopant.

According to one embodiment, the specific dopant may be a p-type dopant. For example, the p-type dopant may be at least one of Mg, C, and Fe.

The p-type dopant may be doped into the superlattice buffer layer 120 in a variety of ways (or methods).

For example, when the p-type dopant is C, a growth rate of GaN is increased to carbon doping the superlattice buffer layer 120 so that the carbon content in the TMGa source itself is formed high in the GaN crystal (or The p-type dopant may be doped in the superlattice buffer layer 120. In this case,

Also, for example, if the p-type dopant is Fe, a new trap is generated by intentionally Fe doping (or on the basis of) the Cp2Fe source, thereby reducing the quality of the thin film and bringing about a semi-insulating effect The superlattice buffer layer 120 having a superlattice buffer structure can be formed.

When the p-type dopant is Fe, the crystallinity of the interface can be improved by minimizing the GaN growth rate of the superlattice buffer layer 120. That is, when Fe (iron) doping is used, a new trap formed by the Fe dopant is maintained while maintaining high-quality crystallinity due to the inherent low-speed growth of GaN, thereby obtaining a semi-insulating effect and reducing the leakage current more efficiently It can have an advantage.

According to an embodiment disclosed herein, the concentration of the p-type dopant may be 1e 16 / cm 3 to 5e 20 / cm 3 . In particular, the concentration of the p-type dopant may be 3e 17 / cm 3 to 1e 20 / cm 3 .

In addition, according to one embodiment, the concentration of the p-type dopant may change in a direction of stacking the superlattice buffer layer 120.

According to one embodiment, the concentration of the p-type dopant may be decreased in the stacking direction of the superlattice buffer layer 120 (for example, a decreasing tendency to decrease).

For example, the concentration of the p-type dopant may be continuously decreased in the stacking direction of the superlattice buffer layer 120.

Also, for example, the concentration of the p-type dopant may be discontinuously decreased in the stacking direction of the superlattice buffer layer 120.

As an example of the discontinuous concentration reduction, there may be a case where the concentration of the p-type dopant is decreased stepwise in the stacking direction of the superlattice buffer layer 120.

In other words, the p-type dopant may be doped based on a doping profile indicating a doping amount with respect to the p-type dopant in the stacking direction of the superlattice buffer layer 120.

Here, the doping profile may be a doping profile in which the doping amount of the p-type dopant is reduced to a specific slope from a specific position of the superlattice buffer layer 120 in the stacking direction.

In addition, the doping profile may be a doping profile in which the doping amount of the p-type dopant is decreased stepwise (or stepwise) from a specific position of the superlattice buffer layer 120 in the stacking direction.

Also, according to one embodiment, the doping amount of the p-type dopant may be less than a minimum doping amount from an upper portion of the superlattice buffer layer 120 to a specific depth.

The specific depth may be 1 nm to 50 nm. The minimum doping amount may be 1e 16 / cm 3 to 1e 17 / cm 3 .

3 is a graph illustrating the doping profile of an Fe dopant according to one embodiment disclosed herein.

3 shows a case where the p-type dopant is Fe.

Referring to FIG. 3, the doping profile for the Fe doping concentration in the superlattice buffer layer 120 can be confirmed.

It can be confirmed that the Fe doping concentration is continuously decreased from the second point P2 to the first point P1 in the superlattice buffer layer 120. [

According to one embodiment, the Fe doping concentration at the second point P2 may be 5e 20 / cm 3 .

Further, according to one embodiment, the doping concentration of the Fe in said first point (P1) may be 1e 16 / cm 3 days.

In addition, according to an exemplary embodiment, the amount of doping may be less than a minimum doping amount from an upper portion of the superlattice buffer layer 120 to a specific depth DELTA l.

For example, the specific depth? 1 may be 2 nm to 50 nm, and FIG. 4 shows a case where the specific depth? 1 is 50 nm.

4 is a graph depicting the doping profile of an Fe dopant according to another embodiment disclosed herein.

Fig. 4 shows a case where the p-type dopant is Fe.

Referring to FIG. 4, the doping profile for Fe doping concentration in the superlattice buffer layer 120 can be confirmed.

It can be confirmed that the Fe doping concentration is decreased stepwise from the sixth point to the third point P6 to P3 in the superlattice buffer layer 120. [

As in FIG. 4, the Fe doping concentration at the sixth point P6 may be 5e 20 / cm 3 , and the Fe doping concentration at the third point may be 1e 16 / cm 3 .

In addition, from the upper portion of the superlattice buffer layer 120 to the specific depth? 1, the doping amount may be less than the minimum doping amount. For example, the specific depth? 1 may be 2 nm to 50 nm, and FIG. 4 shows a case where the specific depth? 1 is 50 nm.

According to another embodiment, the doping of the p-type dopant in the superlattice buffer layer 120 may be performed using the first thin film layer p121, p121 ', p121' 'and the second thin film layer p122, p122', p122 ' The thin film layer may be formed of only one of the thin film layers.

For example, when the first thin film layer p121, p121 ', p121 "is made of Mg x N y (0? X , y? 1) and the second thin film layer is made of GaN, Lt; RTI ID = 0.0 > p-type < / RTI > In this case, the p-type dopant may be one for improving the semi-insulating property of GaN.

Also, in this case, the doping profile disclosed in FIGS. 3 to 4 may be a doping profile corresponding to only the second thin film layer.

Referring again to FIG. 2, the GaN channel layer 130 may have a thickness of 0.1 um to 7 um. Particularly (or preferably), the GaN channel layer 130 may have a thickness of 1 um to 3 um.

The GaN channel layer 130 may be formed in various manners (or methods).

For example, the GaN channel layer 130 may be formed by selectively growing a nitride semiconductor crystal, and may be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and helium vapor deposition (HVPE). ≪ / RTI > However, considering the crystallinity of the GaN channel layer 130, MOCVD may be used for device fabrication.

According to one embodiment, the GaN channel layer 130 may be doped with at least one of C, Fe, Mg, and Mn dopants.

In other words, the semiconductor device 100 includes a GaN channel layer 130 for forming semi-insulating characteristics of a GaN channel formed by implanting at least one dopant of C, Fe, Mg, and Mn dopants, - a resistive GaN layer (not shown).

Here, the concentration of the at least one dopant may be 1e 16 / cm 3 to 5e 20 / cm 3 . In particular, the concentration of the at least one dopant may be 3e 17 / cm 3 to 1e 20 / cm 3 .

Particularly, when the at least one dopant is C, doping of 1e 18 / cm 3 or more may be common.

In addition, as shown, the current end of the GaN channel layer 130 to form a flow channel layer can be minimized in the doping of impurities, in particular C concentration must be doped to less than 1e 17 / cm 3 described above can do.

According to one embodiment, the GaN layer 130 may include a plurality of layers of GaN grown at different temperatures.

Also, according to one embodiment, the number of the plurality of layers made of GaN grown at different temperatures may be 2 to 5.

The AlGaN barrier layer 140 may be formed on the GaN channel layer 130 to form a 2DEG on the channel layer.

That is, the AlGaN barrier layer 140 may be formed on the GaN channel layer 130, and the AlGaN barrier layer 140 may serve as an active layer.

In addition, the thickness of the AlGaN barrier layer 140 may be in the range of 2 nm to 100 nm. In particular (or preferably), the thickness of the AlGaN barrier layer 140 may range from 10 nm to 30 nm.

The AlGaN barrier layer 140 may have a variety of compositions. For example, the composition of Al in the AlGaN barrier layer 140 may be 10% to 30%. It is apparent to those skilled in the art that the AlGaN barrier layer 140 may be formed at various composition ratios.

In particular, the AlGaN barrier layer 140 may have an Al composition of 25% and a thickness of 25 nm.

The AlGaN barrier layer 140 may be formed in a variety of ways (or methods).

For example, the AlGaN barrier layer 140 may be formed by selectively growing a nitride semiconductor crystal. The AlGaN barrier layer 140 may be formed by a metal organic vapor phase epitaxy (MOCVD) method, a molecular beam epitaxial growth method (MBE) (HVPE). ≪ / RTI > However, considering the crystallinity of the AlGaN barrier layer 140, MOCVD may be used for device fabrication.

The GaN cap layer (not shown) may be formed on the AlGaN barrier layer 140 and may be formed by thinly growing a nitride-based material such as GaN or AlGaN.

According to one embodiment, the GaN cap layer may have a thickness of 0.1 nm to 100 nm, particularly 2 nm to 10 nm. The GaN cap layer may serve to prevent surface leakage current.

After the AlGaN barrier layer 140 is grown, a p-GaN gate layer 150 may be grown for a normally-off operation.

As described above for the p-GaN gate layer 150, gate recess, fluorine treatment (or plasma treatment), and p-type gate method (see, for example, Or a p-type gate method).

The gate recess method may be a method of cutting a part of the 2DEG through etching and introducing a Schottky gate to maintain the off characteristic. This can be a drawback to 2DEG loss.

The fluorine treatement method may be a method of depleting electrons by plasma treatment of F ions to maintain off characteristics. This may have drawbacks such as unwanted plasma damage.

Finally, the method of adopting the p-type gate layer may be a method of maintaining the off-off characteristic by using a depletion of the pn junction.

The p-type gate method is a technique capable of performing normally off-switching while maintaining excellent current characteristics of a nitride semiconductor device.

When the p-GaN layer is formed under the gate electrode, the p-GaN layer and the underlying AlGaN / GaN structure form a p-n junction, and a depletion phenomenon may occur.

Therefore, the 2DEG layer disappears at the bottom of the gate, so that when the gate is grounded, the source and the drain can not flow current.

However, when a threshold voltage having a (+) sign is applied to the gate, the lower 2DEG layer of the gate disappears and the current flows and the switching operation can be performed.

 That is, when the p-GaN gate is used, the nitride semiconductor device can be driven to be normally off-driven and high current characteristics can be maintained.

Such a p-GaN gate technique (the technique using the p-GaN gate layer or the p-type gate layer) can be a technique for growing p-type doped GaN on the AlGaN / GaN heterojunction structure and forming a gate electrode therefor. have.

The p-GaN layer may serve to deplete the two-dimensional free electron gas (2DEG) present at the interface between AlGaN and GaN.

The p-GaN gate layer 150 may be a GaN-based (or nitride-based) material doped with a p-type dopant and may be used as a gate layer. Therefore, it may be referred to as a p-type gate layer.

A semiconductor device (e.g., a HEMT or an HFET device) having the p-type gate layer may have the advantage that the normally-off characteristic can be maintained without reducing the 2DEG density.

The thickness of the p-GaN gate layer (or the p-type gate layer 150) may be 2 nm to 300 nm. In particular, the thickness of the p-GaN gate layer 150 may be 10 nm to 100 nm.

The p-type dopant doped in the p-GaN gate layer 150 may be at least one of Mg, C, Zn, and Fe.

For example, the impurity concentration of the p-type dopant doped in the p-GaN gate layer 150 may be 1e 16 / cm 3 to 5e 20 / cm 3 . In particular, the concentration of the impurity may be 3e 17 / cm 3 to 1e 20 / cm 3 .

The semiconductor device 100 may further include a gate electrode 160 (or a p-GaN electrode) formed on the p-GaN gate layer 150.

The semiconductor device 100 may further include a drain electrode 180 and a source electrode 170 formed on a part of the AlGaN barrier layer 140.

The source electrode 170 and the drain electrode 180 may be formed on a portion of the AlGaN barrier layer 140.

In addition, when the semiconductor device 100 further includes the GaN cap layer, the source electrode 170 and the drain electrode 180 may be formed on a part of the GaN cap layer.

A 2DEG (CDEG) current flowing from the drain electrode 180 to the source electrode 170 may be generated through control of the schottky gate electrode 160, as described above.

According to one embodiment, the semiconductor device 100 is formed on a part of the AlGaN barrier layer 140, the source electrode 170, the drain electrode 180, and the gate electrode 160 And may further include an oxide layer 190.

In addition, when the semiconductor device 100 further includes the GaN cap layer, the oxide layer 190 may be formed on a part of the GaN cap layer.

The oxide layer 190 may reduce surface leakage current.

The oxide layer 190 may be formed between the source electrode 170 or the drain electrode 180 and the gate electrode 160.

The oxide layer 190 may have a variety of materials or composition ratios. For example, the oxide layer 190 may be formed of at least one of SiO 2 , Si x N y (for example, Si 3 N 4 ), HfO 2 , Al 2 O 3 , ZnO, and Ga 2 O 3 Lt; / RTI >

According to one embodiment, the thickness of the oxide layer 190 is in the range of 2 nm to 200 nm, and in particular (or preferably) the thickness of the oxide layer 190 may be in the range of 2 nm to 100 nm.

For example, the oxide layer 190 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, a hydride vapor phase epitaxy (HVPE), plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

The work disclosed herein In the embodiment  Description of a method of manufacturing a semiconductor device according to

A method of manufacturing a semiconductor device according to an embodiment disclosed herein may be implemented as a part or a combination of the constituent elements or steps included in the embodiments described above or a combination of the embodiments, Overlapping portions may be omitted for clarity of the method of manufacturing a semiconductor device according to an embodiment.

A method of fabricating a semiconductor device according to an embodiment disclosed herein includes forming a buffer layer on a substrate, forming a superlattice buffer layer on the buffer layer, forming a GaN channel layer on the superlattice buffer layer Forming an AlGaN barrier layer on the GaN channel layer, and forming a p-GaN gate layer on the AlGaN barrier layer.

Here, the superlattice buffer layer may be formed by stacking a plurality of first thin film layers and second thin film layers stacked on each other.

The method of manufacturing a semiconductor device according to an embodiment may further include forming a gate electrode on the p-GaN gate layer.

In addition, the method of manufacturing a semiconductor device according to an embodiment may further include forming a drain electrode and a source electrode on a partial region of the AlGaN barrier layer.

The method of manufacturing a semiconductor device according to an embodiment may further include forming an oxide film layer on the AlGaN barrier layer, the source electrode, the drain electrode, and a part of the gate electrode.

At least one of the buffer layer, the superlattice buffer layer, the GaN channel layer, the AlGaN barrier layer, and the oxide layer may be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) , HILP vapor deposition (HVPE), plasma enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

According to an embodiment, the buffer layer may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

According to an embodiment, at least one of the first thin film layer and the second thin film layer may have a thickness of 1 nm to 100 nm.

According to an embodiment, the first thin film layer may be made of Mg x N y (0? X , y? 1), and the second thin film layer may be made of GaN.

Also, according to one embodiment, the number of the double-layered thin film layers may be 2 to 500.

Also, according to one embodiment, the superlattice buffer layer may be doped with a p-type dopant.

Also, according to one embodiment, the p-type dopant may be at least one of Mg, C, and Fe.

Also, according to one embodiment, the concentration of the p-type dopant may be 3e 17 / cm 3 to 1e 20 / cm 3 .

Also, according to one embodiment, the concentration of the p-type dopant may be decreased along the stacking direction of the superlattice buffer layer.

5 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment disclosed herein.

Referring to FIG. 5, a method of manufacturing a semiconductor device according to an embodiment disclosed herein may include the following steps.

First, a buffer layer may be formed on a substrate (S110).

Next, a superlattice buffer layer may be formed on the buffer layer (S120).

Next, a GaN channel layer may be formed on the superlattice buffer layer (S130).

Next, an AlGaN barrier layer may be formed on the GaN channel layer (S140).

Next, a p-GaN gate layer may be formed on the AlGaN barrier layer (S150).

Here, the superlattice buffer layer may be formed by stacking a plurality of first thin film layers and second thin film layers stacked on each other.

6A to 6F are views showing an example of a method of manufacturing a semiconductor device according to an embodiment disclosed herein.

6A to 6F, a method of manufacturing a semiconductor device according to an embodiment disclosed herein includes sequentially forming a buffer layer 110, a superlattice buffer layer 120, a GaN channel layer 130, And an AlGaN barrier layer 140, as shown in FIG.

As described above, the substrate can be removed after fabrication of the semiconductor device 100. Thus, the final structure of the semiconductor device may be a structure without the substrate.

The method of manufacturing a semiconductor device according to an embodiment disclosed herein may further include the step of forming a gate electrode on the p-GaN gate layer.

The method of manufacturing a semiconductor device according to an embodiment disclosed herein may further include forming a source electrode 170 and a drain electrode 180 on a part of the AlGaN barrier layer 140 .

The method of manufacturing a semiconductor device according to an embodiment disclosed herein may further include the step of forming a gate electrode 160 on the AlGaN barrier layer 140, the source electrode 170, the drain electrode 180, And forming an oxide film layer 190 on the substrate.

6A to 6F, the buffer layer 110 can be formed (or grown) with the MOCVD thin film growth equipment on a substrate (not shown) (FIG. 6A).

As described above, the buffer layer 110 may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

The substrate may be n-type or p-type, and the substrate may be Si, SiC, sapphire, GaN (e.g., Freestanding GaN) substrate, AlN substrate, or the like.

When the buffer layer 110 includes the AlN buffer layer, the AlN buffer layer may be a single layer (or a layer) or may be grown to two to five layers having different temperatures.

TMAl can be used as a raw material of AlN, and NH3 can be used as a raw material of N. [

According to one embodiment, the AlN buffer layer (or AlN nucleation layer) may be used in combination of low temperature and high temperature. That is, the lower portion of the AlN buffer may be formed by the low-temperature growth, and the upper portion of the AlN buffer may be formed by the high-temperature growth (see the first AlN layer and the second AlN layer described above).

In the formation of the AlN buffer layer, an organic metal thin film growth equipment (MOCVD) can be used as a crystal growth method. Trimethylgallium (TMGa), trimethyl aluminum (TMAl) and ammonia (NH3) By synthesizing and growing into an epitaxial layer, a III-V thin film can be formed. The nucleation layer of the conventional method for GaN growth can be grown according to the prepared substrate.

Next, a superlattice buffer layer 120 may be formed on the buffer layer 110 (FIG. 6B).

That is, the superlattice buffer layer 120 may be formed as a buffer on the buffer layer 110.

Specifically, the superlattice buffer layer 120 may be formed by stacking a plurality of the first thin film layer p121 and the second thin film layer p122 stacked on each other.

The manufacturing method disclosed in FIGS. 6A to 6F shows a case where the superlattice buffer layer 120 includes four double-layered films (p120, p120 ', p120' ', p120' '').

Here, each of the four thin film layers p120, p120 ', p120' 'may include a first thin film layer p121, p121', p121 ', p121' '' and a second thin film layer p122, p122 ' '', p122 '' ') may be stacked.

According to one embodiment, the thickness of each of the first thin film layer p121, p121 ', p121' ', p121' '' and the second thin film layer p122, p122 ', p122' May be 1 nm to 100 nm. In particular (or preferably), the thickness of each of the first thin film layer (p121, p121 ', p121' ', p121' '') and the second thin film layer (p122, p122 ', p122' May range from 5 nm to 35 nm.

The superlattice buffer layer 120 may have a Mg x N y / GaN structure.

That is, according to one embodiment, the first thin film layer p121, p121 ', p121'',p121'"is made of Mg x N y (0? X , y? 1) (p122, p122 ', p122'',p122''') may be made of GaN.

It is apparent to those skilled in the art that the superlattice buffer layer 120 may be formed of various materials.

The superlattice buffer layer 120 may be formed by various methods (or methods). For example, the superlattice buffer layer 120 may be formed by selectively growing a nitride semiconductor crystal. The superlattice buffer layer 120 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxial growth method (MBE) (HVPE). ≪ / RTI > However, considering the crystallinity of the superlattice buffer layer 120, MOCVD may be used for device fabrication.

According to one embodiment disclosed herein, the superlattice buffer layer 120 may be formed by doping a specific dopant.

According to one embodiment, the specific dopant may be a p-type dopant. For example, the p-type dopant may be at least one of Mg, C, and Fe.

The p-type dopant may be doped into the superlattice buffer layer 120 in a variety of ways (or methods).

For example, when the p-type dopant is C, a growth rate of GaN is increased to carbon doping the superlattice buffer layer 120 so that the carbon content in the TMGa source itself is formed high in the GaN crystal (or The p-type dopant may be doped in the superlattice buffer layer 120. In this case,

Also, for example, if the p-type dopant is Fe, a new trap is generated by intentionally Fe doping (or on the basis of) the Cp2Fe source, thereby reducing the quality of the thin film and bringing about a semi-insulating effect The superlattice buffer layer 120 having a superlattice buffer structure can be formed.

When the p-type dopant is Fe, the crystallinity of the interface can be improved by minimizing the GaN growth rate of the superlattice buffer layer 120. That is, when Fe (iron) doping is used, a new trap formed by the Fe dopant is maintained while maintaining high-quality crystallinity due to the inherent low-speed growth of GaN, thereby obtaining a semi-insulating effect and reducing the leakage current more efficiently It can have an advantage.

According to an embodiment disclosed herein, the concentration of the p-type dopant may be 1e 16 / cm 3 to 5e 20 / cm 3 . In particular, the concentration of the p-type dopant may be 3e 17 / cm 3 to 1e 20 / cm 3 .

In addition, according to one embodiment, the concentration of the p-type dopant may change in a direction of stacking the superlattice buffer layer 120.

According to one embodiment, the concentration of the p-type dopant may be decreased in the stacking direction of the superlattice buffer layer 120 (for example, a decreasing tendency to decrease). For example, the concentration of the p-type dopant may be continuously decreased in the stacking direction of the multiple buffer layer 120. Also, for example, the concentration of the p- In the direction of the arrow. As an example of the discontinuous concentration reduction, there may be a case where the concentration of the p-type dopant is decreased stepwise in the stacking direction of the superlattice buffer layer 120.

Next, a GaN channel layer 130 may be formed on the superlattice buffer layer 120 (FIG. 7C).

GaN constituting the GaN channel layer 130 may be formed by an organic metal vapor deposition method called MOCVD.

In this case, the GaN channel layer 130 can be formed by epitaxial growth by synthesizing NH 3 , which is a raw material of Ga, as a raw material of Ga, NH 3 in a reactor at a high temperature.

The GaN channel layer 130 may have a thickness of 0.1 um to 7 um. Particularly (or preferably), the GaN channel layer 130 may have a thickness of 1 um to 3 um.

Here, the GaN channel layer 130 may be doped with Fe, Mg or Carbon to form semi-insulating characteristics. The GaN channel layer 130 may also be grown to one temperature or to two to five continuous or discontinuous temperatures.

Next, after the GaN channel layer 130 is grown, an AlGaN barrier layer 140, which is an active layer for forming a hetero-junction 2DEG layer, can be grown (FIG. 6D).

According to one embodiment, the AlGaN barrier layer 140 may be grown at a composition ratio of 10% to 30% Al.

The thickness of the AlGaN barrier layer 150 may be between 10 nm and 50 nm.

The AlGaN barrier layer 150 forms a 2DEG due to a piezo-polarization due to a difference in lattice constant with the GaN channel layer 140. The 2DEG density can be determined according to the Al composition and the thickness.

In addition, after the AlGaN barrier layer 140 (or the active layer) is grown, a GaN cap layer 150 may be grown in the range of 0 nm to 100 nm (preferably in the range of 2 nm to 10 nm) to prevent surface leakage current (Not shown).

Next, the gate electrode 160 may be formed on the p-GaN gate layer.

Additionally, a source electrode 170 and a drain electrode 180 may be formed (or deposited) on a portion of the AlGaN barrier layer 140 (FIG. 6E).

The source electrode 170, the drain electrode 180, and the gate electrode 160 may be deposited using an E-beam as an ohmic electrode.

In addition, in addition, the AlGaN barrier layer 140 (the GaN cap layer 150 when the GaN cap layer 150 is deposited), the source electrode 170, the drain electrode 180, An oxide film layer 190 may be formed on a part of the gate electrode 160 (Fig. 6F).

According to one embodiment of the present invention, a nitride semiconductor device and a method of fabricating the same are provided. The Mg x N y / GaN super lattice buffer (SLs buffer) A nitride semiconductor device having a normally-off characteristic using a p-GaN gate layer and minimizing a leakage current due to an acceptor trap of Mg x N y , and a method of manufacturing the same to provide.

Particularly, according to the semiconductor device disclosed in this specification, the leakage current of the epi is reduced through the Mg x N y / GaN superlattice buffer layer which can block vertical leakage current, and the AlGaN barrier layer (AlGaN active layer or AlGaN barrier The on-off operation of the current by the 2DEG of the p-GaN gate layer is controlled by the pn-junction characteristic of the p-GaN gate layer, thereby providing a semiconductor device having high efficiency switching characteristics.

The scope of the present invention is not limited to the embodiments disclosed herein, and the present invention can be modified, changed, or improved in various forms within the scope of the present invention and the claims.

100: Semiconductor device 110: buffer layer
120: superlattice buffer layer 130: GaN channel layer
140: AlGaN barrier layer 150: p-GaN gate layer

Claims (39)

A buffer layer;
A superlattice buffer layer formed on the buffer layer;
A GaN channel layer formed on the superlattice buffer layer;
An AlGaN barrier layer formed on the GaN channel layer; And
And a p-GaN gate layer formed on the AlGaN barrier layer,
Wherein the superlattice buffer layer comprises:
Wherein the first thin film layer and the second thin film layer are stacked on one another. The method according to claim 1, wherein the thickness of the buffer layer
1 nm to 7 [mu] m. The optical information recording medium according to claim 1,
An AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN. The method of claim 3, wherein the AlN buffer layer
And a plurality of layers of AlN grown at different temperatures. The method according to claim 3, wherein the number of the plurality of layers made of AlN grown at different temperatures,
2 < / RTI > The method of claim 3, wherein the AlN buffer layer
A first AlN layer grown at a low temperature; And
And a second AlN layer formed on the first AlN layer and grown at a high temperature. The method of claim 3, wherein the AlGaN buffer layer
And a plurality of layers made of AlGaN having different compositions of Al. The method according to claim 7, wherein the number of the plurality of layers made of AlGaN,
2 < / RTI > The method according to claim 3, wherein the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer comprises:
And is continuously reduced with a specific inclination in the stacking direction. The method according to claim 3, wherein the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer comprises:
And is discontinuously reduced in the stacking direction. The method according to claim 1, wherein at least one of the first thin film layer and the second thin film layer has a thickness,
1 nm to 100 nm. The method according to claim 1, wherein the first thin film layer
Mg x N y (0? X , y? 1)
The second thin film layer
GaN. The method according to claim 1, wherein the number of the double-
2 < / RTI > The method of claim 1, wherein the superlattice buffer layer comprises:
and doped with a p-type dopant. 15. The method of claim 14, wherein the p-
Mg, C, and Fe. 15. The method of claim 14, wherein the concentration of the p-
3e 17 / cm 3 to 1e 20 / cm 3 . 15. The method of claim 14, wherein the concentration of the p-
And decreases along the stacking direction of the superlattice buffer layer. The GaN substrate according to claim 1,
1 um to 3 um. 2. The GaN substrate according to claim 1,
Mg, < / RTI > C and Fe. 20. The method of claim 19, wherein the at least one dopant concentration is selected from the group consisting of:
3e 17 / cm 3 to 1e 20 / cm 3 . 2. The method of claim 1, wherein the thickness of the AlGaN barrier layer
Wherein the thickness is 10 nm to 30 nm. The method of claim 1, wherein the AlN layer
And is formed on a substrate. 23. The method of claim 22,
Si, SiC, Sapphire, and GaN. The method according to claim 1,
And a gate electrode formed on the p-GaN gate layer. 25. The method of claim 24,
And a drain electrode and a source electrode formed on a part of the AlGaN barrier layer. 26. The method of claim 25,
Further comprising an oxide film layer formed on the AlGaN barrier layer, the source electrode, the drain electrode, and a partial region of the gate electrode. Forming a buffer layer on the substrate;
Forming a superlattice buffer layer on the buffer layer;
Forming a GaN channel layer on the superlattice buffer layer;
Forming an AlGaN barrier layer on the GaN channel layer; And
And forming a p-GaN gate layer on the AlGaN barrier layer,
Wherein the superlattice buffer layer comprises:
Wherein a plurality of the first thin film layer and the second thin film layer are stacked on one another. 28. The method of claim 27,
And forming a gate electrode on the p-GaN gate layer. 29. The method of claim 28,
And forming a drain electrode and a source electrode on a partial region of the AlGaN barrier layer. 30. The method of claim 29,
Forming an oxide film layer on the AlGaN barrier layer, the source electrode, the drain electrode, and a partial region of the gate electrode. 31. The method of claim 30,
At least one of the buffer layer, the superlattice buffer layer, the GaN channel layer, the AlGaN barrier layer,
At least one of metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), helium vapor deposition (HVPE), plasma enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition Wherein the semiconductor device is formed on the basis of a predetermined pattern. 28. The method of claim 27,
An AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN. 28. The method according to claim 27, wherein the thickness of at least one of the first thin film layer and the second thin film layer,
1 nm to 100 nm. 28. The method of claim 27, wherein the first thin film layer
Mg x N y (0? X , y? 1)
The second thin film layer
GaN. ≪ / RTI > 28. The method according to claim 27, wherein the number of the double-
2 < / RTI > to < RTI ID = 0.0 > 500. 28. The method of claim 27, wherein the superlattice buffer layer comprises:
and doped with a p-type dopant. 37. The method of claim 36, wherein the p-
Mg, C, and Fe. 37. The method of claim 36, wherein the concentration of the p-
3e 17 / cm 3 to 1e 20 / cm 3 . 37. The method of claim 36, wherein the concentration of the p-
Wherein the thickness of the superlattice buffer layer is reduced along the stacking direction of the superlattice buffer layer.
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