JP2014238617A - Data processing apparatus, data processing method, and information processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of entire configuration data used for a configuration of a programmable circuit.SOLUTION: In a data processing apparatus processing configuration data on programmable logical elements that can be partially reconfigured, a comparison unit 1 compares the configuration data with each other. Each configuration data includes: a common circuit part data common to all configuration data; and characteristic circuit data different among the configuration data. An extraction unit 2 extracts the common circuit part data from the configuration data on the basis of a comparison result of the comparison unit 1. A deletion unit 3 deletes the common circuit part data extracted by the extraction unit 2 from the configuration data. In a nonvolatile memory storing therein the configuration data on the programmable logical elements, one common circuit part data common to all the configuration data is stored for all the configuration data, and the characteristic circuit data different among the configuration data is stored for each configuration data.

Description

  The present invention relates to a data processing device, a data processing method, and an information processing device.

  Conventionally, a technique for changing the configuration of a programmable circuit by configuring a data input circuit in a programmable circuit and performing configuration based on configuration data input by the data input circuit has been disclosed. (For example, refer to Patent Document 1). Further, a technique is disclosed in which when a failure occurrence of a certain circuit is detected, a programmable spare circuit is reconfigured so as to have the same configuration as that of the failed circuit (see, for example, Patent Document 2).

JP-A-8-307246 JP-A-8-44581

  However, when there are a plurality of configuration data used for the configuration of the programmable circuit, each configuration data has common circuit section data common to all the configuration data and unique circuit data different for each configuration data. . For this reason, since the size of each configuration data becomes large, there is a problem that it takes time to change the configuration of the programmable circuit by the configuration. In addition, since the capacity of the nonvolatile memory for storing all the configuration data increases, the number of memory chips increases or the size of the memory chips increases, resulting in an increase in power consumption, an increase in cost, and other components. There is a problem that the mounting area is reduced. Furthermore, because the size of each configuration data is increased, when changing the configuration data due to changes in specifications or countermeasures for troubles, it takes time to download the entire configuration data after the change to the nonvolatile memory. There is a problem that man-hours increase.

  An object of the present invention is to provide a data processing device, a data processing method, and an information processing device capable of reducing the size of the entire configuration data used for the configuration of a programmable circuit.

  The data processing device processes configuration data of programmable logic elements that can be partially reconfigured. Each configuration data has common circuit section data common to all the configuration data, and unique circuit data different for each configuration data. The data processing apparatus includes a comparison unit, an extraction unit, and a deletion unit. The comparison unit compares the configuration data. The extraction unit extracts common circuit unit data from the configuration data based on the comparison result by the comparison unit. The deletion unit deletes the common circuit unit data extracted by the extraction unit from the configuration data.

  The data processing method is a method of processing configuration data of a programmable logic element that can be partially reconfigured. Each configuration data has common circuit section data common to all the configuration data, and unique circuit data different for each configuration data. The data processing method compares the configuration data, extracts common circuit portion data from the configuration data based on the comparison result, and deletes the extracted common circuit portion data from the configuration data.

  An information processing apparatus includes a programmable logic element that can be partially reconfigured, a nonvolatile memory that stores configuration data of the programmable logic element, and a control device that reads the configuration data from the nonvolatile memory and downloads the data to the programmable logic element . In the nonvolatile memory, one common circuit section data common to all configuration data is stored for the entire configuration data, and unique circuit data different for each configuration data is stored for each configuration data. In a state where the real circuit is configured by the common circuit portion data in the programmable logic element, the control device reads the specific circuit data from the nonvolatile memory, downloads the specific circuit data to the programmable logic element, and re-reads the circuit portion corresponding to the specific circuit data. Configure.

  According to the data processing device, the data processing method, and the information processing device, the size of the entire configuration data used for the configuration of the programmable circuit can be reduced.

FIG. 1 is a diagram illustrating a functional configuration of a first example of the data processing apparatus according to the embodiment. FIG. 2 is a diagram showing a data flow in the data processing apparatus shown in FIG. FIG. 3 is a diagram illustrating an example of a hardware configuration of the data processing apparatus illustrated in FIG. FIG. 4 is a diagram illustrating a first example of the data processing method according to the embodiment. FIG. 5 is a diagram illustrating a first example of the information processing apparatus according to the embodiment. FIG. 6 is a diagram illustrating a second example of the information processing apparatus according to the embodiment. FIG. 7 is a diagram illustrating a configuration example of the main signal device and a configuration data storage example of the nonvolatile memory in the information processing apparatus illustrated in FIG. 6. FIG. 8 is a diagram illustrating an example of configuration data before data processing. FIG. 9 is a diagram illustrating a second example of the data processing method according to the embodiment. FIG. 10 is a diagram illustrating an example of configuration data before data processing when n = 3. FIG. 11 is a diagram showing the transition of the configuration data shown in FIG. (Part 1) FIG. 12 is a diagram showing the transition of the configuration data shown in FIG. (Part 2) FIG. 13 is a diagram illustrating an example of a protocol change processing procedure in the information processing apparatus illustrated in FIG. 6. FIG. 14 is a diagram showing the transition of the circuit configuration of the main signal device in the protocol change process shown in FIG. (Part 1) FIG. 15 is a diagram showing a transition of the circuit configuration of the main signal device in the protocol change process shown in FIG. (Part 2) FIG. 16 is a diagram showing the transition of the circuit configuration of the main signal device in the protocol change process shown in FIG. (Part 3)

  Exemplary embodiments of a data processing device, a data processing method, and an information processing device will be described below in detail with reference to the accompanying drawings. In the following description of each embodiment, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

First Example of Data Processing Device FIG. 1 is a diagram illustrating a functional configuration of a first example of a data processing device according to an embodiment. FIG. 2 is a diagram showing a data flow in the data processing apparatus shown in FIG. As shown in FIGS. 1 and 2, the data processing apparatus includes a comparison unit 1, an extraction unit 2, and a deletion unit 3.

  The comparison unit 1 is connected to the data input terminal 4. The data input terminal 4 receives configuration data of programmable logic elements that can be partially reconfigured. There are a plurality of pieces of configuration data to be processed by the data processing apparatus, and each piece of configuration data has common circuit section data common to all pieces of configuration data and unique circuit data that differs for each piece of configuration data. The comparison unit 1 receives configuration data input from the data input terminal 4 and compares the configuration data.

  The extraction unit 2 is connected to the comparison unit 1. The extraction unit 2 receives the comparison result and configuration data from the comparison unit 1, and extracts common circuit unit data from the configuration data based on the comparison result.

  The deletion unit 3 is connected to the extraction unit 2 and the data output terminal 5. The deletion unit 3 receives the common circuit unit data information and the configuration data from the extraction unit 2, and deletes the common circuit unit data from the configuration data based on the common circuit unit data information. The deletion unit 3 outputs the remaining unique circuit data from the data output terminal 5 as a result of deleting the common circuit unit data from the configuration data.

  FIG. 3 is a diagram illustrating an example of a hardware configuration of the data processing apparatus illustrated in FIG. As illustrated in FIG. 3, the data processing apparatus includes, for example, a CPU (Central Processing Unit) 11, an interface 12, a nonvolatile memory 13, and a volatile memory 14. The CPU 11, interface 12, nonvolatile memory 13, and volatile memory 14 may be connected to the bus 15.

  CPU11 processes the program which implement | achieves the data processing method mentioned later. Thereby, the comparison unit 1, the extraction unit 2, and the deletion unit 3 in the data processing apparatus shown in FIG. 1 are realized. Instead of the CPU 11, for example, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or an FPGA (Field Programmable Gate Array), a programmable field array such as a field programmable gate array. Also good.

  The nonvolatile memory 13 stores a boot program and a program for realizing a data processing method described later. When a programmable logic device is used instead of the CPU 11, the nonvolatile memory 13 may store circuit data used for configuration of the programmable logic device. As an example of the non-volatile memory 13, for example, a ROM (Read Only Memory, ROM) such as a mask ROM (mass chrome), an EEPROM (Electrically Erasable Programmable Read Only Memory), or a flash memory is cited.

  The volatile memory 14 is used as a work area for the CPU 11. The volatile memory 14 holds a program read from the nonvolatile memory 13 and circuit data when the nonvolatile memory 13 is a programmable logic device. The volatile memory 14 holds configuration data to be processed. The volatile memory 14 holds the result of comparison by the comparison unit 1 and information on common circuit unit data by the extraction unit 2. An example of the volatile memory 14 is a RAM (Random Access Memory, RAM) such as a DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory, Eslam).

  The interface 12 controls input of configuration data to be processed and output of specific circuit data output from the deletion unit 3. The configuration data to be processed is stored in a removable medium such as a USB (Universal Serial Bus) memory or an SD memory card (Secure Digital memory card), for example, via the interface 12 from the removable medium. May be stored in the volatile memory 14. Further, the specific circuit data output after the processing may be stored in a removable medium such as a USB memory or an SD memory card via the interface 12 from the volatile memory 14, or a non-volatile in an information processing apparatus described later. May be stored in the memory. In the data processing apparatus illustrated in FIG. 1, the comparison unit 1, the extraction unit 2, and the deletion unit 3 may be realized by hardware.

First Example of Data Processing Method The data processing method may be implemented in the data processing apparatus shown in FIG. In the present embodiment, the data processing method will be described as being implemented in the data processing apparatus shown in FIG.

  FIG. 4 is a diagram illustrating a first example of the data processing method according to the embodiment. As shown in FIG. 4, when data processing is started in the data processing apparatus, configuration data of programmable logic elements that can be partially reconfigured is input to the data processing apparatus. Each configuration data has common circuit section data common to all the configuration data, and unique circuit data different for each configuration data.

  When the configuration data is input to the data processing device, the data processing device compares the configuration data with the comparison unit 1 (step S1). Next, in the data processing apparatus, the extraction unit 2 extracts the common circuit unit data from the configuration data based on the comparison result in the comparison unit 1 (step S2). Then, the data processing device deletes the common circuit portion data extracted by the extracting portion 2 from the configuration data by the deleting portion 3 (step S3), and as a result, the specific circuit data remains, and the series of processing ends.

  A programmable logic element may have a plurality of reconfigurable circuit portions, and a plurality of configuration data may exist for each reconfigurable circuit portion. In that case, the data processing procedure shown in FIG. 4 may be performed for each of the reconfigurable circuit portions.

  According to the data processing apparatus shown in FIG. 1 or the data processing method shown in FIG. 4, the common circuit section data is deleted from each configuration data, and each configuration data becomes only unique circuit data. Therefore, the size of each configuration data is smaller than when each configuration data has common circuit section data and unique circuit data. Therefore, the size of the entire configuration data used for the configuration of the programmable circuit can be reduced.

  As each configuration data size is reduced, the time required to download the configuration data from the non-volatile memory to a partially reconfigurable programmable logic element and change the circuit configuration by configuration is reduced. . As a result, the application switching time in the information processing apparatus having the programmable logic elements that can be partially reconfigured is shortened, and the convenience of the information processing apparatus is improved.

  In addition, when the size of each configuration data is reduced, the capacity of the nonvolatile memory that stores all the configuration data can be reduced. Therefore, the number of memory chips can be reduced, and the memory chip can be reduced in size, so that power consumption and cost can be suppressed, and the mounting area of other components can be increased.

  Further, when the size of each configuration data is reduced, the time required to download the entire configuration data to the nonvolatile memory is shortened. As a result, when the configuration data is changed due to a specification change or countermeasures against defects, the entire configuration data after the change can be downloaded to the non-volatile memory in a short time, thereby reducing the man-hours.

FIG. 5 is a diagram illustrating a first example of the information processing apparatus according to the embodiment. As illustrated in FIG. 5, the information processing apparatus includes a programmable logic element 21, a control device 22, and a nonvolatile memory 23. The programmable logic element 21, the control device 22, and the nonvolatile memory 23 may be connected to the bus 24, for example.

  The programmable logic element 21 is an element having a circuit that can be partially reconfigured, for example. In the following description, a partially reconfigurable circuit may be referred to as a partial reconfiguration area, or PR area for short. Further, partial reconfiguration of a partially reconfigurable circuit may be referred to as partial reconfiguration. Configuring the entire programmable circuit is sometimes referred to as full configuration. The FPGA is an example of the programmable logic element 21.

  The nonvolatile memory 23 stores configuration data used for configuration of the PR area in the programmable logic element 21. The non-volatile memory 23 stores one common circuit section data 25 common to all the configuration data of the programmable logic element 21 for all the configuration data, and different specific circuit data 26 to 28 for each configuration data. Stored for each. The EEPROM or flash memory is an example of the nonvolatile memory 23.

  The control device 22 reads the configuration data from the nonvolatile memory 23 and downloads it to the programmable logic element 21. Thereby, the programmable logic element 21 realizes an application corresponding to the downloaded configuration data. In the state in which the real circuit is configured by the common circuit unit data 25 in the programmable logic element 21, the control device 22 reads the specific circuit data 26 to 28 corresponding to the application from the nonvolatile memory 23 and downloads it to the programmable logic element 21. Thus, the circuit portion corresponding to the specific circuit data 26 to 28 is reconfigured. Thereby, the application realized by the programmable logic element 21 is changed to an application corresponding to the downloaded specific circuit data 26 to 28. An FPGA or ASIC is an example of the control device 22.

  According to the information processing apparatus shown in FIG. 5, the entire configuration data of the programmable logic element 21 includes one common circuit section data 25 and a number of pieces of unique circuit data 26 to 26 corresponding to the number of applications realized by the programmable logic element 21. 28. Therefore, the size of each configuration data is smaller than when each configuration data has common circuit section data 25. Therefore, the size of the entire configuration data used for configuration of the programmable logic element 21 can be reduced.

  When the size of each configuration data is reduced, the time required to download the configuration data from the nonvolatile memory 23 to the programmable logic element 21 and change the circuit configuration by configuration is shortened. Thereby, the application switching time in the information processing apparatus having the programmable logic element 21 is shortened, and the convenience of the information processing apparatus is improved.

  Further, when the size of each configuration data is reduced, the capacity of the nonvolatile memory 23 can be reduced. Therefore, the number of memory chips can be reduced, and the memory chip can be reduced in size, so that power consumption and cost can be suppressed, and the mounting area of other components can be increased.

  Further, when the size of each configuration data is reduced, the time required to download the entire configuration data to the nonvolatile memory 23 is shortened. As a result, when the configuration data is changed due to specification changes or countermeasures against defects, the entire configuration data after the change can be downloaded to the nonvolatile memory 23 in a short time, thereby reducing the man-hours.

  The information processing apparatus illustrated in FIG. 5 can be applied to an optical transmission apparatus such as a muxponder or a transponder that has a function of changing a client port to a plurality of protocols in an optical transmission network, an optical network tester, or the like. As an example of a plurality of protocols, there are protocols such as SONET (Synchronous Optical Network, optical synchronous transmission network), Ethernet (Ethernet: registered trademark), OTN (Optical Transport Network, optical transmission network) and the like. Below, the case where the information processing apparatus shown in FIG. 5 is applied to a muxponder will be described as a second example of the information processing apparatus.

FIG. 6 is a diagram illustrating a second example of the information processing apparatus according to the embodiment. As shown in FIG. 6, the muxponder 31 includes a plurality of client ports 32, a main signal device 33, a network port 34, a control device 35, and a nonvolatile memory 36.

  The main signal device 33 is connected to the client port 32 and the network port 34. The main signal device 33 has a multiplexer and demultiplexer 37. The multiplexer combines signals output from the client ports 32 and outputs the combined signals to the network port 34. The demultiplexer outputs a signal output from the network port 34 to the client port 32.

  The main signal device 33 has a number of PR areas corresponding to the number of client ports 32. By preparing a plurality of configuration data used for the configuration of the PR area and selecting the configuration data from the configuration data to realize the circuit configuration of the PR area, the main signal device 33 can be used as an interface to each client port 32. The protocol is realized. The FPGA is an example of the main signal device 33.

  Each client port 32 is connected to a device on the client side via an optical transmission line such as an optical fiber. The client port 32 receives the optical signal sent from the client side, converts it into an electrical signal, outputs it to the main signal device 33, receives the electrical signal sent from the main signal device 33, and converts it into an optical signal. Convert and output to the client side.

  The network port 34 is connected to the network via an optical transmission line such as an optical fiber. The network port 34 receives an optical signal sent from the network, converts it into an electric signal, outputs it to the main signal device 33, receives an electric signal sent from the main signal device 33, and converts it into an optical signal. And output to the network.

  The nonvolatile memory 36 stores configuration data used for the configuration of the PR area. The EEPROM or flash memory is an example of the nonvolatile memory 36.

  The control device 35 is connected to the nonvolatile memory 36 and the main signal device 33. The control device 35 reads the configuration data from the nonvolatile memory 36 and downloads it to the main signal device 33. Thereby, the main signal device 33 implements various protocols as an interface to each client port 32. The FPGA or ASIC is an example of the control device 35.

  FIG. 7 is a diagram illustrating a configuration example of the main signal device and a configuration data storage example of the nonvolatile memory in the information processing apparatus illustrated in FIG. 6. Although not particularly limited, for example, in the example shown in FIG. 7, ten client ports 32 are provided, and ten PR areas 38 are provided in the main signal device 33 accordingly. The non-volatile memory 36 includes full configuration circuit data 41 used when configuring the entire main signal device 33 and specific circuit data 42 used when configuring each PR area 38 of the main signal device 33. And are stored.

  The full configuration circuit data 41 includes common circuit portion data among circuit data for realizing each protocol of each client port 32. That is, the main signal device 33 is configured by the full configuration circuit data 41 after the information processing apparatus is turned on or reset is released, so that an initial setting protocol is realized in each PR area 38 of the main signal device 33. However, the common circuit part in each PR area 38 is implement | achieved in that case. The full configuration circuit data 41 is an example of initial configuration data.

  Although not particularly limited, for example, in the example illustrated in FIG. 7, five protocols are implemented for each client port 32. Therefore, for example, in the nonvolatile memory 36, specific circuit data for realizing the protocol # 1 for the client port # 1, specific circuit data for realizing the protocol # 2 for the client port # 1,. -Specific circuit data for realizing the protocol # 5 is stored for the client port # 1. Similarly, for each of client ports # 2 to # 10, specific circuit data for realizing protocol # 1, specific circuit data for realizing protocol # 2,..., For realizing protocol # 5 Specific circuit data is stored. That is, the non-volatile memory 36 stores the full configuration circuit data 41 and a total of 50 specific circuit data 42 for each of the 10 client ports 32 using 5 protocols.

Second Example of Data Processing Method FIG. 8 is a diagram illustrating an example of configuration data before data processing. As shown in FIG. 8, in this embodiment, a case where n protocols are realized for the client port #X will be described as an example. In FIG. 8, PR area #X protocol # 1 circuit data 43 is configuration data used when a real circuit of protocol # 1 is configured in PR area #X corresponding to client port #X. The PR area #X protocol #n circuit data 44 is configuration data used when a real circuit of the protocol #n is configured in the PR area #X corresponding to the client port #X. X is an integer of 1 or more, and n is an integer of 2 or more.

  The PR area #X protocol # 1 circuit data 43 and the PR area #X protocol #n circuit data 44 have address information 45 designating an area in the PR area #X at regular intervals, and immediately after the address information 45, It has actual circuit data 46 for configuring a circuit in an area in the PR area #X designated by the address information 45. For example, in the example shown in FIG. 8, m pieces of address information 45 are inserted into the PR area #X protocol # 1 circuit data 43 and the PR area #X protocol #n circuit data 44. m is an integer of 2 or more.

  In the data structure shown in FIG. 8, the data size of the address information 45 is A byte, the data size of the actual circuit data 46 is B bytes, and the data size of the protocol circuit data 43 and 44 for the PR area #X is C bytes. . A, B and C are integers of 1 or more.

  FIG. 9 is a diagram illustrating a second example of the data processing method according to the embodiment. As shown in FIG. 9, for example, when the data processing apparatus shown in FIG. 1 starts data processing on protocol circuit data used for the configuration of PR area #X, first, the number i of comparison of data is set to 0. The number j of data deletion is set to 0 (step S11). i and j are integers of 0 or more.

  Next, the data processor divides the data size C bytes of the protocol circuit data by the value obtained by adding the data size A bytes of the address information 45 and the data size B bytes of the actual circuit data 46 to obtain the quotient m ( Step S12). The obtained quotient m is the number of address information 45 inserted in the protocol circuit data 43 and 44 used for the configuration of the PR area #X.

  Next, the data processing apparatus determines whether or not the current value of i matches the value of m obtained in step S12 (step S13). If they do not match (step S13: No), the data processing apparatus uses (i) all (i.e., n protocol circuit data 43 and 44) (i) for the configuration used in the PR area #X. -J) Data from (A + B) bytes to (i-j + 1) (A + B) bytes are compared (step S14). Then, the data processing device increments the value of i (step S15).

  Next, the data processing apparatus determines whether or not the data compared in step S14 is the same by the comparison unit 1 (step S16). If they are not the same (step S16: No), the data processing device returns to step S13 and repeats the processing after step S13.

  If they are the same (step S16: Yes), the data processing device increments the value of j (step S17). Then, the data processing apparatus extracts the data portion compared in step S14, that is, the common circuit portion data by the extraction unit 2, and all the protocol circuit data 43 used for the configuration of the PR area #X by the deletion unit 3. , 44 delete the common circuit section data. After deleting the common circuit section data, the data processing apparatus shifts the subsequent data of the deleted common circuit section data by A + B bytes in the head direction because the size of the deleted common circuit section data is A + B bytes ( Step S18). Then, the data processing device returns to step S13. Note that either step S17 or step S18 may be first.

  In step S13, the data processing apparatus repeats steps S13 to S18 until the current value of i matches the value of m obtained in step S12. When the current i value matches the m value (step S13: Yes), all the address information 45 and the actual circuit data 46 in the protocol circuit data 43 and 44 used for the configuration of the PR area #X. Since the comparison has been completed for the set, the data processing apparatus ends the series of processes. By the end of the processing, all protocol circuit data used for the configuration of the PR area #X becomes specific circuit data not including the common circuit section data.

  For each PR area provided in the main signal device 33, the data processing device performs the above-described processing of steps S11 to S18 on all protocol circuit data used for configuration of each PR area. For example, in the case of the example shown in FIG. 7, protocol # 1 circuit data, protocol # 2 circuit data, and protocol # 3 circuit data for realizing the protocols # 1 to # 5 in the PR area # 1 corresponding to the client port # 1, respectively. For the protocol # 4 circuit data and the protocol # 5 circuit data, the data processing device performs the processes of steps S11 to S18 described above. Similarly for the PR area # 2 corresponding to the client port # 2, the data for the protocol # 1 circuit data, the protocol # 2 circuit data, the protocol # 3 circuit data, the protocol # 4 circuit data, and the protocol # 5 circuit data The processing device performs the processes of steps S11 to S18 described above. The same applies to PR areas # 3 to # 10 corresponding to client ports # 3 to # 10, respectively.

  FIG. 10 is a diagram illustrating an example of configuration data before data processing when n = 3. The transition of the configuration data in the data processing procedure described above will be specifically described by taking n = 3, that is, a case where three protocols are realized for the client port #X as an example. As shown in FIG. 10, in PR area #X protocol # 1 circuit data 51, PR area #X protocol # 2 circuit data 52, and PR area #X protocol # 3 circuit data 53, for example, each data size C is set to 15 bytes. The data size A of the address information is 1 byte, and the data size B of the actual circuit data is 2 bytes.

  In the PR area #X protocol # 1 circuit data 51, the PR area #X protocol # 2 circuit data 52, and the PR area #X protocol # 3 circuit data 53, for example, the actual circuit data for the address information of 01 is 0123, 0123 and 0123, respectively. 0022. For example, the real circuit data for the address information of 02 is 4567, 4567, and 4567, respectively, and the real circuit data for the address information of 03 is 89AB, 88AA, and 99BB, respectively. For example, it is assumed that the actual circuit data for the address information of 04 is CDEF, CCDD, and CCDD, respectively, and the actual circuit data for the address information of 05 is FFFF, FFFF, and FFFF, respectively. Note that the values of the address information and actual circuit data are expressed in hexadecimal numbers.

  11 and 12 are diagrams showing changes in the configuration data shown in FIG. When the data processing procedure shown in FIG. 9 is started, first, both the value of i and the value of j are set to 0 (step S11), and m = 5 (step S12). Since the value of i does not match the value of m (step S13: No), PR area #X protocol # 1 circuit data 51, PR area #X protocol # 2 circuit data 52, and PR area #X protocol # 3 circuit data 53 The data from the 0th byte to the 3rd byte are compared with each other (step S14). A state 61 shown in FIG. 11 represents the state so far.

  The value of i is incremented to 1 (step S15). Since the data compared in step S14 are 010123, 010123, and 00022, they do not match (step S16: No). Therefore, although it returns to step S13, the value of i does not correspond to the value of m (step S13: No). Therefore, the data from the third byte to the sixth byte of the PR area #X protocol # 1 circuit data 51, the PR area #X protocol # 2 circuit data 52, and the PR area #X protocol # 3 circuit data 53 are compared with each other. (Step S14). A state 62 shown in FIG. 11 represents the state so far.

  The value of i is incremented to 2 (step S15). Since the data compared in step S14 is 024567, 024567, and 024567, they match (step S16: Yes). Therefore, the value of j is incremented to 1 (step S17). Then, the PR area #X protocol # 1 circuit data 51, the PR area #X protocol # 2 circuit data 52, and the PR area #X protocol # 3 circuit data 53 to the data 042567 are deleted, and the subsequent data of 024567 is 3 bytes. It is shifted toward the beginning of the minute (step S18). A state 63 shown in FIG. 11 represents the state so far.

  Returning to step S13, the value of i does not match the value of m (step S13: No). Therefore, the data from the third byte to the sixth byte of the PR area #X protocol # 1 circuit data 51, the PR area #X protocol # 2 circuit data 52, and the PR area #X protocol # 3 circuit data 53 are compared with each other. (Step S14). A state 64 shown in FIG. 12 represents the state so far.

  The value of i is incremented to 3 (step S15). Since the data compared in step S14 is 0389AB, 0388AA and 0399BB, they do not match (step S16: No). Therefore, although it returns to step S13, the value of i does not correspond to the value of m (step S13: No). Therefore, the data from the 6th byte to the 9th byte of the PR area #X protocol # 1 circuit data 51, the PR area #X protocol # 2 circuit data 52, and the PR area #X protocol # 3 circuit data 53 are compared with each other. (Step S14). A state 65 shown in FIG. 12 represents the state so far.

  The value of i is incremented to 4 (step S15). Since the data compared in step S14 are 04CDEF, 04CDDD, and 04CDDD, they do not match (step S16: No). Therefore, although it returns to step S13, the value of i does not correspond to the value of m (step S13: No). Therefore, the data in the 9th to 12th bytes of the PR area #X protocol # 1 circuit data 51, the PR area #X protocol # 2 circuit data 52, and the PR area #X protocol # 3 circuit data 53 are compared with each other. (Step S14). A state 66 shown in FIG. 12 represents the state so far.

  The value of i is incremented to 5 (step S15). Since the data compared in step S14 is 05FFFF, 05FFFF, and 05FFFF, they match (step S16: Yes). Accordingly, the value of j is incremented to 2 (step S17). Then, the data of 05FFFF is deleted from the PR area #X protocol # 1 circuit data 51, the PR area #X protocol # 2 circuit data 52, and the PR area #X protocol # 3 circuit data 53 (step S18). A state 67 shown in FIG. 12 represents the state so far.

  Returning to step S13, since the value of i matches the value of m, a series of data processing ends. When the data processing is completed, the PR area #X protocol # 1 circuit data 51, the PR area #X protocol # 2 circuit data 52, and the PR area #X protocol # 3 circuit data 53 each have a unique circuit portion that constitutes a unique circuit portion. Only circuit data.

Example of Muxponder Protocol Change Processing Procedure FIG. 13 is a diagram showing an example of a protocol change processing procedure in the information processing apparatus shown in FIG. 14 to 16 are diagrams showing changes in the circuit configuration of the main signal device in the protocol change process shown in FIG.

  As shown in FIG. 13, after the muxponder 31 is powered on or reset, the reconfiguration control logic of the control device 35 accesses the non-volatile memory 36 and the full configuration circuit data 41 from the non-volatile memory 36. Is acquired (step S21). A state 71 shown in FIG. 14 represents the state so far. In this state, the main signal device 33 is in a NULL state in which no circuit is configured.

  Next, the reconfiguration control logic of the control device 35 downloads the full configuration circuit data 41 acquired from the non-volatile memory 36 to the main signal device 33 (step S22), and performs full configuration on the entire main signal device 33. Perform As a result, the PR area corresponding to each client port of the main signal device 33 has a circuit configuration that implements the default protocol, and the interfaces of all the client ports are constructed in the default protocol (step S23). A state 72 shown in FIG. 14 represents the state so far.

  Here, it is assumed that the protocol of client port # 1 is changed to protocol #Y, and the protocol of client port #X is changed to protocol # 1. The reconfiguration control logic of the control device 35 accesses the nonvolatile memory 36 and acquires the client port # 1 protocol #Y specific circuit data 47 from the nonvolatile memory 36 (step S24). A state 73 shown in FIG. 15 represents the state so far.

  Next, the reconfiguration control logic of the control device 35 downloads the client port # 1 protocol #Y specific circuit data 47 acquired from the nonvolatile memory 36 to the main signal device 33 (step S25). Then, the reconfiguration control logic performs partial reconfiguration on the PR area # 1_61 corresponding to the client port # 1 of the main signal device 33. As a result, a circuit portion specific to the PR area # 1_61 is reconfigured by the circuit data specific to the client port # 1 protocol #Y. Since the common area of PR area # 1_61 has already been configured in PR area # 1_61 by the full configuration in step S22, PR area # 1_61 has a circuit configuration that implements protocol #Y. Therefore, the interface of the client port # 1 is constructed with the protocol #Y (step S26). A state 74 shown in FIG. 15 represents the state so far.

  In the state 74 shown in FIG. 15, the common circuit part of the PR area # 1_61 is an area indicated by a lattice pattern, and the specific circuit part of the PR area # 1_61 is an area indicated by a dot pattern. Only the area of the specific circuit portion indicated by the dot pattern is reconstructed.

  Next, the reconfiguration control logic of the control device 35 accesses the nonvolatile memory 36 and acquires the client port #X protocol # 1 specific circuit data 48 from the nonvolatile memory 36 (step S27). A state 75 shown in FIG. 16 represents the state so far.

  Next, the reconfiguration control logic of the control device 35 downloads the client port #X protocol # 1-specific circuit data 48 acquired from the nonvolatile memory 36 to the main signal device 33 (step S28). Then, the reconfiguration control logic performs partial reconfiguration for the PR area # X_62 corresponding to the client port #X of the main signal device 33. As a result, the circuit portion specific to the PR area # X_62 is reconfigured by the circuit data specific to the client port #X protocol # 1. Since the common circuit unit of PR area # X_62 has already been configured in PR area # X_62 by the full configuration in step S22, PR area # X_62 has a circuit configuration for realizing protocol # 1. Accordingly, the interface of the client port #X is constructed in the protocol # 1 (step S29). A state 76 shown in FIG. 16 represents the state so far.

  In the state 76 shown in FIG. 16, the common circuit part of the PR area # X_62 is an area indicated by an oblique lattice pattern, and the specific circuit part of the PR area # X_62 is an area indicated by an oblique stripe pattern.

  According to the data processing method shown in FIG. 9 or the information processing apparatus shown in FIG. 6, the common circuit section data is deleted from each configuration data, and subsequent data is shifted in the head direction. Therefore, the size of each configuration data is small. Become. Therefore, for example, the size of the entire configuration data used for the configuration of the main signal device of the Muxponder can be reduced. Further, since the common circuit portion data is included in the full configuration circuit data, the size of the entire configuration data can be reduced as compared with the case where the common circuit portion data is provided separately from the full configuration circuit data. As a result, the time required to change the protocol in the muxponder is shortened, so that the performance of the muxponder is improved.

  According to the data processing method shown in FIG. 9 or the information processing apparatus shown in FIG. 6, the size of each configuration data is reduced by about 30 to 40%, for example, depending on the ratio of common circuit section data to each configuration data. Can do. When full configuration circuit data is included, the size of the entire configuration data can be reduced by about 2.5 to 3.5%, for example.

  The data processing method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program may be recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and may be executed by being read from the recording medium by the computer.

  The data processing apparatus described in this embodiment can also be realized by an application-specific IC such as a standard cell or a structured ASIC, or a PLD (Programmable Logic Device) such as an FPGA. Specifically, for example, the comparison unit 1, the extraction unit 2 and the deletion unit 3 of the data processing apparatus described above are defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD to perform data processing. The device can be manufactured.

  The following additional notes are disclosed with respect to the embodiments including the above-described examples.

(Appendix 1) Configuration data of programmable logic elements that can be partially reconfigured, including configuration data having common circuit section data common to all configuration data and unique circuit data that differs for each configuration data A comparison unit for comparing; an extraction unit for extracting the common circuit unit data from the configuration data based on a result of comparison by the comparison unit; and the common circuit unit data extracted by the extraction unit as the configuration data A data processing apparatus comprising: a deletion unit that deletes the data from the data processing unit.

(Supplementary note 2) The data processing apparatus according to supplementary note 1, wherein the deletion unit shifts subsequent data of the deleted common circuit unit data by a size of the deleted common circuit unit data.

(Supplementary Note 3) Configuration data of programmable logic elements that can be partially reconfigured, including configuration data having common circuit portion data common to all configuration data and unique circuit data that differs for each configuration data A data processing method comprising: comparing, extracting the common circuit section data from the configuration data based on the comparison result, and deleting the extracted common circuit section data from the configuration data.

(Supplementary note 4) The data processing method according to supplementary note 3, wherein data subsequent to the deleted common circuit portion data is shifted by the size of the deleted common circuit portion data.

(Supplementary Note 5) A programmable logic element that can be partially reconfigured, a nonvolatile memory that stores configuration data of the programmable logic element, and the configuration data is read from the nonvolatile memory and downloaded to the programmable logic element A common device section data common to all the configuration data is stored in the nonvolatile memory, and different specific circuit data for each configuration data is stored for each configuration data. The control device reads the specific circuit data from the nonvolatile memory and downloads the specific circuit data to the programmable logic element in a state where an actual circuit is configured by the common circuit unit data in the programmable logic element. To reconfigure the circuit portion corresponding to the specific circuit data. The information processing apparatus characterized by.

(Supplementary note 6) The information processing apparatus according to supplementary note 5, wherein the common circuit section data is included in initial configuration data used when configuring the entire programmable logic element.

DESCRIPTION OF SYMBOLS 1 Comparison part 2 Extraction part 3 Deletion part 21 Programmable logic element 22, 35 Control device 23, 36 Nonvolatile memory 25 Common circuit part data 26-28 Specific circuit data 31 Muxponder 33 Main signal device 41 Full configuration circuit data

Claims (4)

Comparing unit that compares configuration data of programmable logic elements that can be partially reconfigured and that has common circuit unit data common to all configuration data and unique circuit data that differs for each configuration data When,
An extraction unit that extracts the common circuit unit data of the configuration data based on a result of comparison by the comparison unit;
A deletion unit that deletes the common circuit unit data extracted by the extraction unit from the configuration data;
A data processing apparatus comprising:   The data processing apparatus according to claim 1, wherein the deletion unit shifts data subsequent to the deleted common circuit unit data by a size of the deleted common circuit unit data. Configuration data of programmable logic elements that can be partially reconfigured, comparing configuration data having common circuit section data common to all configuration data and unique circuit data that differs for each configuration data,
Extracting the common circuit portion data of the configuration data based on the result of the comparison;
A data processing method, wherein the extracted common circuit section data is deleted from the configuration data. A programmable logic element that is partially reconfigurable;
A non-volatile memory for storing configuration data of the programmable logic element;
A control device that reads the configuration data from the nonvolatile memory and downloads the configuration data to the programmable logic element,
In the non-volatile memory, common circuit unit data common to all configuration data is stored for the entire configuration data, and unique circuit data different for each configuration data is stored for each configuration data,
In a state where an actual circuit is configured by the common circuit portion data in the programmable logic element, the control device reads the specific circuit data from the nonvolatile memory, downloads the specific circuit data to the programmable logic element, and downloads the specific circuit data. An information processing apparatus for reconfiguring a circuit portion corresponding to the above.

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