JP2001320271A - Method for reconfiguring circuit into programmable logic circuit and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate or shorten a waiting time between processings in each of circuits in the case of parallel and successively performing processing in reconfigured circuits while successively reconfiguring plural circuits into programmable logic circuit. SOLUTION: Concerning a circuit, with which a former circuit reconfigured before under executing processing thereof exists in the area of at least one part to next reconfigure a circuit, data for reconfiguration are divided into a part to be overlapped with the area of the former circuit and a part not to be overlapped. In the case of real reconfiguration, the part not to be overlapped is reconfigured parallel with processing in the former circuit and after the end of processing in the former circuit, the part to be overlapped is reconfigured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system capable of processing a part of processing by an application program by a programmable logic circuit whose circuit configuration can be reconfigured, and a method of reconfiguring a circuit into a programmable logic circuit. About. In particular, the present invention relates to a method for executing circuit reconfiguration and processing in parallel and at high speed.

[0002]

2. Description of the Related Art In the field of digital circuit devices, in particular, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and programmable logic devices (PGAs) have been developed in order to shorten the development period of products.
2. Description of the Related Art Programmable logic circuits including LDs) are widely used. By reading circuit information describing the logic circuit into these programmable logic circuits, the connection between the internal logic circuits and the logic circuits can be freely configured.

For this reason, the use of a programmable logic circuit has the advantage that the time required to manufacture an integrated circuit, which conventionally required several weeks to several months after the completion of circuit design, is not required. In particular, electrically reconfigurable programmable logic devices, such as the invention of U.S. Pat. No. 4,700,187, have the advantage that once fabricated circuits can be freely modified as often as needed. It is becoming widely used.

[0004] Recently, logic circuits have increased in complexity, and the circuit scale has increased to a level that cannot be realized by a single programmable logic circuit. As one method for solving this problem, it has been proposed to reconfigure a programmable logic circuit during processing in order to realize different logic circuits at different times. By using this method, there is an advantage that various processes can be performed at relatively high speed even when the size of a circuit that can be built in is limited due to the small size of a device such as a portable information terminal.

However, this method has a drawback in that when reconfiguring a programmable logic circuit, the circuit information of the entire circuit is read again, so that the reconfiguration takes time. Furthermore, reconfiguring in the middle of the process means that the process is temporarily suspended, the data at that time is saved in a storage device outside the programmable logic circuit, new circuit information is read and reconfigured, and the Extra processing of inputting new data with data and reconstruction is required.

[0006] To solve this problem, a programmable logic circuit described in a data book named "CONFIGURABLE LOGIC" of Atmel, USA and a THEPROGR of Xilinx, USA.
A programmable logic circuit described in a data book named "AMMABLE LOGIC" has a data storage device for storing data, and reads part of circuit information from an external storage device during operation of the circuit to partially store the circuit information. By performing the reconfiguration, the time required for the reconfiguration is minimized.

A problem when such a programmable logic circuit is used in an information processing system is that circuit information for forming a desired logic circuit is extracted from a storage destination, and a plurality of pieces of circuit information are synthesized as needed, thereby obtaining a desired logic circuit. Application processing must be performed at high speed and efficiently while reconfiguring the logic circuit.

The above-described information system for processing a plurality of pieces of circuit information by a programmable logic circuit can be used by connecting to a network. As an example, there is a “reconfigurable network computer” disclosed in Japanese Patent Application Laid-Open No. 10-78932, which will be described as a first conventional example with reference to FIG.

The information processing system of the prior art 1 is composed of a plurality of computers connected to a communication network NET, at least one of which is a computer (application server) SB for distributing an application program, and the rest of the computers SB. The computer is a system configured by a computer (client computer) CL which is a client that downloads and executes the application program. An extended hardware (extended HW) 1 capable of changing and reconfiguring functions as needed by a program is mounted on a part of the plurality of client computers CL.

The application program AP stored in the application server SB has, for some of its functions, a program code (extension code) executed by extension hardware and a main processor (main processor) of the client computer CL. P) 2 contains the main processor code executed.

OS of the client computer CL
Has a function of determining whether or not the extended hardware 1 is installed, and includes a code selection function 3 for extracting a code suitable for the hardware configuration from the application program AP based on the determination. When the extension hardware 1 is installed as in the client computer CL on the upper side in FIG. 9, the extension code is extracted from the application program AP through the code selection function 3 and is executed by the extension hardware. The processing is executed.

In the case where the extended hardware 1 is not provided as in the client computer CL shown in the lower part of FIG. 9, the main processor code is extracted from the application program AP through the code selecting function 3 and is executed. The process is executed in 2.

In another configuration, a function realized by the extended hardware 1 is realized as an OS extended function or a dynamic library which can be dynamically added / deleted later on the client computer CL, and an application program Registers the type of an extended function or a dynamic library used during processing with the OS. The OS uses the extended function or the dynamic library if it exists on the client, and if not, transfers and uses the required extended function or the dynamic library from a server on the network.

Further, the code for the main processor 2 and the code for the extended hardware 1 are not integrated, but individual codes for each extended function or dynamic library of the application program or the OS are transferred to the host computer. Can also be provided above.

The configuration of the programmable logic constituting the extended hardware 1 is a client computer C
If different between L, the extension code may be a basic module in which the function of a logic circuit with an appropriate number of gates and the number of input / output terminals is described by a Boolean expression or the like, and a code expressing their connection relation. In the case of a function for assigning each basic module to a basic program of programmable logic, and in the case of a large extension code extending over a plurality of programmable logic chips, the basic module is divided according to the degree of connection and arranged and wired to each programmable logic chip. The function of the application server S
B or on the client computer CL.

A hardware resource management function of reusing unnecessary hardware resources for another application program so that a plurality of applications using the extended hardware 1 can be executed simultaneously;
It has a code replacement function for replacing an extension code that cannot be accommodated in the extension hardware 1 by time division. Priority value appropriately set for each application program executed on the client computer CL, processing capacity value of the main processor 2, processing capacity value of the extended hardware 1, amount of hardware resources, processing capacity required for code replacement It has an extended hardware management function for selecting multiple application programs that cannot fit into the hardware resources based on the values.

When a plurality of applications use the same extension code in the extension hardware 1 at the same time, the function is shared by switching only the internal state by time division.

As described above, when an application program distributed from a server is executed on a client side on a computer connected to a network, the client can use a program to change its function as needed and use reconfigurable extended hardware. The application program installed and stored in the server includes the main processor code and extension code,
The configuration of the computer on the client side is changed by the code selection function that has determined the type, and the application program can be processed at high speed by making the configuration suitable for processing.

Conventionally, when trying to start a new service that requires special hardware on the client side on the network, the user on the client side has to introduce new hardware for that purpose. Service providers have decided to offer new services only to some users with new hardware. Thus, a new service can be started without introducing new hardware.

Next, a new device technology for a programmable logic circuit will be described. Configure a processing circuit according to the processing of the application on a programmable logic circuit,
Programmable logic circuits have begun to be used in reconfigurable computing that realizes high-speed processing using this dedicated processing circuit.

In reconfigurable computing, circuit information of a plurality of processing circuits required for application processing is stored in a storage device in advance, and the circuit information read from the storage device is stored in a programmable logic circuit as needed. By writing, a circuit required at that time is generated. This technology is called cache logic technology or virtual logic technology.

The cache logic technique is a time-division driving technique in which different circuits are formed as necessary on the same programmable logic circuit. As a result, by using a programmable logic circuit having a small circuit scale, a circuit larger than the circuit scale can be realized, and the size and cost of the circuit device can be reduced. However, depending on the size of the circuit information to be written in the programmable logic circuit, there is a problem that the reconfiguration time of the circuit becomes longer and the effect of the reconfigurable computing of realizing high-speed processing using a dedicated processing circuit is impaired. .

This configuration of reconfiguration of the circuit acts as processing overhead, that is, process overhead, and causes a reduction in processing speed. To reduce the impact of this overhead,
Parallel processing of configuration and process is performed. In other words, during the execution of a certain process, the configuration of the next circuit is executed in parallel with the non-operating region of the programmable logic circuit.

Here, as a configuration unit, it is assumed that the circuit is subdivided into functional units according to the processing of the application and configuration data is generated. These generated circuit data units are arranged and reconfigured on the programmable logic circuit. After the reconstruction is completed, data processing is sequentially executed as a process. During this process period, configuration data for reconfiguring the next functional circuit is transferred to another non-operating region on the device, and the circuit is reconfigured.

However, if the area to be configured has already been configured and the process is running, it must wait until the process is completed. Therefore, in some cases, there is a problem that the configuration time becomes longer, the next process cannot be started continuously, a waiting time occurs, and the entire processing is slowed down.

This problem will be described with reference to FIGS.
2 will be described. For example, a case will be described in which the processing circuit is divided into four parts and the processing is performed while sequentially performing partial rewriting.

As shown in FIG. 10, the divided circuit blocks are denoted by A, B, C, and D, and their configuration data is represented by CDa, CDb, CDc, and C.
Dd, and each configuration time is t
It is assumed that ca, tcb, tcc, and tcd, and the process times are tpa, pb, tpc, and tpd, respectively.

The configuration time is determined by the speed at which the configuration data is transferred from the storage location to the programmable device, that is, the transfer speed is determined by the transfer frequency and the bus width of the signal line, and the circuit operates up to the maximum operating frequency of those constituent circuits. Becomes possible. Therefore, assuming that the transfer rate is DTR [bps], each configuration time is obtained for the configuration data.

On the other hand, in the processing of the application,
The process time is determined by the operation speed and the circuit configuration of the programmable logic circuit, can be obtained in advance by a circuit operation simulation, and can be calculated in consideration of the processing data amount.

Therefore, when a series of processes from the circuit block A to the circuit block D are sequentially executed, the circuit block A is first configured, and after the completion of the configuration, the process of the circuit block A is executed. At the same time, the configuration of the next circuit block B is executed in parallel. Similarly, after the configuration of the circuit block D is completed, the processing of the circuit block D is executed. further,
When returning to the processing of the circuit block A and repeating it,
The configuration of the circuit block A is executed in parallel with the processing of the circuit block D. As described above, the configuration data is handled in units of circuit blocks, and the processing can be executed after the configuration is completed.

However, if the size of the configuration data is large and the processing time of the preceding functional circuit block is short during the configuration period, a waiting time is generated until the next processing circuit starts to be executed. Therefore, when viewed from the processing time of the entire application, the processing time is longer by the accumulated time of the waiting time, and there is a problem that the performance is reduced.

Now, each of the circuit blocks A to D has a shape and a size as shown in FIG.
The case of being arranged on the programmable logic circuit 4 in a state as shown in FIG. 11 will be described with reference to the processing timing chart of FIG.

First, from the start time t0, the configuration Ca of the circuit block A is performed. From time t1 when the configuration of the circuit block A is completed, the process Pa by the circuit block A is executed, and the configuration Cb of the next circuit block B is executed in parallel with the process Ca for the configuration time tcb. At time t2, the configuration of the circuit block B is completed.

Since the process Pa by the circuit block A and the process Pb by the circuit block B are continuous, the process Pb is continuously executed from the time t3 when the process Pa is completed, and is performed until the time t4 after the process time tpb. It is.

As shown in FIG. 11, the next circuit block C overlaps with the area of the circuit block A, so that the configuration of the circuit block C is not changed until the process Pa ends. Can not. Therefore, the process Pa ends and the process Pb
After the time point t3 at which the operation starts, the configuration of the circuit block C is also started.

However, if the configuration data CDc of the circuit block C is large and the configuration time tcc is longer than the process time tpb of the process Pb of the circuit block B, the process shown in FIG. A waiting time indicated by a period twc occurs.

In FIG. 12, the waiting time t is also set between the process Pd and the configuration Ca.
wa is generated. These waiting times twa and twc are accumulated by the number of repetition cycles from the process Pa to the process Pd, and the overall processing time becomes longer.

As a means for solving this problem, the configuration time can be shortened by reducing the configuration data or increasing the configuration transfer speed.

However, in order to reduce the configuration data, it is necessary to increase the circuit utilization efficiency of the vacant logic circuit portion in the programmable logic circuit. Complicated processing is required using tools, which requires a great deal of time and effort.

When the configuration transfer speed is increased to reduce the configuration time, there is a limit to the operation speed of a circuit related to the transfer, and the configuration time cannot always be shortened from the processing time. In addition, increasing the operating frequency causes an increase in power consumption, which is inappropriate when a low power consumption specification is required for battery driving or the like.

[0041]

As described above, extended hardware is used to speed up the processing of an application program by a conventional general-purpose CPU and software, or to add a new function. In particular, when a program is executed in parallel while reconfiguring a circuit by using a programmable logic circuit as extended hardware, it is necessary to reduce the influence of the reconfiguration time of the circuit.

Normally, the order of processing is determined in the application program, and the functional circuit used for that is also determined in advance. However, since the size of the programmable logic circuit is selected according to the size of the mounted circuit, processing performance, power consumption, and the like suitable for the application system, the division size and arrangement of the circuit blocks are not optimized in advance.

For this reason, when the size of the programmable logic circuit is particularly reduced, as described above, the arrangement may be such that the circuit blocks overlap each other. If the process of the previously configured circuit is not completed, the next circuit The block cannot be configured. Therefore, there is a drawback that a waiting time until a process to be started by a circuit to be configured occurs and the overall processing performance is reduced.

In view of the above, it is an object of the present invention to reduce the influence of overhead due to the configuration of a circuit block and improve the processing performance of the entire system.

[0045]

In order to solve the above problems, in a method for reconfiguring a circuit into a programmable logic circuit according to the present invention, a plurality of circuits are sequentially reconfigured in the programmable logic circuit. A method for reconfiguring the plurality of circuits in a case where the processes by the reconfigured circuits are sequentially executed in parallel; For a circuit that has been reconfigured and has a previous circuit for which the process is being executed, the data for reconfiguration is divided into a portion that overlaps the area of the previous circuit and a portion that does not overlap. In addition, the non-overlapping part is reconfigured in parallel with the processing of the preceding circuit, and after the processing of the preceding circuit ends, the overlapping part is reconfigured.

[0046]

According to the present invention having the above-described configuration, the circuit to be reconfigured into a programmable logic circuit and the processing time (process time) of the previous circuit in which processing is being executed is to be reconfigured (configured). Therefore, if a waiting time occurs, the data for reconfiguring the circuit is divided into a part overlapping the area of the previous circuit and a part not overlapping the part, and is generated. .

Then, in the actual configuration, a portion which does not overlap with the preceding circuit of the circuit is reconfigured in parallel with the processing of the preceding circuit. Then, after the processing of the preceding circuit is completed, the portion overlapping with the remaining preceding circuit is reconfigured.

Therefore, it is possible to eliminate or shorten the waiting time between the processings of each circuit, and to shorten the processing time as a whole.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an information processing system according to the present invention and a method for reconfiguring a programmable logic circuit will be described below with reference to the drawings. In addition,
In the embodiment described below, it is assumed that the processing flow such as the circuit information to be used and the processing order is determined in advance in the application program.

[First Embodiment] [Example of Hardware Configuration of Information Processing System] FIG. 2 is a block diagram showing an example of a hardware configuration of an information processing system 10 according to a first embodiment of the present invention. . In the information processing system 10 of this embodiment, the host bus 11B of the CPU 11
Is connected to a main memory 13 composed of a DRAM via a memory controller (not shown) included in the chipset 12.

The host bus 11B is connected to a PCI bus 14 via a host-PCI bus bridge (not shown) included in the chipset 12. The programmable logic circuit interface 21, the hard disk interface 15, and the communication interface 16 are connected to the PCI bus 14.

Then, the programmable logic circuit 22 and the local memory 23 are connected to the programmable logic circuit interface 21. The programmable logic circuit 22 is connected to an external device 31 via an external input / output interface 24, and inputs and outputs data.

The programmable logic circuit interface 21 is connected to the C bus by a system bus such as the PCI bus 14.
It is connected to the PU 11, the main memory 13, and the local memory 23 to perform data transfer and control.
The programmable logic circuit interface 21 includes a functional circuit for interpreting header information added to processing data for reconfiguring the circuit of the programmable logic circuit 22, circuit information for circuit reconfiguration, processing data and intermediate processing data. EOF (End Of F
) is included.

A hard disk drive 17 is connected to the hard disk interface 15. An application program is stored in a hard disk that is read and written by the hard disk drive 17. The application program includes a host-PCI bridge (not shown) included in the hard disk interface 15, the PCI bus 14, and the chipset 12.
Is loaded from the hard disk drive 17 to the main memory 13 and executed by the CPU 11.

The hard disk of the hard disk drive 17 may store circuit information reconfigured in the programmable logic circuit 22.

The communication interface 16 can be connected to various devices via a network 32 such as a LAN or the Internet. Thus, the application program can also access information stored in the storage device 33 connected to the network 32, and can obtain various application programs and data. In this case, the information processing system 10 acquires the application program into the main memory 13 via the communication interface 16 connected to the network 32 and executes the application program, or executes the programmable logic via the programmable logic circuit interface 21 directly from the PCI bus 14. It can also be transferred to the circuit 22.

The programmable logic circuit 22 and its associated peripherals, ie, the programmable logic circuit interface 21, the local memory 23, and the external input / output interface 24 are integrated by integration.
The configuration of the programmable logic circuit unit 20 surrounded by a dotted line in FIG. With the configuration of the unit 20, the line load of the input / output unit can be reduced, and the configuration of a dedicated bus can achieve higher speed and lower power consumption.

Next, the structure of the programmable logic circuit 22 is shown in FIGS. Programmable logic circuit 22
Is composed of a configuration memory 41 for storing circuit information, a logic cell 42, a wiring area 43, and an input / output terminal 44.

The configuration memory 41 includes an EEPROM and a S in the logic cell 42 and the wiring area 43.
It is composed of a rewritable memory element such as a RAM. The circuit data is composed of a pair of an address ADR and data DT. As shown in FIG. 4, when the address ADR is given to the configuration memory 41 and the data DT of the new circuit information paired with the address is stored in the memory cell corresponding to the address, according to the circuit information, The circuit configuration in the logic cell 42 and the connection state of the wiring region 43 for interconnecting the logic cell 42 and the input / output terminal 44 are reconfigured. This series of operations is called a configuration. Configuration memory 41
Can partially reconfigure the circuit even when the programmable logic circuit is operating.

As shown in FIG. 4, data to be processed is input to a circuit element 45 formed by being reconfigured in the programmable logic circuit 22 via an input / output terminal 44, and the processing result is output. Is done. The application program specifies the logic cell of the data input destination and the logic cell of the data output source by a control code indicating the cell coordinates corresponding to the position of the logic cell.

With the above system configuration, data processed by the data input / output method of the processing by the programmable logic circuit 22 includes streaming data such as multimedia images and sounds.

[Method of Reconfiguring into Programmable Logic Circuit] In the method of reconfiguring into a programmable logic circuit according to the present embodiment, the order of processes in an application program, the circuit size of a circuit block corresponding to each process, and the placement address Information, and
Based on the size of the programmable logic circuit, the occurrence of a waiting time for the next process due to the overlap during configuration is detected. Then, the configuration data of the circuit block which causes a waiting time due to the overlapping of the configuration is divided into an overlapping portion and a non-overlapping portion, and the configuration of the non-overlapping portion is executed in parallel with the previous process. , So as to execute the configuration of the overlapping portion.

Thus, by eliminating or shortening the waiting time between the processes, the influence of the overhead due to the configuration is reduced, and the processing performance of the entire system is improved. Note that when the generation time of the divided configuration data can shorten the processing time of the application time, the divided configuration data is naturally generated.

The generation of the divided configuration data is performed by the CPU 11, but may be performed by an arithmetic means such as the CPU in a server connected to the network 32.

First, a description will be given of the size and arrangement of the circuit blocks with respect to the programmable logic circuit, the method of detecting the overlap of the circuit blocks, and the method of generating the divided configuration data.

The size of the programmable logic circuit is selected in accordance with the size of the mounted circuit, processing performance, power consumption, etc., which are suitable for the application system. And the arrangement cannot be determined.

However, in general, circuit block data is generated in a circuit block size that can be used even for a small-sized programmable logic circuit.

The layout of the circuit blocks is determined according to the size of the programmable logic circuit, and the layout is specified by an address. That is, in a large-sized programmable logic circuit, the degree of freedom in arrangement is high, and thus the overlap of the circuits is reduced. On the other hand, in a small-sized programmable logic circuit, the overlap is increased due to restrictions on the arrangement.

When the arrangement state is determined, it is possible to determine in advance whether or not the area overlaps between circuit blocks by using the address information.

That is, first, in order to detect whether or not a circuit block to be configured overlaps an area where a process is being executed, the configuration time of the circuit block to be configured and the time of execution during the configuration are determined. Compare with the middle process time. If the configuration time is longer than the process time, a waiting time between processes will occur, so that it is determined to perform the overlap processing. If it is determined that the configuration time is shorter than the process time and does not overlap, the configuration is performed as it is.

Here, in the case of overlapping, a process of generating divided configuration data for separating the overlapping portion and the non-overlapping portion for each logic cell of the programmable logic circuit is performed.

In the process of generating the divided configuration data, the non-overlapping portions are configured in parallel with the previous process, and the overlapping portions are configured after the previous process is completed. In this way, by prioritizing the configuration of the circuit portion having no overlap, the configuration time from the end of the previous process can be reduced.

For example, the circuit blocks A to A shown in FIG.
Taking the case of D as an example, the configuration time tcc of the circuit block C is longer than the process time tpb of the circuit block B, so that the circuit block C does not overlap with the circuit block A as shown in FIG. , A region C1 that does not affect the process in the circuit block A, and a region C2 that overlaps the circuit block A and affects the process in the circuit block A.

Note that, as shown in FIG.
Is divided into an area C1 that does not affect the processing of the circuit block A and an area C2 where the configuration is to be executed after the processing of the circuit block A is completed.
Is required to be completely separated from the circuit block A, so that the programmable logic circuit is divided in units of logic circuit cells. Even if the boundary is not used in the circuit cells related to the circuit block A, It is included in the area C2 as the overlap extension Cm. Similarly, for the wiring, up to the portion included in the circuit block A, the overlapping extension Cm
In the area C2.

There are two modes for detecting the overlap of the circuit blocks and for generating the divided configuration data. One is a method in which the presence or absence of overlapping circuit blocks is checked before application processing is started, and if there is, divided configuration data is first generated, and the application is executed using the data. The other is the first cycle after the start of application processing, checking for the presence or absence of overlapping circuit blocks. If there is an overlap, generate divided configuration data, and in the subsequent processing, use the divided configuration. How to run the application.

In either case of the former case or the latter case, the division and generation processing of the configuration data may be performed by either the CPU 11 in the information processing system 10 or the server connected to the network 32. .

[First Mode; Detection Before Application Processing Starts, and Generation of Divided Data] The first mode of the two modes listed as the method of detecting the overlap of circuit blocks and generating the divided configuration data is shown in FIG. 5 and the timing chart of FIG. 6 and the flowchart of FIG.

Prior to the start of the application processing, the circuit block in which the overlapping portion occurs is determined based on the size of the programmable logic circuit, the individual size and the arrangement address of the functional circuit block, and the processing order as described above. The waiting time is detected by comparing with the process time. This is a processing method for dividing and generating detected configuration data. These processing flows will be described with reference to the flowchart shown in FIG.

Here, a case is shown in which the configuration and the process are sequentially executed for N types of circuit blocks.

First, a variable j indicating the order of the circuit blocks is initialized (j = 1) (step S1), and the time tcj of the configuration Cj of the j-th circuit block is initialized.
Is calculated (step S2). The configuration time tcj is determined by the speed at which the configuration data is transferred from the storage location to the programmable logic circuit, that is, the transfer speed is determined by the transfer frequency and the bus width of the signal line. In this case, the components can operate up to the maximum operating frequency. Therefore, assuming that the transfer rate is DTR [bps], each configuration time is obtained by dividing the configuration data size [bit] by DTR.

Next, it is determined whether or not the order j is the first (step S3). If it is the first time, the process time tp for comparing the configuration time tcj with the configuration time tcj is as follows for an application in which a plurality of circuit blocks are repeated.
Process time tp of the last circuit block PM (j = M)
(M) is determined (step S4). If the order j is not the first, the configuration time tc
The process time tp for time comparison with j is the process time tp (j-1) of the immediately preceding process (step S
5).

The process time is determined by the operation speed and the circuit configuration of the programmable logic circuit and can be obtained in advance by simulation or the like. Therefore, the process time is calculated in consideration of the processing data amount in the application.

Then, the configuration time tcj of the j-th configuration Cj and the process time tp calculated in step S4 or S5
(Step S6). In this case, when the configuration time of the first circuit block (j = 1) is reached, the process time tp = t of the last circuit block
The comparison with p (M) is performed, and in the case of the subsequent configuration time of the circuit block, the comparison is performed with the preceding (j−1) th process time tp = tp (j−1).

When the configuration time tcj is longer than the process time tp, it is determined that an overlap has occurred. The flag Fj indicating the overlap state is set to Fj = 1 (step S7). When the overlap time is short, it is determined that there is no overlap. The flag Fj is set to Fj = 0 (step S8).

When the overlap occurs, the address of the configuration data in the overlap area is calculated from the address of the configuration data whose arrangement is determined with respect to the size of the programmable logic circuit (step S9). Based on the address calculation address data, divided configuration data Cj1 and Cj1
j2 is generated (step S10). Here, Cj1
Are treated as non-overlapping areas, and Cj2 is treated as configuration data of the overlapping areas.

Here, the divided configuration data Cj2 on the overlapping portion side is divided by a logic cell, which is the minimum structural unit of the programmable logic circuit, but also includes a cell portion including wiring from the overlapping portion. Also, regarding the divided configuration data Cj1 in the non-overlapping area, the logic cell, which is the minimum configuration unit of the programmable logic circuit, is set as the minimum unit to be divided.

When the generation of the divided configuration data is completed, the variable indicating the order is set to the next order (step S11). When the flag Fj is set to Fj = 0 in Step S8, Step S8 of calculating the address of the overlapping area is performed.
9 and step S1 for generating a split configuration
0, and the configuration order is set to the next order. The process jumps to step S11.

In the same manner, for the last circuit block of the N circuit blocks, the processing of detecting the overlapping area and generating the divided data is performed for all the circuit blocks where the overlap occurs (step S12).

The application processing is executed using the divided configuration data generated as described above (step S13). In this case, by using the configuration data obtained by dividing the overlapping configuration data into Cj1 and Cj2 according to the overlap determination flag Fj, an area Cj1 that does not overlap first is used.
After the previous process is completed, the overlapping area Cj2 is configured.

In the case of the example of four circuit blocks shown in FIG. 5, as shown in FIG. 6, after the configuration of the circuit block B, without waiting for the end of the process Pa of the circuit block A, In parallel with the process Pa,
The configuration Cc1 of the divided configuration data C1 for the non-overlapping region generated in the divided configuration data generation process is executed. After the completion of the process Pa of the circuit block A, the divided configuration data C2 for the overlapping area is concurrently provided with the process Pb of the circuit block B.
Of the configuration Cc2. As described above, in the case of this embodiment, the application can be executed without generating the waiting time twc as in the case of the related art in FIG.

[Second form: detection and division data generation in the first cycle after the start of application processing] In the second form, application processing is a process in which N circuit blocks are repeatedly executed. In the first cycle after the start of the application processing, it is checked whether or not the circuit blocks overlap.
In this method, divided configuration data is generated, and in the subsequent processing, an application is executed using the divided configuration.

Note that a processing time for generating the divided configuration data is required.
There is no need to wait for the second cycle until the generation of the divided configuration data in the cycle is completed. The divided configuration data is generated by the CPU in parallel with the application processing, or divided by a server connected to a network. The split configuration process can be executed from the cycle at which the configuration data can be generated by the configuration data generation process.

In this example, the application processing is to execute a cycle of sequentially executing the configuration and the process M times for N types of circuit blocks.
A process flow in which overlap detection of circuit blocks and generation of a divided configuration are performed in the first cycle, and processing based on the divided configuration data from the second cycle onward will be described with reference to flowcharts shown in FIGS.

First, a variable i indicating the number of cycles and a variable j (equal to a variable indicating the circuit block) j indicating the order of configuration of the circuit block are initialized (step S21). Next, the configuration C (ij) for the j-th circuit block in the i-th cycle is performed (step S22). Then, the process P (i
j) is executed (step S23).

Next, the configuration C (i
j) and the process P (ij) are in the first processing cycle (i = 1) (step S24).
When it is determined that this is the first processing cycle, the time tc of the configuration C (1j) of the j-th circuit block is determined in the first processing cycle.
j is calculated in the same manner as described above (step S2).
5).

Next, it is determined whether or not the order j is the first in the cycle of the first processing (step S26). If it is the first, the process time tp for comparing the time with the configuration time tcj is the first time. Process time tp of the last circuit block PM (j = M) of the cycle
(M) is determined (step S27). Also, if the order j is not the first in the first cycle,
The process time tp to be compared with the configuration time tcj is the process time tp of the immediately preceding process.
(J-1) (Step S28).

Then, the configuration time tcj of the j-th configuration C (1, j),
A comparison is made with the process time tp calculated in step S27 or S28 (step S31). In this case, at the time of the configuration time of the first circuit block (j = 1), comparison is made with the process time tp = tp (M) of the last circuit block, and at the time of the configuration time of the subsequent circuit block. , The (j−1) th process time tp = tp (tp (j−1))
Compare with.

If the configuration time tcj is longer than the process time tp, it is determined that an overlap has occurred. The overlap state flag Fj is set to Fj = 1 (step S32). If the overlap time is short, it is determined that there is no overlap. The flag Fj is set to Fj = 0 (step S33).

When the overlap occurs, the address of the configuration data in the overlap area is calculated from the address of the configuration data whose arrangement is determined with respect to the size of the programmable logic circuit (step S34). The divided configuration data Cj1 and Cj2 are generated based on the address calculation address data (step S35). Here, Cj
1 is treated as a non-overlapping area, and Cj2 is treated as configuration data of the overlapping area.

Here, the divisional configuration data Cj2 on the overlapping portion side is divided by a logic cell which is the minimum structural unit of the programmable logic circuit, but also includes a cell portion including wiring from the overlapping portion. Also, regarding the divided configuration data Cj1 in the non-overlapping area, the logic cell, which is the minimum configuration unit of the programmable logic circuit, is set as the minimum unit to be divided.

However, each divided area Cj1 or Cj1
When the size of j2 is small, a time for generating the divided configuration data is generated. Therefore, the processing time is calculated by summing the reduction time of the process waiting time by the divided configuration time with respect to the entire processing time of the application. If there is no effect of reducing the length, there is no need to perform the division processing.

When the generation of the divided configuration data is completed, the variables indicating the order are set to the next order (step S36). In step S33, the flag Fj is set to Fj = 0.
In this case, the process skips step S34 for calculating the address of the overlapping area and step S35 for generating the divided configuration, and sets the order of the configuration to the next order, and jumps to step S36.

In the same manner, for the last circuit block of the N circuit blocks, the processing of detecting the overlapping area and generating the divided data is performed for all the circuit blocks where the overlap occurs (step S37).

As described above, in the first processing cycle (i = 1), the detection of the overlap of the circuit blocks and the generation of the divided configuration data are performed. Then, the process proceeds to the second processing cycle or later (step S3).
8, step S39).

After the second processing cycle, application processing is executed using the generated divided configuration data (steps S22 and S23). In this case, the overlap determination flag Fj
By using the configuration data obtained by dividing the overlapping configuration data into Cj1 and Cj2, the non-overlapping region Cj1 is configured as shown in FIGS. 5 and 6, and the previous process is completed. After that, the configuration of the overlapping area Cj2 is performed.

[0106]

As described above, according to the present invention, an overlap between a circuit block which is executing a process and a circuit block to be configured next is detected, and a non-overlapping portion is configured first. In addition, by configuring the remaining overlapping part after the processing by the previous circuit block is completed, the waiting time between processes can be eliminated or shortened, so that the overall processing time can be shortened. I can do it.

Further, in order to shorten the configuration time, it is necessary to increase the power consumption by increasing the transfer rate of the configuration data and the regeneration processing which is complicated and requires much labor and time to reduce the configuration data. No configuration change is required, and a configuration in which the entire configuration time is the same can be used, and no system change is required.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an embodiment of a method for reconfiguring a circuit into a programmable logic circuit according to the present invention.

FIG. 2 is a diagram illustrating an example of a hardware configuration of an information processing system according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating an example of a structure of a programmable logic circuit.

FIG. 4 is a diagram illustrating an example of a structure of a programmable logic circuit.

FIG. 5 is a diagram for explaining an arrangement relationship of circuit blocks to be sequentially reconfigured into a programmable logic circuit by the reconfiguration method according to the embodiment;

FIG. 6 is a diagram illustrating a timing chart of an application execution operation using the reconfiguration method according to the embodiment;

FIG. 7 is a part of a flowchart for explaining another embodiment of the method for reconfiguring a circuit into a programmable logic circuit according to the present invention;

FIG. 8 is a diagram showing the remaining part of the flowchart of FIG. 7;

FIG. 9 is a block diagram of a conventional example of an information processing system using a programmable logic circuit.

FIG. 10 is a diagram illustrating parameters of a plurality of circuit blocks to be sequentially reconfigured into a programmable logic circuit.

FIG. 11 is a diagram for explaining an arrangement relationship of circuit blocks to be sequentially reconfigured into a programmable logic circuit by a conventional reconfiguration method.

12 is a diagram showing a timing chart of an execution operation of an application in the case of the example of FIG. 11;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Information processing system 20 Programmable logic circuit unit 22 Programmable logic circuit A, B, C, D Circuit block C1, C2 Divided circuit block

Claims (8)

[Claims] 1. A method for reconfiguring a plurality of circuits in a case where a plurality of circuits are sequentially reconfigured in a programmable logic circuit while processing by the reconfigured circuits is performed sequentially in parallel. For a circuit in which a previous circuit has been reconfigured before and in which at least a part of a region where the circuit is to be reconfigured, and the processing of which is being performed, the former circuit is Data for reconstruction is divided into a part overlapping with the region and a part not overlapping, and the non-overlapping part is reconstructed in parallel with the processing of the preceding circuit, and the processing of the preceding circuit is completed. A method for reconfiguring a circuit into a programmable logic circuit, comprising reconfiguring the overlapping portion later. 2. The method for reconfiguring a circuit into a programmable logic circuit according to claim 1, wherein the area of the previous circuit overlaps with the area before the reconfiguration of the programmable logic circuit and execution of processing are started. A method for reconfiguring a circuit into a programmable logic circuit, wherein a process for dividing data for reconfiguration into a part and a part that does not overlap is performed. 3. The method for reconfiguring a circuit into a programmable logic circuit according to claim 1, wherein the processing by the plurality of circuits is performed a plurality of times. After the execution of the processing is started, during the execution of the processing, the time required for the reconfiguration of each circuit is compared with the processing time of the previous circuit of the circuit. Detecting, based on the detection result, for a circuit that generates an overlap, divides data for reconstruction into a part that overlaps with the area of the previous circuit and a part that does not overlap, When the divided circuit is used again, the non-overlapping part is reconfigured in parallel with the processing of the preceding circuit, and after the processing of the preceding circuit is completed, the overlapping part is reconfigured. Reconstruction method of the circuit to the programmable logic circuit, characterized in that. 4. The division into a part overlapping with the region of the preceding circuit and a part not overlapping with each other is performed by using a minimum unit cell of the programmable logic circuit as a division unit and including a cell part including wiring from the overlap part. The method for reconfiguring a circuit into a programmable logic circuit according to claim 1, wherein: 5. A method for reconfiguring a circuit into a programmable logic circuit according to claim 3, wherein a circuit causing an overlapping area with the preceding circuit is detected, and a part overlapping with the preceding circuit area and a part not overlapping with the preceding circuit area. Is performed in parallel with the execution of the processing by the plurality of circuits in the first cycle of the iterative processing. In the second and subsequent cycles of the iterative processing, the re-use using the divided circuit data is performed. A method for reconfiguring a circuit into a programmable logic circuit, comprising performing a configuration. 6. A series of processes described by a program are executed as an application program, and a part of the application program is processed by a programmable logic circuit whose function can be changed and reconfigured by the program at any time. A part of the application program is divided into a plurality of processing functions, each processing function is made to correspond to a circuit block, and the circuit block is reconfigured while reconfiguring the circuit block into the programmable logic circuit. In an information processing system configured to execute the configuration and the execution of the processing functions in parallel and sequentially, before reconfiguring the plurality of circuit blocks to the programmable logic circuit and starting execution of the processing, For each circuit block, it is necessary to reconfigure the circuit block. Time, and comparing the process time of the previous circuit, which has been reconfigured to the programmable logic circuit before, and the processing is executed, to determine whether the circuit overlaps with the previous circuit. Discriminating and, for a circuit in which an overlap occurs, a unit that divides data for reconfiguration into a part that overlaps with a region of the previous circuit and a part that does not overlap, and In the reconfiguration of the circuit block and the execution of the processing, the non-overlapping part of the divided circuit block is reconfigured in parallel with the processing of the preceding circuit, and after the processing of the preceding circuit is completed, the overlapping occurs. An information processing system for reconstructing a part. 7. A series of processes described by a program are executed as an application program, and a part of the application program is processed by a programmable logic circuit whose function can be changed and reconfigured by the program at any time. A part of the application program is repeatedly processed by a plurality of processing functions, each of the processing functions is associated with a circuit block, and the circuit blocks are reconfigured into the programmable logic circuit. In an information processing system that performs the reconfiguration and the execution of the processing functions in parallel and sequentially, in the first cycle of the repetitive processing, For a circuit block, reconfigure the circuit block The time required for the circuit is compared with the process time of the previous circuit that has been reconfigured before and is executed in the programmable logic circuit, and the processing is executed. And for circuits where overlap occurs,
Means for dividing data for reconstruction into a part overlapping with the area of the previous circuit and a part not overlapping with the area of the previous circuit, and in the second and subsequent cycles of the repetitive processing, the divided circuit block does not overlap An information processing system, wherein a part is reconfigured in parallel with the processing of the preceding circuit, and after the processing of the preceding circuit is completed, the overlapping part is reconfigured. 8. The information processing system according to claim 6, wherein the data dividing process for reconfiguring the circuit block is performed by a computing unit in a system equipped with a programmable logic circuit. Alternatively, the information processing system is performed by arithmetic processing by arithmetic means connected to a network connected to the system.