JP2013250696A - Processor system and processor control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the synchronization of a plurality of processors while more suppressing power consumption without adding any hardware to the inside of the processor.SOLUTION: A pre-processor 14 and a post-processor 15 operate on the basis of a clock to be supplied, and outputs a program counter showing a position where an instruction to be executed is stored. A shared memory 13 stores data to be shared between the pre-processor 14 and the post-processor 15. A register stores control information showing the control conditions of the pre-processor 14 and the post-processor 15. A clock control part supplies the clock to the pre-processor 14 and the post-processor 15 on the basis of the program counter and the control information.

Description

  The present invention relates to a processor system and a processor control device.

  Recent embedded devices often have a hardware configuration including a plurality of processors (CPUs). In such a configuration, when a plurality of processors process a program whose execution order is restricted in parallel, it is necessary for the processors to monitor each other's processing status and synchronize the execution timing of the program.

  In general, the processor is often synchronized by software such as an OS (Operating System). When the processors are synchronized by software, there is a problem that the operating time of the processor becomes longer due to the execution time of the program, and the power consumption increases.

  A method of synchronizing processors using hardware is also known (see, for example, Patent Document 1). The method described in Patent Document 1 synchronizes a plurality of processors by adding a program counter monitoring unit outside the processor and adding an execution unit inside the processor. The method of synchronizing the processor using hardware can reduce power consumption because the execution time of the program is shorter than the method of synchronizing the processor using software.

JP 2009-75948 A

  However, the technique described in Patent Document 1 has a problem in that the cost of design and verification of the processor increases because it is necessary to add hardware (execution unit) inside the processor. Further, when the processor is developed by a third party, there is a possibility that hardware cannot be added inside the processor.

  Further, in the technique described in Patent Document 1, when the synchronization of the processor is necessary, the execution unit added inside the synchronization source processor inquires the program counter monitoring unit added outside the processor. When there is a synchronization inquiry, the program counter monitoring unit determines whether or not to start processing of the synchronization source processor according to the processing status of the synchronization destination processor, and determines the determination result as the synchronization source processor Output for. The synchronization source processor waits for processing start or processing based on the determination result of the program counter monitoring unit. Therefore, the technique described in Patent Document 1 has a problem that it takes time to obtain the synchronization determination result after the synchronization of the processor is necessary, and the processor operates for that time, so that more power is consumed.

  The present invention has been made to solve the above-described problem, and a processor system capable of controlling synchronization of a plurality of processors while further reducing power consumption without adding hardware inside the processor. An object is to provide a processor control device.

  The present invention includes a plurality of processors that operate based on a supplied clock and output a program counter indicating a position where an instruction to be executed is stored; a shared memory that stores data shared between the processors; A processor system comprising: a register that stores control information indicating a control condition of a processor; and a clock control unit that supplies the clock to the processor based on the program counter and the control information. .

  In the processor system of the present invention, the clock control unit supplies the clock to the processors so that a plurality of the processors do not access the same area of the shared memory at the same time.

  In the processor system of the present invention, the control information includes information indicating a timing for supplying the clock to the processor and a timing for stopping the clock supplied to the processor.

  In the processor system of the present invention, the control information includes information for specifying the processor that supplies the clock.

  Further, the present invention supplies a clock to the processor based on a register that stores control information indicating control conditions of a plurality of processors, a program counter that indicates an instruction to be executed by the processor, and the control information. And a clock control unit that controls driving of the processor.

  According to the present invention, the register stores control information indicating a control condition of the processor. The clock controller supplies the clock to the processor based on the program counter and control information. As a result, it is possible to control the synchronization of a plurality of processors while further reducing power consumption without adding hardware inside the processors.

It is the block diagram which showed the structure of the processor system in one Embodiment of this invention. It is the block diagram which showed the structure of the processor control apparatus in this embodiment. It is the schematic which showed the concept of the operation | movement of the synchronous process of the front | former stage processor and a back | latter stage processor by the processor control apparatus in this embodiment. It is a timing chart which showed the timing of the operation | movement of the synchronous process of the front | former stage processor and back | latter stage processor by the processor control apparatus in this embodiment. It is a timing chart which showed the timing of the operation | movement of the synchronous process of the front | former stage processor and back | latter stage processor by the processor control apparatus in this embodiment.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a processor system in the present embodiment. In the illustrated example, the processor system 1 includes a main processor 11, a processor control device 12, a shared memory 13, a front processor 14 (processor), and a rear processor 15 (processor).

  The main processor 11 outputs control information indicating control conditions for the upstream processor 14 and the downstream processor 15 to the processor control device 12. The processor control device 12 controls synchronization between the upstream processor 14 and the downstream processor 15 based on control information input from the main processor 11. The shared memory 13 stores data used by the upstream processor 14 and the downstream processor 15 for processing. The pre-stage processor 14 executes the process of the pre-stage part of the process executed by the processor system 1. The post-stage processor 15 executes the process of the post-stage part of the process executed by the processor system 1 using the result executed by the pre-stage processor 14. Therefore, it is necessary to start the processing of the subsequent processor 15 after the processing of the upstream processor 14 is completed. Further, the pre-stage processor 14 and the post-stage processor 15 output a program counter indicating a position where an instruction to be executed is stored.

  Next, the configuration of the processor control device 12 will be described. FIG. 2 is a block diagram showing a configuration of the processor control device 12 in the present embodiment. In the illustrated example, the processor control device 12 includes a register 121, a front-stage clock control unit 122 (clock control unit), and a rear-stage clock control unit 123 (clock control unit). The register 121 stores control information input from the main processor 11.

  The pre-stage clock control unit 122 controls the operation of the pre-stage processor 14 based on the control information stored in the register 121, the program counter output from the pre-stage processor 14, and the program counter output from the post-stage processor 15. Specifically, the pre-stage clock control unit 122 operates the pre-stage processor 14 by supplying a clock to the pre-stage processor 14, and stops the operation of the pre-stage processor 14 by stopping the clock supplied to the pre-stage processor 14.

  The post-stage clock control unit 123 controls the operation of the post-stage processor 15 based on the control information stored in the register 121, the program counter output from the pre-stage processor 14, and the program counter output from the post-stage processor 15. Specifically, the post-stage clock control unit 123 operates the post-stage processor 15 by supplying a clock to the post-stage processor 15, and stops the operation of the post-stage processor 15 by stopping the clock supplied to the post-stage processor 15.

  Next, synchronization processing between the upstream processor 14 and the downstream processor 15 by the processor control device 12 will be described. FIG. 3 is a schematic diagram showing the concept of the operation of the synchronization processing between the upstream processor 14 and the downstream processor 15 by the processor control device 12 in the present embodiment.

  Hereinafter, an example in which the processor system 1 alternately executes the process [0] and the process [1] twice will be described. In order to execute the process [0], the processor control device 12 causes the upstream processor 14 to execute the upstream process [0], and then causes the downstream processor 15 to execute the downstream process [0]. Further, in order to execute the process [1], the processor control device 12 causes the pre-stage processor 14 to execute the pre-stage process [1], and then causes the post-stage processor 15 to execute the post-stage process [1].

  The program counters output when the pre-stage processor 14 performs the pre-stage process [0] are the pre-stage PCs [0] [0] to [0] [1]. The program counters output when the pre-stage processor 14 performs the pre-stage process [1] are the pre-stage PCs [1] [0] to [1] [1]. The program counters output when the post-stage processor 15 performs the post-stage process [0] are the post-stage PCs [0] [0] to [0] [1]. The program counters output when the post-stage processor 15 performs the post-stage process [1] are the post-stage PCs [1] [0] to [1] [1].

In this case, the conditions indicated by the processor control information stored in the register 121 are the following (1) to (8).
(1) When the post-stage processor 15 is not accessing the memory area [0] of the shared memory 13, the pre-stage processor 14 is caused to execute a process for accessing the memory area [0] of the shared memory 13 (pre-stage process [0]). .
(2) When the latter processor 15 is accessing the memory area [0] of the shared memory 13, the former processor 14 executes a process for accessing the memory area [0] of the shared memory 13 (previous process [0]). The operation of the preceding processor 14 is stopped immediately before.
(3) When the upstream processor 14 is not accessing the memory area [0] of the shared memory 13, the downstream processor 15 is caused to execute the process of accessing the memory area [0] of the shared memory 13 (the downstream process [0]). .
(4) When the upstream processor 14 is accessing the memory area [0] of the shared memory 13, the downstream processor 15 executes a process of accessing the memory area [0] of the shared memory 13 (backward process [0]). Immediately before, the operation of the subsequent processor 15 is stopped.

(5) When the post-stage processor 15 is not accessing the memory area [1] of the shared memory 13, the pre-stage processor 14 is caused to execute a process for accessing the memory area [1] of the shared memory 13 (pre-stage process [1]). .
(6) When the post-stage processor 15 is accessing the memory area [1] of the shared memory 13, the pre-stage processor 14 executes a process for accessing the memory area [1] of the shared memory 13 (pre-stage process [1]). The operation of the preceding processor 14 is stopped immediately before.
(7) When the upstream processor 14 is not accessing the memory area [1] of the shared memory 13, the downstream processor 15 is caused to execute the process of accessing the memory area [1] of the shared memory 13 (the downstream process [1]). .
(8) When the upstream processor 14 is accessing the memory area [1] of the shared memory 13, the downstream processor 15 executes a process of accessing the memory area [1] of the shared memory 13 (backward process [1]). Immediately before, the operation of the subsequent processor 15 is stopped.

  Accordingly, the pre-stage clock control unit 122 has the pre-stage PC [0] [0] to [0] [1] (pre-stage process [0]) as the program counter output from the pre-stage processor 14 and the program output from the post-stage processor 15. When the counter is the post-stage PC [1] [0] to [1] [1] (post-stage process [1]), the pre-stage processor 14 is clocked to execute the pre-stage process [0]. Supply. Further, the pre-stage clock control unit 122 has the program counter output from the pre-stage processor 14 as the pre-stage PC [0] [0] to [0] [1] (pre-stage process [0]), and the program output from the post-stage processor 15. When the counter is the post-stage PC [0] [0] to [0] [1] (the post-stage process [0]), the pre-stage processor 14 is caused to wait for the pre-stage processor 14 to execute the pre-stage process [0]. Stop the clock supplied to.

  Further, the pre-stage clock control unit 122 has the program counter output from the pre-stage processor 14 as the pre-stage PC [1] [0] to [1] [1] (pre-stage process [1]), and the program output from the post-stage processor 15. When the counter is the post-stage PC [0] [0] to [0] [1] (the post-stage process [0]), the pre-stage processor 14 is clocked to execute the pre-stage process [1]. Supply. Further, the pre-stage clock control unit 122 has the program counter output from the pre-stage processor 14 as the pre-stage PC [1] [0] to [1] [1] (pre-stage process [1]), and the program output from the post-stage processor 15. When the counter is the post-stage PC [1] [0] to [1] [1] (the post-stage process [1]), the pre-stage processor 14 is caused to wait for the pre-stage processor 14 to execute the pre-stage process [1]. Stop the clock supplied to.

  Further, in the post-stage clock control unit 123, the program counter output from the post-stage processor 15 is the post-stage PC [0] [0] to [0] [1] (post-stage process [0]), and the program output from the pre-stage processor 14 When the counter is the preceding stage PC [1] [0] to [1] [1] (previous stage process [1]), in order to cause the latter stage processor 15 to execute the latter stage process [0], the latter stage processor 15 is clocked. Supply. Further, in the post-stage clock control unit 123, the program counter output from the post-stage processor 15 is the post-stage PC [0] [0] to [0] [1] (post-stage process [0]), and the program output from the pre-stage processor 14 When the counter is the preceding stage PC [0] [0] to [0] [1] (the preceding stage process [0]), the latter stage processor 15 is caused to wait for the latter stage processor 15 to execute the latter stage process [0]. Stop the clock supplied to.

  Further, the post-stage clock control unit 123 has the program counter output from the post-stage processor 15 as the post-stage PC [1] [0] to [1] [1] (post-stage process [1]), and the program output from the pre-stage processor 14. When the counter is the preceding stage PC [0] [0] to [0] [1] (previous stage process [0]), in order to cause the latter stage processor 15 to execute the latter stage process [1], the latter stage processor 15 is clocked. Supply. Further, the post-stage clock control unit 123 has the program counter output from the post-stage processor 15 as the post-stage PC [1] [0] to [1] [1] (post-stage process [1]), and the program output from the pre-stage processor 14. When the counter is the preceding stage PC [1] [0] to [1] [1] (previous stage process [1]), the latter stage processor 15 is caused to wait for the latter stage processor 15 to execute the latter stage process [1]. Stop the clock supplied to.

  When processing [0] is executed for the first time, such as when the processor system 1 is started up, the program counter output by the preceding processor 14 is the preceding PC [0] [0], and the program counter output by the succeeding processor 15 Is a post-stage PC [0] [0]. In this case, none of the conditions (1) to (8) indicated by the control information of the processor stored in the register 121 applies. Therefore, when the process [0] is executed for the first time, exceptionally, the pre-stage clock control unit 122 exceptionally determines that the pre-stage processor 14 completes the pre-stage process [0] (the program counter output by the pre-stage processor 14 is the pre-stage PC. [1] until [0]) The clock is supplied to the pre-stage processor 14.

  FIG. 4 is a timing chart showing the operation timing of the synchronization processing between the upstream processor 14 and the downstream processor 15 by the processor control device 12 in this embodiment. In the example shown in the figure, an example in which the operation time of the former processor 14 is longer than the operation time of the latter processor 15 is shown.

  When the process [0] is executed for the first time, the processor control device 12 supplies a clock to the upstream processor 14. Thereby, the pre-stage processor 14 executes the pre-stage process [0] (time a).

  Subsequently, the processor control device 12 supplies a clock to the subsequent processor 15 because the upstream processor 14 finishes the upstream processing [0] and the downstream processor 15 waits for execution of the downstream processing [0]. Thereby, the post-stage processor 15 executes the post-stage process [0]. Further, the processor control device 12 supplies a clock to the upstream processor 14 because the downstream processor 15 executes the downstream processing [0] and the upstream processor 14 waits for execution of the upstream processing [1]. Thereby, the pre-stage processor 14 executes the pre-stage process [1] (time b).

  Subsequently, the processor control device 12 uses the clock supplied to the post-stage processor 15 because the pre-stage processor 14 executes the pre-stage process [1] even if the post-stage processor 15 ends the post-stage process [0]. Stop. As a result, the post-stage processor 15 waits for the execution of the post-stage process [1]. The processor control device 12 supplies a clock to the upstream processor 14 because the upstream processor 14 has not completed the upstream processing [1]. Thereby, the pre-stage processor 14 continues to execute the pre-stage process [1] (time c).

  Subsequently, the processor controller 12 supplies the clock to the post-stage processor 15 because the pre-stage processor 14 finishes the pre-stage process [1] and the post-stage processor 15 waits for the execution of the post-stage process [1]. As a result, the post-stage processor 15 executes the post-stage process [1]. Further, the processor control device 12 supplies a clock to the upstream processor 14 because the downstream processor 15 executes the downstream processing [1] and the upstream processor 14 waits for execution of the upstream processing [0]. Thereby, the pre-stage processor 14 executes the pre-stage process [0] (time d).

  Subsequently, the processor control device 12 uses the clock supplied to the post-stage processor 15 because the pre-stage processor 14 is executing the pre-stage process [0] even if the post-stage processor 15 ends the post-stage process [1]. Stop. As a result, the post-stage processor 15 waits for execution of the post-stage process [0]. The processor control device 12 supplies a clock to the upstream processor 14 because the upstream processor 14 has not completed the upstream processing [0]. Thereby, the pre-stage processor 14 continues to execute the pre-stage process [0] (time e). The times f to g are the same as the times b to c.

  Subsequently, the processor controller 12 supplies the clock to the post-stage processor 15 because the pre-stage processor 14 finishes the pre-stage process [1] and the post-stage processor 15 waits for the execution of the post-stage process [1]. As a result, the post-stage processor 15 executes the post-stage process [1]. Note that the processor control device 12 does not supply a clock to the upstream processor 14 because the upstream processing [0] and the upstream processing [1] are executed twice. As a result, the upstream processor 14 stops the processing. Further, when the post-stage processor 15 finishes the post-stage process [1], the post-stage process [0] and the post-stage process [1] are executed twice, so the processor control device 12 uses the clock supplied to the post-stage processor 15. Stop. As a result, the downstream processor 15 stops the processing (time h).

  FIG. 5 is a timing chart showing the operation timing of the synchronization processing between the upstream processor 14 and the downstream processor 15 by the processor control device 12 in the present embodiment. In the example shown in the figure, an example in which the operation time of the former processor 14 is shorter than the operation time of the latter processor 15 is shown.

  When the process [0] is executed for the first time, the processor control device 12 supplies a clock to the upstream processor 14. Thereby, the pre-stage processor 14 executes the pre-stage process [0] (time A).

  Subsequently, the processor control device 12 supplies a clock to the subsequent processor 15 because the upstream processor 14 finishes the upstream processing [0] and the downstream processor 15 waits for execution of the downstream processing [0]. Thereby, the post-stage processor 15 executes the post-stage process [0]. Further, the processor control device 12 supplies a clock to the upstream processor 14 because the downstream processor 15 executes the downstream processing [0] and the upstream processor 14 waits for execution of the upstream processing [1]. Thereby, the pre-stage processor 14 executes the pre-stage process [1] (time B).

  Subsequently, the processor control device 12 uses the clock supplied to the pre-stage processor 14 because the post-stage processor 15 executes the post-stage process [0] even if the pre-stage processor 14 ends the pre-stage process [1]. Stop. Thereby, the pre-stage processor 14 waits for the execution of the pre-stage process [0]. The processor control device 12 supplies a clock to the subsequent processor 15 because the subsequent processor 15 has not completed the subsequent process [0]. Thereby, the post-stage processor 15 continues to execute the post-stage process [0] (time C).

  Subsequently, the processor controller 12 supplies the clock to the upstream processor 14 because the downstream processor 15 finishes the downstream processing [0] and the upstream processor 14 waits for execution of the upstream processing [0]. Thereby, the pre-stage processor 14 executes the pre-stage process [0]. The processor control device 12 supplies a clock to the subsequent processor 15 because the upstream processor 14 executes the upstream processing [0] and the downstream processor 15 waits for the downstream processing [1]. Thereby, the post-stage processor 15 executes the post-stage process [1] (time D).

  Subsequently, the processor control device 12 uses the clock supplied to the pre-stage processor 14 because the post-stage processor 15 executes the post-stage process [1] even if the pre-stage processor 14 ends the pre-stage process [0]. Stop. Thereby, the pre-stage processor 14 waits for the execution of the pre-stage process [1]. The processor control device 12 supplies a clock to the post-stage processor 15 because the post-stage processor 15 has not completed the post-stage process [1]. Thereby, the post-stage processor 15 continues to execute the post-stage process [1] (time E). Time F is the same as time B.

  Subsequently, the processor control device 12 stops supplying the clock to the upstream processor 14 because the upstream processor 14 finishes the upstream processing [1] and executes the upstream processing [0] and the upstream processing [1] twice. To do. As a result, the upstream processor 14 stops the processing. The processor control device 12 supplies a clock to the post-stage processor 15 because the post-stage processor 15 has not completed the post-stage process [0]. Thereby, the post-stage processor 15 continues to execute the post-stage process [0] (time G).

  Subsequently, the processor control device 12 supplies a clock to the subsequent processor 15 because the subsequent processor 15 finishes the subsequent process [0] and the previous processor 14 waits for the execution of the previous process [0]. As a result, the post-stage processor 15 executes the post-stage process [1]. Further, when the post-stage processor 15 finishes the post-stage process [1], the post-stage process [0] and the post-stage process [1] are executed twice, so the processor control device 12 uses the clock supplied to the post-stage processor 15. Stop. As a result, the downstream processor 15 stops the processing (time H).

  As described above, the pre-stage clock control unit 122 and the post-stage clock control unit 123 are based on the program counter output from the pre-stage processor 14, the program counter output from the post-stage processor 15, and the control information stored in the register 121. By controlling the clock supplied to the upstream processor 14 and the downstream processor 15, the synchronization between the upstream processor 14 and the downstream processor 15 can be controlled.

  Therefore, the processor system 1 and the processor control device 12 can control the synchronization between the pre-stage processor 14 and the post-stage processor 15 while further reducing the power consumption without adding hardware inside the pre-stage processor 14 and the post-stage processor 15. Can do.

  Although one embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes design and the like within a scope not departing from the gist of the present invention. For example, in the above-described embodiment, the processor control device 12 controls the synchronization of the two processors, the front processor 14 and the rear processor 15, but is not limited to this, and controls the synchronization of three or more processors. You may do it. Even in the case of controlling the synchronization of three or more processors, the processor control device 12 controls the control information stored in the program counter and the register 121 output by each processor, as in the process of controlling the synchronization of the two processors. To control the synchronization of three or more processors.

  DESCRIPTION OF SYMBOLS 1 ... Processor system, 11 ... Main processor, 12 ... Processor control apparatus, 13 ... Shared memory, 14 ... Pre-stage processor, 15 ... Subsequent processor, 121 ... Register, 122 ... Previous stage clock controller, 123 ... Back stage clock controller

Claims (5)

A plurality of processors which operate based on a supplied clock and output a program counter indicating a position where an instruction to be executed is stored;
A shared memory for storing data shared between the processors;
A register for storing control information indicating a control condition of the processor;
A clock control unit for supplying the clock to the processor based on the program counter and the control information;
A processor system comprising: The processor system according to claim 1, wherein the clock control unit supplies the clock to the processors so that the plurality of processors do not access the same area of the shared memory simultaneously. The said control information contains the information which shows the timing which supplies the said clock to the said processor, and the timing which stops the said clock supplied to the said processor. The Claim 1 or Claim 2 characterized by the above-mentioned. Processor system. The processor system according to claim 3, wherein the control information includes information for specifying the processor that supplies the clock. A register for storing control information indicating control conditions of a plurality of processors;
A clock control unit that supplies a clock to the processor based on a program counter indicating the instruction to be executed by the processor and the control information, and controls driving of the processor;
A processor control device comprising:

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