JP2009075948A - Multicore processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multicore processor capable of synchizing programs among processor cores by a simple configuration without increasing size of the program executed in each of processor cores. <P>SOLUTION: This multicore processor is provided with the processor cores 10, 20, 30, 40, a program counter 11 holding an address value of the program performed by the processor core corresponding to itself, and program counter monitoring parts 13, 23, 33, 43 for controlling possibility or impossibility of performing the program at synchronizing destination by the processor core corresponding to oneself in accordance with results of comparison of a value of the program counter 11 corresponding to the processor core being the synchronizing mate designated by the processor core corresponding to oneself with a final program address value of the program at synchronizing origin performed by the processor core being the synchronizing partner prior to performing the program at the synchronizing destination. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multi-core processor that performs information processing with a plurality of processor cores.

  In a multi-core processor, each processor core can execute one program while performing processing individually. In this case, the program needs to be divided into a plurality of parts and assigned to each processor core. As a program dividing method, in addition to a method of automatically dividing one program by an automatic parallelizing compiler, a method of dividing a program into a plurality of programs in consideration of cooperation between processes executed by each processor core, etc. There is. However, in any program created by any of the methods, it is necessary to synchronize data transmission and processing timing between the processor cores in order to realize the movement intended by the program author.

  As a technique for synchronizing processor cores, there is a synchronization method called barrier synchronization disclosed in Patent Document 1 and Patent Document 2, for example. In this synchronization method, each processor core is controlled to proceed to the next processing stage when it is guaranteed that all the processor cores have reached a certain processing stage (barrier).

  Patent Document 3 describes a synchronization method between processor cores in which a correspondence relationship between a synchronization source processor core and a synchronization destination processor core is set in advance. This synchronization method does not guarantee the execution status between processor cores as in barrier synchronization. Specifically, the synchronization source processor core increments or decrements the value of the shared area such as the shared register, and the synchronization destination processor core compares the value stored in the local area with the value of the shared area. The operation is synchronized with the operation of the synchronization source processor core.

  In recent years, there is a tendency to increase the number of processor cores of a multi-core processor from the viewpoint of speeding up information processing. In order to efficiently execute processing with such a large number of processor cores installed, it is necessary to average the processing amount of each processor core, and there is a tendency to further reduce the size of a program executed on each processor core. It is getting stronger. For this reason, the number of processes that should be coordinated between processor cores increases, and the number of places that require synchronous processing is increasing.

Japanese Patent Laid-Open No. 7-234841 JP 2000-215182 A Japanese Patent Laid-Open No. 9-305546

  A conventional multi-core processor must add processing for synchronization to a program executed in all processor cores related to synchronization. That is, it is necessary to describe processing for synchronization in both the program executed in the synchronization source processor core and the program executed in the synchronization destination processor core. For this reason, the size of the program executed by each processor core increases, and there is a problem that the execution time increases.

  The present invention has been made in order to solve the above-described problems, and can achieve synchronization between processor cores with a simple configuration without increasing the size of a program executed in each processor core. The purpose is to obtain a processor.

  A multi-core processor according to the present invention includes a plurality of processor cores, a program counter that is provided corresponding to each of the plurality of processor cores and that holds an address value of a program executed by the processor core corresponding to the processor core, Provided in correspondence with each of the processor cores, the value of the program counter corresponding to the synchronization partner processor core designated from the processor core corresponding to itself and the synchronization partner processor core prior to execution of the synchronization destination program And a program counter monitoring unit that controls whether or not the synchronization target program can be executed by the processor core corresponding to the address value of the synchronization source program to be executed.

  According to the present invention, a plurality of processor cores, a program counter provided corresponding to each of the plurality of processor cores and holding an address value of a program executed by the processor core corresponding to itself, and the plurality of processor cores The program counter value corresponding to the synchronization target processor core specified by the processor core corresponding to the program and the synchronization target processor core is executed prior to the execution of the synchronization destination program. And a program counter monitoring unit for controlling whether or not the synchronization target program can be executed by the processor core corresponding to the synchronization source program according to the comparison result with the address value of the synchronization source program. Without adding special processing for synchronization to the processor core, There is an effect that can be synchronized between the processor core in accordance with the execution status of grams.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a multi-core processor according to Embodiment 1 of the present invention. In FIG. 1, the multi-core processor 1 according to the first embodiment includes processor cores 10, 20, 30, and 40 and program counter monitoring units 13, 23, 33, and 43. The processor cores 10, 20, 30, and 40 each include a program counter 11 and an execution unit 12. The program counter 11 holds an address of a program executed by the execution unit 12. In the first embodiment, the execution unit 12 executes the program in ascending order of addresses in principle.

  The execution unit 12 is a component that executes a program assigned to a processor core including the execution unit 12, and the execution stop and execution start of the program are controlled according to the stop request and the release request notified from the program counter monitoring unit. In addition, the execution unit 12 is the final program address value of the synchronization source program that is pre-processed with the program executed by the execution unit 12 as a synchronization destination in the execution unit 12 of another processor core that operates in synchronization with the processor core including the execution unit 12 Immediately before executing the synchronization destination program, the program counter monitoring unit is notified of the identification number of the other processor core and the final program address value of the synchronization source program.

  The program counter monitoring units 13, 23, 33, and 43 are provided corresponding to the processor cores 10, 20, 30, and 40, respectively, and are connected to the execution unit 12 mounted on the processor core corresponding to the processor cores so that data can be transmitted and received. Is done. Further, the program counter monitoring units 13, 23, 33, and 43 are connected to the program counter 11 of the processor core that is not connected to the execution unit 12 and can read the values.

  As described above, the program counter monitoring units 13, 23, 33, and 43 are provided as peripheral circuits of the respective processor cores 10, 20, 30, and 40, and are mounted on processor cores other than the processor core corresponding to the program core monitoring unit 13, 23, 33, and 43. The value of the program counter 11 is monitored. Further, the program counter monitoring units 13, 23, 33, and 43 notify the execution unit 12 of the corresponding processor core of the program execution stop request and the release request according to the monitoring result of the program counter 11.

  For example, the program counter monitoring unit 13 acquires information necessary for monitoring the address information and the like described above from the execution unit 12 of the processor core 10 and monitors the values of the program counter 11 of the processor cores 20, 30, and 40. A request to stop program execution and a request to cancel the program execution are notified to the execution unit 12 of the processor core 10 according to the monitoring result.

  FIG. 2 is a diagram for explaining a program executed by the processor core in FIG. 1 and a dependency relationship between the programs. In FIG. 2, programs 210, 220, 230, and 240 are programs obtained by dividing one program executed by the multi-core processor 1, and are executed by the processor cores 10, 20, 30, and 40, respectively. The program 210 executed by the execution unit 12 of the processor core 10 includes a partial program 211. The program 220 executed by the execution unit 12 of the processor core 20 includes partial programs 221, 222, and 223.

  In FIG. 2, the partial programs 221, 222, and 223 are stored in the memory so that the addresses are in ascending order in the order of the partial program 223, the partial program 221, and the partial program 222. The execution unit 12 of the processor core 20 reads the partial programs from the memory in ascending order and executes the partial programs, thereby executing the partial program 223, the partial program 221, and the partial program 222 in this order, as indicated by arrows in FIG. The program 220 is executed.

  Further, a dependency relationship 250 is set between the partial program 211 executed by the execution unit 12 of the processor core 10 and the partial program 221 executed by the execution unit 12 of the processor core 20. This dependency relationship 250 is that the partial program 211 is executed after the execution of the partial program 221, that is, the partial program 211 is executed by the processor core 10 after the preceding processing of the partial program 221 by the synchronization partner processor core 20 is completed. It shows that there is a dependency of execution order. The information about the dependency relationship 250 includes the identification number of the processor core 20 that executes the synchronization source partial program 221 and the final program address value of the partial program 221, and the information of the processor core 10 that executes the synchronization destination partial program 211. It is held in the execution unit 12.

  FIG. 3 is a diagram for explaining a program executed by the processor core in FIG. 1, a dependency relationship between programs, and a branch process. In FIG. 3, programs 310 and 320 are programs obtained by dividing one program executed by the multi-core processor 1, and are executed by the processor cores 10 and 20, respectively. The program 310 executed by the execution unit 12 of the processor core 10 includes partial programs 311, 312, 313, and 314. The program 320 executed by the execution unit 12 of the processor core 20 includes partial programs 321, 322, and 323.

  As in the case of FIG. 2, the partial programs 311, 312, 313, and 314 are stored in the memory so that the addresses are in ascending order in the order of the partial program 311, the partial program 312, the partial program 313, and the partial program 314. The execution unit 12 of the processor core 10 reads the partial programs from the memory in ascending order and executes the partial programs, thereby executing the partial program 311, the partial program 312, the partial program 313, the partial program as indicated by arrows in FIG. The program 310 is executed in the order of 314.

  The partial program 314 includes a branch instruction at the final program address, and branches to the execution of the partial program 311 when the execution of the partial program 314 is completed. As a result, the value of the program counter 11 of the processor core 10 becomes the start program address value of the smallest partial program 311 from the final program address value of the largest partial program 314.

  The partial programs 321, 322, and 323 are also stored in the memory so that the addresses are in ascending order in the order of the partial program 321, the partial program 322, and the partial program 323. The execution unit 12 of the processor core 20 reads the partial programs from the memory in ascending order and executes the partial programs, so that the partial program 321, the partial program 322, and the partial program 323 are sequentially displayed as indicated by arrows in FIG. The program 320 is executed.

  Similar to the partial program 314, the partial program 323 also includes a branch instruction in the final program address, and branches to the execution of the partial program 321 when the execution of the partial program 323 is completed. In this case, the value of the program counter 11 of the processor core 20 changes from the final program address value of the largest partial program 323 to the start program address value of the smallest partial program 321.

  The partial programs 312 and 314 executed by the execution unit 12 of the processor core 10 have dependency relationships 300 and 302 respectively set between the partial programs 321 and 322 executed by the execution unit 12 of the processor core 20. In addition, a dependency relationship 301 is set between the partial program 323 executed by the execution unit 12 of the processor core 20 and the partial program 312 executed by the execution unit 12 of the processor core 10.

  The dependency relationships 300 and 302 indicate that the partial programs 312 and 314 are executed after the execution of the partial programs 321 and 322 is completed. The information on the dependency relationships 300 and 302 includes the identification number of the processor core 20 that executes the synchronization source partial programs 321 and 322 and the final program address value of the partial programs 321 and 322. It is held in the execution unit 12 of the processor core 10 to be executed.

  Further, the dependency 301 indicates that the partial program 323 is executed after the execution of the partial program 312, that is, the execution order of executing the partial program 323 in the processor core 20 after the preceding processing of the partial program 312 by the processor core 10 is completed. Indicates that there is a dependency. The information related to the dependency relationship 301 includes the identification number of the processor core 10 that executes the synchronization source partial program 312 and the final program address value of the partial program 312, and the information of the processor core 20 that executes the synchronization destination partial program 323. It is held in the execution unit 12.

Next, the operation will be described.
The operation when the program is executed in ascending order of addresses will be described with reference to FIGS.
The execution units 12 of the processor cores 10, 20, 30, and 40 execute the programs 210, 220, 230, and 240 assigned to them. Here, the execution unit 12 of each processor core 10, 20, 30, 40 reads each program from the memory in ascending order and executes it.

  As shown in FIG. 2, a dependency relationship 250 is set in the partial program 221 with the partial program 211 executed by the processor core 10. The execution unit 12 of the processor core 10 uses the identification number of the processor core 20 and the final program address value of the synchronization source partial program 221 as information about the dependency relationship 250 immediately before the execution of the partial program 211 that is the synchronization destination in the dependency relationship 250. The program counter monitoring unit 13 is notified.

  The program counter monitoring unit 13 refers to the value of the program counter 11 of the processor core 20 specified by the identification number included in the information related to the dependency relationship 250, and the final program of the partial program 221 included in the information related to this value and the dependency relationship 250 Compare the address value. Here, when the value of the program counter 11 of the processor core 20 is smaller than the final program address value of the partial program 221 specified by the information on the dependency relationship 250, the program counter monitoring unit 13 causes the execution unit 12 of the processor core 20 to It is determined that the execution of the partial program 221 has not ended, and a stop request is notified to the execution unit 12 of the processor core 10.

  When the execution unit 12 of the processor core 10 receives the stop request, the execution unit 12 temporarily stops the execution of the program 210. Thereafter, the program counter monitoring unit 13 sequentially refers to the value of the program counter 11 of the processor core 20 and continues the above comparison process. The program counter monitoring unit 13 continues to output a stop request to the execution unit 12 of the processor core 10 until it is determined from the comparison result that the execution of the partial program 221 has ended. As a result, the execution unit 12 of the processor core 10 enters the execution standby state of the partial program 211 until the execution of the partial program 221 ends.

  In the comparison process, when the value of the program counter 11 of the processor core 20 becomes larger than the final program address value of the partial program 221 specified by the information related to the dependency relationship 250, the program counter monitoring unit 13 executes the execution unit of the processor core 20. 12 determines that the execution of the partial program 221 has been completed, and notifies the execution unit 12 of the processor core 10 of the stop request cancellation request. When the execution unit 12 of the processor core 10 receives the release request, the execution of the program 210 is resumed and the execution of the partial program 211 is started. In this way, the dependency relationship 250 regarding the processing order between the partial program 221 executed by the execution unit 12 of the processor core 20 and the partial program 211 executed by the execution unit 12 of the processor core 10 can be satisfied.

Next, the operation will be described using the example shown in FIG.
In FIG. 3, the execution unit 12 of the processor core 10 that is the synchronization destination in the dependency relationship 300 immediately before the execution of the partial program 312 performs the identification number of the processor core 20 and the synchronization source partial program in the same manner as in FIG. The program counter monitoring unit 13 is notified of the last program address value of 321 as information related to the dependency relationship 300.

  The program counter monitoring unit 13 refers to the value of the program counter 11 of the processor core 20 specified by using the identification number included in the information related to the dependency relationship 300, and the value of the partial program 321 included in the information related to this value and the dependency relationship 300. Compare the final program address value. Here, when the value of the program counter 11 of the processor core 20 is smaller than the final program address value of the partial program 321 specified by the information regarding the dependency relationship 300, the program counter monitoring unit 13 causes the execution unit 12 of the processor core 20 to It is determined that the execution of the partial program 321 has not ended, and a stop request is notified to the execution unit 12 of the processor core 10.

  When the execution unit 12 of the processor core 10 receives the stop request, the execution unit 12 temporarily stops the execution of the program 310. As a result, the execution unit 12 of the processor core 10 enters an execution standby state of the partial program 312 until the execution of the partial program 321 ends. Thereafter, the program counter monitoring unit 13 sequentially refers to the value of the program counter 11 of the processor core 20 and continues the above-described comparison processing.

  In the comparison process, when the value of the program counter 11 of the processor core 20 becomes larger than the final program address value of the partial program 321 specified by the information regarding the dependency relationship 300, the program counter monitoring unit 13 executes the execution unit of the processor core 20. 12 determines that the execution of the partial program 321 has ended, and notifies the execution unit 12 of the processor core 10 of the cancellation request cancellation request. Upon receiving the release request, the execution unit 12 of the processor core 10 resumes the execution of the program 310 and starts executing the partial program 312.

  The execution unit 12 of the processor core 20 does not perform processing for synchronizing with the execution unit 12 of the processor core 10 when the partial program 321 serving as the synchronization source ends or when the partial program 322 starts.

  Similarly to the case of FIG. 2, the execution unit 12 of the processor core 20 sets the dependency number on the identification number of the processor core 10 and the final program address value of the synchronization source partial program 312 immediately before the execution of the partial program 323. This is notified to the program counter monitoring unit 23 as information about 301.

  The program counter monitoring unit 23 refers to the value of the program counter 11 of the processor core 10 specified by the identification number included in the information related to the dependency relationship 301, and the final program of the partial program 312 included in the information related to this value and the dependency relationship 301. Compare the address value. Here, when the value of the program counter 11 of the processor core 10 is smaller than the final program address value of the partial program 312 specified by the information related to the dependency relationship 301, the program counter monitoring unit 23 causes the execution unit 12 of the processor core 10 to execute. It is determined that the execution of the partial program 312 has not ended, and a stop request is notified to the execution unit 12 of the processor core 20.

  When the execution unit 12 of the processor core 20 receives the stop request, the execution unit 12 temporarily stops the execution of the program 320. As a result, the execution unit 12 of the processor core 20 enters the execution standby state of the partial program 323 until the execution of the partial program 312 is completed. Thereafter, the program counter monitoring unit 23 sequentially refers to the value of the program counter 11 of the processor core 10 and continues the above comparison process.

  In the comparison process, when the value of the program counter 11 of the processor core 10 becomes larger than the final program address value of the partial program 312 specified by the information related to the dependency relationship 301, the program counter monitoring unit 23 executes the execution unit of the processor core 10. 12 determines that the execution of the partial program 312 has been completed, and notifies the execution unit 12 of the processor core 20 of the cancellation request cancellation request. When the execution unit 12 of the processor core 20 receives the release request, the execution of the program 320 is resumed and the execution of the partial program 323 is started.

  The execution unit 12 of the processor core 10 does not perform processing for synchronizing with the execution unit 12 of the processor core 20 when the partial program 312 serving as the synchronization source ends or when the partial program 313 starts.

Next, the operation in the loop processing by the branch instruction will be described.
The program counter monitoring unit 13 compares the final program address value (branch instruction address value) of the partial program 323 notified from the execution unit 12 of the processor core 10 with the value of the program counter 11 of the processor core 20 to perform branch processing. Refer to whether or not On the other hand, the program counter monitoring unit 23 compares the final program address value (the branch instruction address value) of the partial program 314 notified from the execution unit 12 of the processor core 20 with the value of the program counter 11 of the processor core 10. Refers to whether or not branch processing has been reached.

Here, the execution units 12 of the processor cores 10 and 20 that execute the programs having the dependency relationship operate as follows, for example. As a result, the branch process is executed after confirming that each other has reached the branch process (the stage in which the final program addresses of the partial programs 314 and 323 are executed).
When the execution unit 12 of the processor core 10 proceeds to the value immediately before the final program address of the partial program 314 and reaches the stage of executing the branch processing, the execution of the branch instruction in the partial program 314 is temporarily stopped. Further, when the execution unit 12 of the processor core 20 proceeds to the value immediately before the final program address of the partial program 323 and reaches the stage of executing the branch processing, the execution of the branch instruction in the partial program 323 is temporarily stopped.

  At this time, when the value of the program counter 11 of the processor core 20 becomes the value immediately before the final program address of the partial program 323, the program counter monitoring unit 13 notifies the execution unit 12 of the processor core 10 of the execution stop cancellation request. When receiving the release request, the execution unit 12 of the processor core 10 branches to the partial program 311 and resumes processing. As described above, the execution unit 12 of the processor core 10 starts the processing of the partial program 311 after confirming that the execution unit 12 of the processor core 20 that executes the program having the dependency relationship has reached the branching process.

  On the other hand, when the value of the program counter 11 of the processor core 10 becomes a value immediately before the final program address of the partial program 314, the program counter monitoring unit 23 notifies the execution unit 12 of the processor core 20 of a request for canceling execution stop. Upon receiving the release request, the execution unit 12 of the processor core 20 branches to the partial program 323 and resumes processing. As described above, the execution unit 12 of the processor core 20 also restarts the processing of the partial program 321 after confirming that the execution unit 12 of the processor core 10 that executes the program having the dependency relationship has reached the branching process.

  As described above, according to the first embodiment, the processor cores 10, 20, 30, 40 and the processor cores 10, 20, 30, 40 are provided corresponding to the processor cores 10, 20, 30, 40. The program counter 11 that holds the address value of the program to be executed and the processor cores 10, 20, 30, and 40 are provided in correspondence with the processor core of the synchronization partner designated by the processor core corresponding to itself. Depending on the comparison result between the value of the program counter 11 to be executed and the final program address value of the synchronization source program executed by the synchronization partner processor core prior to the execution of the synchronization destination program, Program counter monitoring units 13, 23, 33, 4 that control whether or not to execute the synchronization destination program Therefore, the program counter monitoring units 13, 23, 33, and 43 can wait for the execution of the synchronization destination program according to the execution status of the synchronization source program, and execute the synchronization source program. Synchronization between processor cores can be achieved without adding special processing for synchronization to the cores.

  In the first embodiment, the case where the number of processor cores is four is shown as the circuit configuration, and the processing between the two processor cores has been described. However, the number of cores other than four may be configured. It is also effective when processing is performed between three or more processor cores.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing the configuration of the multi-core processor according to the second embodiment of the present invention, and particularly shows the detailed configuration of the program counter monitoring unit. In addition, the same code | symbol is attached | subjected to the thing corresponded to the component shown in FIG. In FIG. 4, the program counter monitoring unit 13 according to the second embodiment includes a program register 400 and a monitoring execution unit 404. The program register 400 is a register in which monitoring information of the program counter 11 of the processor core that executes a program synchronously with the processor core 10 is set. The processor core number register 401, the program address register 402, A valid flag register 403 is provided.

  In the processor core number register 401, the identification number of the processor core that executes the synchronization source partial program is set, and in the program address register 402, the final program address value of the synchronization source partial program is set. In the valid flag register 403, a flag value indicating whether the monitoring function of the program counter monitoring unit 13 is valid is set. The monitoring execution unit 404 compares the value of the program counter 11 of the processor core specified by the identification number set in the processor core number register 401 with the value of the program address register 402, and stops program execution according to the comparison result. The request and its release request are notified to the execution unit 12 of the processor core 10.

  4 shows the configuration of the processor core 10 and the program counter monitoring unit 13 corresponding thereto, the processor cores 20, 30, and 40 shown in FIG. 1 and the corresponding program counter monitoring units 23, 33, 43 may have the same configuration. Also, the number of processor cores and the corresponding program counter monitoring units may be other than four.

Next, the operation will be described.
When executing the synchronization destination program, the execution unit 12 of the processor core 10 sets a value indicating the validity of the monitoring function in the validity flag register 403 of the program counter monitoring unit 13. For example, in the partial program 211 shown in FIG. 2, since the dependency relationship 250 having the partial program 211 as a synchronization destination is set, the execution unit 12 of the processor core 10 stores the valid flag register 403 of the program counter monitoring unit 13. Set a value indicating that the monitoring function is enabled.

  Furthermore, the execution unit 12 of the processor core 10 sets the identification number of the processor core 20 that executes the partial program 221 that is the synchronization source in the dependency relationship 250 in the processor core number register 401 of the program counter monitoring unit 13, and the synchronization source The final program address value of the partial program 221 is set in the program address register 402 of the program counter monitoring unit 13.

  When a value indicating that the monitoring function is valid is set in the valid flag register 403, the monitoring execution unit 404 reads the value of the program counter 11 of the processor core 20 specified by the processor core number register 401, and this value and the program address The value of the register 402 is compared. Here, when the value of the program counter 11 of the processor core 20 is smaller than the value of the program address register 402, the monitoring execution unit 404 indicates that the execution unit 12 of the processor core 20 has not finished executing the partial program 221. The determination is made and a stop request is notified to the execution unit 12 of the processor core 10.

  When the execution unit 12 of the processor core 10 receives the stop request, the execution unit 12 temporarily stops the execution of the program 210. Thereafter, the monitoring execution unit 404 sequentially refers to the value of the program counter 11 of the processor core 20 and continues the above comparison process. The monitoring execution unit 404 continues to output a stop request to the execution unit 12 of the processor core 10 until it is determined from the comparison result that the execution of the partial program 221 has ended. As a result, the execution unit 12 of the processor core 10 enters the execution standby state of the partial program 211 until the execution of the partial program 221 ends.

  In the comparison process, when the value of the program counter 11 of the processor core 20 becomes larger than the value of the program address register 402, the monitoring execution unit 404 indicates that the execution unit 12 of the processor core 20 has finished executing the partial program 221. The determination is made, and the stop request cancellation request is notified to the execution unit 12 of the processor core 10. When the execution unit 12 of the processor core 10 receives the release request, the execution of the program 210 is resumed and the execution of the partial program 211 is started. When the synchronization processing between the processor core 10 and the processor core 20 is finished, the monitoring execution unit 404 immediately clears the flag value of the valid flag register 403 and disables the monitoring function.

  As described above, according to the second embodiment, the program counter monitoring units 13, 23, 33, and 43 are executed by the processor core identification number designated by the processor core corresponding to the program counter monitoring unit 13, and the processor core. The program register 400 holding the address value of the synchronization source program, the identification number and the address value of the synchronization source program are acquired from the program register 400, and the value of the program counter corresponding to the processor core of this identification number and the synchronization source In accordance with the comparison result with the address value of the program, the monitoring execution unit 404 that controls whether or not the synchronization target program can be executed by the processor core corresponding to itself is provided. Simply write monitoring information to register 400, It is possible to carry out the monitoring process of the data.

  In the second embodiment, the case where a plurality of registers constituting the program register 400 are assigned as the processor core number register 401, the program address register 402, and the valid flag register 403 as shown in FIG. However, the present invention is not limited to this.

  For example, as shown in FIG. 5, one register is a program counter monitoring register 410, and its bit fields are an area for setting a valid flag, an area for setting a processor core number, a program address (the final program of a synchronization source program) (Address value) may be assigned as an area for setting.

  In the second embodiment, a plurality of program registers 400 and program counter monitoring registers 410 may be provided in one program counter monitoring unit. In this case, by setting values in the program register 400 and the program counter monitoring register 410 in accordance with the dependency relationship of the program executed between the plurality of processor cores, the monitoring of the program counter 11 for the plurality of dependency relationships is simultaneously executed. can do.

  Further, the processor core number register and the valid flag register of the program register 400 except for the processor core number register may be provided in the processor core.

Embodiment 3 FIG.
In the third embodiment, the monitoring process by the program counter monitoring unit is executed by a dedicated instruction.
FIG. 6 is a block diagram showing the configuration of the multi-core processor according to the third embodiment of the present invention, and particularly shows the detailed configuration of the program counter monitoring unit. In addition, the same code | symbol is attached | subjected to the thing corresponded to the component shown in FIG. FIG. 7 is a diagram illustrating an example of an instruction code of a dedicated instruction executed by the execution unit of the processor core in FIG.

  In the program counter monitoring unit 13 according to the third embodiment, the monitoring execution unit 404 is executed by the execution unit 12 of the processor core 10 as indicated by an arrow from the execution unit 12 to the monitoring execution unit 404 in FIG. The monitoring process is executed in response to the data specified by the instruction code of the dedicated instruction in the program. The instruction code 500 of the dedicated instruction includes a dedicated instruction identifier 501, a processor core number 502, and a program address 503 as shown in FIG.

  Here, the dedicated instruction identifier 501 is an identifier indicating that the instruction code 500 is a dedicated instruction. The processor core number 502 is an identification number for identifying the processor core that is the synchronization source in the dependency relationship. The program address 503 is the final program address value of the partial program that becomes the synchronization source due to the dependency.

  6 shows the configuration of the processor core 10 and the program counter monitoring unit 13 corresponding thereto, the processor cores 20, 30, 40 and the corresponding program counter monitoring units 23, 33 shown in FIG. , 43 may be similarly configured. Also, the number of processor cores and the corresponding program counter monitoring units may be other than four.

Next, the operation will be described.
The execution unit 12 of the processor core 10 reads and executes an instruction code constituting the program from a memory storing the program assigned to itself. Here, the execution unit 12 of the processor core 10 specifies that the instruction code 500 is a dedicated instruction from the value of the dedicated instruction identifier 501 in the instruction code 500 shown in FIG. The program address 503 is extracted. Subsequently, the execution unit 12 of the processor core 10 outputs the processor core number 502 and the program address 503 extracted from the instruction code 500 to the program counter monitoring unit 13 as information on the dependency relationship.

  Here, a synchronization process for the dependency relationship 250 shown in FIG. 2 is taken as an example. That is, it is assumed that the dedicated instruction is set at the address immediately before the partial program 211, the processor core 20 is specified by the processor core number 502, and the program address 503 is the final program address value of the partial program 221.

  In the monitoring execution unit 404 of the program counter monitoring unit 13, the processor core 20 is identified by the processor core number 502 acquired from the information related to the dependency relationship 250, and becomes the synchronization source based on the value of the program counter 11 of the processor core 20 and the dependency relationship 250. The value of the program address 503 of the partial program 221 is compared. Here, if the value of the program counter 11 of the processor core 20 specified by the processor core number 502 is smaller than the value of the program address 503, the monitoring execution unit 404 causes the execution unit 12 of the processor core 20 to execute the partial program 221. Is not finished, and a stop request is notified to the execution unit 12 of the processor core 10.

  When the execution unit 12 of the processor core 10 receives the stop request, the execution unit 12 temporarily stops the execution of the program 210. Thereafter, the monitoring execution unit 404 sequentially refers to the value of the program counter 11 of the processor core 20 and continues the above comparison process. The monitoring execution unit 404 continues to output a stop request to the execution unit 12 of the processor core 10 until it is determined from the comparison result that the execution of the partial program 221 has ended. As a result, the execution unit 12 of the processor core 10 enters the execution standby state of the partial program 211 until the execution of the partial program 221 ends.

  In the comparison process, when the value of the program counter 11 of the processor core 20 becomes larger than the value of the program address register 402, the monitoring execution unit 404 causes the execution unit 12 of the processor core 20 to finish executing the partial program 221. It is determined that the stop request is released to the execution unit 12 of the processor core 10. When the execution unit 12 of the processor core 10 receives the release request, the execution of the program 210 is resumed and the execution of the partial program 211 is started.

  As described above, according to the third embodiment, the processor core executes the dedicated instruction in which the processor core identification number and the address value of the synchronization source program executed in the processor core are set. The identification number and the address value of the synchronization source program are output as monitoring information to the program counter monitoring unit corresponding to itself, and the program counter monitoring unit displays the program counter corresponding to the processor core of the identification number specified by the monitoring information. Since the monitoring execution unit 404 that controls whether or not the synchronization destination program can be executed by the processor core corresponding to the value according to the comparison result between the value and the address value of the synchronization source program is provided, a register function is provided in the program counter monitoring unit. The synchronization process can be realized without having

  In the third embodiment, the monitoring function of the program counter monitoring unit becomes effective when the execution unit 12 executes the dedicated instruction. For this reason, the information corresponding to the valid flag register 403 shown in FIG.

Embodiment 4 FIG.
In the first to third embodiments, the case where the final program address value of the synchronization source program is directly specified has been described. On the other hand, in the fourth embodiment, the program address handled by the program counter monitoring unit and the value of the program counter 11 are offset based on the start address of the program executed by each processor core 10, 20, 30, 40. By using the address, it is possible to flexibly cope with the program layout change (address change).

  FIG. 8 is a block diagram showing a configuration of a processor core in a multi-core processor according to Embodiment 4 of the present invention. Components corresponding to those shown in FIG. 1 are denoted by the same reference numerals. In FIG. 8, the processor core 10 according to the fourth embodiment includes an offset calculation unit 14 and a base address register 15 in addition to the program counter 11 and the execution unit 12.

  The offset calculation unit 14 outputs an offset value obtained by subtracting the value of the base address register 15 from the value of the program counter 11 of the processor core 10 to the program counter monitoring units 23, 33, and 43 as the value of the program counter 11. A fixed base address value is set in the base address register 15 so that the offset value becomes the same value according to the change of the arrangement area (address) of the program executed by the execution unit 12 of the processor core 10.

  8 shows the configuration of the processor core 10, the processor cores 20, 30, and 40 shown in FIG. 1 may be configured in the same manner. Further, the number of processor cores may be other than four.

Next, the operation will be described.
The execution unit 12 of the processor core 10 reads a program from the memory and executes it. At this time, the offset calculation unit 14 reads the address value of the program set in the program counter 11 and the value of the base address register 15, and subtracts these values to obtain the offset value. This offset value is output as the value of the program counter 11 of the processor core 10 from the offset calculation unit 14 to the program counter monitoring units 23, 33, and 43 corresponding to the other processor cores 20, 30, and 40, respectively.

  Further, the program counter monitoring units 23, 33, and 43 receive synchronization source programs (execution units 12 of the processor cores 20, 30, and 40) executed by the processor core 10 from the execution units 12 of the processor cores 20, 30, and 40. The last program address value of the program executed by the processor core 10 is given as an offset from the start address of the program executed by the processor core 10.

  Here, when the arrangement area of the program executed by the processor core 10 is changed, the value of the base address register 15 is set to be the same value as the offset value before the program arrangement is changed. In this way, when the execution unit 12 of the processor cores 20, 30, and 40 processes a program as a synchronization destination, it is not necessary to change the program address of the synchronization source program.

  As described above, according to the fourth embodiment, the processor core subtracts the base address register 15 in which the base value is set and the base value of the base address register 15 from the value of the program counter corresponding to itself. An offset calculation unit 14 that outputs a value to a program counter monitoring unit corresponding to a program counter 11 other than itself as a value of the program counter 11 corresponding to itself, and the program counter monitoring unit is a synchronization destination program by the processor core corresponding to itself In controlling whether or not to execute the program, the value of the program counter 11 represented by the offset value defined by the base value is compared with the address value of the synchronization source program, so that the program layout can be changed flexibly (address change). Can respond.

  In the above description, the case in which the fourth embodiment is applied to the first embodiment has been described. However, the present invention may be applied to the second and third embodiments.

Embodiment 5 FIG.
In the first embodiment, it is assumed that the program is executed in ascending order of the addresses, and the value of the program counter 11 increases as the program is executed. For example, consider a case where there is a branch instruction for branching to the partial program 223 at the final program address of the partial program 222 shown in FIG. 2 and the partial program 221 ends earlier than the start timing of the partial program 211. In this case, even before the program counter monitoring unit 13 starts determining whether or not the execution of the partial program 221 has started, if the execution unit 12 of the processor core 20 executes the branch instruction, the execution branches to the execution of the partial program 223. .

  At this time, the program counter 11 of the processor core 20 returns to a value smaller than the final program address value of the partial program 221 even though the execution of the partial program 221 has ended. In this case, whether or not the execution of the partial program 221 has ended is determined only by comparing the value of the program counter 11 of the processor core 20 with the final program address value of the partial program 221 included in the information on the dependency relationship 250. It cannot be determined accurately.

  In the fifth embodiment, even if an instruction in which the value of the program counter 11 is not in ascending order by branching out of the partial program, such as a branch instruction, is included in the partial program, the counter that holds the program address of the branch source By providing a value holding unit, the program counter monitoring unit can accurately determine.

  FIG. 9 is a block diagram showing a configuration of a processor core in a multi-core processor according to Embodiment 5 of the present invention. Components corresponding to those shown in FIG. 1 are denoted by the same reference numerals. In FIG. 9, the processor core 10 according to the fifth embodiment includes a counter value holding unit 16 in addition to the program counter 11 and the execution unit 12. The counter value holding unit 16 holds the value of the program counter 11 in accordance with an instruction executed by the execution unit 12, and outputs the held value to the program counter monitoring units 23, 33, and 43 corresponding to other processor cores.

  In the first to fourth embodiments, the value of the program counter 11 indicating the operation status of the processor core is directly output to the program counter monitoring unit. On the other hand, in the fifth embodiment, the value of the program counter 11 held by the counter value holding unit 16 is output according to the operating state of the processor core.

  For example, even if the process is predicted to return after branching, such as subroutine processing or interrupt processing by a combination of a CALL instruction and a RET instruction, the value of the program counter 11 during the branching process Is the value held immediately before branching. As a result, it is possible to prevent the dependency relationship using the branch destination program counter 11 from being determined, and an illegal passage determination is not performed when the branch destination program is executed.

  9 shows the configuration of the processor core 10, the processor cores 20, 30, and 40 shown in FIG. 1 may be configured in the same manner. Further, the number of processor cores may be other than four.

Next, the operation will be described.
The execution unit 12 of the processor core 10 outputs a counter value holding command to the counter value holding unit 16 together with the execution of the CALL instruction included in the program executed by itself and the start of interrupt processing. When the counter value holding unit 16 receives the counter value holding command, the counter value holding unit 16 holds the value of the program counter 11 immediately before the branch by the CALL instruction or interrupt processing. Thereafter, when the execution unit 12 of the processor core 10 executes the branch destination program, the value of the program counter 11 is updated with the address value of the branch destination program.

  On the other hand, while the execution unit 12 of the processor core 10 executes the branch destination program, the counter value holding unit 16 uses the address value immediately before the branch held by itself as the value of the program counter 11 of the processor core 10 as another value. The data is output to the program counter monitoring units 23, 33, and 43 corresponding to the processor cores 20, 30, and 40, respectively. As a result, the program counter monitoring units 23, 33, and 43 execute the dependency determination based on the address value immediately before the branch in the processor core 10.

  Thereafter, when the execution unit 12 of the processor core 10 executes a RET instruction for returning from the branch process by the CALL instruction or an IRET instruction for returning from the interrupt process, the counter value holding unit 16 is associated with this. To output a release command. When the counter value holding unit 16 receives the release command, the counter value monitoring unit 23 corresponding to the other processor cores 20, 30, and 40 uses the value set in the program counter 11 at that time instead of the value held by itself. , 33 and 43, respectively.

  Here, consider a case where the CALL instruction is executed again during the execution of the interrupt processing by the CALL instruction. In this case, the counter value holding unit 16 counts the number of times the CALL instruction has been issued. For example, when the CALL instruction is executed, the counter is set to +1, and when the RET instruction is executed, the counter is set to -1. When the value of the counter is not 0, the value of the program counter 11 of the processor core on which the self is mounted is held. When the value of the counter is 0, the value of the program counter 11 is directly corresponded to another processor core. Output to the program counter monitoring unit.

  FIG. 10 is a diagram for explaining the program executed by the processor core in FIG. 9, the dependency relationship between the programs, and the branch process. The operation in the branch process will be described in detail with reference to FIG. In FIG. 10, a program 510 is a program executed by the execution unit 12 of the processor core 10, and includes partial programs 511 and 512. The partial programs 511 and 512 are stored in the memory so that the addresses are in ascending order in the order of the partial program 511 and the partial program 512. The execution unit 12 of the processor core 10 reads the program from the memory in ascending order and executes the partial programs, thereby executing the program 510 in the order of the partial program 511 and the partial program 512 as indicated by arrows in FIG. Execute.

  The program 520 is a program executed by the execution unit 12 of the processor core 20 and includes a partial program 521 and a subroutine program 522. The partial program 521 and the subroutine program 522 are stored in the memory so that the addresses are in ascending order in the order of the partial program 521 and the subroutine program 522.

  A dependency relationship 530 is set between the partial program 512 and the partial program 521. This dependency relationship 530 is the execution of the partial program 512 by the execution unit 12 of the processor core 10 after the execution of the partial program 521 by the execution unit 12 of the processor core 20, that is, the synchronization destination in the processor core 10. This shows that the execution of the partial program 512 is dependent on the execution of the partial program 521 that is the synchronization source in the processor core 20.

  The partial program 521 includes a CALL instruction, and when this CALL instruction is executed, the process branches to the subroutine program 522 as indicated by an arrow in FIG. On the other hand, when the RET instruction in the subroutine program 522 is executed, the process returns to the execution of the partial program 521 as indicated by an arrow in FIG.

  When the CALL instruction is executed and the process branches to the subroutine program 522, even if the execution of the partial program 521 is not completed, the value of the program counter 11 of the processor core 20 is the final program address of the partial program 521. Larger than the value. For this reason, in the processing based on the assumption that the programs are executed in ascending order of addresses as in the first embodiment, the program counter monitoring unit may erroneously determine the end of execution of the synchronization source program.

  Therefore, the execution unit 12 of the processor core 20 outputs a counter value holding command to the counter value holding unit 16 when executing the CALL instruction in the partial program 521 and branching to the processing of the subroutine program 522. Upon receiving this command, the counter value holding unit 16 changes the value of its own program counter 11 disclosed to the other processor cores 10, 30, 40 via the program counter monitoring units 13, 33, 43 before branching. Keep the value. In this way, the program counter monitoring unit 13 corresponding to the processor core 10 can recognize that the execution unit 12 of the processor core 20 is executing the partial program 521.

  The execution unit 12 of the processor core 20 returns to the processing of the partial program 521 by executing the RET instruction in the subroutine program 522. At this time, the execution unit 12 of the processor core 20 outputs a release command to the counter value holding unit 16. When this command is received, the counter value holding unit 16 uses the value of the program counter 11 in which the address value in the partial program 521 returned by the RET instruction is set as the program counter corresponding to the other processor cores 10, 30, 40. Output to the monitoring unit 13, 33, 43. Thereafter, when the execution of the partial program 521 is completed by the execution unit 12 of the processor core 20, the program counter monitoring unit 13, which is a peripheral circuit of the processor core 10, can accurately determine the end of execution of the partial program 521. it can.

  As described above, according to the fifth embodiment, a branch instruction is provided for each of the plurality of processor cores 10, 20, 30, and 40, and a branch instruction is executed by the processor core corresponding to the processor core. Since the counter value holding unit 16 that holds the value of the program counter 11 until it returns from the branch is provided, even if an instruction that branches outside the partial program such as a branch instruction is included, the dependency by the program counter monitoring unit The relationship can be accurately determined.

  The fifth embodiment can be applied not only to the first embodiment but also to the second to fourth embodiments. For example, the value of the program address area of the program address register 402 or the program counter monitoring register 410 may be held by the counter value holding unit 16 by being applied to the configuration of the second embodiment. Further, by applying to the configuration of the third embodiment, the program address value specified by the dedicated instruction may be held by the counter value holding unit 16. Furthermore, the value calculated by the offset calculation unit 14 may be held by the counter value holding unit 16 by being applied to the configuration of the fourth embodiment.

It is a block diagram which shows the structure of the multi-core processor by Embodiment 1 of this invention. It is a figure for demonstrating the dependency relationship between the program run with the processor core in FIG. 1, and a program. It is a figure for demonstrating the program performed with the processor core in FIG. 1, the dependency between programs, and a branch process. It is a block diagram which shows the structure of the multi-core processor by Embodiment 2 of this invention. It is a figure which shows the structure of a program counter monitoring register. It is a block diagram which shows the structure of the multi-core processor by Embodiment 3 of this invention. It is a figure which shows an example of the instruction code of the dedicated instruction performed by the execution part of the processor core in FIG. It is a block diagram which shows the structure of the processor core in the multi-core processor by Embodiment 4 of this invention. It is a block diagram which shows the structure of the processor core in the multi-core processor by Embodiment 5 of this invention. It is a figure for demonstrating the program performed with the processor core in FIG. 9, the dependence between programs, and a branch process.

Explanation of symbols

  1 multi-core processor, 10, 20, 30, 40 processor core, 11 program counter, 12 execution unit, 13, 23, 33, 44 program counter monitoring unit, 14 offset calculation unit, 15 base address register, 16 counter value holding unit, 210, 220, 230, 240, 310, 320, 510, 520 program, 211, 221-223, 311-314, 321-323, 511, 512, 521 Partial program, 250, 300-302, 530 dependency, 400 Program register, 401 processor core number register, 402 program address register, 403 valid flag register, 404 monitoring execution unit, 500 instruction code, 501 dedicated instruction identifier, 502 processor core number, 503 program Gram address.

Claims (5)

Multiple processor cores,
A program counter which is provided corresponding to each of the plurality of processor cores and holds an address value of a program executed by the processor core corresponding to the processor core;
The synchronization partner is provided corresponding to each of the plurality of processor cores, and the synchronization counter prior to execution of the value of the program counter corresponding to the synchronization partner processor core designated by the processor core corresponding to the processor core and the synchronization destination program A multi-core comprising a program counter monitoring unit that controls whether or not the synchronization target program can be executed by the processor core corresponding to the self according to a comparison result with an address value of a synchronization source program executed by the processor core Processor.   The program counter monitoring unit includes a register that holds an identification number of a processor core designated from a processor core corresponding to itself and an address value of a synchronization source program executed by the processor core, and the identification number and the The address value of the synchronization source program is acquired, and the synchronization by the processor core corresponding to the self is obtained according to the comparison result between the value of the program counter corresponding to the processor core of the identification number and the address value of the synchronization source program The multi-core processor according to claim 1, further comprising a monitoring execution unit that controls whether or not the preceding program can be executed. The processor core executes the dedicated instruction in which the identification number of the processor core and the address value of the synchronization source program executed by the processor core are set, thereby obtaining the identification number and the address value of the synchronization source program. Output to the program counter monitoring unit corresponding to itself as monitoring information,
The program counter monitoring unit, according to a comparison result between the value of the program counter corresponding to the processor core of the identification number specified by the monitoring information input from the processor core and the address value of the synchronization source program, 2. The multi-core processor according to claim 1, further comprising a monitoring execution unit that controls whether or not the synchronization destination program can be executed by a processor core corresponding to the processor core. The processor core uses a base address register in which a base value is set and an offset value obtained by subtracting the base value of the base address register from the value of the program counter corresponding to itself as a value of the program counter corresponding to the self And an offset calculation unit that outputs to the program counter monitoring unit corresponding to
The program counter monitoring unit controls whether or not the synchronization destination program can be executed by the processor core corresponding to itself, and the value of the program counter represented by the offset value specified by the base value and the address of the synchronization source program 4. The multi-core processor according to claim 1, wherein the multi-core processor compares the value with each other.   A counter value holding unit is provided corresponding to each of the plurality of processor cores, and holds the value of the program counter before the branch until returning from the branch when the branch instruction is executed by the processor core corresponding to the processor core. The multi-core processor according to any one of claims 1 to 4, wherein

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