JP2013247574A - Pwm signal generation circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PWM signal generation circuit capable of changing an oscillation frequency of a PWM signal and a semiconductor device therewith which implement a noise reduction.SOLUTION: For example, the PWM signal generation circuit includes a triangular wave generation circuit for generating a triangular wave (Vrmp), and a PWM comparison circuit for comparing the triangular wave (Vrmp) with a reference voltage (Vref) and generating a PWM signal having a duty depending on the level of the reference voltage (Vref). The triangular wave generation circuit changes an oscillation frequency of the triangular wave (Vrmp) by changing the slope of at least either of the rise and fall of the triangular wave (Vrmp) at a transition timing (TS1a-TS1d, TS2a-TS2c) of the rise or fall. This keeps a constant on duty of the PWM signal irrespective of the change in the oscillation frequency.

Description

  The present invention relates to a PWM signal generation circuit and a semiconductor device, for example, a technique effective when applied to a PWM signal generation circuit capable of changing an oscillation frequency of a PWM (Pulse Width Modulation) signal and a semiconductor device including the PWM signal generation circuit.

  For example, Patent Document 1 discloses a PWM amplifier that detects the modulation degree of a PWM signal, raises the oscillation frequency of the PWM signal when the modulation degree is large, and lowers the oscillation frequency of the PWM signal when the modulation degree is small. It is shown. The PWM signal is generated by using a triangular wave generator of a type that alternately repeats charging / discharging operation with respect to the capacity, and the oscillation frequency of the PWM signal is changed by changing the charging / discharging current.

  Further, Patent Document 2 monitors the average output level of a power amplifier that operates using a PWM signal as an input, and changes the oscillation frequency of the PWM signal when the average output level is outside a predetermined range. An apparatus for monitoring whether or not a power amplifier has failed by detecting a change in the oscillation frequency is shown. The PWM signal is generated using a triangular wave generator that alternately repeats charging and discharging operations with respect to a capacitor, and the oscillation frequency of the PWM signal is changed by switching the capacitance value of the capacitor with a switch.

JP-A-6-303049 Japanese Utility Model Publication No. 58-116317

  For example, a PWM signal generation circuit is widely used in various devices in various fields such as a power supply regulator device, a class D amplifier device, and a motor driving device. In such a device, it is important to reduce power consumption in a large social trend such as global environmental conservation in recent years. In order to reduce the power consumption of the device, it is effective to lower the oscillation frequency of the PWM signal. On the other hand, in order to improve the functional performance of the device (such as accuracy and resolution), A higher oscillation frequency of the PWM signal is desirable. In order to solve such a conflicting relationship, for example, it is beneficial to install a function that appropriately switches the oscillation frequency of the PWM signal in accordance with the situation in the apparatus.

  When switching the oscillation frequency of the PWM signal, for example, it is conceivable to change the oscillation frequency of the triangular wave generator using the techniques of Patent Document 1 and Patent Document 2. However, as a result of studies by the present inventors, it has been found that noise can be a problem when the oscillation frequency of the triangular wave generator is changed. As described above, it is beneficial to switch the oscillation frequency of the PWM signal appropriately according to the situation, but in this case, the variable range of the oscillation frequency accompanying the switching may be widened or the switching frequency may be increased. Can be considered. In this case, there is a possibility that noise accompanying the change of the oscillation frequency has a great adverse effect on the apparatus.

  Embodiments to be described later have been made in view of the above, and other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  Of the means for solving the problems disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A PWM signal generation circuit according to an embodiment includes a waveform generation circuit that generates a triangular wave, and a PWM comparison circuit that compares the triangular wave with an input signal and generates a PWM signal having a duty corresponding to the level of the input signal. Here, the waveform generation circuit changes the oscillation frequency of the triangular wave by changing the slope of at least one of the rising edge and the falling edge of the triangular wave from the transition timing of the rising edge and the falling edge.

  According to the one embodiment, noise can be reduced in the PWM signal generation circuit capable of changing the oscillation frequency of the PWM signal and the semiconductor device including the PWM signal generation circuit.

(A), (b) and (c) are explanatory diagrams showing an example of a schematic operation principle in the PWM signal generation circuit according to the first embodiment of the present invention. 1 is a circuit block diagram showing an example of the configuration of a PWM signal generation circuit according to a first embodiment of the present invention. FIG. 3 is a waveform diagram showing a schematic operation example in the PWM signal generation circuit of FIG. 2. It is a wave form diagram which shows the schematic operation example which deform | transformed FIG. FIG. 3 is a circuit diagram showing a detailed configuration example of the variable current source in the PWM signal generation circuit of FIG. 2. 1 is a block diagram showing a schematic configuration example of a semiconductor device according to a first embodiment of the present invention. FIG. 10 is a block diagram showing another schematic configuration example of the semiconductor device according to the first embodiment of the present invention. 5 is a circuit block diagram showing an example of the configuration of a PWM signal generation circuit according to a second embodiment of the present invention. FIG. FIG. 9 is a waveform diagram showing a schematic operation example in the PWM signal generation circuit of FIG. 8. FIG. 10 is a waveform diagram showing a schematic operation example of the PWM signal generation circuit according to the third embodiment of the present invention. In the PWM signal generation circuit by Embodiment 4 of this invention, it is a wave form diagram which shows the schematic operation example. FIG. 10 is a circuit diagram showing a configuration example of a triangular wave generation circuit in a PWM signal generation circuit according to a fifth embodiment of the present invention. FIG. 5 is a waveform diagram showing a schematic operation example of a PWM signal generation circuit studied as a premise of the present invention.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as a MOS transistor) is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), but a non-oxide film is not excluded as a gate insulating film. Absent.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<< Operation of PWM signal generation circuit (comparative example) >>
FIG. 13 is a waveform diagram showing a schematic operation example of the PWM signal generation circuit studied as a premise of the present invention. In FIG. 13, the PWM signal (PWM ′) is generated by comparing the triangular wave (Vrmp ′) and the reference voltage Vref, and the frequency of PWM ′ is changed by changing the oscillation frequency of Vrmp ′. . Here, since PWM ′ is generally demodulated by a low-pass filter in practical use, the oscillation frequency can be switched at an arbitrary timing. For example, as shown in FIG. It is possible to switch at an arbitrary timing TS1 ′. Specifically, as in Patent Document 1 and Patent Document 2 described above, the capacitance value or charge / discharge current value of the triangular wave generation circuit is changed.

  As shown in FIG. 13, the PWM signal (PWM ′) is demodulated into an output voltage signal Vo ′ having a predetermined ripple component with a predetermined average voltage Vc ′ as a center through a low-pass filter. Here, when the PWM cycle T3 is compared with the subsequent PWM cycle T4, the ON period Tw2 of PWM ′ is the same, but the cycle is shorter in the cycle Tck2 in T3 than in the cycle Tck3 in T4. As a result, the average voltage Vc ′ determined by the PWM on-duty is higher by ΔVc ′ in the case of T3 (Tw2 / Tck2) than in the case of T4 (Tw2 / Tck3). However, due to the effect of the low-pass filter, in the PWM cycle after T4, the operation converges to the constant average voltage Vc '(or is maintained at the constant average voltage Vc').

  However, when there is a PWM cycle T3 in which the on-duty fluctuates in this way, the average voltage Vc ′ fluctuates once with the transition from the PWM cycle T2 to T3, and then returns to the original value in the next PWM cycle T4. Since this is an operation, extra noise may occur in the output voltage signal Vo ′ with the fluctuation of Vc ′. In particular, when the variable range of the oscillation frequency of the PWM signal is large (that is, when the difference between the period Tck1 at T2 and the period Tck3 at T4 is large), the fluctuation range (ΔVc ′) of Vc ′ becomes large, and the oscillation When the frequency switching frequency is high, the frequency of occurrence of the noise is high, so that the noise cannot be ignored. Therefore, it is beneficial to use the method of this embodiment described later.

<< Operation principle of PWM signal generation circuit >>
FIG. 1A, FIG. 1B, and FIG. 1C are explanatory diagrams illustrating an example of a schematic operation principle in the PWM signal generation circuit according to the first embodiment of the present invention. FIG. 1A shows a triangular wave (Vrmp) that transitions between the lower limit voltage Vl and the upper limit voltage Vh, and the rising or falling slope (slope) can be arbitrarily changed. However, the slope is changed at the timing of switching from falling to rising (timing to reach the lower limit voltage Vl) TS1a to TS1d, or the timing switching from rising to falling (timing to reach the upper limit voltage Vh) TS2a to TS2c. , Not within the rising or falling period.

  When such a switching timing is used, for example, as shown in FIGS. 1B and 1C, it is possible to keep the PWM on-duty constant within a certain range of the reference voltage value with respect to the triangular wave. . In the upper example of FIG. 1B, the triangular wave (Vrmp_1) and the reference voltage Vref_1 are compared, and a PWM signal (PWM_1) having an on-duty of 33% is generated. Here, as shown in the lower diagram of FIG. 1B, for example, when a triangular wave (Vrmp_2) having a rising slope larger than that of the triangular wave (Vrmp_1) is used, based on the comparison with the same reference voltage Vref_1 as in the upper diagram. , A PMW signal (PWM_2) is generated. However, the PWM_2 has an on-period of 33% in the rising period and an on-period of 33% in the falling period because of the similar relationship of the triangles, and therefore has the same on-duty of 33% as in the above figure as a whole. It will be.

  On the other hand, in the example of the upper diagram in FIG. 1C, the triangular wave (Vrmp_1) and the reference voltage Vref_2 are compared, and a PWM signal (PWM_3) having an on-duty of 50% is generated. Here, as shown in the lower diagram of FIG. 1C, for example, when a triangular wave (Vrmp_3) having a smaller rising slope than the triangular wave (Vrmp_1) is used, based on the comparison with the same reference voltage Vref_2 as in the upper diagram. , A PMW signal (PWM_4) is generated. However, since the PWM_4 has a 50% on-period in the rising period and a 50% on-period in the falling period because of the similar relation of the triangle, the entire PWM_4 has the same 50% on-duty as the above figure. It will be. In this way, by setting the switching timing as shown in FIG. 1A, the PWM on-duty is maintained within a certain range of the reference voltage value regardless of how the rising slope and / or the falling slope are changed. Can be kept constant.

<< Configuration of PWM signal generation circuit >>
FIG. 2 is a circuit block diagram showing an example of the configuration of the PWM signal generation circuit according to the first embodiment of the present invention. The PWM signal generation circuit PWMG1 shown in FIG. 2 includes a triangular wave generation circuit TWG1, a buffer circuit BF, and a PWM comparison circuit PWMCMP. The TWG1 includes a capacitor Cw, variable current sources ISVc and ISVd, switches SWc and SWd, comparison circuits CMPh and CMPl, and a control circuit CTL1. Cw is coupled between the output node (Vrmp1) and the ground power supply voltage GND. ISVc and SWc are coupled in series between the power supply voltage VDD and the output node (Vrmp1), and perform charging operation on Cw when SWc is on. SWd and ISVd are coupled in series between the output node (Vrmp1) and GND, and perform a discharging operation on Cw when SWd is on.

  The comparison circuit CMPh detects that the output voltage Vrmp1 of the capacitor Cw has reached the upper limit voltage Vh, and the comparison circuit CMPl detects that Vrmp1 has reached the lower limit voltage Vl. The control circuit CTL1 controls on / off of the switches SWc and SWd according to the detection results of CMPh and CMPl, receives a current value setting signal (frequency setting signal) ISET, and supplies a current value corresponding to the variable current source. Set for ISVc and ISVd. Vrmp1 is input to one of two inputs in the PWM comparison circuit PWMCMP after passing through a buffer circuit BF such as a voltage follower circuit. The PWM CMP compares the output voltage (that is, Vrmp1) of the BF with the reference voltage Vref, and outputs a PWM signal (PWM1) based on the comparison result. Note that BF can be omitted.

<< Operation of PWM signal generation circuit [1] >>
FIG. 3 is a waveform diagram showing a schematic operation example of the PWM signal generation circuit of FIG. In the PWM cycle T1, the control circuit CTL1 controls the switch SWc to be on and the switch SWd to be off with the current value of the variable current source ISVc set to I1. As a result, the output voltage Vrmp1a of the capacitor Cw rises with a slope corresponding to I1. Subsequently, when the comparison circuit CMPh detects that Vrmp1a has reached the upper limit voltage Vh, the CTL1 controls SWc to be turned off and SWd to be turned on while the current value of the variable current source ISVd is set to I1. . As a result, Vrmp1a falls with a slope corresponding to I1. Thereafter, when it is detected by the comparison circuit CMPl that Vrmp1a has reached the lower limit voltage Vl, the CTL1 controls the SWc to be on and the SWd to be off with the ISVc being set to I1, as in the case of T1. Thus, the PWM cycle T2 is executed.

  Here, after the PWM cycle T3, the oscillation frequency of the triangular wave composed of the output voltage Vrmp1a is changed. In this case, the control circuit CTL1 sets the current value of the variable current source ISVc to I2 in advance in accordance with the current value setting signal (frequency setting signal) ISET during the falling period of Vrmp1a in the PWM cycle T2, which is the previous cycle. Change it. At T2, when the comparison circuit CMPl detects that Vrmp1a has reached the lower limit voltage Vl, the CTL1 controls the switch SWc to be turned on and the switch SWd to be turned off with ISVc set to I2. Thus, the setting change is actually effective, and Vrmp1a rises with a slope corresponding to I2 (here, I2 <I1), and shifts to the PWM cycle T3.

  Subsequently, in the PWM cycle T3, the control circuit CTL1 changes the current value of the variable current source ISVd to I2 in advance during the rising period of the output voltage Vrmp1a according to the current value setting signal (frequency setting signal) ISET. Keep it. When the comparison circuit CMPh detects that Vrmp1a has reached the upper limit voltage Vh, the CTL1 controls SWc to be turned off and SWd to be turned on while the current value of ISVd is set to I2. Thereby, the setting change is actually effective, and Vrmp1a descends with a slope corresponding to I2. Thereafter, when it is detected by the comparison circuit CMPl that Vrmp1a has reached the lower limit voltage Vl, the CTL1 complementarily controls on / off of the SWc and SWd while maintaining the current values of the ISVc and ISVd at I2. Then, the PWM cycle T4 is executed as in the case of T3.

  In the PWM cycles T1 to T4, the PWM comparison circuit PWMCMP outputs a PWM signal (PWM1a) by comparing the triangular wave (Vrmp1a) from the triangular wave generation circuit TWG1 with a constant reference voltage Vref. At this time, since the slope is changed starting from the falling-to-rising switching timing TS11 of the triangular wave (Vrmp1a) at T3 and the subsequent rising-to-falling switching timing TS21, the PWM 1a in FIG. As described with reference to a) to FIG. 1C, the on-duty value is kept constant. That is, in FIG. 3, the period at T1 and T2 is Tck1, the on period is Tw1, the period at T3 and T4 is Tck3, the on period is Tw2, and (Tw1 / Tck1) = (Tw2 / Tck3). As a result, when the PWM 1a is demodulated by the low-pass filter, the average voltage Vc11 is kept constant over T1 to T4, and an output voltage signal Vo11 having a predetermined ripple component around the Vc11 is obtained. .

<< Operation of PWM signal generation circuit [2] >>
FIG. 4 is a waveform diagram showing a schematic operation example obtained by modifying FIG. In FIG. 4, unlike the case of FIG. 3, the slope switching timing TS22 from the rising edge to the falling edge of the triangular wave (Vrmp1b) in the PWM cycle T3 and the switching timing TS12 from the falling edge to the rising edge in the subsequent PWM cycle T4 are set as starting points. Changes have been made. Accordingly, the change from the current value I1 to I2 of the variable current source ISVd is performed during the rising period of the triangular wave (Vrmp1b) at T3, and the change from I1 to I2 of the variable current source ISVc is performed at T3. This is performed during the falling period of the triangular wave (Vrmp1b).

  Even in this case, the on-duty value of the PWM signal (PWM1b) generated using the triangular wave (Vrmp1b) is kept constant as described in FIGS. 1 (a) to 1 (c). That is, in FIG. 4, the period at T1 and T2 is Tck1, the on period is Tw1, the period at T3 is Tck4, the on period is Tw3, the period at T4 is Tck3 (> Tck4), and the on period is Tw2 (> Tw3), and (Tw1 / Tck1) = (Tw3 / Tck4) = (Tw2 / Tck3). As a result, when the PWM 1b is demodulated by the low-pass filter, the average voltage Vc12 is kept constant over the PWM cycles T1 to T4, and an output voltage signal Vo12 having a predetermined ripple component around the Vc12 is obtained. become.

<Details of variable current source>
FIG. 5 is a circuit diagram showing a detailed configuration example of the variable current source in the PWM signal generation circuit of FIG. The variable current sources ISVc and ISVd are not particularly limited. For example, the variable current sources ISVc and ISVd can be realized by using a current mirror circuit as shown in FIG. 5 and a reference current source IREFG. In the example of FIG. 5, the reference current from IREFG is input between the source and drain of the NMOS transistor MN1, and the current flowing through MN1 is transferred to the NMOS transistors MN2 and MN3 constituting the current mirror circuit with MN1, respectively. The The source-drain current of MN2 is turned back by the PMOS transistor MP1 connected in series to MN2. The current flowing through MP1 is transferred to the PMOS transistor MP2 that forms a current mirror circuit with MP1.

  Thereby, the PMOS transistor MP2 functions as the variable current source ISVc, and the NMOS transistor MN3 functions as the variable current source ISVd. Here, as shown in FIGS. 3 and 4, when changing the rising and falling slopes of the triangular wave, for example, the transistor sizes of MP2 and MN3 may be configured to be dynamically variable. . In this case, the transistor size of MP2 in the inactive state (state in which no current flows) can be changed while MN3 is in the active state (state in which current is flowing), and inactive state while MP2 is in the active state The transistor size of MN3 can be changed.

<< Main effects of the first embodiment >>
As described above, by using the PWM signal generation circuit according to the first embodiment, even if the oscillation frequency of the PWM signal is changed, the average voltage (Vc11, Vc12) accompanying the PWM signal is kept constant. , Excess noise generated in the output voltage signals (Vo11, Vo12) as described in FIG. 13 can be reduced. As a result, in various devices equipped with the PWM signal generation circuit, it is possible to frequently switch the oscillation frequency of the PWM signal in a wide variable range depending on the situation, and the power consumption and performance of the various devices can be reduced ( High accuracy and high resolution).

  In FIGS. 3 and 4, both the rising slope and falling slope of the triangular wave are changed, but in principle, it is also possible to change only one of them. Thereby, the circuit area may be reduced. However, in this case, since the shape balance of the triangular wave can change greatly, it is preferable to configure both to change the balance from the viewpoint of maintaining this balance. In FIG. 5, the currents of the variable current sources ISVc and ISVd are generated using one reference current source IREFG. However, in some cases, the currents of ISVc and ISVd are separately independent using two reference current sources. It is also possible to configure so that it can be set.

  Further, in FIG. 5, the variable current sources ISVc and ISVd are realized by the transistor size (MP2, MN3), but it is also possible to realize ISVc and ISVd by changing the current value from the reference current source IREFG instead. . Thereby, the circuit area may be reduced. Further, for example, in FIG. 2, it is possible to change the oscillation frequency of the triangular wave by changing the capacitance Cw to a variable capacitance instead of the variable current sources ISVc and ISVd. However, in these cases, as described in FIGS. 3 to 5, for example, it is difficult to perform an operation in which a changed current value is set in advance for MP2 before MP2 is actually activated. obtain.

  That is, in the case of the former method, for example, an operation for changing the current value of the reference current source IREFG from the time of the switching timing TS11 in FIG. 3 and immediately reflecting the change in the variable current source ISVc to enable the setting change. It becomes. Similarly, in the case of the latter method, for example, the setting change and the activation of the capacitance value are started simultaneously from the time of the switching timing TS11 in FIG. In the case of these operations, there may be a slight delay from the time of the switching timing until the desired setting change is actually effective, and this delay may lead to an on-duty setting error in the PWM signal. Therefore, when such a delay becomes a problem, it is desirable to use the operation method and the circuit method as described in FIGS.

<< Overall Configuration and Operation of Semiconductor Device >>
FIG. 6 is a block diagram showing a schematic configuration example of the semiconductor device according to the first embodiment of the present invention. The semiconductor device shown in FIG. 6 is a power supply regulator device such as a step-down DC-DC converter DCDC. The DCDC includes switches (here, NMOS transistors) Qh1 and Ql1, a coil L1 and a capacitor C1, a driver circuit block DRVBK1, a PWM signal generation circuit PWMG1, and an error amplifier circuit EA. The high side switch Qh1 has a source coupled to the switch node Nsw1 and a drain coupled to the power supply voltage VCC, and the low side switch Ql1 has a source coupled to the ground power supply voltage GND and a drain coupled to Nsw1. Body diodes Dh and Dl having an anode on the source side are coupled between the source and drain of Qh1 and Ql1, respectively. Note that Ql1 may be realized only by a diode.

  One end of the coil L1 is coupled to the switch node Nsw1, one end of the capacitor C1 is coupled to the ground power supply voltage GND, and the other ends of L1 and C1 are coupled in common and the output power supply voltage Vout for the external load circuit LD. Supply node. The error amplifier circuit EA amplifies an error between Vout and a predetermined set voltage Vset, and outputs the amplification result as a reference voltage Vref. The PWM signal generation circuit as described with reference to FIGS. 1 to 5 is applied to the PWM signal generation circuit PWMG1, and as described above, the PWMG1 has a triangular wave having a frequency based on the current value setting signal ISET, the Vref, And a PWM signal (PWM1) corresponding to the comparison result is output. For example, the driver circuit block DRVBK1 drives the switch Qh1 on and the switch Ql1 off during the on period of the PWM1, and drives Ql1 on and Qh1 off during the off period of the PWM1.

  When the switch Qh1 / Ql1 is turned on / off, electric power is accumulated in the coil L1, and then when Qh1 / Ql1 is turned off / on, a so-called recirculation operation is performed using L1 as an electromotive force. By repeating such a switching operation, the power supply voltage VCC is converted to an output power supply voltage Vout lower than that. For example, when Vout is higher than the set voltage Vset, the reference voltage Vref increases. As a result, the on-duty of the PWM signal (PWM1) decreases, and control in the direction of decreasing Vout is performed. Here, the coil L1 and the capacitor C1 correspond to the low-pass filter described in FIG. 1 and the like. For example, the PWM1a demodulated signal in FIG. 3 corresponds to Vout in FIG.

  In such a power supply regulator device, if the oscillation frequency (switching frequency) of the PWM signal is increased, the ripple component in the output power supply voltage Vout can be reduced, and a sufficient current can be supplied to the load circuit LD. For example, it becomes possible to improve the response to the current fluctuation of the LD. On the other hand, so-called switching loss associated with the switching operation increases, and power consumption can increase. On the other hand, if the switching frequency is lowered, power consumption can be reduced, but an increase in ripple components and a decrease in responsiveness to the LD can occur. Therefore, for example, it is desirable to switch the switching frequency appropriately according to the operating state of the load circuit LD. When the PWM signal generation circuit of the first embodiment described above is used, a noise component (power supply noise) of Vout can be suppressed when switching the switching frequency, and a beneficial effect is obtained.

  FIG. 7 is a block diagram showing another schematic configuration example of the semiconductor device according to the first embodiment of the present invention. The semiconductor device shown in FIG. 7 is, for example, a class D amplifier device DAMP. The DAMP includes a high side switch (PMOS transistor here) Qh2, a low side switch (NMOS transistor here) Ql2, a low pass filter LPF, a driver circuit block DRVBK2, and a PWM signal generation circuit PWMG1. Qh2 has a source coupled to the power supply voltage VCC, a drain coupled to the switch node Nsw2, and Ql2 has a source coupled to the power supply voltage (eg, a negative power supply voltage) VEE and a drain coupled to Nsw2.

  The low pass filter LPF has an LC type configuration as shown in FIG. 6, for example, and has an input coupled to the switch node Nsw2 and an output coupled to an external load circuit LD. The PWM signal generation circuit described with reference to FIGS. 1 to 5 is applied to the PWM signal generation circuit PWMG1, and as described above, the PWMG1 has a triangular wave having a frequency based on the current value setting signal ISET and the reference voltage Vref. And a PWM signal (/ PWM1) corresponding to the comparison result is output. Here, Vref is input by, for example, an external AC signal source VAC, and the PWM signal (/ PWM1) is, for example, a signal generated by switching the input polarity of the PWM comparison circuit PWMCMP in FIG. As a result, the PWM signal (/ PWM1) becomes a signal having a larger on-duty as the voltage level of the AC signal Vaci from the VAC increases.

  For example, the driver circuit block DRVBK2 drives the switch Qh1 to be on and the switch Ql1 to be off when the PWM signal (/ PWM1) is on, and drives Ql1 to be on and Qh1 to be off when the PWM signal (/ PWM1) is off. To do. As a result, a signal obtained by amplifying the “H” level / “L” level amplitude of the PWM signal (/ PWM1) to the power supply voltage VCC level / VEE level is generated at the switch node Nsw2. The low-pass filter LPF averages the Nsw2 signal, and as a result, outputs the AC signal Vaco that is obtained by amplifying the AC signal Vaci from the AC signal source VAC toward the load circuit LD. Here, for example, the PWM1a demodulated signal in FIG. 3 corresponds to Vaco in FIG.

  In such a class D amplifier device, if the oscillation frequency (switching frequency) of the PWM signal is increased, the ripple component in the AC signal Vaco can be reduced and the output waveform quality (linear amplification between Vaci and Vaco, etc.) It becomes possible to improve. On the other hand, so-called switching loss associated with the switching operation increases, and power consumption can increase. On the other hand, if the switching frequency is lowered, power consumption can be reduced, but an increase in ripple components and a decrease in output waveform quality can occur. Therefore, for example, it is desirable to switch the switching frequency as appropriate in accordance with the operating state of the load circuit LD (for example, how much waveform quality is required). When the PWM signal generation circuit of the first embodiment described above is used, the noise component of Vaco can be suppressed when switching the switching frequency, and a beneficial effect can be obtained. For example, when the class D amplifier device is applied as an audio amplifier, so-called pop noise can be reduced.

  As described above, by using the PWM signal generation circuit and the semiconductor device according to the first embodiment, typically, the oscillation frequency of the PWM signal can be changed, and noise associated therewith can be reduced.

(Embodiment 2)
<< Configuration and Operation of PWM Signal Generation Circuit (Modification) >>
In the first embodiment described above, a PWM signal is generated using a triangular wave. In the second embodiment, a PWM signal is generated using a so-called sawtooth wave that is one form of a triangular wave. FIG. 8 is a circuit block diagram showing an example of the configuration of the PWM signal generation circuit according to the second embodiment of the present invention. The PWM signal generation circuit PWMG2 shown in FIG. 8 is obtained by changing the triangular wave generation circuit TWG1 of FIG. 2 to the triangular wave generation circuit TWG2 of FIG. 8 as compared with the PWM signal generation circuit PWMG1 of FIG. . Compared with TWG1 in FIG. 2, the discharge side variable current source ISVd and the lower limit voltage Vl side comparison circuit CMPl are deleted, and the operation of the control circuit CTL2 is slightly changed in TWG2 in FIG. It has become a thing. Since the configuration other than this is the same as that in the case of FIG. 2, detailed description thereof is omitted.

  FIG. 9 is a waveform diagram showing a schematic operation example of the PWM signal generation circuit of FIG. As shown in FIG. 9, the control circuit CTL2 of FIG. 8 charges the capacitor Cw using the variable current source ISVc in a state where the switch SWc is turned on and the switch SWd is turned off in each PWM cycle T1 to T4. Make it. However, after that, when the comparison circuit CMPh detects that the output voltage Vrmp2 from the CW has reached the upper limit voltage Vh, the CTL2 turns off SWc in a predetermined short period, unlike the case of FIG. SWd is controlled to be on, and Cw is rapidly discharged. As a result, a triangular wave (saw faction) (Vrmp2) as shown in FIG. 9 is generated.

  In FIG. 9, as in the case of FIG. 3, the oscillation frequency of the triangular wave (saw group) (Vrmp2) is changed in the PWM cycle T3. In this case, as in the case of FIG. 3, the control circuit CTL2 controls the variable current source ISVc during the period in which the discharging operation of the capacitor Cw (the switch SWc is off and the switch SWd is on) in the previous PWM cycle T2. Is changed from I1 to I2 (here, I2 <I1). The CTL 2 controls the SWc to be on and the SWd to be off at the switching timing TS13 after the discharging operation in a state where the current value has been changed.

  Even when such a configuration and operation are used, the on-duty of the PWM signal (PWM2) can be kept constant regardless of the change of the oscillation frequency according to the principle described in the first embodiment. As a result, the same effect as in the first embodiment can be obtained. Further, since the variable current source and the comparison circuit can be reduced as compared with the case of the first embodiment, the circuit area can be reduced.

(Embodiment 3)
<< Operation of PWM signal generation circuit (application example [1]) >>
FIG. 10 is a waveform diagram showing a schematic operation example of the PWM signal generation circuit according to the third embodiment of the present invention. Here, for example, the operation as shown in FIG. 10 is performed using the circuit configuration as shown in FIG. In FIG. 10, the oscillation frequency of the PWM signal (PWM1c) is not changed suddenly in one PWM cycle as shown in FIG. 3 or the like, but is changed in stages through a plurality of PWM cycles T1 to T3. ing.

  Specifically, first, the capacitor Cw is charged with the current value | I11 | set for the variable current source ISVc, and then the current value smaller than | I11 | for the variable current source ISVd. In a state where | I12 | is set, discharging is performed from Cw, and subsequently, Cw is charged in a state where a current value | I13 | smaller than | I12 | is set for ISVc. Thereafter, in the current values | I14 |, | I15 |, and | I16 |, the operation of alternately setting the current values having different magnitudes in steps with respect to ISVc and ISVd is repeated, so that the triangular wave (Vrmp1c ) Is changed stepwise toward the target oscillation frequency. In this example, the oscillation frequency f1 → f2 (<f1) → f3 (<f2) is changed step by step with the transition of the PWM cycle T1 → T2 → T3.

  Even in such an operation, the on-duty in the PWM signal (PWM1c) can be kept constant regardless of the change of the oscillation frequency, as in the case of each of the previous embodiments. As a result, the same effect as in the first embodiment can be obtained. Furthermore, since the oscillation frequency is changed stepwise here, the noise component of the output voltage signal Vo13 obtained by demodulating the PWM signal (PWM1c) can be reduced as compared with the case where the oscillation frequency is changed once. It becomes possible.

  That is, the output voltage signal Vo13 has a predetermined ripple component around the constant average voltage Vc13 in each PWM cycle T1 to T3, and the ripple component increases as the oscillation frequency decreases. Here, when the oscillation frequency is changed stepwise, the fluctuation amount of the ripple component between T1 and T2 is ΔV1, and the fluctuation amount of the ripple component between T2 and T3 is ΔV2. When T1 is changed to T3, the fluctuation amount of the ripple component can be (ΔV1 + ΔV2). Since the noise component is generated by the fluctuation amount in addition to the ripple component itself, it is beneficial to reduce the fluctuation amount by the operation as shown in FIG.

  Here, the slope is changed every time the triangular wave (Vrmp1c) rises and falls, and every transition from the fall to the rise. However, for example, the slope can be changed every PWM cycle. Further, it is possible to change the slope not for each PMW cycle but for each of a plurality of PWM cycles, for example.

(Embodiment 4)
<< Operation of PWM signal generation circuit (application example [2]) >>
FIG. 11 is a waveform diagram showing a schematic operation example of the PWM signal generation circuit according to the fourth embodiment of the present invention. Here, for example, the operation as shown in FIG. 11 is performed using the circuit configuration as shown in FIG. The operation of FIG. 11 is substantially the same as the operation of FIG. 3 described above, but here, PWM is performed in a period TT1 in which the variation of the reference voltage Vref input to the PWM signal generation circuit is large and a period TT2 in which the variation is small. The oscillation frequency of the signal (PWM1d) is switched. For example, taking the power supply regulator as shown in FIG. 6 as an example, the period TT1 is generated when the generation operation of the output power supply voltage Vout is started (power supply startup period) or ended (power supply shutdown period), or Vout. This corresponds to a period in which the amount of change in Vref is large, such as when changing the value of V. On the other hand, the period TT2 corresponds to a period in which the amount of change in Vref is small, such as after Vout has reached a predetermined target value.

  In the period TT1, the current values of the variable current sources ISVc and ISVd are both set to | I21 |, and a triangular wave (Vrmp1d) is generated in this state. Thereafter, when the period TT2 is entered, the current values of ISVc and ISVd are both set to | I22 |, which is smaller than | I21 |, and a triangular wave (Vrmp1d) is generated in this state. As a result, the PWM signal (PWM1d) is generated at the oscillation frequency f11 in the period TT1, and the PWM signal (PWM1d) is generated at the oscillation frequency f12 lower than the f11 in the period TT2.

  In the period TT1, for example, since it is required to shorten the length of the period, the oscillation frequency f11 is set high. As a result, the resolution and responsiveness of the control by the PWM signal (PWM1d) can be improved, and as a result, the target stable state can be quickly converged. On the other hand, in the period TT2, since the reduction of power consumption is particularly required, the oscillation frequency f12 is set low. As a result, so-called switching loss can be reduced. Even in such an operation, the on-duty in the PWM signal (PWM1d) can be kept constant regardless of the change of the oscillation frequency, as in the case of each of the previous embodiments. As a result, the same effect as in the first embodiment can be obtained.

(Embodiment 5)
<< Configuration of Triangular Wave Generation Circuit (Modification) >>
FIG. 12 is a circuit diagram showing a configuration example of the triangular wave generation circuit in the PWM signal generation circuit according to the fifth embodiment of the present invention. The triangular wave generation circuit TWG1 shown in FIG. 2 is not necessarily limited to the circuit system, and can be realized by using various circuit systems as shown in FIG. 12, for example. A triangular wave generation circuit TWG3 shown in FIG. 12 has a circuit system that generates a triangular wave by combining a Schmitt circuit including a comparison circuit CMP1 and resistors R1 to R3 and an integration circuit including a resistor R4 and a capacitor C2.

  In FIG. 12, for example, when the output of the comparison circuit CMP1 is at the level of the power supply voltage VDD, the charging operation of the capacitor C2 is performed in a state where the current value is limited by the resistor R4. The charging operation is performed until the output voltage Vrmp3 of the capacitor C2 reaches the upper limit value determined by the resistance voltage division between the parallel resistor including the resistor R1 and the resistor R3 and the resistor R2 connected in series to the parallel resistor. When the upper limit value is reached, the output of CMP1 becomes the level of the ground power supply voltage GND, and the discharging operation of C2 is performed in a state where the current value is limited by R4. The discharge operation is performed until Vrmp3 reaches a lower limit value (<upper limit value) determined by a resistance partial pressure between R1 and a parallel resistance composed of R2 and R3. When the lower limit is reached, the output of CMP1 becomes the VDD level, and thereafter the same operation is repeated. In this case, since the current value of the discharge current and the charging current changes according to the voltage value of Vrmp3, illustration is omitted. However, for example, a circuit combining a Schmitt circuit and an integration circuit using a so-called operational amplifier may be used.

  When such a triangular wave generation circuit is used, it is possible to change the oscillation frequency of the triangular wave (Vrmp3) by using one or both of the resistor R4 and the capacitor C2 as a variable element. Therefore, the control circuit CTL3 switches the set value of the variable element according to the current value setting signal (frequency setting signal) ISET. In this case, for example, the setting value change and validation of the variable element are started simultaneously from the time point of the switching timing TS11 in FIG. Therefore, when there is a problem with the delay time from the time of this switching timing until it is actually effective, it is desirable to use the operation method and circuit method as described in FIGS.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  For example, here, a power supply regulator device and a class D amplifier device are shown as an example of a semiconductor device provided with a PWM signal generation circuit. However, the device is of course not limited to the device, and includes various motor drive devices. This is applicable to various devices. Further, the power supply regulator device is not limited to the step-down DC-DC converter as shown in FIG. 6, but may be a step-up DC-DC converter, an AC-DC converter, a DC-AC converter (so-called inverter), or the like. . Similarly, the class D amplifier device is not limited to the half-bridge configuration as shown in FIG. 7, but may be a full-bridge (H-bridge) configuration or the like.

  In the third and fourth embodiments, the example using the triangular wave according to the first embodiment has been described. Of course, the triangular wave according to the second embodiment (so-called sawtooth wave) can also be used. Furthermore, it is of course possible to use Embodiments 3 and 4 in combination. That is, when the oscillation frequency is changed according to the start-up state of the power supply as in the fourth embodiment, it is also beneficial to change the oscillation frequency step by step as in the third embodiment.

BF buffer circuit C capacitance CMP comparison circuit CTL control circuit D diode DAMP class D amplifier device DCDC DC-DC converter DRVBK driver circuit block EA error amplifier circuit GND ground power supply voltage IREFG reference current source ISET current value setting signal (frequency setting signal)
ISV variable current source L coil LD load circuit LPF low pass filter MN NMOS transistor MP PMOS transistor PWM, PWM 'PWM signal PWM CMP PWM comparison circuit PWMG PWM signal generation circuit Q switch R resistor SW switch TS switching timing TT period TWG triangular wave generation circuit VAC AC signal source VCC, VDD, VEE Power supply voltage Vaci, Vaco AC signal Vc, Vc 'Average voltage Vh Upper limit voltage Vl Lower limit voltage Vo, Vo' Output voltage signal Vout Output power supply voltage Vref Reference voltage Vrmp Output voltage Vset Setting voltage

Claims (12)

A waveform generation circuit for generating a triangular wave;
A PWM comparison circuit that compares the voltage level of the triangular wave with the voltage level of the input signal and generates a PWM signal having a duty according to the voltage level of the input signal;
The waveform generation circuit generates a PWM signal for changing an oscillation frequency of the triangular wave by changing a slope of at least one of a rising edge and a falling edge in the triangular wave with a transition timing of rising and falling edges in the triangular wave as a starting point circuit. The PWM signal generation circuit according to claim 1,
The waveform generation circuit includes:
When changing the rising slope in the triangular wave, after changing the setting of the rising slope while the triangular wave is falling, the setting change is started from the transition timing from falling to rising in the triangular wave. Enable,
When changing the falling slope in the triangular wave, after changing the setting of the falling slope while the triangular wave is rising, the setting change is started from the transition timing from rising to falling in the triangular wave. PWM signal generation circuit that validates as The PWM signal generation circuit according to claim 2, wherein
The waveform generation circuit includes:
A first current source and a first switch inserted in series between the first power supply voltage and the first node;
A second current source and a second switch inserted in series between the second power supply voltage having a voltage level different from that of the first power supply voltage and the first node;
A capacitor having one end coupled to the first node;
A first voltage detection circuit that outputs a first detection signal when the voltage level of the first node reaches a predetermined first set voltage;
A second voltage detection circuit that outputs a second detection signal when the voltage level of the first node reaches a predetermined second setting voltage that is different from the first setting voltage;
A control circuit,
The first current source is a variable current source;
The control circuit includes:
(A) controlling the first switch on and the second switch off with the first current source set to the first current;
(B) After the step (a), when the first detection signal is output, the first switch is turned off with the second current source set to the second current, and the second switch is turned on. Setting the first current source to a third current having a current value different from that of the first current;
(C) After the step (b), when the second detection signal is output, the first switch is turned on with the first current source set to the third current, and the second switch A PWM signal generation circuit that executes a step of controlling the power off. The PWM signal generation circuit according to claim 3.
Further, the second current source is a variable current source,
When the first detection signal is output after the step (c), the control circuit further executes a step (d),
In the step (c), the second current source is further set to a fourth current having a current value different from that of the second current,
In the step (d), a PWM signal generation circuit that controls the first switch to be turned off and the second switch to be turned on in a state where the second current source is set to the fourth current. The PWM signal generation circuit according to claim 2, wherein
The waveform generation circuit includes:
A first current source and a first switch inserted in series between the first power supply voltage and the first node;
A second switch inserted between a second power supply voltage having a voltage level different from that of the first power supply voltage and the first node;
A capacitor having one end coupled to the first node;
A first voltage detection circuit that outputs a first detection signal when the voltage level of the first node reaches a predetermined first set voltage;
A control circuit,
The first current source is a variable current source;
The control circuit includes:
(A) controlling the first switch on and the second switch off with the first current source set to the first current;
(B) After the step (a), when the first detection signal is output, the first switch is turned off and the second switch is turned on in a predetermined period, and the first current is controlled. Setting the source to a second current having a current value different from the first current;
(C) After the step (b), a PWM signal for executing the step of controlling the first switch on and the second switch off with the first current source set to the second current Generation circuit. The PWM signal generation circuit according to claim 1,
The waveform generation circuit uses a third oscillation frequency that is a value between the first oscillation frequency and the second oscillation frequency when changing the oscillation frequency of the triangular wave from the first oscillation frequency to the second oscillation frequency. A PWM signal generation circuit for changing from the first oscillation frequency to the second oscillation frequency via the output cycle of the triangular wave having the third oscillation frequency. A high-side switch coupled between the high-side power supply voltage and the switch node;
A low-side switch coupled between a low-side power supply voltage and the switch node;
A waveform generation circuit for generating a triangular wave;
A PWM comparison circuit that compares the voltage level of the triangular wave with the voltage level of the input signal and generates a PWM signal having a duty according to the voltage level of the input signal;
A drive circuit that complementarily controls on / off of the high-side switch and the low-side switch based on the PWM signal;
The semiconductor device, wherein the waveform generation circuit changes an oscillation frequency of the triangular wave by changing a slope of at least one of rising and falling in the triangular wave with a transition timing of rising and falling in the triangular wave as a starting point. The semiconductor device according to claim 7.
The waveform generation circuit includes:
When changing the rising slope in the triangular wave, after changing the setting of the rising slope while the triangular wave is falling, the setting change is started from the transition timing from falling to rising in the triangular wave. Enable,
When changing the falling slope in the triangular wave, after changing the setting of the falling slope while the triangular wave is rising, the setting change is started from the transition timing from rising to falling in the triangular wave. As a semiconductor device that validates as The semiconductor device according to claim 8.
The waveform generation circuit includes:
A first current source and a first switch inserted in series between the first power supply voltage and the first node;
A second current source and a second switch inserted in series between the second power supply voltage having a voltage level different from that of the first power supply voltage and the first node;
A capacitor having one end coupled to the first node;
A first voltage detection circuit that outputs a first detection signal when the voltage level of the first node reaches a predetermined first set voltage;
A second voltage detection circuit that outputs a second detection signal when the voltage level of the first node reaches a predetermined second setting voltage that is different from the first setting voltage;
A control circuit,
The first current source is a variable current source;
The control circuit includes:
(A) controlling the first switch on and the second switch off with the first current source set to the first current;
(B) After the step (a), when the first detection signal is output, the first switch is turned off with the second current source set to the second current, and the second switch is turned on. Setting the first current source to a third current having a current value different from that of the first current;
(C) After the step (b), when the second detection signal is output, the first switch is turned on with the first current source set to the third current, and the second switch And a step of controlling to turn off the semiconductor device. The semiconductor device according to claim 8.
The waveform generation circuit includes:
A first current source and a first switch inserted in series between the first power supply voltage and the first node;
A second switch inserted between a second power supply voltage having a voltage level different from that of the first power supply voltage and the first node;
A capacitor having one end coupled to the first node;
A first voltage detection circuit that outputs a first detection signal when the voltage level of the first node reaches a predetermined first set voltage;
A control circuit,
The first current source is a variable current source;
The control circuit includes:
(A) controlling the first switch on and the second switch off with the first current source set to the first current;
(B) After the step (a), when the first detection signal is output, the first switch is turned off and the second switch is turned on in a predetermined period, and the first current is controlled. Setting the source to a second current having a current value different from the first current;
(C) After the step (b), a step of controlling the first switch to be turned on and the second switch to be turned off with the first current source set to the second current. . The semiconductor device according to claim 7.
The waveform generation circuit uses a third oscillation frequency that is a value between the first oscillation frequency and the second oscillation frequency when changing the oscillation frequency of the triangular wave from the first oscillation frequency to the second oscillation frequency. A semiconductor device that changes from the first oscillation frequency to the second oscillation frequency via an output cycle of the triangular wave having the third oscillation frequency. The semiconductor device according to claim 7.
The semiconductor device is a power supply regulator,
The waveform generation circuit determines an oscillation frequency of the triangular wave as a fourth oscillation frequency during a period when the output voltage of the power supply regulator is raised from the level of the ground power supply voltage toward a predetermined target value, A semiconductor device that sets the oscillation frequency of the triangular wave to a fifth oscillation frequency lower than a fourth oscillation frequency in a period after the output voltage reaches the target value.

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