JP2013153122A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of suppressing peeling of a support body and a wiring circuit board when the wiring circuit board is being formed on the support body, and peeling the support body and the wiring circuit board after a semiconductor chip is mounted on the wiring circuit board.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: preparing a support body 1 having a peeling layer 5; forming a wiring circuit board 2 on the peeling layer of the support body; mounting a semiconductor chip 3 on the wiring circuit board; and peeling the support body together with the peeling layer with the surface on the side opposite to the support body in the peeling layer as an interface after mounting the semiconductor chip. The peeling layer includes an imido group and a diamine-derived constituent unit having an ether structure at at least a part thereof.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, semiconductor elements composed of various semiconductor materials (hereinafter also simply referred to as “elements”) such as ICs using silicon semiconductors and organic EL elements using organic semiconductors are usually provided on the wafer substrate surface. Are repeatedly formed in a matrix, and then divided into individual semiconductor chips (also referred to as bare chips) by dicing.

  In recent years, as a method of connecting (mounting) a chip to an external wiring circuit board, a method of connecting the two by associating the conductor portion of the wiring circuit board with the electrode position of the chip (for example, flip chip bonding) has been used. It has become. The external printed circuit board is a package circuit board sealed together with a chip, a general circuit board on which many other elements are mounted, or the like. In addition, a flexible printed circuit board with contacts called an interposer may be interposed between the chip and the package circuit board (Patent Documents 1 and 2).

  Such a flexible printed circuit board such as an interposer is not easy to handle in a manufacturing process such as chip mounting because of its flexible nature. Therefore, conventionally, as shown in Patent Documents 1 and 2, etc., first, a flexible printed circuit board is formed on a metal support board to obtain the wired circuit board having appropriate rigidity, and is handled in the process. A method is used in which chip mounting is performed with improved performance, and the metal support substrate is removed after the chip that is a rigid body is mounted.

  In the state where the chip is mounted on the printed circuit board and the metal support board is removed, the connection with the external conductor (external circuit, etc.) is easier than the bare chip with the electrode pads exposed. It is one semiconductor device provided with a conductor.

JP 2000-349198 A JP 2001-44589 A

  Conventionally, as described above, a flexible printed circuit board is formed on a metal support substrate, and after the chip is mounted, the metal support substrate is removed. Here, the metal support substrate and the printed circuit board are formed as an integral inseparable laminate, and etching is used to remove the metal support substrate after chip mounting. However, if the metal support substrate is removed by etching, the metal support substrate disappears. Therefore, there is a problem that the metal support substrate cannot be reused. In addition, although there has been no particular problem in the past, since there is a process of removing the metal support substrate by etching, the manufacturing process such as application and removal of resist becomes complicated, and the manufacturing cost increases. It is also a problem.

  In order to solve the above-mentioned problems, the present inventors have provided a wiring support board with a metal support layer in a peelable manner (that is, the wiring circuit board is made of the metal support layer on the metal support layer). It has been found that the above problem can be solved by forming the support layer so as to be peelable from the support layer, and a method for manufacturing a semiconductor device having the following configuration (1) has already been invented (for example, JP 2010-2010 A). -141126).

  (1) A method of manufacturing a semiconductor device having a structure in which a semiconductor chip is mounted on a printed circuit board, wherein the printed circuit board having a connecting conductor portion that can be connected to an electrode of the semiconductor chip is made of a metal support. Forming on the layer so as to be peelable from the support layer and so that the connecting conductor is exposed on the upper surface of the wired circuit board; and the connecting conductor and the semiconductor of the wired circuit board A step of connecting a chip electrode and mounting a semiconductor chip on the wiring circuit board; and a step of peeling the metal support layer from the wiring circuit board after the mounting, the metal support layer A method of manufacturing a semiconductor device in which a peeling layer is formed between the wiring circuit board and the wiring circuit board, whereby the wiring circuit board can be peeled from the metal support layer.

  According to the configuration of (1) above, after the chip is mounted on the printed circuit board, the metal support layer can be removed without being etched, and the metal support layer can be reused. Thus, the manufacturing cost can be reduced. In addition, due to the rigidity (stiffness) of the metal support layer, deformation of the printed circuit board directly under the semiconductor chip to be mounted can be prevented.

  When the method for manufacturing a semiconductor device is employed, first, a printed circuit board needs to be formed on a support. However, in the process of forming the printed circuit board, a relatively high temperature thermal history is received a plurality of times. Therefore, higher heat resistance is required for the release layer. Further, after the semiconductor chip is mounted on the printed circuit board, a peeling property is required.

  The inventors of the present application have found that the above-mentioned problems can be solved by adopting the following configuration, and have completed the present invention.

That is, the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a structure in which a semiconductor chip is mounted on a printed circuit board,
Preparing a support having a release layer;
Forming a printed circuit board on the release layer of the support;
Mounting a semiconductor chip on the wired circuit board;
After the mounting, the step of peeling the support together with the release layer, using the surface of the release layer opposite to the support as an interface,
The release layer has a structural unit derived from a diamine having an imide group and at least partially having an ether structure.

According to the said structure, since a peeling layer has an imide group, it is excellent in heat resistance. Whether or not the release layer has an imide group can be confirmed by whether or not a spectrum having an absorption peak at 1400 to 1500 cm ⁻¹ exists in a FT-IR (fourier transform infrared spectroscopy) spectrum. That is, when a spectrum having an absorption peak at 1400-1500 cm ⁻¹ is present, it can be determined that it has an imide group.

Moreover, since the said peeling layer has the structural unit derived from the diamine which has an ether structure, when a peeling layer is heated, a shearing adhesive force can be reduced. With respect to this phenomenon, the present inventors presume that the ether structure is detached from the resin constituting the release layer when heated, and the shear adhesive force is reduced due to the removal.
Whether or not the release layer has a diamine having an ether structure can be confirmed by whether or not there is a spectrum having an absorption peak at 2700 to 3000 cm ⁻¹ in a Fourier transform infrared spectroscopy (FT-IR) spectrum. That is, when a spectrum having an absorption peak at 2700 to 3000 cm ⁻¹ exists, it can be determined that the diamine has an ether structure.
Note that the ether structure is detached from the resin constituting the release layer, for example, by comparing FT-IR (Fourier Transform Infrared Spectroscopy) spectra before and after heating at 300 ° C. for 30 minutes, 2800 to 3000 cm. ^It can be confirmed that the spectrum of ⁻¹ decreases before and after heating.

  Thus, according to the said structure, a peeling layer has higher heat resistance, and has peelability at a higher temperature. As a result, it is possible to prevent the support and the printed circuit board from being peeled off while the printed circuit board is formed on the support, and to peel off after mounting the semiconductor chip on the printed circuit board. Can do.

In the above structure, the structural unit derived from the diamine having an ether structure preferably has a glycol skeleton or a glycol skeleton derived from a diamine having an alkylene glycol. When the structural unit derived from the diamine having an ether structure has a glycol skeleton or a glycol skeleton derived from a diamine having an alkylene glycol, it exhibits better peelability when heated.
Whether or not the release layer has a diamine having a glycol skeleton can be confirmed by whether or not a spectrum having an absorption peak at 2700 to 3000 cm ⁻¹ exists in the FT-IR spectrum. That is, when a spectrum having an absorption peak at 2700 to 3000 cm ⁻¹ exists, it can be determined that the diamine has a glycol skeleton.
In particular, whether or not the release layer has a diamine having a glycol skeleton derived from a diamine having an alkylene glycol is confirmed by whether or not a spectrum having an absorption peak at 2700 to 3000 cm ⁻¹ exists in the FT-IR spectrum. it can.

  In the above structure, the release layer is composed of a polyimide resin obtained by imidizing polyamic acid obtained by reacting an acid anhydride, a diamine having an ether structure, and a diamine having no ether structure. The mixing ratio of the diamine having the ether structure and the diamine not having the ether structure when the acid anhydride, the diamine having the ether structure, and the diamine not having the ether structure are reacted, The molar ratio is preferably in the range of 100: 0 to 10:90. The mixing ratio of the diamine having the ether structure and the diamine not having the ether structure when the acid anhydride, the diamine having the ether structure, and the diamine not having the ether structure are reacted is a molar ratio. When the ratio is in the range of 100: 0 to 10:90, the thermal peelability at high temperature is excellent.

  In the above configuration, the molecular weight of the diamine having the ether structure is preferably in the range of 200 to 5,000. The molecular weight of the diamine having an ether structure is a value (weight average molecular weight) measured by GPC (gel permeation chromatography) and calculated in terms of polystyrene.

  According to the present invention, while forming the printed circuit board on the support, the support and the printed circuit board can be prevented from peeling, and after mounting the semiconductor chip on the printed circuit board, A method for manufacturing a semiconductor device that can be easily peeled can be provided.

It is a cross-sectional schematic diagram for demonstrating the outline of the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the outline of the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the outline of the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. FIG. 4 is a schematic cross-sectional view for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4 is a schematic cross-sectional view for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4 is a schematic cross-sectional view for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4 is a schematic cross-sectional view for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4 is a schematic cross-sectional view for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4 is a schematic cross-sectional view for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4 is a schematic cross-sectional view for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4 is a schematic cross-sectional view for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG. 3.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. 1 to 3 are schematic cross-sectional views for explaining an outline of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Below, the outline of the manufacturing method of the semiconductor device concerning this embodiment is explained first. Note that the terms “upper surface”, “lower surface”, and the like used in the present invention are only for explaining the positional relationship between layers, and are the actual vertical postures of the printed circuit board and the semiconductor device. It is not intended to limit.

  The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having a structure in which a semiconductor chip is mounted on a printed circuit board, the step of preparing a support having a release layer, and the support A step of forming a wiring circuit board on the release layer, a step of mounting a semiconductor chip on the wiring circuit board, and after the mounting, the surface of the release layer opposite to the support is used as an interface. And a step of peeling the support together with the release layer, wherein the release layer has a structural unit derived from a diamine having an imide group and at least partially having an ether structure.

  In the manufacturing method, first, a support 1 having a release layer 5 is prepared (see FIG. 1). Next, the printed circuit board 2 having the connecting conductor portion 21 that can be connected to the electrode 31 of the semiconductor chip 3 is formed on the release layer 5 so that the connecting conductor portion 21 is exposed on the upper surface of the printed circuit board 2. To do. The printed circuit board 2 has an external connection conductor 22 for electrical connection to the outside on the release layer 5 side. Although FIG. 1 shows the case where the connecting conductor portion 21 is convexly exposed on the upper surface of the printed circuit board 2, in the present invention, the connecting conductor portion is exposed on the upper surface of the printed circuit board. The upper surface of the connecting conductor portion may be flush with the upper surface of the printed circuit board.

  Next, as shown in FIG. 2, the connection conductor portion 21 of the wired circuit board 2 and the electrode 31 of the semiconductor chip 3 are connected, and the semiconductor chip 3 is mounted on the wired circuit board 2. In FIG. 2, the protrusions of the connecting conductor portion 21 and the electrode 31 after mounting are omitted.

  Next, as shown in FIG. 3, the support 1 is peeled together with the release layer 5 with the surface of the release layer 5 opposite to the support 1 as an interface. Thereby, the semiconductor device 4 in which the semiconductor chip 3 is mounted on the printed circuit board 2 is obtained. In addition, you may give the process of giving a solder ball with respect to the printed circuit board 2 which peeled the support body 1. FIG.

  The outline of the semiconductor device manufacturing method according to the present embodiment has been described above. Hereinafter, an example of the semiconductor device manufacturing method according to the present embodiment will be described in detail with reference to FIGS. 4 to 11 are schematic cross-sectional views for explaining in detail an example of a method for manufacturing the semiconductor device shown in FIG.

(Preparation of support having release layer)
First, the support body 1 is prepared (refer FIG. 4). The support 1 preferably has a certain strength or more.

  Although it does not specifically limit as the support body 1, Metal wafers, such as compound wafers, such as a silicon wafer, a SiC wafer, and a GaAs wafer, a glass wafer, SUS, 6-4 Alloy, Ni foil, Al foil, etc. are mentioned. In the case of adopting a round shape in plan view, a silicon wafer or a glass wafer is preferable. Moreover, when it is a rectangle by planar view, a SUS board or a glass plate is preferable.

  Examples of the support 1 include low density polyethylene, linear polyethylene, medium density polyethylene, high density polyethylene, ultra low density polyethylene, random copolymer polypropylene, block copolymer polypropylene, homopolyprolene, polybutene, and polymethylpentene. Such as polyolefin, ethylene-vinyl acetate copolymer, ionomer resin, ethylene- (meth) acrylic acid copolymer, ethylene- (meth) acrylic acid ester (random, alternating) copolymer, ethylene-butene copolymer, Ethylene-hexene copolymer, Polyester such as polyurethane, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyetheretherketone, polyimide, polyetherimide, polyamide, wholly aromatic polyamid , Polyphenyl sulphates id, aramid (paper), can be glass, glass cloth, fluorine resin, polyvinyl chloride, polyvinylidene chloride, cellulose resin, silicone resin, also possible to use paper or the like.

  The support 1 may be used alone or in combination of two or more. Although the thickness of a support body is not specifically limited, For example, it is about 10 micrometers-about 20 mm normally.

  Next, the release layer 5 is formed on the support 1.

  The release layer 5 is composed of a polyimide resin having a structural unit derived from a diamine having an imide group and at least partially having an ether structure.

  The polyimide resin can be generally obtained by imidizing (dehydrating and condensing) a polyamic acid that is a precursor thereof. As a method for imidizing the polyamic acid, for example, a conventionally known heat imidization method, azeotropic dehydration method, chemical imidization method and the like can be employed. Of these, the heating imidization method is preferable. When the heat imidization method is employed, it is preferable to perform heat treatment under a nitrogen atmosphere or an inert atmosphere such as a vacuum in order to prevent deterioration of the polyimide resin due to oxidation.

  The polyamic acid is charged in an appropriately selected solvent such that an acid anhydride and a diamine (including both a diamine having an ether structure and a diamine not having an ether structure) have a substantially equimolar ratio. Can be obtained by reaction.

The polyimide resin has a structural unit derived from a diamine having an ether structure. The diamine having an ether structure is not particularly limited as long as it is a compound having an ether structure and having at least two terminals having an amine structure. Among the diamines having an ether structure, a diamine having a glycol skeleton is preferable. When the polyimide resin has a structural unit derived from a diamine having an ether structure, in particular, a structural unit derived from a diamine having a glycol skeleton, heating the release layer 5 may reduce the shear adhesive force. it can.
The fact that the ether structure or the glycol skeleton is detached from the resin constituting the release layer 5 is, for example, an FT-IR (Fourier Transform Infrared Spectroscopy) spectrum before and after heating at 300 ° C. for 30 minutes. And the spectrum of 2800 to 3000 cm ⁻¹ can be confirmed by decreasing before and after heating.

  Examples of the diamine having a glycol skeleton include a polypropylene glycol structure and a diamine having one amino group at each end, a polyethylene glycol structure, and one amino group at each end. Examples thereof include a diamine having a polytetramethylene glycol structure and a diamine having an alkylene glycol such as a diamine having one amino group at each end. Moreover, the diamine which has two or more of these glycol structures and has one amino group in both the ends can be mentioned.

  The molecular weight of the diamine having an ether structure is preferably in the range of 100 to 5000, and more preferably 150 to 4800. When the molecular weight of the diamine having an ether structure is in the range of 100 to 5000, it is easy to obtain the release layer 5 having high adhesive strength at low temperatures and exhibiting peelability at high temperatures.

  In the formation of the polyimide resin, a diamine having no ether structure can be used in combination with a diamine having an ether structure. Examples of the diamine having no ether structure include aliphatic diamines and aromatic diamines. By using a diamine having no ether structure in combination, the adhesion with the adherend can be controlled. The mixing ratio of the diamine having an ether structure and the diamine having no ether structure is preferably in the range of 100: 0 to 10:90, more preferably 100: 0 to 20: in terms of molar ratio. 80, more preferably 99: 1 to 30:70. When the mixing ratio of the diamine having an ether structure and the diamine having no ether structure is within a range of 100: 0 to 10:90 in terms of molar ratio, the thermal peelability at a high temperature is excellent.

  Examples of the aliphatic diamine include ethylenediamine, hexamethylenediamine, 1,8-diaminooctane, 1,10-diaminodecane, 1,12-diaminododecane, 4,9-dioxa-1,12-diaminododecane, , 3-bis (3-aminopropyl) -1,1,3,3-tetramethyldisiloxane (α, ω-bisaminopropyltetramethyldisiloxane) and the like. The molecular weight of the aliphatic diamine is usually 50 to 1,000,000, preferably 100 to 30,000.

  Examples of the aromatic diamine include 4,4′-diaminodiphenyl ether, 3,4′-diaminodiphenyl ether, 3,3′-diaminodiphenyl ether, m-phenylenediamine, p-phenylenediamine, and 4,4′-diaminodiphenylpropane. 3,3′-diaminodiphenylmethane, 4,4′-diaminodiphenyl sulfide, 3,3′-diaminodiphenyl sulfide, 4,4′-diaminodiphenyl sulfone, 3,3′-diaminodiphenyl sulfone, 1,4-bis (4-aminophenoxy) benzene, 1,3-bis (4-aminophenoxy) benzene, 1,3-bis (3-aminophenoxy) benzene, 1,3-bis (4-aminophenoxy) -2,2- Dimethylpropane, 4,4'-diaminobenzophenone, etc. It is. The molecular weight of the aromatic diamine is usually 50 to 1000, preferably 100 to 500. The molecular weight of the aliphatic diamine and the molecular weight of the aromatic diamine are values measured by GPC (gel permeation chromatography) and calculated in terms of polystyrene (weight average molecular weight).

  Examples of the acid anhydride include 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride, 2,2 ′, 3,3′-biphenyltetracarboxylic dianhydride, 3,3 ′, 4,4′-benzophenone tetracarboxylic dianhydride, 2,2 ′, 3,3′-benzophenone tetracarboxylic dianhydride, 4,4′-oxydiphthalic dianhydride, 2,2-bis (2, 3-dicarboxyphenyl) hexafluoropropane dianhydride, 2,2-bis (3,4-dicarboxyphenyl) hexafluoropropane dianhydride (6FDA), bis (2,3-dicarboxyphenyl) methane dianhydride Bis (3,4-dicarboxyphenyl) methane dianhydride, bis (2,3-dicarboxyphenyl) sulfone dianhydride, bis (3,4-dicarboxyphenyl) sulfone Anhydride, pyromellitic dianhydride, ethylene glycol bis trimellitic dianhydride and the like. These may be used alone or in combination of two or more.

  Examples of the solvent for reacting the acid anhydride with the diamine include N, N-dimethylacetamide, N-methyl-2-pyrrolidone, N, N-dimethylformamide, and cyclopentanone. These may be used alone or in combination. Further, in order to adjust the solubility of raw materials and resins, a nonpolar solvent such as toluene or xylene may be appropriately mixed and used.

The release layer 5 is preferably 0.25 kg / 5 × 5 mm or more, and preferably 0.30 kg / 5 × 5 mm or more in terms of shear adhesion to the silicon wafer at the temperature after being held at 200 ° C. for 1 minute. More preferably, it is more preferably 0.50 kg / 5 × 5 mm or more. In addition, the release layer 5 has a shear adhesive force with respect to the silicon wafer at the temperature after being held for 3 minutes at any temperature in the temperature range higher than 200 ° C. and lower than 500 ° C. is less than 0.25 kg / 5 × 5 mm. Is preferably less than 0.10 kg / 5 × 5 mm, and more preferably less than 0.05 kg / 5 × 5 mm. After holding at 200 ° C. for 1 minute, the shear adhesive strength to the silicon wafer at that temperature is 0.25 kg / 5 × 5 mm or more, and held for 3 minutes at any temperature in the temperature range above 200 ° C. and below 500 ° C. If the shearing adhesive force to the silicon wafer at the temperature after the treatment is less than 0.25 kg / 5 × 5 mm, the release layer 5 exhibiting release properties at a higher temperature can be obtained. The shear adhesive force of the release layer can be controlled by, for example, the number of functional groups included in the release layer.
Further, the temperature at which the shear adhesion of the release layer to the silicon wafer is less than 0.25 kg / 5 × 5 mm (preferably less than 0.10 kg / 5 × 5 mm, more preferably less than 0.05 kg / 5 × 5 mm). Is not particularly limited as long as it is any temperature in a temperature range exceeding 200 ° C. and 500 ° C. or less, preferably exceeding 220 ° C. and not more than 480 ° C., more preferably exceeding 240 ° C., It is 450 degrees C or less.
In addition, even if the said peeling layer is 200 degrees C or less, if it hold | maintains for a long time, the said shearing adhesive force with respect to a silicon wafer may become less than 0.25 kg / 5x5 mm. Further, even if the release layer is held at a temperature higher than 200 ° C., the shear adhesive force to the silicon wafer may not be less than 0.25 kg / 5 × 5 mm for a short time.
That is, “the shear adhesive force to the silicon wafer at the temperature after holding for 3 minutes at any temperature in the temperature range greater than 200 ° C. and less than 500 ° C. is less than 0.25 kg / 5 × 5 mm” It is an index for evaluating the property, and when “any temperature in a temperature range of greater than 200 ° C. and less than or equal to 500 ° C.” is set, it means that the shear adhesive force to the silicon wafer is immediately less than 0.25 kg / 5 × 5 mm. Not what you want. Further, unless the temperature is set to “any temperature in the temperature range greater than 200 ° C. and less than or equal to 500 ° C.”, this does not mean that peelability is not exhibited.

  The release layer 5 preferably has a weight reduction rate of less than 1% by weight, more preferably less than 0.9% by weight after being immersed in a 3% tetramethylammonium hydroxide aqueous solution for 5 minutes. More preferably, it is less than 8% by weight. Moreover, although the said weight decreasing rate is so preferable that it is small, it is 0 weight% or more and 0.001 weight% or more, for example. If the weight loss after immersion in a 3% tetramethylammonium hydroxide aqueous solution for 5 minutes is less than 1% by weight, the dissolution into the 3% tetramethylammonium hydroxide aqueous solution is small, so solvent resistance (particularly , Solvent resistance to tetramethylammonium hydroxide aqueous solution can be improved. The weight reduction rate of the release layer 5 can be controlled by, for example, the composition of the diamine used (solubility of the diamine in tetramethylammonium hydroxide aqueous solution).

  When the release layer 5 is peeled off after being bonded to a silicon wafer, the amount of increase of particles of 0.2 μm or more on the silicon wafer surface is less than 1000/6 inch wafers before being bonded to the silicon wafer. The number of wafers is preferably less than 900/6 inch wafers, and more preferably less than 800/6 inch wafers. When the amount of particles of 0.2 μm or more on the surface of the silicon wafer when peeled after being bonded to the silicon wafer is less than 1000/6 inch wafers before being bonded to the silicon wafer, Later adhesive residue can be suppressed.

  The release layer 5 preferably has a weight reduction rate of 1.0% by weight or more after being immersed in N-methyl-2-pyrrolidone (NMP) at 50 ° C. for 60 seconds and dried at 150 ° C. for 30 minutes. It is more preferably 1% by weight or more, and further preferably 1.2% by weight or more. Moreover, although the said weight decreasing rate is so preferable that it is large, it is 50 weight% or less and 40 weight% or less, for example. When the weight reduction rate after dipping in N-methyl-2-pyrrolidone (NMP) at 50 ° C. for 60 seconds and drying at 150 ° C. for 30 minutes is 1.0% by weight or more, the release layer 5 is N-methyl- It can be said that it is dissolved in 2-pyrrolidone and sufficiently reduced in weight. As a result, the peeling layer 5 can be easily peeled with N-methyl-2-pyrrolidone. The said weight decreasing rate of the peeling layer 5 can be controlled by the solubility with respect to NMP of a raw material, for example. That is, as the raw material having a higher solubility in NMP is selected, the release layer 5 obtained using the raw material has higher solubility in NMP.

  The release layer 5 is produced, for example, as follows. First, a solution containing the polyamic acid is prepared. Next, the solution is applied on a substrate to a predetermined thickness to form a coating film, and then the coating film is dried under a predetermined condition. Examples of the base material include metal foil such as SUS304, 6-4 alloy, aluminum foil, copper foil, Ni foil, polyethylene terephthalate (PET), polyethylene, polypropylene, fluorine-based release agent, and long-chain alkyl acrylate release agent. A plastic film, paper, or the like whose surface is coated with a release agent such as, can be used. Moreover, it does not specifically limit as a coating method, For example, roll coating, screen coating, gravure coating, spin coat coating etc. are mentioned. As drying conditions, for example, the drying temperature is 50 to 150 ° C. and the drying time is 3 to 30 minutes. Thereby, the peeling layer 5 which concerns on this embodiment is obtained.

  The support 1 having the release layer 5 can be produced by transferring the release layer 5 to the support 1. The support 1 having the release layer 5 may be prepared by directly applying a solution containing polyamic acid to the support 1 to form a coating film, and then drying the coating film under predetermined conditions. .

[Formation of printed circuit board]
Next, the printed circuit board 2 is formed on the release layer 5 of the support 1. Conventionally known circuit board and interposer manufacturing techniques such as a semi-additive method and a subtractive method may be applied to the method for forming a wired circuit board on a support having a release layer. By forming the printed circuit board on the support, the dimensional stability is improved during the manufacturing process, and the handleability of the thin printed circuit board is improved. Hereinafter, an example of a method for forming a printed circuit board will be described.

[Formation of base insulating layer]
As shown in FIG. 5, the base insulating layer 20 a is formed on the release layer 5 of the support 1. The material of the base insulating layer 20a is not particularly limited. For example, polyimide resin, acrylic resin, polyether nitrile resin, polyether sulfone resin, epoxy resin, polyethylene terephthalate resin, polyethylene naphthalate resin, polyvinyl chloride resin, etc. Known synthetic resins, and those resins and synthetic fiber cloths, glass cloths, glass nonwoven cloths, and composite resins of fine particles such as TiO ₂ , SiO ₂ , ZrO ₂ , minerals, and clays. In particular, after peeling the support 1, it is thinner, has higher mechanical strength, and becomes a flexible insulating layer having more preferable electrical characteristics (insulating characteristics, etc.), polyimide resin, epoxy resin, A glass cloth composite epoxy resin is a preferred material. Among them, those having photosensitivity are preferable. The thickness of the base insulating layer 20a is preferably 3 to 50 μm.

  Next, an opening h1 is formed at a position where the external connection conductor portion 22 is to be formed (see FIG. 6). As a method for forming the opening h1, a conventionally known method can be employed. For example, when the base insulating layer 20a is formed using a resin having photosensitivity, the opening h1 is formed by irradiating light through a photomask in which a pattern corresponding to the opening h1 is formed and then developing. be able to. The opening shape is not particularly limited, but a circular shape is preferable, and the diameter can also be set as appropriate, but can be set to, for example, 5 μm to 500 μm.

[Formation of metal film for contact]
Next, a contact metal film 211 is formed in the opening h1. By forming the metal film 211, electrical connection can be performed more favorably and corrosion resistance can be improved. The formation method of the metal film 211 is not particularly limited, but plating is preferable, and the material of the metal film is copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium, etc. These single metals or alloys composed of two or more of these may be mentioned. Among these, preferable materials include gold, tin, nickel, and the like. A preferable example of the metal film includes a two-layer structure in which the base layer is Ni and the surface layer is Au.

[Formation of seed film, lower conductive path, conductor layer]
Next, if necessary, a seed film (metal thin film) 23a for satisfactorily depositing a metal material is formed on the conductor layer 23 and the wall surface of the portion that should be the conduction path 25. The seed film 23a can be formed by sputtering, for example. As a material for the seed film, for example, a single metal such as copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium, or an alloy composed of two or more of these is used. It is done. The thickness of the conductor layer 23 is not particularly limited, but may be appropriately selected within a range of 1 to 500 nm. Further, the conducting path 25 is preferably in a columnar shape, and the diameter thereof is 5 to 500 μm, preferably 5 to 300 μm. Thereafter, a conductor layer 23 and a conduction path 25 having a predetermined wiring pattern are formed. The wiring pattern can be formed by, for example, electrolytic plating. Thereafter, the seed film in the portion without the conductor layer 23 is removed.

  Next, as shown in FIG. 9, the conductor layer 23 is covered with a plating resist r1 (except for a portion where a conduction path is to be formed), and the lower surface of the support 1 is entirely covered with a resist r2. The conductive path 24 is formed by electrolytic plating.

(Formation of adhesive layer)
Next, the plating resists r1 and r2 are removed, and an adhesive layer 20b mainly composed of epoxy and polyimide is formed so as to bury the exposed conductor layer 23 and the conduction path 24. The upper end surface of the conduction path 24 is The adhesive layer is etched with an alkaline solution or the like so as to be exposed on the upper surface of the adhesive layer as a terminal portion (see FIG. 10).

[Formation of metal film on end face of connecting conductor]
Next, as illustrated in FIG. 11, the connecting conductor portion 21 is formed on the upper end surface of the conduction path 24 by, for example, electrolytic plating. The connecting conductor portion 21 can be formed of, for example, a nickel film or a gold film.

[Mounting process, peeling process, dicing]
Next, a chip is mounted on the printed circuit board 2 obtained above (with the support 1 being peelable). Thereafter, the adhesive layer 20b is aged, and further, resin sealing is applied to each chip 3 on the printed circuit board 2. For resin sealing, a sheet-like sealing resin sheet may be used, or a liquid resin sealing material may be used. Thereafter, the support 1 is peeled together with the release layer 5 using the surface of the release layer 5 opposite to the support 1 as an interface. Thereby, the semiconductor device 4 in which the semiconductor chip 3 is mounted on the printed circuit board 2 is obtained. In mounting a chip on the printed circuit board 2 (flip chip connection), an underfill resin may be used between the printed circuit board 2 and the chip. The underfill resin may be a sheet or a liquid. In the above-described embodiment, the case where the resin sealing is performed after the chip is mounted has been described. Instead of the resin sealing, a conventionally known flip chip type semiconductor back film is formed on the chip. It may be used. The flip-chip type semiconductor back film is a film for forming on the back surface of a chip (semiconductor element) flip-chip connected on an adherend, and details are disclosed in, for example, Japanese Patent Application Laid-Open No. 2011-249739. Since it is disclosed, a description thereof is omitted here.
The lower limit of the temperature at the time of the peeling step can be set to 50 ° C., 80 ° C., 100 ° C., 150 ° C., and 180 ° C., for example. Moreover, the upper limit of the temperature at the time of the peeling step is preferably 260 ° C, more preferably 230 ° C, and further preferably 200 ° C. Moreover, although the time maintained under the said temperature conditions in the said peeling process changes according to temperature, 0.05-120 minutes are preferable and 0.1-30 minutes are more preferable.
Note that it is preferable not to be exposed to heat of 260 ° C. or higher in the steps after the mounting step. Thereby, it can suppress that solder etc. melt.

In the method for manufacturing a semiconductor device according to the present invention, a printed circuit board is formed on a support having a release layer (for example, a long support), a plurality of semiconductor chips are mounted on the printed circuit board, and resin sealing is performed. And then cutting to obtain a plurality of semiconductor devices. According to the method for manufacturing a semiconductor device, a printed circuit board for a plurality of semiconductor devices can be formed on one support.
As mentioned above, although the example of the manufacturing method of the semiconductor device which concerns on this embodiment was demonstrated, the manufacturing method of the semiconductor device in this invention is not limited to the example mentioned above, In the range of the summary of this invention, it can change suitably. .

  Hereinafter, preferred embodiments of the present invention will be described in detail by way of example. However, the materials, blending amounts, and the like described in this example are not intended to limit the gist of the present invention only to those unless otherwise limited. The term “parts” means parts by weight.

Example 1
In an atmosphere under a nitrogen stream, 13.41 g of 4,4′-polyetherdiamine (manufactured by Heinzmann, D-4000, molecular weight: 4023.5) in 127.69 g of N, N-dimethylacetamide (DMAc) Diaminodiphenyl ether (DDE, molecular weight: 200.2) 8.51 g and pyromellitic dianhydride (PMDA, molecular weight: 218.1) 10.00 g were mixed and reacted at 70 ° C. to obtain a polyamic acid solution A. Obtained. After cooling to room temperature (23 ° C.), the polyamic acid solution A was applied onto the mirror surface of an 8-inch silicon wafer with a spin coater and dried at 90 ° C. for 20 minutes to obtain a support A with polyamic acid. The support A with polyamic acid was heat-treated at 300 ° C. for 2 hours in a nitrogen atmosphere to form a polyimide film (peeling layer) having a thickness of 30 μm, thereby obtaining a support A with a peeling layer.

(Example 2)
In an atmosphere under a nitrogen stream, polyether diamine (manufactured by Heinzmann, D-2000, molecular weight: 1990.8) 16.20 g, 4,4′- in 135.00 g of N, N-dimethylacetamide (DMAc) Diaminodiphenyl ether (DDE, molecular weight: 200.2) 7.55 g and pyromellitic dianhydride (PMDA, molecular weight: 218.1) 10.00 g were mixed and reacted at 70 ° C. Obtained. After cooling to room temperature (23 ° C), the polyamic acid solution B was applied on a SUS foil (thickness 50 µm) so that the thickness after drying was 30 µm, dried at 90 ° C for 20 minutes, and with polyamic acid A support B was obtained. The support B with polyamic acid was heat-treated at 300 ° C. for 2 hours in a nitrogen atmosphere to form a polyimide film (peeling layer) having a thickness of 30 μm, thereby obtaining a support B with a peeling layer.

(Example 3)
In an atmosphere under a nitrogen stream, polyether diamine (manufactured by Heinzmann, D-400, molecular weight: 422.6), 14.47 g, 4,4′- in 107.17 g of N, N-dimethylacetamide (DMAc). Diaminodiphenyl ether (DDE, molecular weight: 200.2) 2.33 g and pyromellitic dianhydride (PMDA, molecular weight: 218.1) 10.00 g were mixed and reacted at 70 ° C. to obtain a polyamic acid solution C. It was. After cooling to room temperature (23 ° C), the polyamic acid solution C was applied onto a nickel foil (thickness 100 µm) so that the thickness after drying was 50 µm, dried at 90 ° C for 20 minutes, and with polyamic acid A support C was obtained. The support C with polyamic acid was heat-treated at 300 ° C. for 2 hours in a nitrogen atmosphere to form a polyimide film (peeling layer) having a thickness of 50 μm, thereby obtaining a support C with a peeling layer.

(Confirmation of presence of imide group)
The presence of the imide group in the release layer according to the example was confirmed by analyzing the presence of an absorption peak derived from the imide group by FT-IR. As a result, an absorption peak derived from an imide group could be confirmed in the release layer of the example.

(Confirmation of desorption of ether structure by heating)
Confirmation of desorption of the ether structure portion by heating the release layer according to the example was performed by FT-IR. Specifically, FT-IR (Fourer Transform Infrared Spectroscopy) spectra before and after heating at 300 ° C. for 30 minutes are compared, and when the spectrum of 2800 to 3000 cm ⁻¹ decreases before and after heating, the ether structure It was judged that there was partial elimination, and when it was not decreased, it was judged that there was no elimination of the ether structure part. As a result, in the release layer of the example, desorption of the ether structure portion by heating was confirmed.

(Measurement of shear adhesion to silicon wafer)
After a 5 mm square (500 μm thick) silicon wafer chip is placed on a release layer formed on a support (silicon wafer, SUS foil, or glass wafer) and laminated under conditions of 60 ° C. and 10 mm / s The shear adhesive strength between the release layer and the silicon wafer chip was measured using a shear tester (Dage 4000, manufactured by Dage). The conditions for the shear test were as follows. The results are shown in Table 1.
<Condition 1 of shear test>
Stage temperature: 200 ° C
Time from holding on stage to starting shearing adhesive strength measurement: 1 minute Measurement speed: 500 μm / s
Measurement gap: 100 μm
<Condition 2 of shear test>
Stage temperature: 260 ° C
Time from holding on stage to starting shearing adhesive strength measurement: 3 minutes Measurement speed: 500 μm / s
Measurement gap: 100 μm

(Measurement of weight loss when immersed in tetramethylammonium hydroxide aqueous solution)
First, the support body was peeled from the support body with a peeling layer which concerns on an Example. Next, the peeled release layer was cut into a 100 mm square, and its weight was measured. Next, it was immersed in a 3% tetramethylammonium hydroxide aqueous solution (TMAH) at 23 ° C. for 5 minutes. After sufficiently washing with water, drying was performed at 150 ° C. for 30 minutes. Then, the weight was measured and set as the weight after immersion.
The weight reduction rate was determined by the following formula. The results are shown in Table 1.
(Weight reduction rate (% by weight)) = [1-((weight after immersion) / (weight before immersion))] × 100

(Measurement of weight loss when immersed in N-methyl-2-pyrrolidone)
First, the support body was peeled from the support body with a peeling layer which concerns on an Example. Next, the peeled release layer was cut into a 100 mm square, and its weight was measured. Next, it was immersed in N-methyl-2-pyrrolidone (NMP) at 50 ° C. for 60 seconds. After sufficiently washing with water, drying was performed at 150 ° C. for 30 minutes. Then, the weight was measured and set as the weight after immersion.
The weight reduction rate was determined by the following formula. The results are shown in Table 1.
(Weight reduction rate (% by weight)) = [((weight after immersion) / (weight before immersion))-1] × 100

(Adhesive residue evaluation)
First, the support body was peeled from the support body with a peeling layer which concerns on an Example. Next, the release layer of the example was processed to a size of 6 inches in diameter, and was laminated on a wafer of 8 inches in diameter at 60 ° C. and 10 mm / s. Then, it was left for 1 minute and peeled off. Using a particle counter (SFS6200, manufactured by KLA), the number of particles of 0.2 μm or more on the surface of an 8-inch diameter wafer was measured. Further, in comparison with the case before lamination, the case where the amount of increase in particles after peeling was less than 1000/6 inch wafer was evaluated as ◯, and the case where it was 1000 particles / 6 inch or more was evaluated as x. The results are shown in Table 1.

(Peeling temperature)
About the peeling layer which concerns on an Example, it was set as the magnitude | size of 30 mm square, and 10 mm square (thickness: 2 mm) glass was affixed on the peeling layer using the laminator. Using this sample, the glass was heated with a high temperature observation device (product name: SK-5000) manufactured by Sanyo Seiko under the conditions of a heating rate of 4 ° C./min and a measurement temperature of 20 to 350 ° C. The temperature at which the film peels from the release layer was confirmed. The results are shown in Table 1.

(Gas visual temperature)
About the peeling layer which concerns on an Example, it was set as the magnitude | size of 30 mm square, and 10 mm square (thickness: 2 mm) glass was affixed on the peeling layer using the laminator. Using this sample, it was heated with a high-temperature observation device (product name: SK-5000) manufactured by Sanyo Seiko under the conditions of a heating rate of 4 ° C./minute and a measurement temperature of 20 to 350 ° C. The temperature at which smoke was generated was confirmed. The results are shown in Table 1.

(surface hardness)
About the peeling layer which concerns on an Example, the load-unloading test was done by the load 0.5mN using the hardness meter (product name: DUH-210) by Shimadzu Corporation, and the surface hardness was measured. The results are shown in Table 1.

(Dynamic hardness)
For the release layer according to the example, a load-unloading test at a load of 0.5 mN using a hardness meter (product name: DUH-210) manufactured by Shimadzu Corporation and an indenter (trade name: Triangular115, manufactured by Shimadzu Corporation) The dynamic hardness was measured. The results are shown in Table 1.

(result)
The release layer according to the example has a high shear adhesive force to the silicon wafer at the temperature after being held at 200 ° C. for 1 minute, and the shear adhesive force to the silicon wafer at the temperature after being held at 260 ° C. for 3 minutes is Compared with the case after holding at 200 ° C. for 1 minute, it was greatly reduced.

(Manufacturing evaluation of semiconductor devices)
First, a semiconductor device was manufactured as follows.

[Formation of base insulating layer]
An insulating base layer was formed on the support with a release layer of the example. Specifically, a solution containing photosensitive polyimide and polybenzoxazole (PBO) was applied so that the thickness after curing (after imidization) was 10 μm. Then, solvent drying was performed for 10 minutes at 150 degreeC, and it exposed with the predetermined pattern. The exposure amount was 1000 mJ / cm ² with i-line (mercury spectrum line of wavelength 365 nm). Next, post-exposure baking (PEB) was performed at 150 ° C. for 1 hour. Thereafter, development was performed using a 3% aqueous tetramethylammonium hydroxide solution (TMAH) at 50 ° C. for 60 seconds to form a pattern. Thereafter, imidization was performed at 350 ° C. for 3 hours in a nitrogen atmosphere to form a base insulating layer.

[Formation of seed film]
A 30 nm chromium (Cr) film was formed on the base insulating layer by sputtering. Further, an 80 nm copper (Cu) film was formed thereon by sputtering.

[Formation of resist]
Next, a dry film resist was formed. The thickness was 20 μm. Next, exposure was performed to form a predetermined pattern. The exposure amount was 300 mJ / cm ² with i-line (mercury spectrum line having a wavelength of 365 nm). Thereafter, development was performed using an alkaline solution (10% NaOH) at 50 ° C. for 60 seconds, and patterning was performed.

[Formation of wiring]
Copper plating corresponding to the pattern of the formed resist was formed by electrolytic plating. The thickness of the copper plating was 10 μm.

[Resist stripping]
The resist was peeled off by dipping in an alkali solution (10% KOH) at 50 ° C. for 60 seconds.

[Seed film peeling]
At room temperature (23 ° C.), the substrate was immersed in sulfuric acid (10%) for 30 seconds to peel off the Cu sputtered film. Next, it was immersed in an aqueous potassium ferricyanide solution (10%) at 50 ° C. for 60 seconds to peel off the Cr sputtered film.

[Formation of cover coat (adhesive layer)]
The epoxy resin was applied so that the thickness after curing was 10 μm, and dried at 100 ° C. for 10 minutes. Next, exposure was performed to form a predetermined pattern. The exposure amount was 300 mJ / cm ² with i-line (mercury spectrum line having a wavelength of 365 nm). Thereafter, development was performed using an alkaline solution (10% NaOH) at 50 ° C. for 60 seconds, and patterning was performed. Then, it heated at 150 degreeC for 1 hour, and the epoxy resin was hardened.

[Formation of connecting conductor (terminal)]
A nickel (Ni) layer having a thickness of 1 μm and a gold (Au) layer having a thickness of 0.5 μm were formed by plating on the portion where the terminal is to be formed. As a result, a printed circuit board having a connecting conductor (terminal) was obtained.

〔Implementation〕
A semiconductor chip having electrodes corresponding to the formed connecting conductor portions (terminals) was mounted on a printed circuit board. Thereafter, the temperature was maintained at 260 ° C. for 3 minutes.

(Evaluation)
Attempts were made to peel the printed circuit board from the support. With the base insulating layer and the release layer as the interface, the case where the support was able to be peeled off together with the release layer was evaluated as ◯, and the case where the support was not peeled was evaluated as x. The results are shown in Table 1.

DESCRIPTION OF SYMBOLS 1 Support body 2 Wiring circuit board 20a Base insulating layer 20b Adhesive layer 21 Connection conductor part 22 External connection conductor part 23 Conductor layer 23a Seed film 24 Conductive path 25 Conductive path 211 Metal film 3 Semiconductor chip 31 Electrode 4 Semiconductor device 5 Release layer r1 resist r2 resist

Claims (4)

A method of manufacturing a semiconductor device having a structure in which a semiconductor chip is mounted on a printed circuit board,
Preparing a support having a release layer;
Forming a printed circuit board on the release layer;
Mounting a semiconductor chip on the wired circuit board;
After the mounting, the step of peeling the support together with the release layer, using the surface of the release layer opposite to the support as an interface,
The method for manufacturing a semiconductor device, wherein the release layer has a structural unit derived from a diamine having an imide group and having an ether structure at least in part.   2. The method for manufacturing a semiconductor device according to claim 1, wherein the structural unit derived from a diamine having an ether structure has a glycol skeleton or a glycol skeleton derived from a diamine having an alkylene glycol. The release layer is composed of a polyimide resin obtained by imidizing a polyamic acid obtained by reacting an acid anhydride, a diamine having an ether structure, and a diamine not having an ether structure,
The mixing ratio of the diamine having the ether structure and the diamine not having the ether structure when the acid anhydride, the diamine having the ether structure, and the diamine not having the ether structure are reacted is a molar ratio. The method for manufacturing a semiconductor device according to claim 1, wherein the ratio is in a range of 100: 0 to 10:90. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the diamine having an ether structure has a molecular weight in a range of 200 to 5000. 5.

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