JP2013149877A - Wafer processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wafer processing method which never contaminates the inside of a dry etching chamber.SOLUTION: A wafer processing method comprises the steps of: covering a surface of a wafer 11 by an adhesive 27 which cures when an external stimulus is applied thereto; putting the adhesive 27 into a semi-cured state by applying an external stimulus to the adhesive 27; cutting the wafer 11 along an outer peripheral edge of the wafer 11 from the adhesive side with a cutting blade and removing a chamfering part up to at least a depth from a surface of the wafer 11 to a finishing thickness together with the adhesive by cutting; sticking a support substrate onto the adhesive of the wafer 11 and sticking the wafer 11 and the support substrate by completely curing the adhesive 11 by applying an external stimulus thereto; holding the support substrate side of the stuck wafer on a chuck table and thinning the wafer 11 to a prescribed thickness by grinding a rear surface of the wafer; and dry-etching the rear surface of the wafer 11.

Description

  The present invention relates to a wafer processing method, and more particularly to a wafer processing method in which a plurality of electrode posts are embedded.

  In recent years, in order to achieve high integration, high density, miniaturization, and thinning of semiconductor devices, a stacked type in which a plurality of semiconductor chips such as MCP (multi-chip package) and SIP (system in package) are stacked. Semiconductor packages have been proposed.

  Such a stacked semiconductor package is formed by stacking a plurality of semiconductor chips on a package substrate called an interposer. In general, the interposer and the semiconductor chip electrodes, or the electrodes of the stacked semiconductor chips are electrically connected with a gold wire, and then the semiconductor chip is molded and sealed with resin to the interposer. A semiconductor package is manufactured.

  However, in this method, since the gold wire bonded to the electrode of the semiconductor chip protrudes to the outer peripheral surplus region of the semiconductor chip, there is a problem that the package size becomes larger than the semiconductor chip.

  In addition, when the mold is sealed with the resin, the wire wire is deformed to cause a disconnection or a short circuit, or the air remaining in the mold resin expands upon heating and causes damage to the semiconductor package. .

  Therefore, a technique has been proposed in which a through electrode is provided in the semiconductor chip to penetrate the semiconductor chip in the thickness direction and connected to the electrode of the semiconductor chip, and the semiconductor chips are stacked and the through electrodes are joined to each other for electrical connection. (For example, refer to JP-A-2005-136187).

  In this method, a plurality of semiconductor devices are formed on the surface of the silicon wafer, and from each semiconductor device, a plurality of embedded copper electrodes (copper posts) that are connected to the electrodes of the semiconductor device and extend to the back side of the silicon wafer are formed. A so-called TSV (Through Silicon Via) wafer is used.

  The embedded copper electrode has a height equal to or higher than the finished thickness of the semiconductor chip, and the back surface of the wafer is ground and polished by a grinding device to reduce the thickness to the finished thickness of the semiconductor chip, and the embedded copper electrode is formed on the surface of the wafer. Make it appear. Thereafter, by selectively etching only the silicon wafer, the tip of the buried copper electrode protrudes from the back surface of the wafer to form a through electrode.

  When grinding the back surface of the wafer, a surface protection tape or a support substrate as a protective member is attached to the surface of the wafer via an adhesive in order to protect the device formed on the surface of the wafer.

  Generally, an arc-shaped chamfer from the front surface to the back surface is formed on the outer periphery of the semiconductor wafer. When the wafer is thinned by grinding the back surface of the wafer, the chamfered portion is formed by the arc surface and the ground surface. Further, the knife edge may remain dangerous, and the outer periphery may be chipped to deteriorate the quality of the device.

  In order to solve this problem, Japanese Patent Laid-Open No. 2000-173961 discloses that a chamfered portion formed on the outer periphery of a semiconductor wafer is cut to a depth from the surface of the wafer to a finished thickness to partially cut off the chamfered portion (edge A method of manufacturing a semiconductor device is disclosed, in which trimming is performed, and then the wafer is ground back until the wafer thickness becomes thinner than the depth of cut.

JP 2004-107606 A JP 2000-173961 A

  When the edge-trimmed wafer is attached to the support substrate via an adhesive and then the back surface is ground and thinned, the adhesive is exposed on the outer periphery of the back surface of the wafer. Even if the wafer is not edge-trimmed, if the wafer is ground to a thickness smaller than the chamfered portion of the wafer after the wafer is bonded to the support substrate, the adhesive is exposed on the outer periphery of the wafer.

  In order to remove grinding distortion generated by wafer grinding, or in a TSV (Through Silicon Via) wafer in which an electrode post (copper post) is embedded, the head of the electrode post (the end face of the electrode post protrudes from the back surface of the wafer) Therefore, dry etching may be performed on the ground wafer.

  When dry etching is performed on the ground wafer in this way, in the bonded wafer in which the wafer is bonded to the support substrate via the adhesive, the adhesive exposed on the outer periphery of the back surface of the wafer reacts with the dry etching gas. There is a problem that the inside of the dry etching chamber is contaminated.

  The present invention has been made in view of these points, and an object of the present invention is to provide a wafer processing method that does not contaminate the dry etching chamber.

  According to the present invention, there is provided a method for processing a wafer having a chamfered portion on the outer periphery, the coating step of coating the surface of the wafer with an adhesive that cures by applying an external stimulus, and after performing the coating step, A semi-curing step for semi-curing the adhesive to a semi-cured state in which adhesiveness remains by applying an external stimulus to the adhesive, and after performing the semi-curing step, a wafer is cut with a cutting blade from the adhesive side. Cutting along the outer peripheral edge of the wafer, cutting at least the chamfered portion from the wafer surface to the depth of the finished thickness by cutting with the adhesive, and after performing the cutting step, the adhesive of the wafer A support substrate is attached to the substrate, and the external stimulus is applied to completely cure the adhesive to bond the wafer and the support substrate together to form a bonded wafer. A bonding step, and after performing the bonding step, holding the support substrate side of the bonded wafer with a chuck table, grinding the back surface of the wafer, and grinding the wafer to a predetermined thickness; And a step of dry etching the back surface of the wafer after performing the grinding step.

  Preferably, the wafer is composed of a wafer in which a plurality of electrode posts extending from at least the surface to the finished thickness are embedded, and in the grinding step, the back surface of the wafer is ground to reduce the finished thickness to the finished thickness. The electrode post is exposed on the back surface, and in the etching step, the back surface of the wafer is dry-etched to project the end face of the electrode post from the back surface.

  In the wafer processing method of the present invention, after the surface of the wafer is coated with an adhesive, the chamfered portion formed on the outer periphery of the wafer and the adhesive are cut and removed together, so that the back surface of the wafer is ground and the wafer is ground. Even if the thickness of the wafer is reduced, the adhesive is not exposed on the outer periphery of the back side of the wafer. Therefore, even if the wafer is dry etched after grinding, the inside of the dry etching chamber is not contaminated.

It is a surface side perspective view of a semiconductor wafer. 1 is a schematic cross-sectional view of a semiconductor wafer. It is sectional drawing of the state which coat | covered the adhesive agent on the surface of the semiconductor wafer. It is a perspective view which shows the edge trimming process which removes the chamfering part of a wafer with an adhesive agent. It is sectional drawing of the state by which edge trimming was carried out. It is sectional drawing of the bonding wafer which bonded the support substrate to the surface of the wafer via the adhesive agent. It is a perspective view which shows a grinding process. It is sectional drawing of the bonding wafer after completion | finish of a grinding process. It is a partial cross section side view explaining a dry etching process (plasma etching process). It is sectional drawing of the bonding wafer after completion | finish of a dry etching process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, a perspective view of a semiconductor wafer 11 before being ground to a predetermined thickness is shown. The semiconductor wafer shown in FIG. 1 is made of, for example, a silicon wafer having a thickness of 700 μm, and a plurality of streets (division lines) 13 are formed in a lattice shape on the surface 11 a and are partitioned by the plurality of streets 13. A semiconductor circuit 15 such as an IC or LSI is formed in each region.

  The semiconductor wafer 11 configured as described above includes a device region 17 in which the semiconductor circuit 15 is formed and an outer peripheral surplus region 19 that surrounds the device region 17. A notch 21 is formed on the outer periphery of the semiconductor wafer 11 as a mark indicating the crystal orientation of the silicon wafer.

  Referring to FIG. 2, a schematic cross-sectional view of the semiconductor wafer 11 is shown. From each semiconductor circuit 15 formed on the semiconductor wafer 11, a plurality of electrode posts (embedded electrodes) 25 embedded at a depth equal to or larger than the finished thickness t1 of the semiconductor device extend to the back surface 11b side. An arc-shaped chamfer 23 extending from the front surface to the back surface is formed on the outer periphery of the semiconductor wafer 11.

  In the wafer processing method of the present invention, as shown in FIG. 3, first, a coating step of coating the surface 11a of the wafer 11 with an adhesive 27 that is cured by applying an external stimulus is performed. The external stimulus includes heating or ultraviolet irradiation, and a thermosetting resin or an ultraviolet curable resin can be adopted as the adhesive 27.

  After the adhesive 27 is coated on the surface 11 a of the wafer 11, the adhesive 27 is subjected to an external stimulus such as heating or ultraviolet irradiation to semi-cur the adhesive 27 in a semi-cured state in which adhesiveness remains. Perform a curing step. This semi-cured state is a so-called B-stage state, in which the adhesive 27 is incompletely cured.

  After carrying out the semi-curing step, cutting is performed along the outer peripheral edge of the wafer 11 with a cutting blade from the adhesive 27 side, and at least the chamfer 23 from the surface 11a of the wafer 11 to the depth reaching the finished thickness t1 is cut together with the adhesive 27. Then, a cutting step (edge trimming step) to be removed is performed.

  That is, as shown in FIG. 4, the semiconductor wafer 11 with the semi-cured adhesive 27 adhered to the surface 11a is sucked and held by the chuck table 4 of the cutting apparatus 2 with the wafer 11 side down, and the cutting blade 10 Is positioned on the adhesive 27 on the upper side of the chamfered portion 23 of the wafer 11, and a predetermined depth is cut along the outer peripheral edge of the wafer 11 with the cutting blade 10 from the adhesive 27 side, and the cutting blade 10 is rotated at high speed in the direction of arrow B. While the chuck table 4 is rotated at least once in the direction of the arrow A, a part of the chamfered portion 23 together with the adhesive 27 is cut and removed (edge trimming step). A cross-sectional view after completion of the edge trimming step is shown in FIG. Reference numeral 29 indicates a trimmed portion.

  In FIG. 4, reference numeral 6 denotes a cutting unit (cutting means) of the cutting apparatus, in which a spindle (not shown) that is rotationally driven by a motor is accommodated in a spindle housing 8, and a cutting blade 10 is attached to the tip of the spindle. ing.

  After performing the cutting step or the edge trimming step, as shown in FIG. 6, the support substrate 31 is stuck on the adhesive 27 of the wafer 11, and an external stimulus such as heating or ultraviolet irradiation is applied to the adhesive 27. Is completely cured, and a bonding step is performed in which the wafer 11 and the support substrate 31 are bonded together to form a bonded wafer 33. At this time, the adhesive 27 is completely cured while pressing the support substrate 31 against the semi-cured adhesive 27.

  The support substrate 31 is made of glass or silicon wafer. When an ultraviolet curable resin is employed as the adhesive 27, the support substrate 31 needs to be formed from a transparent body such as glass.

  After the bonded wafer 33 is formed, a grinding step for holding the support substrate 31 side of the bonded wafer 33 with a chuck table of a grinding device and grinding the back surface 11b of the wafer 11 to thin the wafer 11 to a predetermined thickness. To implement.

  In this grinding step, as shown in FIG. 7, the support substrate 31 side of the bonded wafer 33 is sucked and held by the chuck table 28 of the grinding device to expose the back surface 11 b of the wafer 11.

  A wheel mount 20 is fixed to the tip of the spindle 18 of the grinding unit 16, and a grinding wheel 22 is detachably attached to the wheel mount 20 with a plurality of screws. The grinding wheel 22 is configured by fixing a plurality of grinding wheels 26 in which diamond abrasive grains having a particle diameter of 2 to 60 μm are hardened by vitrified bond or the like to a free end portion of an annular base 24.

  In the grinding process, while rotating the chuck table 28 in the direction of arrow a at 300 rpm, for example, the grinding wheel 22 is rotated in the same direction as the chuck table 28, that is, in the direction of arrow b at 6000 rpm, for example. It operates to bring the grinding wheel 26 into contact with the back surface 11 b of the wafer 11.

  Then, the grinding wheel 22 is ground and fed by a predetermined amount at a predetermined grinding feed speed (for example, 3 to 5 μm / second), and the wafer 11 is ground. While measuring the thickness of the wafer 11 with a contact-type or non-contact-type thickness measurement gauge (not shown), the wafer 11 is ground until the electrode post 25 is exposed on the back surface 11b of the wafer 11 as shown in FIG.

  When grinding is performed, a grinding strain is generated on the back surface 11b of the wafer 11. Therefore, if necessary, the back surface 11b of the wafer 11 is dried after polishing the back surface 11b of the wafer 11 by CMP (Chemical Mechanical Polishing) or the like. A dry etching step is performed in which the electrode post 15 is exposed from the back surface 11 b of the wafer 11 by etching.

  This dry etching step will be described with reference to FIG. In FIG. 9A, a dry etching apparatus (plasma etching apparatus) 30 includes a housing 32 that defines a plasma etching chamber 34 that is a sealed space. An opening 32 a is provided in the housing 32, and the opening 32 a is opened and closed by a gate 46 that moves up and down by an air cylinder 44.

  An upper electrode 36 and a lower electrode 38 are disposed in the housing 32. The upper electrode 36 is supported by the support portion 44, and the upper electrode 36 moves up and down in the plasma etching chamber 34 by driving the lift driving means 42.

  First, as shown in FIG. 9A, the upper electrode 36 is moved upward, the gate 46 is lowered by the air cylinder 44 to open the opening 32a, and then the bonded wafer 33 is adsorbed by the transfer device 48. Then, the bonded wafer 33 is introduced into the plasma etching chamber 34, and the bonded wafer 33 is placed on the lower electrode 38 as shown in FIG. In this state, the back surface 11b of the wafer 11 is exposed.

  Next, as shown in FIG. 9C, after the transfer device 48 is retracted from the plasma etching chamber 34, the air cylinder 44 is driven to open the opening 32a with a gate 46 fixed to the tip of the piston rod 44a. Close.

  Then, the upper / lower drive means 42 is operated to lower the upper electrode 36, and the distance between the lower surface of the upper electrode 36 and the back surface 11 b of the wafer 11 placed on the lower electrode 38 is suitable for the plasma etching process. It is positioned at a predetermined interelectrode distance. This predetermined interelectrode distance is set to about 10 mm, for example.

  Next, after the inside of the plasma etching chamber 34 is evacuated, a gas supply means (not shown) is operated to use a mixed gas of fluorine-based gas and oxygen gas as a plasma generating gas via a gas supply path (not shown). To supply.

  The plasma generating gas is jetted toward the back surface 11b of the wafer 11 through a gas jetting portion (not shown) formed on the upper electrode 36, and the inside of the plasma etching chamber 34 is maintained at a predetermined gas pressure.

  A high frequency voltage is applied between the upper electrode 36 and the lower electrode 38 from a high frequency power source (not shown) in a state where the mixed gas for generating plasma is supplied in this manner. Thereby, a plasma discharge is generated in the space between the upper electrode 36 and the lower electrode 38, and the back surface 11b of the semiconductor wafer 11 is etched by the action of the active material generated by the plasma discharge.

  As shown in FIG. 10, the plasma etching process is performed until the tip of the electrode post 25 protrudes a predetermined amount from the back surface 11 b of the semiconductor wafer 11. By the plasma etching process, grinding distortion such as micro cracks generated on the back surface 11b of the semiconductor wafer 11 by grinding is removed.

  In addition, the semiconductor wafer 11 can be peeled from the support substrate 31 by immersing the bonded wafer 33 shown in FIG. 10 in a dedicated stripper solution.

  According to the wafer processing method of the present invention, after the surface 11a of the semiconductor wafer 11 is coated with the adhesive 27, the chamfered portion of the wafer 11 is cut from the adhesive 27 side, and a part of the chamfered portion 23 together with the adhesive 27 is removed. Even if the wafer 11 is thinned by grinding the back surface 11b of the wafer 11 after the wafer 11 is bonded to the support substrate via the adhesive 27 in order to remove, the adhesive 27 remains on the outer periphery of the back surface 11b of the wafer 11. There is no exposure.

  In this state, since the bonded wafer 33 is carried into the plasma etching chamber 34 and plasma etching is performed, there is no adhesive exposed on the outer periphery of the back surface of the wafer 11, so that the inside of the plasma etching chamber 34 is not contaminated. .

2 Cutting device 4 Cutting blade 11 Semiconductor wafer 15 Semiconductor circuit 16 Grinding unit 22 Grinding wheel 23 Chamfer 25 Electrode post (embedded electrode)
27 Adhesive 30 Plasma Etching Device 31 Support Substrate 32 Housing 33 Bonding Wafer 34 Plasma Etching Chamber 36 Upper Electrode 38 Lower Electrode

Claims (2)

A wafer processing method having a chamfered portion on the outer periphery,
A coating step of coating the surface of the wafer with an adhesive that cures by applying an external stimulus;
A semi-curing step of applying an external stimulus to the adhesive and semi-curing the adhesive into a semi-cured state in which the adhesive property remains, after performing the coating step;
After performing the semi-curing step, cut along the outer peripheral edge of the wafer with a cutting blade from the adhesive side, and remove at least the chamfered portion from the wafer surface to the depth to the finished thickness by cutting with the adhesive. Cutting step to
After carrying out the cutting step, a support substrate is attached onto the adhesive of the wafer and the external stimulus is applied to completely cure the adhesive, and the wafer and the support substrate are bonded together and attached. A bonding step for forming a laminated wafer;
After performing the bonding step, holding the support substrate side of the bonded wafer with a chuck table, grinding the back surface of the wafer, and grinding the wafer to a predetermined thickness;
An etching step of dry etching the back surface of the wafer after performing the grinding step;
A wafer processing method characterized by comprising: The wafer is composed of a wafer in which a plurality of electrode posts from the surface to the finished thickness are embedded,
In the grinding step, the back surface of the wafer is ground and thinned to the finished thickness, and the electrode post is exposed on the back surface,
The wafer processing method according to claim 1, wherein in the etching step, the back surface of the wafer is dry-etched so that an end surface of the electrode post protrudes from the back surface.

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