JP2013084663A - Bonded soi wafer manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of an SOI wafer having an SOI layer film thickness excellent in in-plane uniformity.SOLUTION: A bonded SOI wafer manufacturing method comprises: bonding a surface of a bond wafer on which an ion implantation layer is formed on the ion implanted side with a surface of a base wafer via an insulation film; subsequently detaching a part of the bond wafer at the ion implantation layer to form a bonded SOI wafer; and subsequently performing planarization. The bonded SOI wafer manufacturing method comprises: performing an RTA treatment on the bonded SOI wafer after the detachment in an atmosphere containing hydrogen gas so as to remove a natural oxide film on a peripheral part of an SOI layer surface and leave a natural oxide film on a central part; and performing the planarization on the bonded SOI wafer on which the natural oxide film is left on the central part such that an in-plane film thickness range of the SOI layer surface becomes 1.5 nm or under.

Description

  The present invention relates to a method for manufacturing a bonded SOI wafer using an ion implantation separation method.

  Recently, as a method of manufacturing bonded wafers, a method of manufacturing bonded wafers by bonding and bonding ion-implanted bond wafers (a technique called ion-implantation separation method: Smart Cut Method (registered trademark)) has been newly introduced. It has begun to attract attention. In this ion implantation separation method, an oxide film is formed on at least one of two wafers, and gas ions such as hydrogen ions and rare gas ions are implanted from the upper surface of one wafer (bond wafer). After a microbubble layer (encapsulation layer) is formed inside, the surface into which the ions are implanted is brought into close contact with the other wafer (base wafer) directly or through an oxide film (insulating film), and then heat treatment (peeling) A bonded wafer having a thin film on the base wafer by peeling off one wafer (bond wafer) into a thin film with a microbubble layer as a cleaved surface by applying a heat treatment, and further bonding by heat treatment (bonding heat treatment) This is a technique for manufacturing (see Patent Document 1). In this method, an SOI wafer having a good mirror surface as a cleavage plane (peeling surface) and a high degree of uniformity in the thickness of a thin film, particularly an SOI layer, can be easily obtained.

  However, when a bonded wafer is manufactured by the ion implantation separation method, there is a damage layer due to ion implantation on the surface of the bonded wafer after separation, and the surface roughness is compared with a mirror surface of a normal product level silicon wafer. And big. Therefore, in the ion implantation separation method, it is necessary to remove such a damaged layer and surface roughness.

  Conventionally, in order to remove the damaged layer and the like, mirror polishing (removal allowance: about 100 nm) called “polishing polish” has been performed in the final step after the bonding heat treatment.

  However, if the thin film on the base wafer is polished including a machining element, the polishing allowance is not uniform. Therefore, the film thickness uniformity achieved to some extent by implantation and peeling of hydrogen ions and the like is achieved. The problem of getting worse arises.

  As a method for solving such a problem, a flattening process for improving the surface roughness by performing a high-temperature heat treatment instead of the touch polish has been performed.

  For example, in Patent Document 2, a heat treatment under a reducing atmosphere containing hydrogen (rapid heating / rapid cooling heat treatment (RTA treatment)) is performed after polishing heat treatment (or after bonding heat treatment) without polishing the surface of the SOI layer. Propose that. Further, in Patent Document 3, after the peeling heat treatment (or after the bonding heat treatment), an oxide film is formed on the SOI layer by heat treatment in an oxidizing atmosphere, and then the oxide film is removed (sacrificial oxidation treatment), and then reduced. It has been proposed to add atmospheric heat treatment (rapid heating / rapid cooling heat treatment (RTA treatment)).

  In Patent Document 4, the SOI wafer after peeling is subjected to sacrificial oxidation treatment after planarization heat treatment in an inert gas, hydrogen gas, or mixed gas atmosphere thereof, thereby planarizing the peeled surface and OSF. Avoidance at the same time.

  As described above, a flattening process for improving the surface roughness by performing a high-temperature heat treatment instead of the touch polish is performed, and at present, the film thickness range of the SOI layer with a diameter of 300 mm (maximum in the plane). An SOI wafer having a film thickness uniformity of 3 nm or less (a value obtained by subtracting the minimum film thickness value from the film thickness value) is obtained at the mass production level by the ion implantation delamination method.

  Patent Document 5 discloses a method for manufacturing an SOI wafer in which two-stage heat treatment of RTA and a batch furnace is performed in order to reduce the surface roughness (short cycle and long cycle) of the peeling surface. Describes a process in which heat treatment is performed at RTA (1000 ° C. to melting point or less, 1 to 300 seconds) and Ar annealing is performed in a batch furnace.

  Furthermore, in Patent Document 6, in order to reduce the concave defects in the SOI layer, bonding is performed by ozone cleaning after peeling, heat treatment at RTA (1100 to 1250 ° C.) in a hydrogen-containing atmosphere, sacrificial oxidation treatment, and Ar annealing. A method for manufacturing a wafer is described.

JP-A-5-211128 Japanese Patent Laid-Open No. 11-307472 Japanese Patent Application Laid-Open No. 2000-124092 WO2003 / 009386 Publication WO2001 / 8000 publication JP 2009-32972 A

  With the recent low power consumption, miniaturization, and high functionality of semiconductor devices, the SOI layer thickness uniformity is the conventional in-plane film thickness range (the value obtained by subtracting the minimum film thickness from the maximum in-plane film thickness). ) Of about 3 nm is not necessarily sufficient, and further improvement of the in-plane film thickness range is required.

  When an SOI wafer is manufactured by an ion implantation separation method, there are various methods for planarization after the SOI layer is peeled as described above. Typical processes include polishing (touch polishing), sacrificial oxidation treatment, heat treatment, etching, and the like.

  In addition, even when heat treatment is performed at a high temperature for a long time in an inert gas atmosphere, which may be performed as a process that does not aim to reduce the thickness, such as Ar annealing, it is actually a process in which some SOI layer is removed. It has become. In particular, when Ar annealing is performed in a vertical heat treatment furnace, the SOI film thickness at the periphery of the wafer becomes thin, and the in-plane uniformity is deteriorated.

  On the other hand, when flattening is performed by polishing, there is a phenomenon that only the peripheral part of the wafer called sagging is thinned, and a phenomenon that only the peripheral part of the wafer called sacrificial is thickened, which deteriorates the in-plane uniformity of the SOI layer. . In addition, as a sacrificial oxidation process (a process for performing thermal oxidation and oxide film removal), when the thermal oxidation is processed in a vertical furnace, there may be a case where a concentric in-plane film thickness distribution is present, and the surface of the SOI layer This is a cause of worsening the uniformity.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing an SOI wafer in which the in-plane uniformity of the film thickness of the SOI layer after the planarization process is further improved.

The present invention has been made in order to solve the above-described problem, and at least one kind of gas ion of hydrogen ion or rare gas ion is ion-implanted from the surface of a bond wafer made of a silicon single crystal. An ion implantation layer is formed on the surface of the bond wafer and the surface of the base wafer and the surface of the base wafer are bonded together via an insulating film, and then a part of the bond wafer is peeled off by the ion implantation layer. A bonded SOI wafer manufacturing method in which a bonded SOI wafer having an SOI layer made of a thin film of the bond wafer is fabricated on the base wafer, and then a planarization process for planarizing the release surface is performed. ,
The bonded SOI wafer after peeling is subjected to an RTA process in an atmosphere containing hydrogen gas so that the natural oxide film at the periphery of the SOI layer surface is removed and the natural oxide film at the center remains. A bonded SOI wafer comprising: a bonded SOI wafer having a natural oxide film remaining in a central portion; wherein the planarization process is performed so that an in-plane film thickness range of the SOI layer is 1.5 nm or less. A manufacturing method is provided.

  With such a manufacturing method, in the planarization process of the SOI layer after peeling, the deterioration of the in-plane uniformity of the SOI layer thickness is suppressed, and the in-plane uniformity of the SOI layer thickness is excellent. A bonded SOI wafer can be manufactured. In particular, a bonded SOI wafer having an in-plane film thickness range after planarization of the SOI layer of 1.5 nm or less can be manufactured.

  As the planarization process, at least one of at least one of a polishing process, a sacrificial oxidation process, and a heat treatment in an inert gas atmosphere can be performed.

  In the heat treatment using an inert gas, for example, Ar atmosphere, since the atmosphere gas flow is better in the peripheral portion of the wafer by performing in a vertical furnace, the film thickness tends to be thinner than the central portion of the wafer. In CMP (Chemical Mechanical Polishing), only the periphery of the wafer may be thin (sag), and even in the sacrificial oxidation treatment, there may be a concentric in-plane distribution. However, in the method for manufacturing a bonded SOI wafer according to the present invention, since the RTA process is performed so that the natural oxide film remains in the central portion of the SOI layer surface, these processes are performed as a planarization process. A bonded SOI wafer with good in-plane uniformity of layer thickness can be manufactured.

  Further, the RTA treatment is preferably performed in a temperature range of 1025 to 1075 ° C. and a heat treatment time of 1 to 60 seconds.

  Under such processing conditions, the natural oxide film in the peripheral portion of the SOI layer surface is easily removed, and the natural oxide film in the central portion remains and the entire natural oxide film is not removed.

  As described above, according to the method for manufacturing a bonded SOI wafer of the present invention, in the planarization process of the SOI layer after peeling, the deterioration of the in-plane uniformity of the thickness of the SOI layer is suppressed, and the SOI layer A bonded SOI wafer having excellent in-plane uniformity of film thickness can be manufactured. In particular, a bonded SOI wafer having an in-plane film thickness range after planarization of the SOI layer of 1.5 nm or less can be manufactured. In addition, even when polishing treatment, sacrificial oxidation treatment, and heat treatment in an inert gas atmosphere are performed as the planarization treatment, a bonded SOI wafer with excellent in-plane uniformity of the SOI layer thickness can be manufactured.

It is a flowchart of the manufacturing method of the bonding SOI wafer of this invention. 4 is a graph showing the film thickness distribution of SOI layers in Example 1, Comparative Example 3 and 4. It is a graph which shows the film thickness distribution of the SOI layer of Example 2, Comparative Examples 7 and 8. It is a graph which shows the film thickness distribution of the SOI layer of Example 3 and Comparative Examples 11 and 12.

  Hereinafter, the present invention will be described in detail, but the present invention is not limited thereto. As described above, in the planarization process of the SOI layer after peeling, the deterioration of in-plane uniformity of the SOI layer film thickness is suppressed, and a bonded SOI wafer with excellent in-plane uniformity of the SOI layer film thickness is obtained. A method that can be manufactured has been desired.

  As a result of intensive studies on the above problems, the present inventors have appropriately performed an RTA process using a hydrogen gas-containing atmosphere prior to the planarization process in accordance with the characteristics of the planarization process (characteristics that the peripheral portion becomes thinner). By adding under conditions, it was found that a bonded SOI wafer having an in-plane film thickness range after planarization of the SOI layer of 1.5 nm or less could be obtained, and the present invention was completed. Hereinafter, the present invention will be described in more detail.

  FIG. 1 shows a method for manufacturing a bonded SOI wafer according to the present invention. As shown in FIG. 1, in the present invention, (a) at least one kind of gas ion of hydrogen ion and rare gas ion is ion-implanted from the surface of a bond wafer 1 made of silicon single crystal, and ion implantation is performed inside the bond wafer 1. After the layer 4 is formed and (b) the ion-implanted surface of the bond wafer 1 and the surface of the base wafer 2 are bonded together via the insulating film 3, (c) a part of the bond wafer 1 is A bonded SOI wafer having a SOI layer 6 made of the thin film of the bond wafer 1 is produced on the base wafer 2 by peeling off with the ion implantation layer 4, and then (d) the bonded SOI wafer after peeling. Then, RTA treatment is performed in an atmosphere containing hydrogen gas so that the natural oxide film 5 in the peripheral portion of the surface of the SOI layer 6 is removed and the natural oxide film 5 ′ in the central portion remains. ) Uniformity by performing planarization treatment on the bonded SOI wafer with the natural oxide film 5 ′ remaining in the center so that the in-plane film thickness range of the planarized SOI layer 6 ′ is 1.5 nm or less. A bonded SOI wafer having a sufficient thickness can be manufactured.

  Note that the natural oxide film 5 is naturally formed on the surface of the SOI layer 6 during the transition from the step (c) to the step (d). Further, after the step (c), SC-1 cleaning and / or SC-2 cleaning may be performed, and the natural oxide film 5 can be formed also by this. Although FIG. 1 shows an example in which the insulating film 3 is formed on the bond wafer 1, there is no particular limitation, and the insulating film 3 may be formed on the base wafer 2 or both.

  It is known that the natural oxide film 5 on the surface of the SOI layer 6 is removed and flattened by migration by performing RTA treatment with a gas containing hydrogen at a high temperature of 1100 ° C. or higher. On the other hand, when the RTA treatment is performed with a gas containing hydrogen at a temperature lower than 1100 ° C., the natural oxide film 5 is removed from the peripheral portion of the surface of the SOI layer 6 to a substantially constant distance depending on the heat treatment time. As a result, the natural oxide film 5 ′ may remain without being removed at the center of the wafer. The size of the natural oxide film 5 ′ that remains without being removed in the central portion of the wafer varies depending on the heat treatment temperature and the heat treatment time. However, this is contrary to the fact that the surface state in which the natural oxide film remains in the central portion can obtain a uniform and good surface state in the wafer surface by the RTA process. For this reason, the RTA process is not generally completed under such conditions.

  Specifically, an RTA process is performed on an SOI wafer (with a natural oxide film 5 formed on the SOI surface) immediately after peeling by an ion implantation peeling method at 1000 ° C., 1050 ° C., 1100 ° C. for 30 seconds in a hydrogen-containing atmosphere. After that, these wafers were subjected to sacrificial oxidation treatment (treatment for performing oxidation and oxide film removal), and the thickness of the SOI layer 6 ′ was measured. As a result, the thickness of the SOI layer 6 ′ treated with the RTA at 1000 ° C. is generally thin, and the thickness of the SOI layer 6 ′ treated with the RTA at 1100 ° C. is thicker than that when the RTA treatment is performed at 1000 ° C. The film thickness of the RTA-treated SOI layer 6 ′ was thicker at the periphery as in the RTA-treated wafer at 1100 ° C., and the other region (center portion) was as thin as the wafer that was RTA-treated at 1000 ° C. The same tendency was observed when polishing or Ar annealing was performed instead of the sacrificial oxidation treatment as the planarization treatment.

  As described above, the thickness of the SOI layer 6 'becomes thinner as a whole because the reduction rate of the SOI layer by the planarization process is faster, and the thickness of the SOI layer 6' becomes slower because of the reduction of the thickness of the SOI layer due to the planarization process. It is caused by becoming.

  Further, when the SOI wafer immediately after the RTA treatment is observed, when the RTA treatment is performed at 1000 ° C., the haze immediately after the wafer peeling is not changed and the natural oxide film 5 remains on the entire surface. The strained layer (due to ion implantation damage) remained as it was immediately after peeling. On the other hand, when the RTA treatment was performed at 1100 ° C., the natural oxide film 5 was removed and the haze was improved over the entire surface as compared with immediately after the wafer was peeled off, and the crystallinity of the strained layer was recovered when TEM observation was performed. Further, the RTA-treated wafer at 1050 ° C. has the natural oxide film 5 removed at the peripheral portion to improve the haze. When TEM observation is performed, the crystallinity is recovered at the peripheral portion, and the haze is the same as immediately after peeling at the central portion. The natural oxide film 5 ′ remained without being improved, and strain was left after TEM observation. The region where the natural oxide film 5 is removed and the region where the crystallinity is improved do not completely coincide, but there are many overlapping portions.

  From the above, the RTA treatment in the atmosphere containing hydrogen gas is in an incomplete removal of the natural oxide film 5 on the surface of the SOI layer 6 (the natural oxide film 5 is removed at the peripheral portion and the natural oxide film 5 at the central portion). The crystallinity is recovered when the RTA treatment is performed under the condition that 'is left, in other words, the crystallinity is recovered in the peripheral portion and the strained layer remains in the central portion, and then the planarization is performed. It was found that the thickness reduction rate in the region (peripheral portion) was slow, and the thickness reduction rate was high in the region (center portion) where the strained layer remained.

  By utilizing this phenomenon, an RTA process using a hydrogen gas-containing atmosphere is added under an appropriate condition before the planarization process in accordance with the characteristics of the planarization process (characteristic that the peripheral portion becomes thinner). In this planarization process, it is possible to suppress the deterioration of the in-plane uniformity of the film thickness of the SOI layer 6 and to manufacture a bonded SOI wafer having a good in-plane uniformity of the film thickness of the SOI layer 6 ′.

  Such RTA treatment conditions (temperature, heat treatment time) are such that the natural oxide film 5 at the periphery of the surface of the SOI layer 6 is removed and the natural oxide film 5 ′ at the center remains. There is no particular limitation. The conditions for such RTA treatment are in-plane distribution characteristics of the removal amount of the SOI layer 6 in the planarization treatment step so that the in-plane film thickness range of the planarized SOI layer 6 ′ is 1.5 nm or less. It can be set experimentally.

  Specifically, the natural oxide film 5 on the entire surface of the SOI layer 6 is removed in a short time at a temperature of 1100 ° C. or higher, and the natural oxide film 5 is hardly removed at a temperature of 1000 ° C. or lower. Therefore, it is preferable that the RTA treatment is performed in a temperature range of 1025 ° C. to 1075 ° C. and a heat treatment time of 1 to 60 seconds.

  In the present invention, a planarization process is performed on the bonded SOI wafer in which the natural oxide film 5 ′ remains in the center so that the in-plane film thickness range of the planarized SOI layer 6 ′ is 1.5 nm or less. . Such planarization processing conditions are experimental, considering the in-plane distribution characteristics of the removal amount of the SOI layer 6 when the planarization processing step is performed on the SOI wafer subjected to the RTA processing under a predetermined condition. Can be set to

  As the planarization treatment, at least one of at least one of a polishing treatment, a sacrificial oxidation treatment, and a heat treatment in an inert gas atmosphere can be performed. The planarization treatment can be performed by combining a plurality of treatments in accordance with the finally manufactured bonded SOI wafer.

  Flattening treatment such as polishing treatment, sacrificial oxidation treatment, and heat treatment in an inert gas atmosphere impairs the in-plane uniformity of the SOI layer 6. However, if these processes are performed as a planarization process after the RTA process is performed so that the natural oxide film 5 ′ remains in the center of the surface of the SOI layer 6 as in the present invention, the planarized SOI layer 6 is obtained. A bonded SOI wafer with good in-plane uniformity of film thickness can be manufactured.

  EXAMPLES Hereinafter, although the Example and comparative example of this invention are given and demonstrated further in detail, this invention is not limited to the following Example.

[Example 1, Comparative Examples 1 to 4]
A bond-type wafer having a diameter of 300 mm, a resistivity of 10 Ωcm, and a p-type silicon single crystal wafer is prepared. An oxide film of 150 nm is formed on the bond wafer by thermal oxidation, and hydrogen ions are transferred through the oxide film to 5.5 × 10 ¹⁶ / Ion implantation was performed under conditions of cm ³ and 40 keV. These wafers were bonded to a base wafer of a p-type silicon single crystal wafer having a resistivity of 10 Ωcm and subjected to a peeling heat treatment at 500 ° C. for 30 minutes to produce an SOI wafer.

  These SOI wafers are cleaned (SC-1 cleaning and SC-2 cleaning. At this time, a 1.6 nm-thick natural oxide film is formed on the SOI surface), and in a hydrogen gas atmosphere with a concentration of 50% (Ar RTA treatment was performed at 1050 ° C. for 5, 10, and 20 seconds at 50% gas. The natural oxide film in the peripheral part of the SOI layer surface of the SOI wafer was removed, and the natural oxide film in the central part remained. Mattson 3000 manufactured by Mattson was used as the RTA treatment apparatus. An SOI wafer (RTA treatment at 1000 ° C. for 30 seconds) in which the entire surface native oxide film is not removed as a reference, and an SOI wafer (1100 ° C.) in which the entire surface native oxide film is removed and the strain layer recovers crystallinity. 30 seconds of RTA processing).

  Thereafter, CMP (touch polishing) was performed as a planarization process. In CMP, polishing conditions were set so that the polishing rate at the peripheral portion of the wafer was increased (peripheral sagging was formed). The machining allowance was set to 100 nm.

(Comparative Example 1)
When an SOI wafer subjected to RTA treatment at 1000 ° C. for 30 seconds was subjected to CMP, the average machining allowance was 120 nm, and the peripheral portion of the wafer tended to be about 5 nm thinner than the central portion.

(Comparative Example 2)
When an SOI wafer subjected to RTA treatment at 1100 ° C. for 30 seconds was subjected to CMP, the average machining allowance was 98 nm, and the wafer peripheral portion tended to be 4 nm thinner than the wafer central portion.

(Comparative Example 3)
When an SOI wafer subjected to RTA treatment at 1050 ° C. for 5 seconds was subjected to CMP, the average machining allowance was 112 nm. Looking at the film thickness distribution of the wafer, a ring-shaped region thinner than the average by about 4 nm was present in the vicinity of the outer peripheral portion of 10 mm.

Example 1
When an SOI wafer subjected to RTA treatment at 1050 ° C. for 10 seconds was subjected to CMP, the average machining allowance was 110 nm. Looking at the film thickness distribution of the wafer, it was within 1.5 nm in the plane, and there was no particularly thin or thick area, and the film thickness uniformity of the SOI layer was good.

(Comparative Example 4)
When an SOI wafer subjected to RTA treatment at 1050 ° C. for 20 seconds was subjected to CMP, the average machining allowance was 105 nm. Looking at the film thickness distribution of the wafer, a ring-shaped region thicker than the average by about 4 nm was present in the vicinity of the outer peripheral portion of 30 mm.

  As in Example 1, the native oxide film at the periphery of the SOI layer surface is removed, and the RTA processing conditions are appropriately selected so that the natural oxide film at the center remains, so that the film thickness is uniform even when CMP is performed. It was found that the sex became smaller. In addition, it is possible to select RTA conditions according to the characteristics of CMP. FIG. 2 shows the SOI film thickness distribution of Example 1 and Comparative Examples 3 to 4, and the film thickness of the SOI layer at the center of the wafer was set to zero. As described above, the film thickness range can be reduced to 1.5 nm or less by combining the RTA condition and the planarization condition.

[Example 2, Comparative Examples 5 to 8]
A bond-type wafer having a diameter of 300 mm, a resistivity of 10 Ωcm, and a p-type silicon single crystal wafer is prepared. An oxide film of 150 nm is formed on the bond wafer by thermal oxidation, and hydrogen ions are transferred through the oxide film to 5.5 × 10 ¹⁶ / Ion implantation was performed under conditions of cm ³ and 40 keV. These wafers were bonded to a base wafer of a p-type silicon single crystal wafer having a resistivity of 10 Ωcm and subjected to a peeling heat treatment at 500 ° C. for 30 minutes to produce an SOI wafer.

  These SOI wafers are cleaned (SC-1 cleaning and SC-2 cleaning. At this time, a 1.6 nm-thick natural oxide film is formed on the SOI surface), and in a hydrogen gas atmosphere with a concentration of 50% (Ar RTA treatment was performed at 1050 ° C. for 5, 10, and 20 seconds at 50% gas. The natural oxide film in the peripheral part of the SOI layer surface of the SOI wafer was removed, and the natural oxide film in the central part remained. Mattson 3000 manufactured by Mattson was used as the RTA treatment apparatus. An SOI wafer (RTA treatment at 1000 ° C. for 30 seconds) where the natural oxide film is not removed as a reference and an SOI wafer (30 ° C. at 1100 ° C.) where the natural oxide film is removed and the strained layer recovers crystallinity. Second RTA processing).

  Thereafter, sacrificial oxidation treatment was performed as a planarization treatment. The oxidation temperature was 900 ° C. and the oxide film thickness was 200 nm. The thickness distribution of the SOI layer after removing the oxide film of the reference wafer with RHF treatment at 1000 ° C. for 30 seconds and 1100 ° C. for 30 seconds with HF is not a particularly characteristic distribution, and the film thickness range is about 1.5 nm. there were.

  On the other hand, the thickness distribution of the SOI layer after sacrificial oxidation of an SOI wafer subjected to RTA treatment at 1050 ° C. for 5, 10 and 20 seconds is thicker at the periphery than the wafer center, and the film thickness range exceeds 2 nm. It was.

  Thereafter, CMP was further performed as a planarization process. In CMP, polishing conditions were set so that the polishing rate at the peripheral portion of the wafer was increased (peripheral sagging was formed). The machining allowance was set to 100 nm.

(Comparative Example 5)
When the SOI wafer after the sacrificial oxidation treatment at 1000 ° C. for 30 seconds was further CMP, the average machining allowance was 120 nm, and the peripheral portion of the wafer tended to be about 5 nm thinner than the central portion.

(Comparative Example 6)
When the SOI wafer after the sacrificial oxidation treatment at 1100 ° C. for 30 seconds was further subjected to CMP, the average machining allowance was 98 nm, and the peripheral portion of the wafer tended to be 4.5 nm thinner than the central portion of the wafer.

(Comparative Example 7)
When the SOI wafer after the sacrificial oxidation treatment at 1050 ° C. for 5 seconds was further subjected to CMP, the average machining allowance was 114 nm. Looking at the film thickness distribution of the wafer, a ring-shaped region thinner than the average by about 3.5 nm was present in the vicinity of the outer peripheral portion of 10 mm.

(Example 2)
When the SOI wafer after the sacrificial oxidation treatment at 1050 ° C. for 10 seconds was further subjected to CMP, the average machining allowance was 111 nm. Looking at the film thickness distribution of the wafer, it was within 1.5 nm in the plane, and there was no particularly thin or thick area, and the film thickness uniformity of the SOI layer was good.

(Comparative Example 8)
When the SOI wafer after the sacrificial oxidation treatment at 1050 ° C. for 20 seconds was further subjected to CMP, the average machining allowance was 104 nm. Looking at the film thickness distribution of the wafer, a ring-shaped region thicker than the average by about 4.2 nm was present in the vicinity of the outer peripheral portion of 30 mm.

  As described above, even if sacrificial oxidation treatment and CMP are performed by selecting the RTA treatment conditions so that the natural oxide film in the peripheral portion of the SOI layer surface is removed and the natural oxide film in the central portion remains, the film thickness uniformity is small. I found out that It has also been found that an SOI wafer with good uniformity can be manufactured by appropriately selecting the RTA conditions even in a combination of sacrificial oxidation treatment and CMP characteristics. FIG. 3 shows the SOI film thickness distribution of Example 2 and Comparative Examples 7 to 8. The film thickness of the SOI layer at the center of the wafer was set to zero.

[Example 3, Comparative Examples 9-12]
A bond-type wafer having a diameter of 300 mm, a resistivity of 10 Ωcm, and a p-type silicon single crystal wafer is prepared. An oxide film of 150 nm is formed on the bond wafer by thermal oxidation, and hydrogen ions are transferred through the oxide film to 5.5 × 10 ¹⁶ / Ion implantation was performed under conditions of cm ³ and 40 keV. These wafers were bonded to a base wafer of a p-type silicon single crystal wafer having a resistivity of 10 Ωcm and subjected to a peeling heat treatment at 500 ° C. for 30 minutes to produce an SOI wafer.

  These SOI wafers are cleaned (SC-1 cleaning and SC-2 cleaning. At this time, a 1.6 nm-thick natural oxide film is formed on the SOI surface), and in a hydrogen gas atmosphere with a concentration of 50% (Ar RTA treatment was performed at 1050 ° C. for 5, 10, and 20 seconds at 50% gas. The natural oxide film in the peripheral part of the SOI layer surface of the SOI wafer was removed, and the natural oxide film in the central part remained. Mattson 3000 manufactured by Mattson was used as the RTA treatment apparatus. An SOI wafer (RTA treatment at 1000 ° C. for 30 seconds) where the natural oxide film is not removed as a reference and an SOI wafer (30 ° C. at 1100 ° C.) where the natural oxide film is removed and the strained layer recovers crystallinity. Second RTA processing).

  Thereafter, sacrificial oxidation treatment was performed as a planarization treatment. The oxidation temperature was 900 ° C. and the oxide film thickness was 200 nm. The thickness distribution of the SOI layer after removing the oxide film of the reference wafer with RHF treatment at 1000 ° C. for 30 seconds and 1100 ° C. for 30 seconds with HF is not a particularly characteristic distribution, and the film thickness range is about 1.5 nm. there were.

  On the other hand, the thickness distribution of the SOI layer after sacrificial oxidation of an SOI wafer subjected to RTA treatment at 1050 ° C. for 5, 10 and 20 seconds is thicker at the periphery than the wafer center, and the film thickness range exceeds 2 nm. It was.

  Further, as a planarization treatment, Ar annealing treatment (Ar 100% atmosphere) was performed on these SOI wafers at 1200 ° C. for 4 hours.

  If annealing is performed at a high temperature for a short time, the film thickness distribution in the SOI layer after heat treatment will not be greatly deteriorated. However, if the annealing is performed for a long time, the film thickness distribution becomes large and becomes a problem.

(Comparative Example 9)
When the SOI wafer after the sacrificial oxidation treatment at 1000 ° C. for 30 seconds was further subjected to Ar annealing, the thickness of the SOI layer tended to be 3 nm thinner at the peripheral portion than at the central portion.

(Comparative Example 10)
When the SOI wafer after the sacrificial oxidation treatment at 1100 ° C. for 30 seconds was further subjected to Ar annealing, the thickness of the SOI layer tended to be 3 nm thinner at the peripheral portion than at the central portion.

(Example 3)
An SOI wafer obtained by further Ar-annealing an SOI wafer after sacrificial oxidation treatment at 1050 ° C. for 5 seconds has an in-plane uniformity of 1 nm or less, no special pattern such as a ring shape is seen, and the thickness of the SOI layer is uniform. The property was good.
(Comparative Example 11)

  Looking at the film thickness distribution of the SOI wafer obtained by further Ar-annealing the SOI wafer after the sacrificial oxidation treatment at 1050 ° C. for 10 seconds, a ring-shaped region thicker than the average by about 3 nm was present in the vicinity of the outer periphery of 25 mm.

(Comparative Example 12)
When the film thickness distribution of the SOI wafer obtained by further Ar-annealing the SOI wafer after the sacrificial oxidation treatment at 1050 ° C. for 20 seconds was seen, a ring-shaped region thicker than the average by about 3.5 nm was present in the vicinity of the outer periphery of 35 mm.

  As described above, even if sacrificial oxidation treatment and Ar annealing are performed by selecting the RTA treatment conditions so that the natural oxide film in the peripheral portion of the SOI layer surface is removed and the natural oxide film in the central portion remains, the film thickness uniformity is It turned out to be smaller. It was also found that an SOI wafer with good uniformity can be manufactured by appropriately selecting the RTA conditions even in combination of the characteristics of sacrificial oxidation treatment and Ar annealing. FIG. 4 shows the SOI film thickness distribution of Example 3 and Comparative Examples 11 to 12, and the film thickness of the SOI layer at the center of the wafer was set to zero.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

DESCRIPTION OF SYMBOLS 1 ... Bond wafer, 2 ... Base wafer, 3 ... Insulating film, 4 ... Ion implantation layer, 5 ... Natural oxide film, 5 '... Natural oxide film of center part, 6 ... SOI layer, 6' ... SOI after planarization layer

Claims (3)

At least one kind of gas ion of hydrogen ion and rare gas ion is ion-implanted from the surface of the bond wafer made of silicon single crystal to form an ion-implanted layer inside the bond wafer, and on the ion-implanted side of the bond wafer. After bonding the surface and the surface of the base wafer through an insulating film, a part of the bond wafer is peeled off by the ion implantation layer, and an SOI layer made of the bond wafer thin film is formed on the base wafer. A method for producing a bonded SOI wafer, in which a bonded SOI wafer is manufactured, and then a flattening process is performed to flatten the release surface.
The bonded SOI wafer after peeling is subjected to an RTA process in an atmosphere containing hydrogen gas so that the natural oxide film at the periphery of the SOI layer surface is removed and the natural oxide film at the center remains. A bonded SOI wafer comprising: a bonded SOI wafer having a natural oxide film remaining in a central portion; wherein the planarization process is performed so that an in-plane film thickness range of the SOI layer is 1.5 nm or less. Production method.   2. The bonded SOI wafer production according to claim 1, wherein at least one of a polishing process, a sacrificial oxidation process, and a heat treatment in an inert gas atmosphere is performed as the planarization process. Method. 3. The method for manufacturing a bonded SOI wafer according to claim 1, wherein the RTA treatment is performed in a temperature range of 1025 to 1075 ° C. for a heat treatment time of 1 to 60 seconds.

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