JP2012181677A - Physical quantity measuring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a physical quantity measuring device with high reliability that executes an error notification with respect to bit error and the like during communication as well as with respect to a failure in a circuit by using a serial communication system such as an SPI.SOLUTION: A physical quantity measuring device includes: a sensor element 4 that detects a predetermined physical quantity so as to output first signals 90 and 92; a detecting circuit 6 for generating a second signal 40 based on the first signals 90 and 92; a driving circuit 5 that generates a driving signal 82 so as to supply the driving signal 82 to the sensor element; a fault diagnosis section 20 that receives third signals 42 and 44 being internal signals from at least one of the detecting circuit 6 and the driving circuit 5 so as to execute a fault diagnosis and to output a fourth signal 30; and an interface section 10 that receives a command and serially transmits response data including data requested by the command. The interface section 10 causes the response data to include at least a command error flag indicating whether or not an error occurs with respect to the command during communication.

Description

  The present invention relates to a physical quantity measuring device and the like.

  High reliability is required for physical quantity measuring devices mounted on automobiles, airplanes, ships, railways, and the like that require safety. Such a physical quantity measuring apparatus needs to output a signal corresponding to the physical quantity detected in response to a request from the host CPU, for example. If an error occurs, it is required to notify the host CPU immediately.

  In the invention of Patent Document 1, an error is notified by providing one bit of a flag indicating the presence / absence of an error for each byte as a transmission unit. The invention of Patent Document 2 prepares fault diagnosis output data including a 4-bit error code and notifies an error.

JP 2007-285745 A JP 2007-230514 A

  However, in the inventions of Patent Document 1 and Patent Document 2, an error is notified about a failure of the circuit of the detection apparatus, but errors that occur during communication are not targeted. For example, the detection device may receive a command from the host CPU and select an appropriate one from a plurality of data depending on the content of the command. At this time, if the command cannot be received correctly, the inventions of Patent Document 1 and Patent Document 2 cannot transmit correct data.

  Here, for example, by adopting a communication method that performs handshake such as I2C, it is possible to receive a command reliably. However, I2C has a low transmission speed and does not satisfy the demand for high-speed communication in recent years. In addition, when a command is garbled due to noise during communication, data corresponding to an erroneous command may be transmitted even if the detection device receives the command reliably.

  The present invention has been made in view of such problems. According to some aspects of the present invention, it is possible to use a higher-speed serial communication method such as SPI (Serial Peripheral Interface) used in Patent Document 1, for example, not only a circuit failure but also communication. Provided is a highly reliable physical quantity measuring device that provides error notification even when bits are garbled.

(1) The present invention is a physical quantity measuring device that detects a predetermined physical quantity, detects the predetermined physical quantity, and outputs a first signal that is a signal corresponding to the detected magnitude of the predetermined physical quantity. A sensor element that generates a second signal according to the predetermined physical quantity based on the first signal, and a drive circuit that generates a drive signal and supplies the drive signal to the sensor element And receiving a third signal that is an internal signal from at least one of the detection circuit and the drive circuit, and performing a failure diagnosis on at least one of the detection circuit and the drive circuit based on the third signal. A failure diagnosis unit that outputs a fourth signal that is a signal corresponding to the result of the failure diagnosis; and a command is received, command request data that is data requested by the command is generated, and An interface unit that serially transmits response data including command request data, and the interface unit generates the command request data based on at least one of the second signal and the fourth signal The response data includes an error flag indicating whether or not an error has occurred, and the error flag includes at least a command error flag indicating whether or not an error has occurred during communication for the command.

(2) In this physical quantity measuring device, the interface unit serially receives command data having a predetermined value in only one unique bit that does not overlap with another command, and based on the command data, The value of the error flag may be determined by determining whether an error has occurred during communication.

  According to these inventions, the interface unit included in the physical quantity measuring device serially transmits response data including a command error flag indicating whether or not an error has occurred during communication for the received command. For this reason, it is possible to provide a highly reliable physical quantity measuring apparatus that performs error notification not only for circuit failures but also for garbled bits during communication.

  At this time, the interface unit serially receives command data having a predetermined value (for example, 1) in only one unique bit that does not overlap with another command, and an error has occurred during communication based on the command data. It may be determined whether or not. For example, when two or more bits are 1 in the received command data, or when there is no 1, the interface unit can immediately determine that an error has occurred during communication.

  Here, the predetermined physical quantity detected by the sensor element of the physical quantity measuring device may be, for example, angular velocity, acceleration, velocity, displacement, flow rate, temperature, pressure, illuminance, etc., but is not limited thereto. For example, when the predetermined physical quantity is an angular velocity, the physical quantity measuring device functions as an angular velocity sensor. At this time, the sensor element detects the angular velocity based on the Coriolis force acting in the direction orthogonal to the vibration direction of the object and the rotation axis when the vibrating object is rotated. The sensor element of the angular velocity sensor is composed of a vibrator, for example.

  The interface unit performs serial communication, but the communication method may be SPI, for example, or 3-wire serial communication using a bidirectional data line. The internal signals from the drive circuit and the detection circuit mean the signals representing the internal state of these circuits, and do not necessarily indicate the signals closed inside the circuits.

(3) In this physical quantity measuring device, the interface unit includes the command including each result of the failure diagnosis performed by the failure diagnosis unit when receiving a failure diagnosis result output command which is one of the commands. Request data may be generated.

  According to the present invention, when the interface unit receives a failure diagnosis result output command, the interface unit generates command request data including each result of the failure diagnosis performed by the failure diagnosis unit. At this time, for example, since the host CPU can know the details of the failure diagnosis, the failure location can be identified at an early stage, and an early response can be performed.

(4) In this physical quantity measuring device, the interface unit may include a checksum for the command request data and the error flag in the response data.

  According to the present invention, the interface unit calculates a checksum for data including not only command request data but also an error flag. Then, response data including the checksum is transmitted. Thereby, for example, the host CPU can immediately know whether or not an error has occurred during transmission from the physical quantity measuring device, so that the reliability of the response data is increased.

  Further, since the error flag is also subject to the checksum, there is no problem that the correctness cannot be confirmed except for the command request data.

  The checksum may be a sum of 1 in all bits of the command request data and the error flag. Further, when it is included in the response data, its complement may be used.

(5) In this physical quantity measuring device, the interface unit may transmit the response data in a plurality of times.

  According to the present invention, since the response data can be transmitted in a plurality of times, for example, even when the number of bits of the signal output from the detection circuit increases with improvement in detection accuracy, it is possible to easily cope with the response data. Therefore, a physical quantity measuring device excellent in expandability can be provided.

(6) In this physical quantity measuring device, the sensor element may detect an angular velocity as the predetermined physical quantity.

  According to the present invention, the predetermined physical quantity may be an angular velocity. At this time, not only the failure of the circuit but also the error notification about the garbled bits during communication is performed, so that the reliability is high. Thus, for example, it can be used as an angular velocity sensor that is mounted on a vehicle that requires reliability and used for travel control, dead reckoning navigation, and the like.

The block diagram of the physical quantity measuring apparatus in 1st Embodiment. The figure which shows the structural example of the failure diagnosis part of 1st Embodiment. The block diagram of the interface part of 1st Embodiment. The figure which shows the command data of 1st Embodiment. The figure which shows the response data of 1st Embodiment. The timing diagram of transmission / reception of the command data and response data of 1st Embodiment. FIG. 3 is a block diagram illustrating an example of a drive circuit according to the first embodiment. The block diagram showing one example of the detection circuit of a 1st embodiment. The block diagram showing another example of the detection circuit of a 1st embodiment.

1. First Embodiment A first embodiment of the present invention will be described with reference to FIGS.

1.1. Configuration of Physical Quantity Measuring Device of this Embodiment FIG. 1 is a block diagram of a physical quantity measuring device 1 of this embodiment. The physical quantity measuring device 1 includes a sensor element 4, a drive circuit 5, a detection circuit 6, a failure diagnosis unit 20, and an interface unit 10. The physical quantity measuring device 1 may further include an operation setting circuit 7.

  The sensor element 4 of the present embodiment includes, for example, integrated vibrators 2 and 3 and detects angular velocity. Here, a signal corresponding to the magnitude of the angular velocity and output from the sensor element 4 is a first signal. In FIG. 1, the first signals are differential signals 90 and 92. In the present embodiment, the differential signals 90 and 92 are output from the vibrator 3 for noise resistance, but one signal that is not differential may be output.

  The drive circuit 5 generates a drive signal 82 and supplies it to the vibrator 2, receives the excitation current 80 from the vibrator 2, and forms an oscillation loop. The magnitudes of the differential signals 90 and 92 are proportional to the excitation current 80. Therefore, the drive circuit 5 controls the drive signal 82 so that the amplitude of the excitation current 80 is constant regardless of changes in the measurement environment.

  The detection circuit 6 generates an output signal 40 based on the differential signals 90 and 92. Here, a signal corresponding to the magnitude of the angular velocity detected by the sensor element 4 and output from the detection circuit 6 is a second signal. In FIG. 1, the second signal is the output signal 40.

  The output signal 40 is serially transmitted to the host CPU, for example, via the interface unit 10. The detection circuit 6 receives the differential signals 90 and 92 and performs conversion into a format required by the host CPU, for example, to generate an output signal 40.

  Here, in the present embodiment, the operation setting circuit 7 performs optimal operation settings for the drive circuit 5 and the detection circuit 6. The operation setting circuit 7 includes, for example, a reference voltage circuit, a memory circuit, and the like, and performs optimization by voltage setting, parameter setting, and the like of the drive circuit 5 and the detection circuit 6.

  The failure diagnosis unit 20 performs failure diagnosis for at least one of the drive circuit 5 and the detection circuit 6. In the present embodiment, failure diagnosis is executed for both circuits. An internal signal of the drive circuit 5 and the detection circuit 6 including information necessary for performing the failure diagnosis is a third signal. In FIG. 1, the third signals are internal signals 42 and 44.

  A signal representing the result of the fault diagnosis executed by the fault diagnosis unit 20 is defined as a fourth signal. In FIG. 1, the fourth signal is signal 30. The signal 30 is a value representing each result of the fault diagnosis executed by the fault diagnosis unit 20 (for example, high level “1” at the time of error), and “1” if any one of all the fault diagnoses has an error. The error flag value may be included.

  The interface unit 10 performs data communication with, for example, a host CPU outside the physical quantity measuring device 1. At this time, data communication is performed by the serial method, and the number of terminals of the interface unit 10 can be reduced as compared with the parallel method.

  In the present embodiment, the interface unit 10 uses SPI as a communication method. As shown in FIG. 1, four signals of a slave selection signal SS, a serial clock SCK, a serial input signal MOSI, and a serial output signal MISO are used.

  The interface unit 10 performs data communication using these signals in accordance with a request from the master. In the following description, it is assumed that a host CPU (not shown) exists as a master in communication using SPI, and the physical quantity measuring device 1 functions as one slave.

  The slave selection signal SS is a signal used by the host CPU (master) to select the physical quantity measuring device 1 (slave), and may be, for example, a low active signal. When the slave selection signal SS is “0” (low level), the interface unit 10 communicates with the host CPU.

  The serial clock SCK is a clock for synchronizing serial transmission, and the communication speed is determined by the clock frequency of the serial clock SCK. In the present embodiment, for example, by using a serial clock SCK of 10 MHz, high-speed communication is possible even compared with, for example, I2C in the standard mode.

  The serial input signal MOSI and the serial output signal MISO are data from the host CPU to the physical quantity measuring device 1, and data from the physical quantity measuring device 1 to the host CPU, respectively.

  The interface unit 10 receives a command from the host CPU and generates command request data that is data requested by the command. The command is a command from the host CPU and is given in the form of command data input as the serial input signal MOSI. A specific example of command data will be described later.

  The interface unit 10 generates command request data based on at least one of the output signal 40 (second signal) and the signal 30 (fourth signal). Then, response data including command request data and having a predetermined number of bits and format is generated. The response data is data output as the serial output MISO, and a specific example thereof will be described later.

  At this time, the interface unit 10 includes not only the command request data but also an error flag in the response data. The error flag is data of 1 bit or more indicating whether or not an error has occurred. At this time, a command error flag indicating whether or not an error is included in the command received from the host CPU is included as an error flag.

  Since the interface unit 10 receives the result of the failure diagnosis for the drive circuit 5 and the detection circuit 6 as the signal 30, the failure of the circuit can be included in the command request data. Then, not only the command request data but also a command error flag indicating whether or not an error has occurred during communication for the received command itself is transmitted to the host CPU. Therefore, for example, it becomes possible for the host CPU to grasp bit corruption during communication, and the physical quantity measuring device 1 with high data reliability can be provided.

1.2. Configuration Example of Drive Circuit and Detection Circuit The physical quantity measuring device 1 of the present embodiment is an angular velocity sensor, for example. At this time, the sensor element 4 includes, for example, the integrated vibrators 2 and 3 and detects the angular velocity. And the drive circuit 5 and the detection circuit 6 are implement | achieved by the following structures, for example.

1.2.1. Drive Circuit FIG. 7 shows a configuration example of the drive circuit 5. In addition, the same code | symbol is attached | subjected to the same element as FIG. 1, and description is abbreviate | omitted.

  The drive circuit 5 includes, for example, a current-voltage conversion circuit 52, a full-wave rectification circuit 53, a comparison adjustment circuit 54, and a drive signal generation circuit 55.

  The current-voltage conversion circuit 52 converts the excitation current 80 from the vibrator 2 into a voltage and outputs a signal 202. The amplitude of the signal 202 is proportional to the amplitude of the excitation current 80. The full-wave rectification circuit 53 performs full-wave rectification on the signal 202 from the current-voltage conversion circuit 52 to obtain a voltage close to direct current, and outputs a signal 204.

  The comparison adjustment circuit 54 compares the signal 204 from the full wave rectification circuit 53 with the voltage from the comparison voltage supply circuit 56, and outputs a signal 206 that is a signal reflecting the comparison result to the drive signal generation circuit 55.

  The drive signal generation circuit 55 generates the drive signal 82 based on the signal 202 from the current-voltage conversion circuit 52, and adjusts the amplitude of the drive signal 82 based on the signal 206.

  The magnitude of the differential signals 90 and 92 (first signal, see FIG. 1) is proportional to the excitation current 80. Therefore, the drive circuit 5 controls and outputs the drive signal 82 so that the amplitude of the excitation current 80 is constant so that the angular velocity can be accurately measured regardless of the environmental change.

1.2.2. Detection Circuit FIG. 8 shows one configuration example of the detection circuit 6. In addition, the same code | symbol is attached | subjected to the same element as FIG. 1, and description is abbreviate | omitted.

  The detection circuit 6 receives differential signals 90 and 92 from the sensor element 4 (see FIG. 1). Then, necessary processing is performed on the differential signals 90 and 92, and an output signal 40 corresponding to the angular velocity detected by the sensor element 4 is generated.

  Here, although conversion to a DC signal is performed by the synchronous detection circuit 66, for convenience of explanation, a circuit that performs processing up to the conversion is expressed as a pre-stage circuit 70, and a circuit after that is expressed as a post-stage circuit 72. .

  As shown in FIG. 8, the pre-stage circuit 70 includes, for example, current-voltage conversion circuits 62-1 and 62-2, a differential amplifier circuit (differential amplifier) 63, a high-pass filter (HPF) 64, an amplifier circuit (AC amplifier) 65, A part of the synchronous detection circuit 66 is included.

  Further, the post-stage circuit 72 includes, for example, a part of the synchronous detection circuit 66, a signal output unit 67, and an offset adjustment circuit 69.

  The current-voltage conversion circuits 62-1 and 62-2 convert the currents of the differential signals 90 and 92 into voltages, respectively. The differential signals 90 and 92 have a current value corresponding to the angular velocity detected by the sensor element 4 (see FIG. 1). The current-voltage conversion circuit 62-1 and the current-voltage conversion circuit 62-2 have the same configuration.

  The differential amplifier circuit 63 receives both the signals 210 and 212 output from the current-voltage conversion circuits 62-1 and 62-2, amplifies the difference between these signals, and outputs the amplified signal 214.

  The high pass filter 64 transmits the high frequency component of the signal 214 and outputs it as the signal 216.

  Then, the amplifier circuit 65 amplifies the signal 216 and outputs a signal 218.

  The synchronous detection circuit 66 receives the signal 218 and performs synchronous detection. At this time, an offset signal 226 is input from the offset adjustment circuit 69 to the synchronous detection circuit 66 in order to accurately measure the angular velocity.

  The signal output unit 67 receives the signal 220 output from the synchronous detection circuit 66, and performs filtering or amplification using, for example, a low-pass filter. Then, an output signal 40 corresponding to the angular velocity detected by the sensor element is generated.

  Here, FIG. 9 shows a detection circuit 6A which is another configuration example. Instead of the detection circuit 6 (see FIG. 8), a detection circuit 6A may be used. The same elements as those in FIGS. 1 and 8 are denoted by the same reference numerals, and description thereof is omitted.

  The detection circuit 6 </ b> A includes, for example, a differential input / output current-voltage conversion circuit 62 and an AD converter (ADC) 68 as the pre-stage circuit 70. Further, the post-stage circuit 72 includes, for example, a signal output unit 67A and an offset adjustment circuit 69.

  Unlike the detection circuit 6, the detection circuit 6A converts the current of the differential signals 90 and 92 into a voltage by the current-voltage conversion circuit 62, and immediately thereafter, a signal corresponding to the DC signal of the detection circuit 6 by the AD converter 68. Conversion to 222 is performed.

  The signal output unit 67A of the post-stage circuit 72 performs filtering and amplification in the same manner as the signal output unit 67 of the detection circuit 6, and also performs offset adjustment based on the offset signal 226. The detection circuit 6A can be reduced in circuit scale as compared with the detection circuit 6.

  Here, when a failure occurs in either the drive circuit 5 or the detection circuit 6 (or the detection circuit 6A), the output signal 40 does not represent an accurate angular velocity. Therefore, it is necessary to immediately notify the host CPU or the like when a failure occurs in these circuits in an application that requires particularly high reliability.

1.3. Failure Diagnosis Unit FIG. 2 illustrates a configuration example of the failure diagnosis unit 20. The failure diagnosis unit 20 performs failure diagnosis on the drive circuit 5 and the detection circuit 6 and outputs a failure diagnosis result.

  The failure diagnosis unit 20 receives the internal signals 42 and 44 (see FIG. 1) of the drive circuit 5 and the detection circuit 6, and performs failure diagnosis by comparing with a predetermined voltage value using a comparator, for example. Then, the fault diagnosis result is output individually or via a logic circuit.

  In the example of FIG. 2, the failure diagnosis unit 20 performs failure diagnosis at 16 locations, but the number of diagnosis locations may be an arbitrary number of 1 or more. In the example of FIG. 2, the failure diagnosis unit 20 receives signals 42 </ b> A, 42 </ b> B, 44 </ b> A, 44 </ b> B and the like that indicate the operation states of the drive circuit 5 and the detection circuit 6. For example, the signals 42A and 42B may correspond to the internal signal 42 of the drive circuit 5, and the signals 44A and 44B may correspond to the internal signal 44 of the detection circuit 6.

  Note that the signal received by the failure diagnosis unit 20 is appropriately selected depending on the target of failure diagnosis. For example, a signal indicating the internal operation state may be received from only one of the drive circuit 5 and the detection circuit 6.

In the example of FIG. 2, the failure diagnosis unit 20 includes comparators CMP0 to CMP15, signals 42A, 42B, 44A, 44B and the like indicating the operation states of the drive circuit 5 and the detection circuit 6, and a predetermined voltage value V _th0 to Compare with _Vth15 . In FIG. 2, the signals 42A, 42B, 44A, 44B and the like are assigned to the input terminals of the comparators, and the voltage values V _{th0 to} V _th15 are assigned to the inverting input terminals. Settings (predetermined voltage values and terminal assignments) may be changed independently for each comparator.

  EF [0] to EF [15], which are output signals of the comparators CMP0 to CMP15, represent the results of failure diagnosis. In the present embodiment, for each of EF [0] to EF [15], “1” indicates that there is a failure, and “0” indicates that there is no failure and that the device is normal.

  At this time, the failure diagnosis unit 20 may output a signal 30A indicating whether or not there is a failure as a whole. The signal 30A is an output of the OR circuit to which EF [0] to EF [15] are input. Each of EF [0] to EF [15] is output as the signals 30B to 30E in FIG. Here, the signals 30A to 30E correspond to the signal 30 from the failure diagnosis unit 20 in FIG.

Furthermore, the failure diagnosis unit 20 may have a mode in which failure diagnosis of the comparators CMP0 to CMP15 itself is performed by a command from the host CPU. Based on the test signal TEST of FIG. 2, voltage values V _{test0 to} V _{test 15} prepared in advance are selected instead of the signals 42A, 42B, 44A, 44B and the like. At this time, if the signals 30A to 30E match the expected value, it can be confirmed that the comparators CMP0 to CMP15 are operating normally.

  Since the failure diagnosis unit 20 has a mode for performing failure diagnosis of the comparator itself, the reliability of data can be further improved. The failure diagnosis of the comparator itself may be performed only once, for example, when the physical quantity measuring device 1 is activated.

1.4. Interface Unit FIG. 3 shows a configuration example of the interface unit 10. In addition, the same code | symbol is attached | subjected to the same element as FIG. 1, and description is abbreviate | omitted.

  The interface unit 10 includes shift registers 11 and 29, buffers 12 and 13, a command determination circuit 14, a storage circuit 15, a checksum circuit 16, registers 17 and 18, and a multiplexer 19.

  Two buffers 12 and 13 and two registers 17 and 18 are prepared respectively, which means that two identical buffers and registers are included. In the present embodiment, for example, 32-bit data is transmitted and received 16 bits at a time in two steps. That is, serial communication is performed using 16 bits as a unit of transmission and reception. With such a transmission method, it becomes possible to handle larger data (for example, 64 bits) without changing the size of the shift registers 11 and 29.

  Here, command data (for example, 32 bits) representing a command from the host CPU is divided by a reception unit (for example, 16 bits), and data transmitted first is referred to as command 1, and data transmitted thereafter is referred to as command 2. . Command 1 may be on the upper side or lower side of the command data.

  Similarly, response data (for example, 32 bits) output from the interface unit 10 is divided by a transmission unit (for example, 16 bits), and data that is transmitted first is referred to as a response 1, and data that is transmitted thereafter is referred to as a response 2. The response 1 may be on the upper side or lower side of the response data.

1.4.1. The shift register and buffer interface unit 10 converts the command data received from the host CPU as the serial input signal MOSI into parallel data by the shift register 11 and outputs it (signal 101). In the present embodiment, since the command data is received in two steps, the command 1 converted into parallel is temporarily stored in the buffer 12 and the command 2 is temporarily stored in the buffer 13.

1.4.2. Command determination circuit The command determination circuit 14 receives command data from the buffers 12 and 13 (signals 102 and 103). Then, the command determination circuit 14 determines a command requested by the host CPU from the command data.

  The command determination circuit 14 outputs a signal 104 for selecting necessary data from the storage circuit 15 in order to generate data required by the determined command (command request data). In this embodiment, the signal 104 is an address of the storage circuit 15 that is a register, for example, but may be another signal.

  Further, the command determination circuit 14 determines whether or not an error has occurred during communication for the command, and changes the command error flag (CEF) according to the result. An error in communication with respect to a command means that, for example, the command data is garbled during communication from the host CPU and the command is not a correct code.

  Note that the command determination circuit 14 may write to the memory circuit 15 using the signal 105 when it is necessary to update or change data based on the command. In the present embodiment, the signal 105 is data of the storage circuit 15 that is a register, for example, but may be another signal.

  Here, FIG. 4 shows command data of this embodiment. In this example, there are first to eighth commands, and different command data are assigned to each of them. For example, the first command may be a command for normal operation that requests output of a signal according to the detected physical quantity (for example, angular velocity). In addition, the second command may be a command for starting a failure diagnosis for acquiring data indicating where a failure has occurred. The second command may be a command for outputting a failure diagnosis result for specifying a failure location.

  As shown in FIG. 4, bit 15 of command 1 is 0 to indicate that it is command data. The command determination circuit 14 can easily distinguish command data from other data by the bit 15 of the command 1.

  In the command 1, each command is assigned a unique bit that does not overlap with other commands, and the value of the unique 1 bit is set to 1. In the example of FIG. 4, this unique 1 bit is in bits 14 to 7 (8 bits in total) corresponding to 8 commands.

  For example, in the first command, bit 14 is 1 and bits 13 to 7 are 0. In the second command, bit 13 is 1, and bits 12 to 7 and bit 14 are 0. In this way, since only one of the bits 14 to 7 is set to 1 so that the respective commands do not overlap, the command determination circuit 14 can easily determine the command.

  Here, in order to distinguish the eight commands, it is possible to make a determination only by encoding and using 3 bits. For example, using bits 14 to 12, “000b” may be assigned to the first command and “001b” may be assigned to the second command.

  However, in the case of this method, the command determination circuit 14 cannot detect an error when the command data is garbled during communication. For example, if the bit 12 is garbled from 0 to 1, the command determination circuit 14 erroneously determines the first command as the second command.

  Therefore, in the present embodiment, the unique bit that does not overlap with other commands is set to 1 as shown in FIG. 4 so that the command determination circuit 14 can detect that the bit is garbled during communication.

  In the example of FIG. 4, for example, when the host CPU specifies the first command and the bit 14 of the command 1 is garbled, all the bits of the command 1 become 0, so the command determination circuit 14 Can detect errors. When bit 12 of command 1 is garbled, since the two bits are 1, the command determination circuit 14 can detect an error.

  When detecting a command error, the command determination circuit 14 can set the command error flag (CEF) to 1 and request the host CPU to retransmit the command. Therefore, the physical quantity measuring device 1 with high data reliability can be realized.

  In the example of FIG. 4, all bits of command 2 are 0, but may be a reserved area when 16 or more commands are prepared, or a part of bits 14 to 7 of command 1 may be changed to command 2. The command data may be configured by providing it.

1.4.3. Storage Circuit The storage circuit 15 stores an output signal 40 corresponding to the detected angular velocity from the detection circuit, a signal 30 indicating a failure diagnosis result from the failure diagnosis unit 20, and a signal 105 that is data from the command determination circuit 14. .

  The storage circuit 15 is a register, for example. Note that it may be an SRAM, a DRAM, a non-volatile memory, or another memory. Then, according to the address (signal 104) from the command determination circuit 14, the selected data 106 is output.

1.4.4. Checksum Circuit The interface unit 10 of this embodiment includes a checksum circuit 16. The checksum circuit 16 generates a checksum included in response data (for example, 32 bits) output from the interface unit 10. As a result, for example, when the response data is garbled during communication, the host CPU can detect an error. At this time, the host CPU can make a retransmission request and obtain correct response data. That is, the reliability of data can be further improved by the checksum.

  The checksum may be a sum of the values of the target bits. For example, if the checksum is 5 bits, the checksum is a number obtained by adding 27-bit values other than the checksum of the response data. For example, if all the 27 bits are 1, the checksum value is 27. At this time, if one bit becomes 0 due to bit corruption or the like, the checksum value does not match. Therefore, the host CPU can know the occurrence of an error during communication.

  In FIG. 3, the checksum circuit 16 calculates a checksum based on the signal 106 and outputs it as a signal 107. However, instead of the signal 106, the checksum may be calculated by reading data (signals 108 and 109) temporarily stored in the registers 17 and 18 as response data.

1.4.5. Register and shift register The interface unit 10 divides the response data into transmission units and temporarily stores them in the registers 17 and 18. Register 17 temporarily stores response 1 and register 18 temporarily stores response 2. Here, in this embodiment, the value of the signal 107 that is a checksum is also stored in the register 17.

  The signals 108 and 109 output from the respective registers are sequentially selected by the multiplexer 19. The signal 110 that is the output of the multiplexer 19 is converted into a serial signal by the shift register 29 and transmitted as a serial output signal MISO.

  Here, FIG. 5 shows the response data of this embodiment. Note that the first to eighth commands in FIG. 5 correspond to those in FIG. Note that the contents of each bit are not displayed in the second command, but the second command (beginning of failure diagnosis) is a command that does not require data transmission to the host CPU, indicating that there is no response data. Yes.

  Bit 15 to bit 7 of response 1 are assigned the same data regardless of the command. First, bits 11 to 7 are a checksum calculated by a checksum circuit (see FIG. 3).

  In the present embodiment, the target bits when calculating the checksum include not only all bits 6 to 0 of response 1 and all bits of response 2, but also bits 15 to 12 of response 1 that are flags. Although the flag 1 to flag 4 are not command request data requested by the host CPU as a command, it is possible to detect the occurrence of an error other than the command request data by using these as the checksum target bits.

  Bits 15 to 12 of the response 1 are flag 4 to flag 1, and are error flags that particularly indicate the presence or absence of an error. In the present embodiment, the flag 4 of bit 15 is a command error flag. For example, when the command error flag is 1, the host CPU may take measures such as retransmitting the command.

  In the present embodiment, the flag 3 of the bit 14 is a constant failure diagnosis flag indicating that an error has occurred somewhere as a result of the failure diagnosis. The constant failure diagnosis flag corresponds to the signal 30A in FIG. For example, when the failure diagnosis flag is always 1, the host CPU may transmit a second command for instructing the start of failure diagnosis in order to identify the failure location.

  Note that other error flags may be assigned to flags 2 to 1 of bits 13 to 12. For example, the failure diagnosis results 30B and 30C of FIG. 2 may be assigned, respectively. Bits 13 to 12 may be assigned signals representing statuses of the drive circuit 5 and the detection circuit 6 instead of error flags.

  For example, a status signal indicating that the result of failure diagnosis can be output may be assigned as the flag 2 of bit 13 when, for example, failure diagnosis by the second command is started. Further, as the flag 1 of the bit 12, for example, a status signal indicating a test mode for performing a test of the comparator of the failure diagnosis unit 20 may be assigned. The test mode status signal corresponds to the TEST signal in FIG.

  Since bit 15 to bit 12 are error flags (or status signals) output regardless of the command, the host CPU immediately grasps the latest information including the presence / absence of an error based on the contents of flags 4 to 1. It becomes possible.

  Bit 6 to bit 0 of response 1 and all bits of response 2 are used as command request data corresponding to each command. For example, in the case of the first command, a signal value corresponding to the detected physical quantity (for example, angular velocity) is output. Further, for example, in the case of the third command, all failure diagnosis results EF [15: 0] in the failure diagnosis unit 20 are output. Note that EF [15: 0] corresponds to EF [15] to EF [0] in FIG.

  For other commands, various data can be output as command request data. For example, the fourth command may output a measured value such as temperature, which is different from the angular velocity, and for example, the eighth command may output a status signal indicating a load state or the like. The number of commands is not limited to eight, and expansion to the ninth command and later can be easily performed.

1.4.6. Serial Communication Timing FIG. 6 is a diagram illustrating transmission / reception timings of command data and response data according to the present embodiment. In addition, the same code | symbol is attached | subjected to the same element as FIGS. 1-5, and description is abbreviate | omitted.

  The interface unit 10 receives command data in two times, command 1 and command 2. The response data is divided into two outputs, response 1 and response 2.

  During a period during which data is transmitted and received (for example, times t0 to t1), the slave selection signal SS is “0”. This period is 16 clocks of the serial clock SCK, and the interface unit receives, for example, command data bit by bit. In the present embodiment, the clock frequency of the serial clock SCK is 10 MHz, and high-speed communication is possible even compared with I2C in the standard mode.

  First, the interface unit 10 receives the Nth command data in the order of the Nth command 1 (time t0 to t1) and the Nth command 2 (time t2 to t3). Then, Nth response data including data requested by the Nth command is generated.

  The interface unit 10 receives the (N + 1) th command 1 (time t4 to t5) and the (N + 1) th command 2 (time t6 to t7), the Nth response 1 (time t4 to t5), and the Nth response. 2 (time t6 to t7) is transmitted.

  After that, the (N + 1) th response data for the (N + 1) th command is transmitted in the order of the (N + 1) th response 1 (time t8 to t9) and the (N + 1) th response 2 (time t10 to t11).

  The physical quantity measuring apparatus 1 according to the present embodiment can use a high-speed serial communication method such as SPI, and performs error notification not only for failure of a drive circuit and a detection circuit but also for garbled bits during communication. A high physical quantity measuring device 1 or the like can be provided.

  Therefore, the physical quantity measuring device 1 of the present embodiment can be mounted on automobiles, airplanes, ships, railways, and the like that require safety. For example, it can be suitably applied as a part of an automobile travel control device.

  The present invention is not limited to these exemplifications, and includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 ... Physical quantity measuring device (angular velocity sensor), 2 ... Vibrator, 3 ... Vibrator, 4 ... Sensor element, 5 ... Drive circuit, 6 ... Detection circuit, 6A ... Detection circuit, 7 ... Operation setting circuit, 10 ... Interface part 11 ... shift register, 12 ... buffer, 13 ... buffer, 14 ... command determination circuit, 15 ... memory circuit, 16 ... checksum circuit, 17 ... register, 18 ... register, 19 ... multiplexer, 20 ... failure diagnosis unit, 29 ... shift register, 30, 30A, 30B, 30C, 30D, 30E ... signal (fourth signal), 40 ... output signal (second signal), 42, 42A, 42B ... internal signal (third signal) , 44, 44A, 44B ... internal signal (third signal), 52 ... current-voltage conversion circuit, 53 ... full-wave rectifier circuit, 54 ... comparison and adjustment circuit, 55 ... drive signal generation circuit 56 ... Comparison voltage supply circuit 62, 62-1, 62-2 ... Current / voltage conversion circuit 63 ... Differential amplifier circuit (differential amplifier) 64 ... High pass filter (HPF) 65 ... Amplifier circuit (AC amplifier) , 66 ... Synchronous detection circuit, 67, 67A ... Signal output unit, 68 ... AD converter (ADC), 69 ... Offset adjustment circuit, 70 ... Pre-stage circuit, 72 ... Post-stage circuit, 80 ... Excitation current, 82 ... Drive signal, 90, 92 ... differential signal (first signal), 202, 204, 206, 210, 212, 214, 216, 218, 220, 222 ... signal, 210A, 212A ... differential signal, 226 ... offset signal, CMP0 -CMP15 ... comparator, EF ... error flag, SS ... slave selection signal, SCK ... serial clock, MOSI ... serial input signal, MISO ... si Al output signal

Claims (6)

A physical quantity measuring device for detecting a predetermined physical quantity,
A sensor element that detects the predetermined physical quantity and outputs a first signal that is a signal corresponding to the detected magnitude of the predetermined physical quantity;
A detection circuit that generates a second signal according to the predetermined physical quantity based on the first signal;
A drive circuit that generates a drive signal and supplies the drive signal to the sensor element;
Receiving a third signal that is an internal signal from at least one of the detection circuit and the drive circuit, performing a fault diagnosis on at least one of the detection circuit and the drive circuit based on the third signal, and A fault diagnosis unit that outputs a fourth signal that is a signal corresponding to a result of the fault diagnosis;
An interface unit that receives a command, generates command request data that is data requested by the command, and serially transmits response data including the command request data;
The interface unit is
Generating the command request data based on at least one of the second signal and the fourth signal;
The response data includes an error flag indicating whether an error has occurred,
A physical quantity measuring device including at least a command error flag indicating whether an error has occurred during communication for the command in the error flag. The physical quantity measuring device according to claim 1,
The interface unit is
Serially receiving command data having a predetermined value in only one unique bit that does not overlap with the other commands,
A physical quantity measuring apparatus that determines whether an error has occurred during communication of the command based on the command data and determines a value of the error flag. The physical quantity measuring device according to claim 1,
The interface unit is
When a failure diagnosis result output command that is one of the commands is received,
A physical quantity measuring device that generates the command request data including each result of the failure diagnosis performed by the failure diagnosis unit. In the physical quantity measuring device according to any one of claims 1 to 3,
The interface unit is
A physical quantity measuring device that includes a checksum for the command request data and the error flag in the response data. In the physical quantity measuring device according to any one of claims 1 to 4,
The interface unit is
A physical quantity measuring device that transmits the response data in a plurality of times. In the physical quantity measuring device according to any one of claims 1 to 5,
The sensor element is
A physical quantity measuring device that detects an angular velocity as the predetermined physical quantity.

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