JP2012160889A - Filtering circuit and data repeating device with filtering circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data repeating device mounting a filtering circuit which discards a short frame (short packet) shorter than 64 byte from the Ethernet (trade mark) and does not transmit the short frame to the WAN side.SOLUTION: When a frame being processed currently is referred to a current frame and the data part of the current frame is smaller than a minimum data size, a data size detection unit (14) generates transfer prohibition instruction. In response to the transfer prohibition instruction, a write memory address generation unit (15) specifies a write memory address for overwriting the data part of the current frame stored in a memory block (12) with the data part of a frame next to the current frame.

Description

  The present invention relates to a filtering circuit and a data relay device including the filtering circuit.

  With the spread of services using the Internet and the advancement of information and communication technologies, relay devices that connect a LAN (Local Area Network) and a WAN (Wide Area Network) have become widespread. The relay device has a function of connecting networks having different protocols and the like. A technique of a relay device that appropriately connects networks is known (see, for example, Patent Documents 1 to 4).

  Patent Document 1 discloses a technique for simplifying a logic circuit in an HDLC circuit and reducing power consumption by preventing generation of an HDLC short packet or discarding a short packet. In the technique of Patent Document 1, the HDLC transmission circuit adds an FCS data portion to input transmission packet data, and adds a flag data portion in octets to transmission packet data in octets to which the FCS data portion is added. Then, “0” insertion is performed on the transmission packet data to which the flag data portion is added. Further, the HDLC reception circuit deletes the flag data portion from the input reception packet data, and discards the short packet whose packet length of the reception packet data from which the flag data portion is deleted is less than a predetermined number of bytes. The bit inserted with '0' is deleted from the received packet data not discarded, and the FCS data portion is deleted from the received packet data with the bit inserted with '0' deleted. The technique described in Patent Document 2 achieves an effect of reducing power consumption by suppressing transmission to a subsequent block of a received packet to be discarded by a filtering block having such a configuration and operation.

  Patent Document 2 discloses a technique relating to a data filtering apparatus that can perform high-speed and flexible data filtering with a simple configuration. In the data filtering apparatus, a counter circuit 33 as a data pattern generation circuit sequentially generates pattern data CNT [5: 0] corresponding to a position in a data frame in synchronization with frame data MRD [7: 0] The data MRD [7: 0] is input to the address input terminal of the memory 36. As a result, whether or not the value of the frame data MRD [7: 0] stored at the address specified by the frame data MRD [7: 0] and the pattern data CNT [5: 0] satisfies the selection condition. Data having the indicated value is output from the memory 36. Then, based on the data value, the determination circuit 40 determines whether or not to output the input data frame. The technique described in Patent Document 2 realizes a data filtering device that can perform high-speed and flexible data filtering with a simple configuration by such a configuration and operation.

  Patent Document 3 discloses a technology related to a LAN relay device that can reduce relay delay and reduce the frequency of relaying illegal frames. The LAN relay device includes a checksum confirmation unit and a buffer control unit. The checksum confirmation unit obtains an error confirmation value based on the frame buffer and a predetermined range of the received frame. Further, error detection information for error confirmation generated by the transmission side and stored in the received frame is obtained. The checksum confirmation unit determines that the received frame is an illegal frame when the error detection information does not match the error confirmation value. The buffer control unit buffers the received frame from the head of the frame, ends the buffering when the determination result is notified, and discards the received frame when it is determined to be an illegal frame. Such a technique realizes the effects of reducing the relay delay and reducing the frequency of relaying illegal frames.

  Patent Document 4 discloses a technique for managing a switch-type relay device of a computer network. In that technique, management of the relay device is achieved by a relay device having a segment bus connected to a port of the relay device. The switch engine supplies packets that are sent to the segment bus by the port that received the packet from the Ethernet network. The arbiter unit determines which ports are allowed to send packets to the segment bus. The management unit receives an instruction to transfer the selected port from the first segment bus to the second segment bus, and the arbiter unit transfers the selected port from the first segment bus to the second segment bus. Both ports are activated to prevent sending packets to the first and second segment buses. With such a technique, a packet is relayed from a network having a high data rate of 100 megabits / second to a network having a low data rate of 10 megabits / second. In addition, a relay is realized from a network with a low data rate of 10 megabits / second to a network with a high data rate of 100 megabits / second.

JP 2004-40658 A Japanese Patent Laid-Open No. 2004-40708 JP 2010-148031 A Japanese Patent Laid-Open No. 10-210065

  As described above, from LAN (Local Area Network) using Ethernet (registered trademark) provided corresponding to standards such as IEEE 802.3, provided corresponding to standards such as SDH (Synchronous Digital Hierarchy) A technique for relaying data to a WAN (Wide Area Network) is known.

  Although the minimum frame (packet) size is 64 bytes according to the Ethernet (registered trademark) standard, a short frame (short packet) of less than 64 bytes is generated due to power on / off at an unexpected timing or hot-swapping. May be entered. When such a short frame (short packet) occurs, there is a problem that a useless short frame (short packet) is transmitted and transfer efficiency is lowered.

  The problem to be solved by the present invention is to provide a data relay apparatus equipped with a filtering circuit that discards a short frame (short packet) of less than 64 bytes from Ethernet (registered trademark) and does not transmit it to the WAN side. .

  [Means for Solving the Problems] will be described below using the numbers used in [DETAILED DESCRIPTION]. These numbers are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

In order to solve the above problem, a filtering circuit (3) for receiving and filtering a frame supplied via a LAN (Local Area Network) line (6) is configured as follows. The filtering circuit (3) holds an SFD detection unit (13) that extracts a data portion from a frame based on an SFD (Start Frame Delimiter) of the frame, and a data portion supplied from the SFD detection unit (13). A memory block (12), a data size detector (14) for determining whether or not the data size of the data portion supplied from the SFD detector (13) is less than the minimum allowable data size, and a memory block (12 ) Includes a write memory address generation unit (15) for designating a write memory address for storing the data portion.
Here, the data size detection unit (14) generates a transfer prohibition instruction when the data portion of the current frame when the currently processed frame is the current frame is less than the minimum data size. The write memory address generator (15) overwrites the data portion of the current frame stored in the memory block (12) with the data portion of the next frame of the current frame in response to the transfer prohibit command. Specify the memory address.

  To briefly explain the effects obtained by the representative inventions disclosed in the present application, a short frame (short packet) of less than 64 bytes from Ethernet (registered trademark) is discarded and not transmitted to the WAN side. It is possible to provide a data relay device equipped with a filtering circuit.

FIG. 1 is a block diagram illustrating the configuration of a frame (packet) received by the data transfer apparatus of this embodiment. FIG. 2 is a block diagram illustrating the configuration of the data relay device 1 of this embodiment. FIG. 3 is a block diagram illustrating the configuration of the chip substrate 11 including the data relay device 1 of this embodiment. FIG. 4 is a timing chart illustrating the operation of the data relay device 1 of this embodiment. FIG. 5 is a block diagram illustrating the configuration of the filtering circuit 3 of this embodiment. FIG. 6 is a timing chart illustrating the operation of the filtering circuit 3 of this embodiment. FIG. 7 is a timing chart illustrating the operation of the filtering circuit 3 of this embodiment. FIG. 8 is a timing chart for explaining a comparative example of the present embodiment. FIG. 9 is a block diagram conceptually showing the configuration of the filtering circuit constituted by registers. FIG. 10 is a layout diagram showing a layout of a filtering circuit constituted by registers. FIG. 11 is a block diagram illustrating the configuration of the second embodiment of the filtering circuit 3 of the data relay device 1 of the present invention.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram illustrating the configuration of a frame (packet) received by the data transfer apparatus of this embodiment. As shown in FIG. 1, a frame (packet) corresponding to Ethernet (registered trademark) includes a 7-byte preamble, a 1-byte SFD (Start Frame Delimiter), and 60 A payload of at least bytes and a 4-byte FCS (Frame Check Sequence) are provided. Of these, the payload and the FCS portion that are valid data are called valid frames (valid packets).

  According to the Ethernet (registered trademark) standard, the minimum frame (packet) size is 64 bytes. Therefore, the normal frame is configured to be 64 bytes or more. If the data to be transmitted is small and the effective frame length is less than 64 bytes even though the minimum frame length in the Ethernet (registered trademark) is 64 bytes = 512 bits, the missing frame is padded with 0 to 64. Bytes.

  However, a short frame (short packet) of less than 64 bytes may be generated due to power supply On / Off at an unexpected timing, hot-line insertion, or the like. If a short frame (short packet) is generated and transmitted through the short frame (short packet), the transfer efficiency is lowered.

  The data relay apparatus of this embodiment is equipped with a filtering circuit that discards short frames (short packets) of less than 64 bytes from Ethernet (registered trademark) and does not transmit them to the WAN side. The filtering circuit uses a memory circuit (memory IC) to realize discarding of a short frame (short packet) of less than 64 bytes.

  FIG. 2 is a block diagram illustrating the configuration of the data relay device 1 of this embodiment. As shown in FIG. 2, the data relay device 1 is disposed between the LAN 6 and the WAN 7. The data relay device 1 includes a data conversion block 2. The data conversion block 2 receives a LAN enable signal LAN_EN and LAN data LAN_DT supplied from the LAN side, generates WAN data WAN_DT, and supplies it to the WAN 7.

  The data conversion block 2 includes a filtering circuit 3, a speed conversion FIFO 4, and a WAN data creation unit 5, and executes data conversion from the LAN 6 to the WAN 7.

The filtering circuit 3 receives LAN data (LAN data LAN_DT) supplied from the LAN side and an enable signal (LAN enable signal LAN_EN) indicating the validity of the data.
The filtering circuit 3 extracts necessary data (FIFO write data FIFO_WD). Further, the filtering circuit 3 supplies a data valid signal (FIFO write valid signal FIFO_WVALID) to the speed conversion FIFO 4. In the data conversion block 2, the operations so far are performed at the communication speed on the LAN side.

  The speed conversion FIFO 4 reads the data (FIFO write data FIFO_WD) supplied from the filtering circuit 3 at the WAN communication speed and supplies it to the WAN data creation unit 5.

  The WAN data creation unit 5 reads the data written in the FIFO as FIFO read data FIFO_RD. Further, the WAN data creation unit 5 reads the data valid signal (FIFO read valid signal FIFO_RVALID), generates WAN data (WAN data WAN_DT), and supplies it to the WAN 7 side.

  In the data conversion block 2 of the present embodiment, the filtering circuit 3 has a function of filtering data on the LAN side. By such configuration and operation. It is possible to prevent a decrease in transfer efficiency.

  FIG. 3 is a block diagram illustrating the configuration of the chip substrate 11 including the data relay device 1 of this embodiment. The data conversion block 2 of the data relay device 1 includes a filtering circuit 3. The filtering circuit 3 is provided with a memory block 12. The memory block 12 is provided with a memory cell 12a, a Y decoder 12b, and an X decoder 12c. The filtering circuit 3 of the present embodiment extracts necessary data (FIFO write data FIFO_WD) and stores it in the memory cell 12a of the memory block 12 instead of the shift register configuration. By providing the memory block 12, storage areas in the filtering circuit 3 are concentrated. Therefore, it is possible to avoid timing problems due to variations in wiring delay. In addition, it becomes easy to cope when the frame (packet) size of the filtering condition is changed.

  FIG. 4 is a timing chart illustrating the operation of the data relay device 1 of this embodiment. As shown in the time chart of FIG. 4, in the data conversion block 2 of the data relay device 1 according to the present embodiment, the data relay device 1 includes a filtering circuit 3 in the data conversion block 2 that has a frame of 64 bytes or more. When (packet) is received, a FIFO write valid signal FIFO_WVALID and FIFO write data FIFO_WD are output. When receiving a short frame (packet) of less than 64 bytes, the filtering circuit 3 prohibits the output of the FIFO write valid signal FIFO_WVALID and the FIFO write data FIFO_WD. Thereby, a short frame (packet) of less than 64 bytes is discarded. With this configuration and operation, frame (packet) transfer efficiency can be increased. Furthermore, by discarding short frames (packets) of less than 64 bytes, it is possible to avoid problems caused by unexpected operations and to reduce power consumption by avoiding unnecessary frame (packet) transfers.

  FIG. 5 is a block diagram illustrating the configuration of the filtering circuit 3 of the data conversion block 2 in the data relay device 1 of this embodiment. As shown in FIG. 5, the filtering circuit 3 includes a memory block 12, an SFD detection block 13, a packet size detection block 14, a write address generation block 15, and a read address generation block 16. . The packet size detection block 14 includes a counter 17 and a determination unit 18.

  The SFD detection block 13 detects a start portion of a frame (packet) from frames input from the Ethernet (registered trademark). The packet size detection block 14 monitors whether a frame (packet) is less than 64 bytes or more. The write address generation block 15 generates a write address for writing a frame (packet) to the memory block 12. The read address generation block 16 issues a read command to the memory block 12 after confirming 64 bytes or more in the packet size detection block 14. The memory block 12 using the dual port RAM holds a frame (packet) input from the Ethernet (registered trademark) and outputs it to the WAN 7 side.

  The SFD detection block 13 receives the LAN data LAN_DT and the LAN enable signal LAN_EN. The SFD detection block 13 generates memory write data MEM_WD, a memory write enable signal MEM_WE, and a VALID signal (packet valid signal PKT_VALID) for a frame (packet) and supplies it to a subsequent functional block.

  The counter 17 of the packet size detection block 14 receives the packet valid signal PKT_VALID, and counts the number of bytes of the frame (packet) based on the packet valid signal PKT_VALID. The counter 17 supplies the counted result to the determination unit 18. The determination unit 18 determines whether the frame (packet) size is 64 bytes or more based on the count value supplied from the counter 17.

  The determination unit 18 of the packet size detection block 14 supplies a read non-permission signal READ_NG to the write address generation block 15 when the frame (packet) size is less than 64 bytes. The determination unit 18 of the packet size detection block 14 supplies a read permission signal READ_OK to the read address generation block 16 when the frame (packet) size is 64 bytes or more.

  The write address generation block 15 receives the memory write enable signal MEM_WE. The write address generation block 15 generates a memory write address MEM_WA in response to the memory write enable signal MEM_WE and supplies it to the memory block 12. The write address generation block 15 stops supplying the memory write address MEM_WA in response to the read disapproval signal READ_NG.

  The read address generation block 16 receives the read permission signal READ_OK. The read address generation block 16 supplies the memory read address MEM_RA and the memory read permission signal MEM_RE to the memory block 12 in response to the read permission signal READ_OK.

  In response to the memory read address MEM_RA and the memory read permission signal MEM_RE, the memory block 12 generates the FIFO write data FIFO_WD and the FIFO write valid signal FIFO_WVALID, and supplies the FIFO write data FIFO_WDVALID to the subsequent speed conversion FIFO 4.

  Below, operation | movement of the filtering circuit 3 of this embodiment is demonstrated. 6 and 7 are timing charts illustrating the operation of the filtering circuit 3 of this embodiment. FIG. 6 illustrates the operation of the filtering circuit 3 when the data relay apparatus 1 receives a frame (packet) of 64 bytes or more. FIG. 7 illustrates the operation of the filtering circuit 3 when the data relay apparatus 1 receives a frame (packet) of less than 64 bytes.

  Referring to FIG. 6, in the operation when a frame (packet) of 64 bytes or more is received, LAN data LAN_DT and LAN enable signal LAN_EN are received at time t1. At this time, the byte count value BYTE_CNT of the packet size detection block 14 is set to 0. Thereafter, the end of the frame (packet) is determined when LAN_EN becomes inactive.

  At time t2, the SFD detection block 13 detects the SFD in order to recognize the head of the frame (packet). Specifically, the SFD detection block 13 receives regular data (preamble) from LAN_DT after LAN_EN becomes active, but the data becomes irregular by 1 bit at a certain timing. This is judged as SFD, and the next data of SFD is recognized as the head of the frame (packet). The SFD detection block 13 deletes the preamble and the SFD, and supplies data to be written to the memory (memory write data MEM_WD) and a memory write enable signal MEM_WE to the subsequent circuit block. Further, the SFD detection block 13 supplies the packet valid signal PKT_VALID to the packet size detection block 14 in response to the detection of the SFD. The write address generation block 15 generates a memory write address MEM_WA as a write address of the memory block 12 corresponding to the memory write data MEM_WD by the write enable signal generated by the SFD detection block 13.

  After time t2, the counter 17 of the packet size detection block 14 monitors the number of bytes of the frame (packet) with a signal (packet valid signal PKT_VALID) for indicating that the frame (packet) is valid. Based on the monitoring result, the determination unit 18 generates a command (read permission signal READ_OK) for starting the read if it is 64 bytes or more.

  As shown in FIG. 6, at time t3, it is determined that the number of bytes in the packet size detection block 14 frame (packet) is 64 bytes or more. At time t4, the packet size detection block 14 generates a read permission signal READ_OK and supplies it to the read address generation block 16.

  When the read permission signal READ_OK is output from the packet size detection block 14, the read address generation block 16 notifies the memory block 12 of an enable signal (memory read permission signal MEM_RE) and a memory read address MEM_RA. To do. In response to the memory read permission signal MEM_RE and the memory read address MEM_RA, a frame (packet) is read from the memory block 12. The read data is supplied to the subsequent speed conversion FIFO 4. The data read from the memory block 12 is supplied to the speed conversion FIFO 4 as FIFO write data FIFO_WD. The filtering circuit 3 outputs a VALID signal of a frame (packet) and a write enable signal of FIFO.

  The operation when a frame (packet) of less than 64 bytes is received will be described. Referring to FIG. 7, the operations from receiving LAN data LAN_DT and LAN enable signal LAN_EN to monitoring the number of bytes of a frame (packet) are the same as when receiving a frame (packet) of 64 bytes or more. .

  As shown in FIG. 7, at time t5, the packet size detection block 14 monitors the number of bytes of the frame (packet) by the VALID signal (packet valid signal PKT_VALID) for the frame (packet), and It is determined that the (packet) size is less than 64 bytes. At time t6, the packet size detection block 14 supplies the write address generation block 15 with a signal (read non-permission signal READ_NG) indicating that the frame (packet) is less than 64 bytes.

  When the frame (packet) size is less than 64 bytes, the write address generation block 15 returns the write address to the start address of the discard frame (packet). The write address generation block 15 counts up from the address in response to the write enable of the next frame (packet).

  As described above, after the SFD is recognized as the head of the actual data in the filtering circuit 3 of the present embodiment, the write address generation block 15 generates (counts up) the write address therefrom. The write address generation block 15 holds the final address at which the previous write has been completed. The write address generation block 15 starts from the final address and thereafter counts up from there. When the address reaches the Full state, it returns to zero and counts up.

  As described above, when the data length is less than 64 bytes, the filtering circuit 3 according to the present embodiment returns the write address to the last address at which the previous write was completed. Then, the returned address is started and counted up again with the next packet. The read address starts counting up when the counter monitoring the packet length recognizes 64 bytes or more. The read address is also counted up from the last address where the previous read was completed.

[Comparative example]
Below, the comparative example of this embodiment is demonstrated. FIG. 8 is a timing chart for explaining a comparative example of the present embodiment. FIG. 8 illustrates the operation of the data relay device 1 that does not include the filtering circuit 3 of the present embodiment. As shown in FIG. 8, when a short frame (packet) is generated, the data relay device 1 that does not include the filtering circuit 3 transmits the useless short frame (packet). Therefore, the transfer efficiency in the entire network is lowered.

  Further, the technique of the above-mentioned patent document includes a filtering circuit configured by a register for the purpose of discarding a short frame (packet). FIG. 9 is a block diagram conceptually showing the configuration of the filtering circuit constituted by registers. The circuit shown in FIG. 9 includes a data signal shift unit, a level conversion unit, a control signal shift unit, a packet size detection block, and a VALID generation unit.

  The data signal shift unit shifts the packet data input DIN by 4 bytes (32 bits) and outputs the packet data output DOUT. The Level converter extends the PLS input 1-bit pulse by 1 byte (8 bits). The control signal shift unit shifts and outputs the output signal extended by 1 byte (8 bits) by 4 bytes (32 bits) by the level conversion unit.

  The packet size detection unit generates a signal for mask control on the output signal from the control signal shift unit. Also, a short packet of less than 4 bytes is detected. The VALID generation unit is a NOR logic circuit that receives an output signal from the control signal shift unit and an output signal from the packet size detection unit, and outputs the output signal VALID_OUT after mask processing.

  FIG. 10 is a layout diagram showing a layout of a filtering circuit constituted by registers. As shown in FIG. 10, when the filtering circuit has a register configuration, it is difficult to centrally arrange individual FFs at the time of layout. For this reason, the wiring delay varies, and high speed operation cannot be supported. Further, it is not easy to correct the circuit when the frame (packet) size, which is a filtering condition, is changed.

  The data relay device 1 according to the present embodiment discards a short frame (packet) of less than 64 bytes, thereby increasing frame (packet) transfer efficiency. The filtering circuit 3 of the data relay device 1 according to the present embodiment includes a memory block 12. By configuring the storage area for holding the frame with a memory, it is possible to reduce variations in wiring variations and circuit changes. This makes it possible to configure the data relay device 1 that can easily avoid the influence of degradation or the like. Also, by discarding short frames (packets) of less than 64 bytes, it is possible to avoid problems caused by unexpected operations and to reduce power consumption by avoiding unnecessary frame (packet) transfers.

[Second Embodiment]
Below, 2nd Embodiment of this invention is described. FIG. 11 is a block diagram illustrating the configuration of the second embodiment of the filtering circuit 3 of the data relay device 1 of the present invention. In the filtering circuit 3 of the second embodiment, the determination unit 18 includes a comparison value holding region 21. The comparison value holding area 21 is configured so that the comparison value can be changed. By changing the comparison value of the determination unit 18, it is possible to change the frame (packet) size of the filtering condition in the filtering circuit 3. As a result, the filtering circuit 3 of the second embodiment not only discards short frames (packets) of less than 64 bytes, but also easily copes with changes in the frame (packet) size that is a filtering condition. Is possible.

  The embodiment of the present invention has been specifically described above. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

[Appendix]
(Supplementary Note 1) A filtering circuit that receives a frame supplied via a LAN (Local Area Network) line;
A speed conversion FIFO that is arranged in a subsequent stage of the filtering circuit and holds data obtained by removing the preamble from the frame;
It is arranged after the speed conversion FIFO, reads the data stored in the speed conversion FIFO, generates WAN (Wide Area Network) data, and uses the WAN (Wide Area Network). A WAN data generator for supplying data to a WAN (Wide Area Network) line,
The above filtering circuit is
An SFD detection unit that extracts a data portion from the frame based on an SFD (Start Frame Delimiter) of the frame;
A memory block for holding the data portion supplied from the SFD detector;
A data size detection unit for determining whether the data size of the data portion supplied from the SFD detection unit is less than a minimum allowable data size;
A write memory address generation unit for designating a write memory address when storing the data portion in the memory block,
The above data size detector
When the data portion of the current frame when the frame is the current frame is less than the minimum data size, a transfer prohibit command is generated,
The above write memory address generation unit
In response to the transfer prohibition instruction, a write memory address is specified that overwrites the data portion of the current frame stored in the memory block with the data portion of the next frame of the current frame. Data relay device.

(Appendix 2) In the above data relay device,
The SFD detection unit is
In response to the start of extraction of the data part, a write start instruction is supplied to the write memory address generation unit,
The above write memory address generation unit
After receiving the transfer prohibition instruction and when receiving a write start instruction for the data portion of the next frame, as a write memory address for storing the data portion of the next frame, A data relay device that designates a write memory address that overwrites a data portion less than the minimum data size stored in the memory block.

(Appendix 3) In the above data relay device,
The above write memory address generation unit
The write memory address when storing the above data part in the above memory block is designated by a continuous address,
After receiving the above transfer prohibition instruction and when receiving a write start instruction for the data portion of the next frame, the start memory address of the continuous address is set to the data portion of the next frame. Specify it as the write memory address when storing the beginning,
A data relay device that designates a continuous address from the top memory address as a write memory address when storing the data portion of the next frame.

(Appendix 4) In the above data relay device,
The above filtering circuit further includes:
A read memory address generation unit that specifies a read memory address when reading the data portion from the memory block,
The above data size detector
When the data portion is equal to or larger than the minimum data size, a read start instruction is supplied to the read memory address generation unit,
The above read memory address generation unit
In response to the read start command, the read memory address and the read permission signal are supplied to the memory block.
The memory block above is
A data relay device for supplying the data portion read in correspondence with the read memory address to the speed conversion FIFO.

(Appendix 5) In the above data relay device,
The above data size detector
A counter that outputs a counter value indicating a measurement result obtained by measuring the data size of the data portion;
The comparison setting value used for comparison with the counter value is held, and the data size of the data portion is set to the minimum value based on the comparison result between the counter value and the comparison setting value. A determination unit for determining whether the data size is less than or not,
The determination unit is
A data relay device that holds the set value for comparison so that the minimum data size is 64 bytes.

(Appendix 6) In the above data relay device,
The determination unit is
A data relay device that updates the comparison set value in response to the comparison set value change command.

(Appendix 7) In the above data relay device,
The memory block above is
A memory cell array having a plurality of memory cells arranged in an array;
A control circuit for controlling input / output of data to / from the memory cell array,
The above control circuit is
A data relay device that specifies a storage area of the memory cell array based on the write memory address and stores the data portion supplied from the SFD detection unit in the storage area.

DESCRIPTION OF SYMBOLS 1 ... Data relay apparatus 2 ... Data conversion block 3 ... Filtering circuit 4 ... Speed conversion FIFO
5 ... WAN data creation unit 6 ... LAN
7 ... WAN
DESCRIPTION OF SYMBOLS 11 ... Chip substrate 12 ... Memory block 12a ... Memory cell 12b ... Y decoder 12c ... X decoder 13 ... SFD detection block 14 ... Packet size detection block 15 ... Write address generation block 16 ... Read address generation block 17 ... Counter 18 ... Determination part 21 ... Comparison value holding area LAN_EN ... LAN enable signal LAN_DT ... LAN data FIFO_WVALID ... FIFO write valid signal FIFO_WD ... FIFO write data FIFO_RVALID ... FIFO read valid signal FIFO_RD ... FIFO read data WAN_DT ... WAN data MEM_WD ... Memory write data MEM_MEM_MEM_WD Memory write enable signal MEM_WA ... Memory write address PKT_VALID ... Packet valid signal REA _NG ... read inhibit signal READ_OK ... read enable signal MEM_RA ... memory read address MEM_RE ... memory read enable signal PKT_VALID ... packet valid signal BYTE_CNT ... byte count value

Claims (8)

A filtering circuit that receives and filters frames supplied via a LAN (Local Area Network) line,
The filtering circuit includes:
An SFD detection unit that extracts a data portion from the frame based on an SFD (Start Frame Delimiter) of the frame;
A memory block that holds the data portion supplied from the SFD detector;
A data size detection unit for determining whether the data size of the data portion supplied from the SFD detection unit is less than a minimum allowable data size;
A write memory address generation unit for designating a write memory address when storing the data portion in the memory block;
The data size detection unit
When the data portion of the current frame when the frame is the current frame is less than the minimum data size, a transfer prohibit command is generated,
The write memory address generation unit
A filtering circuit for designating a write memory address that overwrites the data portion of the current frame stored in the memory block with the data portion of the next frame of the current frame in response to the transfer inhibition command; The filtering circuit of claim 1,
The SFD detection unit
In response to the start of extraction of the data portion, a write start instruction is supplied to the write memory address generation unit,
The write memory address generation unit
After receiving the transfer prohibition command and when receiving a write start command for the data portion of the next frame, a write memory address for storing the data portion of the next frame is stored in the memory block. A filtering circuit for designating a write memory address that overwrites a stored data portion smaller than the minimum data size. The filtering circuit according to claim 2, wherein
The write memory address generation unit
A write memory address when storing the data portion in the memory block is designated by a continuous address,
After receiving the transfer prohibition command and when receiving a write start command for the data portion of the next frame, the head memory address of the continuous address is stored as the head of the data portion of the next frame Specify as write memory address when
A filtering circuit that designates a continuous address from the start memory address as a write memory address when storing a data portion of the next frame. The filtering circuit according to any one of claims 1 to 3,
further,
A read memory address generation unit for designating a read memory address when reading the data portion from the memory block;
The data size detection unit
When the data portion is equal to or larger than the minimum data size, a read start instruction is supplied to the read memory address generation unit,
The read memory address generation unit
In response to the read start command, the read memory address and a read permission signal are supplied to the memory block,
The memory block is
A filtering circuit that provides the data portion read in correspondence with the read memory address to a speed conversion FIFO. The filtering circuit according to any one of claims 1 to 4,
The data size detection unit
A counter that outputs a counter value indicating a measurement result obtained by measuring the data size of the data portion;
A comparison setting value used for comparison with the counter value is held, and based on a comparison result between the counter value and the comparison setting value, whether the data size of the data portion is less than the minimum data size or not A determination unit for determining whether or not
The determination unit
A filtering circuit that holds the setting value for comparison so that the minimum data size is 64 bytes. The filtering circuit according to claim 5, wherein
The determination unit
A filtering circuit that updates the set value for comparison in response to an instruction to change the set value for comparison. The filtering circuit according to any one of claims 1 to 6,
The memory block is
A memory cell array having a plurality of memory cells arranged in an array;
A control circuit for controlling input / output of data to / from the memory cell array,
The control circuit includes:
A filtering circuit that identifies a storage area of the memory cell array based on the write memory address and stores the data portion supplied from the SFD detection unit in the storage area. A filtering circuit for receiving a frame supplied via a LAN (Local Area Network) line;
A speed conversion FIFO which is arranged in a subsequent stage of the filtering circuit and holds data obtained by removing a preamble portion from the frame;
It is arranged after the speed conversion FIFO, reads the data held in the speed conversion FIFO, generates WAN (Wide Area Network) data, and generates the WAN (Wide Area Network) data as WAN ( Wide Area Network) WAN data generation unit for supplying to the line,
The filtering circuit includes:
An SFD detection unit that extracts a data portion from the frame based on an SFD (Start Frame Delimiter) of the frame;
A memory block that holds the data portion supplied from the SFD detector;
A data size detection unit for determining whether the data size of the data portion supplied from the SFD detection unit is less than a minimum allowable data size;
A write memory address generation unit for designating a write memory address when storing the data portion in the memory block;
The data size detection unit
When the data portion of the current frame when the frame is the current frame is less than the minimum data size, a transfer prohibit command is generated,
The write memory address generation unit
A data relay device that designates a write memory address that overwrites the data portion of the current frame stored in the memory block with the data portion of the next frame of the current frame in response to the transfer inhibition command.

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