CN103560977A - E1 framing controller with accurate allocation capacity for output delay and working method - Google Patents
E1 framing controller with accurate allocation capacity for output delay and working method Download PDFInfo
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Abstract
The invention discloses an E1 framing controller with an accurate allocation capacity for output delay and a working method. The controller comprises a bus interface unit, an FIFO and related control logical unit, a parameter configuration and storage unit and an E1 framing device. The bus interface unit is used for interfaces between units in the E1 framing controller and a CPU or business processing units in external gateway equipment; the FIFO and related control logical unit is used for storing and buffering E1 payload data and starting the E1 framing device; the parameter configuration and storage unit transmits output signals to the E1 framing device, is used for transmitting schema configuration information and signaling information and used for transmitting the output signals to the FIFO and related control logical unit to control read and output of the FIFO; the E1 framing device is used for performing parallel-serial conversion on the E1 payload data and outputting the data in a framing mode. The E1 framing controller and the working method improve the integration level of a system, provide the uniform data access interfaces simultaneously, set shake buffer delay parameters, a time slot occupation configuration table and channel associated signallings, and omit an external storage and a corresponding store controller unit.
Description
Technical field
The present invention relates to have output delay accurately E1 one-tenth frame controller and the method for work of allocative abilities.
Background technology
Packet switching network (PSN) or group transmission network (PTN) are the transport networks towards Packet Service, can pass through the transmission that Pseudo Wire Emulation Edge-to-Edge (PWE3, with reference to RFC3985 standard) is supported TDM service (as E1/T1/E3/STM-n etc.).Corresponding tunneling standard is that structureless SAToP (with reference to RFC4553), structurized CESoPSN(are with reference to RFC5086) and TDMoIP(with reference to RFC5087).
Due to the intrinsic network congestion of group transmission network, network node load is inconsistent and route changing causes message to there are differences (being called delay variation) time of advent, for TDM service, gateway device just must adopt wobble buffer to compensate message time delay difference.The message data receiving enters wobble buffer in the different moment, and after buffer buffers, data can be left buffering area with constant speed, thereby can export uniformly stable tdm traffic, send to subscriber equipment.Wobble buffer need possess from being cached to the ability that can freely arrange the time of delay of output, to adapt to different packet transmission networks characteristics.
At present, the U.S. letter of Maxim() company has released a series of TDMoP chips, mainly comprises: DS34T10x series, DS34S10x is serial, DS34S132 is serial.
Said chip dynamic delay wobble buffer is realized by external memory, by executing, amplifies external memory, can effectively improve delay variation buffer capacity (by increasing the degree of depth of delay variation buffer), increases the flexibility of application.But, to the less application scenarios of time of delay sensitivity and network delay shake, just there is no need to use large capacity external memory, and use external memory can increase to a certain extent the not confirmability of processor expense and running time, can increase system cost, system dimension and failure probability simultaneously.
Summary of the invention
Object of the present invention is exactly in order to address the above problem, and provides and has output delay accurately E1 one-tenth frame controller and the method for work of allocative abilities.The minimum interval that postpones to control is 3.9 μ s.It has improved the integrated level of system, unified data access interface is provided simultaneously, can arrange the numerical value of jitter buffer delay parameter, Time Slot Occupancy allocation list, channel associated signalling (at TS16 time slot), save external memory and corresponding storage control unit advantage.
To achieve these goals, the present invention adopts following technical scheme:
There is the accurately E1 one-tenth frame controller of allocative abilities of output delay, comprising:
Bus Interface Unit, data and address signal that CPU in reception gateway device or Service Processing Unit are sent, and respectively data-signal is sent into FIFO and relevant control logical block and parameter configuration memory cell, described Bus Interface Unit becomes frame controller internal element and the CPU of exterior gateway equipment or the interface between Service Processing Unit for E1;
FIFO and relevant control logical block, receive the signal of parameter configuration memory cell, and data flow and control stream exported to E1 framer, and described FIFO and relevant control logical block are for storage, buffering E1 payload data and start E1 framer;
Parameter configuration memory cell, is transferred to E1 framer by output signal, for transfer mode configuration information and signaling information; Output signal is transferred to FIFO and relevant control logical block, for what control FIFO, reads and export control;
E1 framer, for E1 payload data is carried out to parallel-serial conversion, and framing ground is exported.
Described Bus Interface Unit, comprising:
Address decoding unit, the input of described address decoding unit is respectively A2, A1 and A0 tri-bit address lines enable mouth with writing, and the output of described address decoding unit is connected with signaling information register with FIFO, time slot configuration memory, delay parameter and mode register respectively; Described address decoding unit is written to different memory cell for control interface data.
Described parameter configuration memory cell comprises:
Time slot configuration memory, the input of described time slot configuration memory is respectively that A2 and A1 two bit address lines, time slot configuration are write enable signal, write data line and read time slot configuration memory address line, the output of described time slot configuration memory is connected with E1 framer by sending into the time slot enable signal line of E1 framer, the output of described time slot configuration memory is also read control logic unit by time slot enable signal line with FIFO and is connected, and described time slot configuration memory is used for preserving 32 E1 time slots and enables to control;
Delay parameter and mode register, the input of described delay parameter and mode register is connected with write data line, the input of described delay parameter and mode register also passing threshold is write enable signal line wr_threshold and is connected with address decoding unit, the output of described delay parameter and mode register is read control logic unit by model selection line with FIFO respectively and is connected, by pattern configurations control line, be connected with E1 framer and be connected with FIFO by delay parameter data wire, described delay parameter and mode register are used for preserving jitter buffer delay parameter and model selection,
Signaling information register, the input of described signaling information register is write enable signal line wr_ce by signaling information and is connected with address decoding unit, the input of described signaling information register is also connected with write data line, the output of described signaling information register is connected with E1 framer by signaling information data wire, and described signaling information register is for preserving the signaling information of E1 frame.
Described FIFO and relevant control logic comprise:
FIFO reads control logic unit, the input that described FIFO reads control logic unit is connected with time slot configuration memory, is connected with the fifo signal line of reading by E1 framer is connected with E1 framer by model selection line with delay parameter and modular register by time slot enable signal line respectively, the output that described FIFO reads control logic unit is connected with FIFO by FIFO read control signal line, and described FIFO reads control logic unit for controlling reading of E1 payload data in FIFO;
FIFO, the input of described FIFO is read control logic unit by FIFO read control signal line with FIFO and is connected, the input of described FIFO is also connected with write data line, the input of described FIFO is also write enable signal line wr_fifo by FIFO and is connected with address decoding unit, the input of described FIFO is connected with delay parameter and mode register by delay parameter data wire, the output of described FIFO is connected with E1 framer by FIFO read data line, the output of described FIFO is also connected with startup control logic unit by " programming is full " holding wire, FIFO is also connected with " almost full " signal designation port by " almost full " holding wire, described FIFO is realized by asynchronous FIFO memory cell, data width is 8, storage depth customizes as required, asynchronous FIFO memory cell is for buffer memory E1 payload data,
Start control logic unit, the input of described startup control logic unit is connected with the output of FIFO by " programming is full " holding wire, the output of described startup control logic unit is connected with E1 framer by E1 framer enabling signal line, and described startup control logic unit is used for starting E1 framer and starts working.
Described E1 framer comprises:
FAS unit (Frame Alignment Signal frame alignment signal), reading and going here and there and conversion, the generation of Frame Alignment Signal (FAS), the generation of time slot counter for E1 payload data;
CRC4 unit (Cyclic Redundancy Check4-4 bit cyclic redundancy), for the calculating of 4 bit cyclic redundancy of E1 frame sub-block and be inserted into E1 frame.
There is the accurately method of work of the E1 one-tenth frame controller of allocative abilities of output delay, mainly comprise the steps:
Step (1): enable mouthful as high level when writing, and system clock mouth is while being high level, determines that the content of write data line is sent into different internal storages by different addresses is set; Described different internal storage comprises time slot configuration memory, FIFO, delay parameter and mode register and signaling information register; Described FIFO is for buffer memory E1 payload data; Described time slot configuration memory is used for preserving 32 E1 time slots and enables to control; Described delay parameter and a mode register part are used for preserving jitter buffer delay parameter, and a part is for model selection; Described signaling information register is for preserving the signaling information of E1 frame;
Step (2): if when the inner E1 payload data of FIFO is full, " almost full " index signal can be sent signal designation, writes data and can suspend the data writing to FIFO;
Step (3): when the E1 payload data amount writing in FIFO surpasses delay parameter, " programming is full " signal becomes high level, in starting control logic unit, should be latched by " programming is full " signal, even if " programming is full " signal is set to low level owing to reading FIFO, output signal can be maintained high level always, starts E1 framer and starts working; In FIFO, amount of buffered data approaches fullly, and while reaching the FIFO degree of depth-1 byte, can put " almost full " signal is high level, and the CPU in notification gateway equipment or Service Processing Unit stop the write operation to FIFO;
Step (4):
When adopting SAToP agreement, be that model selection line is high level, E1 framer periodically reads FIFO, every 8 E1 clocks output read signal, FIFO reads the read signal of control logic cell enable E1 framer, fifo signal is read in output, thereby from FIFO, reads 1 byte data, by FIFO read data line, sends into E1 framer.
When adopting CESoPSN agreement, be that model selection line is low level, E1 framer is exported 5 digit time slot counters, as address access time slot, enable memory, 1 bit value of output determines whether to use current time slots, if " 1 ", FIFO reads control logic cell enable and reads fifo signal, from FIFO, read 1 byte data, send into E1 framer and send, otherwise FIFO reads control logic unit shielding FIFO read signal; Time slot configuration bit is sent into E1 framer by time slot enable signal line, and when time slot is not used, E1 framer can be exported " 0 " signal entirely at this time slot;
Step (5): if SAToP pattern will shield inner FAS module and CRC4 module;
If CESoPSN pattern will be enabled FAS module, whether enable CRC4 module and controlled by model selection position;
When selecting TS16 time slot to be used for transmitting channel associated signalling, signaling information is sent into E1 framer by signaling information data wire line.
Beneficial effect of the present invention:
1 the present invention adopts hardware description language to realize the E1 that FIFO memory is integrated with controller to become frame controller, avoid using external memory, improved the integrated level of system.Unified data access interface is provided simultaneously, can arranges jitter buffer delay parameter, Time Slot Occupancy allocation list, channel associated signalling (TS16) numerical value.Its structural design is supported SAToP and two kinds of encapsulation format of CESoPSN of in RFC4553 and RFC5086 agreement, defining, and allows any time slot of CESoPSN form to use setting.Design available hardware descriptive language form provides, and FPGA easy to use or ASIC realize.
2 the invention provides unified data-interface, can simplify the operation of Service Processing Module; Integrated built-in FIFO has simplified system configuration, has saved external memory and corresponding storage control unit.
Accompanying drawing explanation
Fig. 1 entire system block diagram;
Fig. 2 system block diagram;
Fig. 3 writes enable logic;
Fig. 4 starts control logic figure;
Fig. 5 FIFO reads control logic figure;
Wherein, 1, FIFO, 11, write data line, 12, delay parameter data wire, 13, signaling information data wire, 15, pattern configurations control line, 16, FIFO read data line, 17, " almost full " holding wire, 18, read time slot configuration memory address line, 19, E1 framer DOL Data Output Line, 2, E1 framer, 21, FAS module, 22, CRC4 module, 4, address decoding unit, 41, write and enable mouth, 42, A2, A1 and A0 tri-bit address lines, 43, FIFO writes enable signal line wr_fifo, 44, time slot configuration is write enable signal line wr_slot, 45, threshold value is write enable signal line wr_threshold, 46, signaling information is write enable signal line wr_ce, 421, A2 and A1 two bit address lines, 5, start control logic unit, 51, " programming is full " holding wire, 52, E1 framer enabling signal line, 6, FIFO reads control logic unit, 61, time slot enable signal line, 62, model selection line, 63, E1 framer read fifo signal line, 64, FIFO read control signal line, 611, send into the time slot enable signal line of E1 framer, 7, time slot configuration memory, 8, delay parameter and mode register, 9, signaling information register, 10, Bus Interface Unit, 20, FIFO and relevant control logical block, 30, parameter configuration memory cell.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the invention will be further described.
There is the accurately E1 one-tenth frame controller of allocative abilities of output delay, comprising:
Bus Interface Unit 10, data and address signal that CPU in reception gateway device or Service Processing Unit are sent, and respectively data-signal is sent into FIFO and relevant control logical block and parameter configuration memory cell, described Bus Interface Unit becomes frame controller internal element and the CPU of exterior gateway equipment or the interface between Service Processing Unit for E1;
FIFO and relevant control logical block 20, receive the signal of parameter configuration memory cell, and data flow and control stream exported to E1 framer 2, and described FIFO and relevant control logical block are for storage, buffering E1 payload data and start E1 framer 2;
Parameter configuration memory cell 30, is transferred to E1 framer 2 by output signal, for transfer mode configuration information and signaling information; Output signal is transferred to FIFO and relevant control logical block, for what control FIFO, reads and export control;
E1 framer 2, for E1 payload data is carried out to parallel-serial conversion, and framing ground is exported.
Described Bus Interface Unit, comprising:
Address decoding unit 4, the input of described address decoding unit 4 is respectively A2, A1 and A0 tri-bit address lines 42 enable mouth 41 with writing, and the output of described address decoding unit 4 is connected with signaling information register 9 with FIFO1, time slot configuration memory 7, delay parameter and mode register 8 respectively; Described address decoding unit 4 is written to different parameter configuration memory cell for control interface data.
Described parameter configuration memory cell comprises:
Time slot configuration memory 7, the input of described time slot configuration memory 7 is respectively that A2 and A1 two bit address lines 421, time slot configuration are write enable signal line wr_slot44, write data line 11 and read time slot configuration memory address line 18, the output of described time slot configuration memory 7 is connected with E1 framer 2 by sending into the time slot enable signal line 611 of E1 framer, the output of described time slot configuration memory 7 is also read control logic unit 6 by time slot enable signal line 61 with FIFO and is connected, and described time slot configuration memory 7 enables to control for preserving 32 E1 time slots;
Delay parameter and mode register 8, the input of described delay parameter and mode register 8 is connected with write data line 11, the input of described delay parameter and mode register 8 also passing threshold is write enable signal line wr_threshold45 and is connected with address decoding unit 4, the output of described delay parameter and mode register 8 is read control logic unit 6 by model selection line 62 with FIFO respectively and is connected, by pattern configurations control line 15, be connected with E1 framer 2 and be connected with FIFO1 by delay parameter data wire 12, described delay parameter and mode register 8 are for preserving jitter buffer delay parameter and model selection,
Signaling information register 9, the input of described signaling information register 9 is write enable signal line wr_ce46 by signaling information and is connected with address decoding unit 4, the input of described signaling information register 9 is also connected with write data line 11, the output of described signaling information register 9 is connected with E1 framer 2 by signaling information data wire 13, and described signaling information register 9 is for preserving the signaling signaling information of E1 frame.
Described FIFO and relevant control logic comprise:
FIFO reads control logic unit 6, the input that described FIFO reads control logic unit 6 is connected with time slot configuration memory 7, is connected with the fifo signal line 63 of reading by E1 framer is connected with E1 framer 2 by model selection line 62 with delay parameter and mode register 8 by time slot enable signal line 61 respectively, the output that described FIFO reads control logic unit 6 is connected with FIFO1 by FIFO read control signal line 64, and described FIFO reads control logic unit 6 for controlling reading of E1 payload data in FIFO1;
FIFO1, the input of described FIFO1 is read control logic unit 6 by FIFO read control signal line 64 with FIFO and is connected, the input of described FIFO1 is also connected with write data line 11, the input of described FIFO is also write enable signal line wr_fifo43 by FIFO and is connected with address decoding unit 4, the input of described FIFO1 is connected with delay parameter and mode register 8 by delay parameter data wire 12, the output of described FIFO1 is connected with E1 framer 2 by FIFO read data line 16, the output of described FIFO1 is also connected with startup control logic unit 5 by " programming is full " holding wire 51, FIFO1 is also connected with " almost full " signal designation port by " almost full " holding wire 17, described FIFO1 is realized by asynchronous FIFO memory cell, data width is 8, storage depth customizes as required, asynchronous FIFO memory cell is for buffer memory E1 payload data,
Start control logic unit 5, the input of described startup control logic unit 5 is connected with the output of FIFO1 by " programming is full " holding wire 51, the output of described startup control logic unit 5 is connected with E1 framer 2 by E1 framer enabling signal line 52, starts working for starting E1 framer 2 in described startup control logic unit 5.
Described E1 framer 2 comprises:
FAS module 21(Frame Alignment Signal frame alignment signal), reading and going here and there and conversion, the generation of Frame Alignment Signal (FAS), the generation of time slot counter for E1 payload data;
CRC4 module 22(cyclic redundancy check4-4 bit cyclic redundancy), for the calculating of 4 bit cyclic redundancy of E1 frame sub-block and be inserted into E1 frame.
The output of described E1 framer 2 is connected with E1 framer DOL Data Output Line 19.
There is the accurately method of work of the E1 one-tenth frame controller of allocative abilities of output delay, mainly comprise the steps:
Step (1): enable mouthfuls 41 for high level when writing, and system clock mouth is while being high level, determines that the content of write data line 11 is sent into different internal storages by different addresses is set; Described different internal storage comprises time slot configuration memory 7, FIFO1, delay parameter and mode register 8 and signaling information register 9; Described FIFO1 is for buffer memory E1 payload data; Described time slot configuration memory 7 enables to control for preserving 32 E1 time slots; Described delay parameter and mode register 8 parts are used for preserving jitter buffer delay parameter, and a part is for model selection; Described signaling information register 9 is for preserving the signaling information of E1 frame;
Step (2): if when the inner E1 payload data of FIFO1 is full, " almost full " index signal line 17 can send " almost full " index signal indication, writes data and can suspend the data writing to FIFO1;
Step (3): when the E1 payload data amount writing in FIFO1 surpasses delay parameter, " programming is full " signal becomes high level, in starting control logic unit 5, should be latched by " programming is full " signal, even if " programming is full " signal is set to low level owing to reading FIFO, output signal can be maintained high level always, starts E1 framer 2 and starts working; In FIFO1, amount of buffered data approaches fullly, and while reaching the FIFO degree of depth-1 byte, can put " almost full " signal is high level, and the CPU in notification gateway equipment or Service Processing Unit stop the write operation to FIFO;
Step (4):
When adopting SAToP agreement, be that model selection line 62 is high level, E1 framer 2 periodically reads FIFO, every 8 E1 clocks output read signal, FIFO reads the read signal output that control logic unit 6 enables E1 framer 2 and reads fifo signal, thereby from FIFO, read 1 byte data, by FIFO read data line 16, send into E1 framer 2.
When adopting CESoPSN agreement, be that model selection line 62 is low level, E1 framer 2 output 5 digit time slot counters, as address access time slot, enable memory, 1 bit value of output determines whether to use current time slots, if " 1 ", FIFO reads control logic unit 6 enable read fifo signals, from FIFO, read 1 byte data, send into E1 framer 2 and send, otherwise FIFO reads control logic unit 6 shielding FIFO read signals; Time slot configuration bit is sent into E1 framer 2 by time slot enable signal line, and when time slot is not used, E1 framer 2 can be exported " 0 " signal entirely at this time slot;
Step (5): if SAToP pattern will shield inner FAS module 21 and CRC4 module 22;
If CESoPSN pattern will be enabled FAS module 21, whether enable CRC4 module 22 and controlled by model selection position;
When selecting TS16 to be used for transmitting channel associated signalling, signaling information is sent into E1 framer 2 by signaling information data wire line.
The input port of this controller comprises: 8 bit data mouths, and 3 bit address mouths, 1 enables mouth, 1 system clock mouth, 1 E1 clock mouth, writes for 1 and enables mouthfuls 41, and other ports such as reset; Output port comprises 1 E1 data output, 1 " almost full " signal (when amount of buffered data reaches the FIFO degree of depth-1 byte in FIFO) indication port, and other ports.Inside comprises: 2,1 FIFO of 1 E1 framer, 14 byte dual-port asynchronous memory, 12 byte register, 1 byte register, and some other logical circuits.
Fig. 1 has provided the entire block diagram of this controller.Comprise Bus Interface Unit 10, FIFO and relevant control logical block 20, parameter configuration memory cell 30 and E1 framer 2.
Wherein, Bus Interface Unit 10 is CPU in gateway device or Service Processing Unit (for example PWE3 processing unit) and the interface becoming between frame controller of the present invention, and it comprises address decoding unit 4 and related register in Fig. 2.
FIFO and relevant control logic are the main bodys that in sheet, wobble buffer is realized, and some control logics, and it comprises the FIFO1 in Fig. 2, and FIFO reads control logic unit 6 and starts control logic unit 5 three parts.
Parameter configuration memory cell is several and the closely-related parameter configuration unit of framing, comprises time slot configuration memory 7, delay parameter and mode register 8 in Fig. 2, for preserving signaling information register more than 9 parts of E1 channel associated signalling.
E1 framer 2 is concrete actuators of E1 framing.
This controller has been realized following functions:
1) when writing, enable mouthfuls 41 for high level, and system clock mouth is while being high level, according to table 1,3 bit address mouths have determined that data port content sends into different internal storages.
2) FIFO is realized by asynchronous FIFO memory cell, and data width is 8, and storage depth can customize as required.FIFO memory cell is for buffer memory E1 payload data.4 byte dual-ported memories are used for preserving 32 E1 time slots and enable to control, 2 byte register parts are used for preserving jitter buffer delay parameter (abbreviation delay parameter), a part (is for example distinguished SAToP and CESoPSN for model selection, whether use CRC4), byte register is for preserving the signaling information of E1 frame, as the byte data of TS16 time slot.
3) the outside writing module time-out of " almost full " index signal writes E1 payload data to FIFO.
4) support the PWE3 encapsulation format of SAToP and two kinds of forms of CESoPSN.According to E1 rules and the agreement of communicating pair, before output E1 data flow, need to set related register.As the isSAToP bit in model selection position, selecting the PWE3 tunneling being used, is SAToP agreement or CESoPSN agreement.If use CESoPSN, time slot need be set and enable the time slot that control storage preservation transmission is used.
5) CPU of E1 interface board or Service Processing Unit (for example PWE3 processing unit) are through sequence of operations, the E1 data that encapsulate in PWE3 are extracted, write inner FIFO, in inner FIFO, data volume surpasses jitter buffer delay parameter, export and keep " enabling signal " of high level, start framer and start working.1 unit of delay parameter is equivalent to 1 E1 bytes of payload time, is equivalent to 3.9 μ s, the minimum interval of the time of delay that can arrange and granularity.
6) when adopting SAToP agreement, E1 framer 2 periodically reads FIFO, and every 8 E1 clocks output read signal, reads FIFO1 time; Adopt CESoPSN agreement, E1 framer 2 output 5 digit time slot counters (count value from 0 to 31), as address access time slot, enable memory, 1 bit value of output determines whether to use current time slots, " 1 " if, enable read fifo signal, from FIFO, read 1 byte data, send into E1 framer 2 and send, otherwise fifo signal is read in shielding, at this time slot E1 framer 2, transmit " 0 " signal of 8 bits.
7) Fig. 2 has provided the concrete block diagram of this controller.This controller by FIFO1(as delay variation buffer), E1 framer 2, time slot configuration memory 7, delay parameter and mode register 8, signaling information register 9, and address decoding unit 4, start control logic unit 5, FIFO reads control logic control unit 6, and some holding wires form.Suppose that buffer depth is made as 1024 bytes, can be set to data width be 8 to FIFO1 so, and data depth is 1024, having the full function of programming, and the FPGA manufacturer such as Xilinx, Altera and open source software all can provide this design conventionally.Time slot configuration memory 7 adopts 4 byte dual-ported memories, the write data line 11 that width is 8, and the write address line 421 that width is 2, the read data line 61 that width is 1, width is 5 reads address wire 18.Delay parameter and mode register 8 adopts double byte registers, and wherein to take number of bits be that 10, pattern parameters are 3 to delay parameter.
Table 1
8) table 1 has been listed three bit address line A
2a
1a
0control data flow direction.By different addresses is set, the CPU in gateway device or Service Processing Unit write FIFO1, time slot configuration memory 7, delay parameter and mode register 8 and signaling information register 9 to controller.
9) Fig. 3 provides address decoding logic.When carrying out write operation, writing enable signal wr is high level, and according to three bit address lines, (address 3 bits are from high to low respectively A
2, A
1and A
0) difference, according to the requirement of table 1, controlled 4 memory cell write enable signal, as FIFO writes enable signal wr_fifo, time slot configuration is write enable signal wr_slot, threshold value writes enable signal wr_threshold and signaling information is write enable signal wr_ce, thereby 8 bit data of write data line 11 just deposit respectively FIFO1, time slot configuration memory 7, delay parameter and mode register 8 and signaling information register 9 in.The A2 of time slot configuration memory 7 and A1 two bit address lines 421 comprise A2, the A in A1 and A0 tri-bit address lines 42
2and A
1.
10) delay parameter data wire 12 is sent into FIFO " programming is full " threshold value port.When the E1 payload data amount writing in FIFO surpasses delay parameter, " programming is full " signal 51 becomes high level, in starting control logic 5, as shown in Figure 4, this signal is latched, even if " programming is full " signal 51 is set to low level owing to reading FIFO, output signal 52 can be maintained high level always, starts E1 framer 2 and starts working.In FIFO, amount of buffered data approaches fullly, and while reaching the FIFO degree of depth-1 byte, can put " almost full " signal is high level, and CPU or Service Processing Unit in notification gateway equipment stop write operation.
11) E1 framer 2 can be exported the time slot counter signal that width is 5, and as the address signal of reading of time slot configuration memory, 1 bit information of memory 7 outputs, represents to use this time slot during for high level, and this signal is useful under CESoPSN pattern.Be in particular in that FIFO reads in control logic unit 6, its concrete logic is as Fig. 5.When model selection line 62 is high level (being SAToP pattern), or low level is the use of (being CESoPSN pattern) time slot (61 is high level), enable the read signal of E1 framer 2, fifo signal is read in output, thereby from FIFO1, read 1 byte data, by FIFO read data line 16, send into E1 framer 2.Time slot configuration bit also needs to send into E1 framer 2 by sending into the time slot enable signal line 611 of E1 framer, and when time slot is not used, E1 framer 2 can be exported " 0 " signal entirely at this time slot.
12) operation principle of E1 framer 2 is described below: its inside has FAS module 21 and CRC4 module 22.According to pattern configurations control line 15, wherein comprise the selection of SAToP and CESoPSN, whether use CRC4 module 22, whether TS16 is used for transmitting Channel Associated Signaling.If SAToP pattern will shield inner FAS module 21 and CRC4 module 22; If CESoPSN pattern will be enabled FAS module 21, whether enable CRC4 module 22 and controlled by model selection position; When selecting TS16 to be used for transmitting channel associated signalling, signaling information is sent into E1 framer 2 by signaling information data wire 13.
Although above-mentioned, by reference to the accompanying drawings the specific embodiment of the present invention is described; but be not limiting the scope of the invention; one of ordinary skill in the art should be understood that; on the basis of technical scheme of the present invention, those skilled in the art do not need to pay various modifications that creative work can make or distortion still in protection scope of the present invention.
Claims (6)
1. there is the accurately E1 one-tenth frame controller of allocative abilities of output delay, it is characterized in that, comprising:
Bus Interface Unit, data and address signal that CPU in reception gateway device or Service Processing Unit are sent, and respectively data-signal is sent into FIFO and relevant control logical block and parameter configuration memory cell, described Bus Interface Unit becomes frame controller internal element and the CPU of exterior gateway equipment or the interface between Service Processing Unit for E1;
FIFO and relevant control logical block, receive the signal of parameter configuration memory cell, and data flow and control stream exported to E1 framer, and described FIFO and relevant control logical block are for storage, buffering E1 payload data and start E1 framer;
Parameter configuration memory cell, is transferred to E1 framer by output signal, for transfer mode configuration information and signaling information; Output signal is transferred to FIFO and relevant control logical block, for what control FIFO, reads and export control;
E1 framer, for E1 payload data is carried out to parallel-serial conversion, and framing ground is exported.
As claimed in claim 1 have output delay accurately the E1 of allocative abilities become frame controller, it is characterized in that, described Bus Interface Unit, comprising:
Address decoding unit, the input of described address decoding unit is respectively A2, A1 and A0 tri-bit address lines enable mouth with writing, and the output of described address decoding unit is connected with signaling information register with FIFO, time slot configuration memory, delay parameter and mode register respectively; Described address decoding unit is written to different memory cell for control interface data.
As claimed in claim 1 have output delay accurately the E1 of allocative abilities become frame controller, it is characterized in that, described parameter configuration memory cell comprises:
Time slot configuration memory, the input of described time slot configuration memory is respectively that A2 and A1 two bit address lines, time slot configuration are write enable signal, write data line and read time slot configuration memory address line, the output of described time slot configuration memory is connected with E1 framer by sending into the time slot enable signal line of E1 framer, the output of described time slot configuration memory is also read control logic unit by time slot enable signal line with FIFO and is connected, and described time slot configuration memory is used for preserving 32 E1 time slots and enables to control;
Delay parameter and mode register, the input of described delay parameter and mode register is connected with write data line, the input of described delay parameter and mode register also passing threshold is write enable signal line wr_threshold and is connected with address decoding unit, the output of described delay parameter and mode register is read control logic unit by model selection line with FIFO respectively and is connected, by pattern configurations control line, be connected with E1 framer and be connected with FIFO by delay parameter data wire, described delay parameter and mode register are used for preserving jitter buffer delay parameter and model selection,
Signaling information register, the input of described signaling information register is write enable signal line wr_ce by signaling information and is connected with address decoding unit, the input of described signaling information register is also connected with write data line, the output of described signaling information register is connected with E1 framer by signaling information data wire, and described signaling information register is for preserving the signaling information of E1 frame.
As claimed in claim 1 have output delay accurately the E1 of allocative abilities become frame controller, it is characterized in that, described FIFO and relevant control logic comprise:
FIFO reads control logic unit, the input that described FIFO reads control logic unit is connected with time slot configuration memory, is connected with the fifo signal line of reading by E1 framer is connected with E1 framer by model selection line with delay parameter and modular register by time slot enable signal line respectively, the output that described FIFO reads control logic unit is connected with FIFO by FIFO read control signal line, and described FIFO reads control logic unit for controlling reading of E1 payload data in FIFO;
FIFO, the input of described FIFO is read control logic unit by FIFO read control signal line with FIFO and is connected, the input of described FIFO is also connected with write data line, the input of described FIFO is also write enable signal line wr_fifo by FIFO and is connected with address decoding unit, the input of described FIFO is connected with delay parameter and mode register by delay parameter data wire, the output of described FIFO is connected with E1 framer by FIFO read data line, the output of described FIFO is also connected with startup control logic unit by " programming is full " holding wire, FIFO is also connected with " almost full " signal designation port by " almost full " holding wire, described FIFO is realized by asynchronous FIFO memory cell, data width is 8, storage depth customizes as required, asynchronous FIFO memory cell is for buffer memory E1 payload data,
Start control logic unit, the input of described startup control logic unit is connected with the output of FIFO by " programming is full " holding wire, the output of described startup control logic unit is connected with E1 framer by E1 framer enabling signal line, and described startup control logic unit is used for starting E1 framer and starts working.
As claimed in claim 1 have output delay accurately the E1 of allocative abilities become frame controller, it is characterized in that, described E1 framer comprises:
FAS unit, for E1 payload data read and go here and there and conversion, the generation of Frame Alignment Signal, the generation of time slot counter;
CRC4 unit, for the calculating of 4 bit cyclic redundancy of E1 frame sub-block and be inserted into E1 frame.
As described in above-mentioned arbitrary claim have output delay accurately the E1 of allocative abilities become the method for work of frame controller, it is characterized in that, mainly comprise the steps:
Step (1): enable mouthful as high level when writing, and system clock mouth is while being high level, determines that the content of write data line is sent into different internal storages by different addresses is set; Described different internal storage comprises time slot configuration memory, FIFO, delay parameter and mode register and signaling information register; Described FIFO is for buffer memory E1 payload data; Described time slot configuration memory is used for preserving 32 E1 time slots and enables to control; Described delay parameter and a mode register part are used for preserving jitter buffer delay parameter, and a part is for model selection; Described signaling information register is for preserving the signaling information of E1 frame;
Step (2): if when the inner E1 payload data of FIFO is full, " almost full " index signal can be sent signal designation, writes data and can suspend the data writing to FIFO;
Step (3): when the E1 payload data amount writing in FIFO surpasses delay parameter, " programming is full " signal becomes high level, in starting control logic unit, should be latched by " programming is full " signal, even if " programming is full " signal is set to low level owing to reading FIFO, output signal can be maintained high level always, starts E1 framer and starts working; In FIFO, amount of buffered data approaches fullly, and while reaching the FIFO degree of depth-1 byte, can put " almost full " signal is high level, and the CPU in notification gateway equipment or Service Processing Unit stop the write operation to FIFO;
Step (4):
When adopting SAToP agreement, be that model selection line is high level, E1 framer periodically reads FIFO, every 8 E1 clocks output read signal, FIFO reads the read signal of control logic cell enable E1 framer, fifo signal is read in output, thereby from FIFO, reads 1 byte data, by FIFO read data line, sends into E1 framer;
When adopting CESoPSN agreement, be that model selection line is low level, E1 framer is exported 5 digit time slot counters, as address access time slot, enable memory, 1 bit value of output determines whether to use current time slots, if " 1 ", FIFO reads control logic cell enable and reads fifo signal, from FIFO, read 1 byte data, send into E1 framer and send, otherwise FIFO reads control logic unit shielding FIFO read signal; Time slot configuration bit is sent into E1 framer by time slot enable signal line line, and when time slot is not used, E1 framer can be exported " 0 " signal entirely at this time slot;
Step (5): if SAToP pattern will shield inner FAS module and CRC4 module;
If CESoPSN pattern will be enabled FAS module, whether enable CRC4 module and controlled by model selection position;
When selecting TS16 time slot to be used for transmitting channel associated signalling, by signaling information by sending into E1 framer by signaling information data wire.
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