CN101753388B - Router and interface device suitable for the extending on and among sheets of polycaryon processor - Google Patents
Router and interface device suitable for the extending on and among sheets of polycaryon processor Download PDFInfo
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- CN101753388B CN101753388B CN2008102275183A CN200810227518A CN101753388B CN 101753388 B CN101753388 B CN 101753388B CN 2008102275183 A CN2008102275183 A CN 2008102275183A CN 200810227518 A CN200810227518 A CN 200810227518A CN 101753388 B CN101753388 B CN 101753388B
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Abstract
The present invention discloses a router and an interface device suitable for the extending on and among sheets of a polycaryon processor, which comprises a router for route calculation, exchange and transmission of received logic microchip data. The router comprises a plurality of router interfaces for directly connecting routers on other sheets, one or two local network interfaces for networks on separating sheets and processing units in sheets to convert data types and connecting the routers and the processing units in the sheets, and one or a plurality of network interfaces among the sheets for converting data outside the sheets and route network data and connecting third part of chips outside the sheets through high-speed series unstring modules or butting with network interfaces among the sheets on network chips outside the sheets with the same type. By using the present invention, for different interface or agreement types, only a network interface unit needs to be collocated, which can realize connection. Thus, the present invention is easy to extend on and among the sheets of the polycaryon processor in a uniform method, can realize correction and detection for the received data, and improves the reliability of transmission.
Description
Technical field
The present invention relates to the expansion technique field of polycaryon processor, especially a kind ofly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement.
Background technology
Along with the continuous development of large scale integrated circuit and various high-end applications to improving constantly that systematic function requires, only rely on the performance of single core processor to seem unable to do what one wishes, so the development of polycaryon processor is more and more paid close attention to by people.Along with improving constantly of technological level, the processor technology develops on the processor structure that has more kernels gradually.
Yet along with the continuous growth of processor quantity in the system, the bus structures that generally adopt can't satisfy the communicating requirement of internal system now, the substitute is a kind of NOC (network-on-chip) technology.The NOC technology is to carry out packet switch on based on the network of routing infrastructure at one to come communication between the supporting pieces coker.Because the applied environment of processor is not unique and fixing, processor is except will also needing to communicate by letter with outside various device, so require the structure of polycaryon processor to have very strong extendible ability with other processor cores are communicated by letter on the sheet.On the other hand, reliability of information transmission also is the key factor of decision communication efficiency height, and the transmission of these information all is to be finished by the route device of NOC.
NOC route device commonly used at present is traditional 5 bidirectional port routers that have, and 5 ports are respectively east, south, west, north and local interface.Adjacent with the four direction respectively router of preceding four ports joins, and local port links to each other with local processor interface.5 ports use identical signal definition.Usually the method for routing that is adopted is the packing data of needs transmission, adds that information is divided into some flit (logic microplate) later on end to end to send, and the logic microplate is transmitted according to certain routing policy by route device again.
Traditional route device only is responsible for the transmission of packet, and no matter the form and the type of data.But generally, data packet delivery agreement between the on-chip processor nuclear is different often with the data packet delivery agreement of chip chamber with chip, just requires the processor node on the sheet to design according to protocol requirement when designing in order to satisfy this different data protocol.In case host-host protocol is different, that just means needs redesign processor node with satisfied application, thereby brings a large amount of extra works.On the other hand, the packing data in traditional network-on-chip is just simply carried out segmentation to data, and adds end to end and just send after the information, in case make a mistake in the transmission course, receiving terminal also has no way of learning, has influenced the reliability of transmission.Therefore need to explore a kind of new transmission method and device and overcome these shortcomings in traditional route, thus reach energy highly reliable, be convenient to be applied on the polycaryon processor sheet and route of expanding between sheet and interface arrangement.
Summary of the invention
(1) technical problem that will solve
In view of this, it is low that the present invention has mainly solved among the existing NOC routing infrastructure reliability, be not easy on the polycaryon processor sheet and the problem of expanding with unified method between sheet, proposed a kind ofly to be applicable on the polycaryon processor sheet reliably and route of expanding between sheet and interface arrangement, this installs network interface (NI) unit between main 1 to two local network interface unit, one or more sheet that can dispose and one can form with the router that all directions are communicated with, and has increased cyclic redundancy (CRC) testing mechanism in inside.
(2) technical scheme
For achieving the above object, the technical solution used in the present invention is as follows:
A kind ofly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, this device comprises:
Router, be used for to the logic microplate data that receive carry out that route is calculated, exchange and transmitting, this router has: a plurality of router interfaces, be used for other sheets on router directly be connected;
1 or 2 local network interface is used to isolate processing unit in network-on-chip and the sheet, carries out the conversion of data type, and connects processing unit in router and the sheet;
1 or a plurality of between network interface, its number is determined according to the needed maximum transmitted port number of expansion between sheet; Be used for outer data of sheet and route network data are changed, and be connected by stringization/(SerDes) module of unstringing and sheet third-party chip outward at a high speed, perhaps with sheet outer network chip of the same type on sheet between network interface dock, thereby realize extension of network between sheet.
In the such scheme, will send when local node has data, then data are delivered to router after packing through local network interface, send to network between network-on-chip or sheet by the some router interfaces in a plurality of router interfaces of router again; Have data will deliver on the local node on several directions on the network-on-chip, then data are delivered to local network interface by router, are resolved by local network interface and deliver to processing unit in the local sheet after unpacking.
In the such scheme, described router comprises a plurality of input channels, a plurality of tunnel, a plurality of arbitration unit, cross bar switch, a plurality of output channel, allocation units, route computing unit, router state register and controller and a credit computing unit; Wherein,
Router receives logic microplate data by a plurality of input channels, and in different tunnels, each input channel is assigned with several tunnels, is used to improve network efficiency with the logic microplate deposit data that receives;
Route computing unit uses certain routing algorithm that the logic microplate data in the tunnel are carried out route and calculates, and logic microplate forwarding of data in notice router state register and the controller control router;
The output of some tunnels that arbitration unit control is corresponding with each input channel, this output is connected with cross bar switch;
The logic microplate data that certain allocation algorithm exchange that cross bar switch is determined according to allocation units is imported are at last by a plurality of output channels outputs;
The credit computing unit is according to the information of router state register and controller, export credit amount data, and an input credit data processing of information offered routing state register and controller;
Router state register and controller receive the information of credit computing unit and the information of route computing unit, the behavior of control arbitration unit and allocation units.
In the such scheme, described local network interface is a bridge of local node data type and the conversion of network-on-chip wire data type, constitute by input channel and output channel, the transport layer data that output channel is used for on-chip processor is transmitted is cut apart according to certain agreement and rule, changes into the used logic microplate data of network-on-chip transmission and outputs to network; Input channel is used for that network-on-chip is transmitted used logic microplate data and changes into the local node data type according to the same rule.
In the such scheme, described local network interface comprises:
Configuration and status register are used to deposit control information, protocol analysis information and interrupting information;
The input rank unit is used to carry out the isolation of data buffering and different clock-domains;
Import and dateout bag dual port memory unit, be used to store the data message of a complete data packet that need transmit;
Input and output state machine and control logic unit are used for analysis protocol and receive logic microplate type;
Input and output error detection verification unit are used for the data of output are carried out scrambling, and the data that receive are carried out the cyclic redundancy detection check; And
Bus control unit is used to finish total line traffic control.
In the such scheme, input channel is by input rank unit, input packet dual port memory cell, input error detection verification unit, input state machine and control logic unit, configuration and status register, and bus control unit constitutes, the logic microplate of importing into from network-on-chip passes through the data queue that channel selecting outputs to Virtual Channel, input state machine and the empty full signal of control logic output are given in formation, the read-write input signal is by input state machine and control logic output, the data input and output of control formation, and export to data memory input; Data memory input is asynchronous, be used for data cached bag and isolate different clock zones, storing process is by the output control of input state machine and control logic, input store is also exported to input state machine and control logic to the state of self, memory can also be exported to input error detection verification unit data simultaneously, carries out the verification of cyclic redundancy; After verification finished, input error detection verification meeting output status signal was given input state machine and control logic, and is correct or packet is wrong with the notice verification; Input state machine and control logic, receive the status signal of each module and control each module transmission data, when signal is finished in verification, will be by finishing total line traffic control with bus control unit, if receiving is control signal or operation acknowledge signal, then starts interrupt signal int_n and make the processor reading of data also operate; If chunk data receives back notice bus control unit and starts DMA transmission data; Input state machine and control logic can be given external routing unit to local network interface unit outside export credit amount signal according to the state of input rank simultaneously.
In the such scheme, described output channel is by bus control unit, dateout packet memory, output error detection unit, output state machine and control logic, and configuration and status register formation; Output state machine and control logic are received the input of bus control unit, when the order of transfer of data, if local network interface is idle at present, then can receive data, the output state machine control logic is packed to data according to protocol information and the state information imported in configuration and the status register, produce internal control signal and export to packet memory, control storage reads in data, the controller that input is initiated transmission command can continue to send transmission, output state machine and control logic also send according to the state of each module input and by the credit signal controlling Memory Controller that external routing unit is imported and allow read command, output state machine and control logic merge the data and the data of output detection check unit input that memory inputs to self and are converted into that router sends in the outside contact pin of logic microplate through the position in addition, and the significance bit that sends data is simultaneously set out on a journey by device to outer contact pin; Memory has the output to verification unit simultaneously, and to the output state machine output state, is used for data cached bag and clock zone to isolate, and the data of memory output will be exported to output state machine and control logic; Memory data is exported to after the output detection check unit scrambling the scrambled data buffer memory simultaneously to memory cell and export to output state machine idle running logic, and to state machine and control logic output state.
In the such scheme, network interface is made of input channel and output channel between described, and output channel is cut apart the transport layer data that sheet transmits outward according to certain agreement and rule, changes into the used logic microplate data of network-on-chip transmission and outputs to network; Input channel is transmitted used logic microplate data with network-on-chip and is transformed outer in flakes data type according to the same rule.
In the such scheme, the internal structure of network interface and local network interface are basic identical between described, its output channel is dissolved string module data based certain agreement and the rule that transmit with string and is cut apart, and changes into the used logic micro sheet structure data of network-on-chip transmission and outputs to network; Input channel is then opposite, is network-on-chip to be transmitted used logic micro sheet structure data change into the outer data type of certain sheet according to the same rule; The difference of network interface and local network interface is that the bus control unit of local network interface becomes outside third party's translation interface unit between sheet, and this translation interface unit is configurable; Outer what connect is the chip of network interface unit between similar strap as chankings, then do not carry out input and output error detection verification by being configured in output, directly send at a high speed string to dissolve the string module at output packet and send, and form packet in the data that input is dissolved the input of string module to string at a high speed; As the outer connection of chankings is third-party chip, then use output error detection unit to carry out data check by being configured in output, and be converted into the protocol data of third-party chip, send at a high speed string to dissolve the string module through output and send, input at a high speed the string protocol data of dissolving the third-party chip of string module input be converted to the packet of network-on-chip; Therefore, the functional structure of network interface unit can connect the dissimilar transfer modes that are configured to the transfer mode of compatible third-party chip interface or are configured to compatible similar chip interface of chip according to sheet outward between sheet.The configurable structure of network interface unit between sheet has been simplified the interconnect extended of chip chamber.Because the interconnect extended agreement between similar chip adopts the route switching mode of same protocol, improved the efficient that data transmit simultaneously.
(3) beneficial effect
From such scheme as can be seen, the present invention has following beneficial effect:
1, the invention provides and be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, this device mainly can be made of with the router of all directions UNICOM network interface interface unit 1 to 2 local network interface unit, one or more sheet that can dispose and one, for different interfaces or protocol type, only need be configured and to realize connecting, be easy to expand with unified method on the polycaryon processor sheet and between sheet network interface unit between sheet.
2, among the present invention,, can realize that transceive data is carried out verification to be detected, and has improved the reliability based on the route transmission data because network interface unit inside has increased also that cyclic redundancy (CRC) detects and verification unit on the sheet and between sheet.
3, utilize the present invention, when being connected with third-party chip, the data of routing forwarding network interface unit between sheet converts packet and the agreement that third-party chip can be supported automatically to, improves the compatibility and the easy autgmentability of this device; Simultaneously when linking to each other, adopt the route switching mode of same protocol, and the data of routing forwarding network interface unit between sheet do not need to carry out CRC check, thereby improved the efficient that data transmit with the similar chip that comprises this device.
Description of drawings
Fig. 1 provided by the inventionly is applicable on the polycaryon processor sheet and the structural representation of route of expanding between sheet and interface arrangement;
Fig. 2 is a router topology block diagram among the present invention, is used for microplate is carried out route and exchange;
Fig. 3 is route and pack arrangement and a type that interface arrangement adopted among the present invention;
Fig. 4 is the structured flowchart of local network interface among the present invention, is logic microplate data conversion the logic microplate for local available data and local data conversion;
Fig. 5 is the structured flowchart of network interface unit between sheet among the present invention, is network microplate data conversion the outer available data of sheet and is sheet data conversion outward the network microplate;
Fig. 6 is that route and interface arrangement node carry out a kind of embodiment of expanding in the network topology sheet among the present invention on two dimensional surface;
Fig. 7 is a kind of embodiment that route and interface arrangement are expanded between sheet among the present invention;
Fig. 8 is the route of band network interface interface among the present invention and the node structure that interface arrangement links to each other and forms with native processor in the three dimensions expanded application;
Fig. 9 is based on the node described in Fig. 8 carries out the expansion of three-dimensional mesh topology on three-dimensional planar a kind of embodiment.
Embodiment
The present invention mainly comprises two parts: a part is a kind of route device that has self-defined network interface (NI) unit, this device has increased the plurality of network interface unit on traditional route basis, make route device of the present invention can realize on the polycaryon processor sheet easily and the expansion between sheet by configuration and definition to network interface unit, make the design of processor core and internal and external relatively independent the opening of Interface design, reduced development difficulty.A part is to introduce check logic microplate (check flit) at the Routing Protocol layer in addition, some check informations in the packing data algorithm, have been increased, promptly in this route device, increase cyclic redundancy (CRC) verification unit and come the correctness of detected transmission, cyclic redundancy check (CRC) code (CRC) is a kind of system shorten cyclic codes, is widely used in frame check.It is to utilize the principle of division and remainder to make error detection.During practical application, dispensing device calculates the cyclic redundancy value and together sends to receiving system with data, receiving system recomputates cyclic redundancy to the data of receiving and compares with the cyclic redundancy of receiving, if two cyclic redundancy value differences illustrate that then mistake appears in data communication.
After this route and interface arrangement were introduced check logic microplate and cyclic redundancy check (CRC) code testing mechanism, feasible reliability based on route transmission was improved, and transmits insecure problem thereby solved present network-on-chip (NoC) data.
In order not obscure the present invention, will some generic nouns and notion that traditional route adopted not done too much explanation in the present invention's narration, these notions include but not limited to following content: Virtual Channel, grid (mesh) topological structure, packet (packet).Those skilled in the art can understand.
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Fig. 1 provided by the inventionly is applicable on the polycaryon processor sheet and the structural representation of route of expanding between sheet and interface arrangement, each router has a plurality of interfaces that directly link to each other with other routers, also has 1 to 2 local network interface, this local network interface is used for isolating processing unit in network-on-chip and the sheet, the conversion of the line data type of going forward side by side, router links to each other with processing unit in the sheet after via local network interface, processing unit can be on-chip processor but is not limited to that this is a kind of in this sheet, it equally also can be the processing unit of other types, according to the difference of processing unit in this sheet, the configuration register content of local network interface is also different.If local node has data to send, data are delivered to router after packing through local network interface, send on the network by the some interfaces in several interfaces of router again; Same when having data will deliver on the local node on several directions on the network, then data are delivered to local network interface by router, are resolved by local network interface and deliver to processing unit in the local sheet (for example on-chip processor) after unpacking.Simultaneously when communicating outside router and the sheet, can carry out interconnection between sheet by network interface between sheet, the effect of network interface mainly is that outer data of sheet and route network data are changed between sheet, be used for outer data of sheet and route network data are changed, and be connected by stringization/(SerDes) module of unstringing and sheet third-party chip outward at a high speed, perhaps with similar sheet outer network chip on the external network interface butt joint, thereby realize extension of network between sheet.
Fig. 2 is a router topology block diagram among the present invention, and router is mainly used to that the logic microplate data that receive are carried out route and calculates and exchange and transmit.The input of router all is the data of logic microplate form, can be the logic microplate data that network interface is exported to router, also can be the logic microplate data that other router sends to this router.The data that receive can leave in the different tunnels, and each input channel allows to distribute several tunnels, is used for improving network efficiency.Route computing unit uses certain routing algorithm that the microplate in the tunnel is carried out route and calculates and notify logic microplate forwarding of data in router state register and the controller control router simultaneously.Arbitration unit is controlled the output of the tunnel of each passage, and these outputs link to each other with cross bar switch.The logic microplate data that certain allocation algorithm exchange that cross bar switch is determined according to allocation units is imported, the output of exporting to router at last.Credit (Credit) computing unit is according to the information of router state register and controller, export credit amount data, and an input credit data processing of information offered routing state register and controller.Router state register and controller receive the information of credit computing unit and the information of route computing unit, and the behavior of control arbitration unit and allocation units is status units main in the router.
Fig. 3 is bag (packet) structure and microplate (flit) type that route device of the present invention adopted, and the type of bag mainly is divided into 2 classes: request package and respond packet.Request package and respond packet mainly are used for transmitting the request and the response of the data processing of sending from terminal on transport layer.Request package and respond packet can be broken down into flit (microplate) transmission, are divided into a microplate (head flit), body microplate (body flit), tail microplate (tail flit) and verification microplate (check flit) again.Be used for telling the position of head and tail of route device one string data and the destination address that these data need be sent to respectively.The verification microplate is used for that data are carried out cyclic redundancy and detects comparison after finishing, thereby determines whether this packet transmits correct.
Fig. 4 is the structured flowchart of local network interface among the present invention.The local network interface unit is a bridge of local node data type and the conversion of network-on-chip wire data type, and it mainly is made up of 2 passages, i.e. the input and output passage.Its major function is that output channel is cut apart the transport layer data that on-chip processor transmits according to certain agreement and rule, changes into the used logic micro sheet structure data of network-on-chip transmission and outputs to network; Input channel is then opposite, is the used logic micro sheet structure data of network-on-chip transmission are changed into the local node data type according to the same rule.In order to improve the reliability of transmission, added the cyclic redundancy testing mechanism in the route device of the present invention, therefore an error detection verification unit is arranged in the local network interface unit, be used for the data of output are done scrambling and the data that receive are done verification.The local network interface unit mainly comprises the input and output two large divisions.
With reference to Fig. 4, the effect of each functional module of local network interface unit is as follows: configuration and status register are used for depositing some control informations, protocol analysis information and interrupting information etc.Content in this register can define voluntarily and dispose according to the difference of agreement or the difference of user's needs.The input rank unit is used for doing the isolation of data buffering and different clock-domains, and the packet dual port memory unit stores the data message of a complete data packet that need transmit.Transmission state machine and control logic unit are used for analysis protocol and receive logic microplate type.The datacycle redundancy detection that the error detection verification unit is unpacked later.The bus control unit interface unit is finished total line traffic control etc.
With reference to Fig. 4, the importation of local network interface unit mainly comprises following module: input rank unit, input packet memory, input error detection unit, input state machine and control logic, configuration and status register and bus control unit etc.The logic microplate of importing into from network-on-chip passes through the data queue that channel selecting outputs to Virtual Channel, input state machine and the empty full signal of control logic output are given in formation, the read-write input signal is by input state machine and control logic output, the data input and output of control formation, and export to data memory input.Data memory input can be asynchronous, be used for data cached bag and isolate different clock zones, storing process is by the output control of input state machine and control logic, input store is also exported to input state machine and control logic to the state of self, memory can also be exported to input error detection verification unit data simultaneously, carries out the verification such as cyclic redundancy.After verification finished, input error detection verification meeting output status signal was given input state machine and control logic, and is correct or packet is wrong with the notice verification.Input state machine and control logic, receive the status signal of each module and control each module transmission data, when signal is finished in verification, can be by finishing total line traffic control with bus control unit, such as if reception is control signal or operation acknowledge signal, then start interrupt signal int_n and make the processor reading of data also operate; If chunk data receives back notice bus control unit and starts DMA transmission data.Input state machine and control logic can be given external routing unit to local network interface unit outside export credit amount signal according to the state of input rank simultaneously.Configuration and status register have with control logic with output state machine with input and are connected, be mainly used to deposit some control informations, protocol analysis information and interrupting information etc., the content in this register can define voluntarily and dispose according to the difference of agreement or the difference of user's needs.Bus control unit receives the data input of data memory input, and to input state machine and control logic output state, the processing unit interior with sheet links to each other.
With reference to Fig. 4, the output of local network interface unit is mainly by bus control unit, and the dateout packet memory is exported the error detection unit, and modules such as output state machine and control logic and configuration and status register constitute.Output state machine and control logic are received the input of bus control unit, when the order of transfer of data, if local network interface is idle at present, then can receive data, the output state machine control logic is packed to data according to the protocol information and the state information of the input in configuration and the status register, produce internal control signal and export to packet memory, control storage reads in data, the controller that input is initiated transmission command can continue to send transmission, output state machine and control logic also send according to the state of each module input and by the credit signal controlling Memory Controller that external routing unit is imported and allow read command, output state machine and control logic can also merge the data and the data of output detection check unit input that memory input to self and be converted into that router sends in the outside contact pin of logic microplate through the position in addition, and the significance bit that sends data is simultaneously set out on a journey by device to outer contact pin.Memory has the output to verification unit simultaneously, and to the output state machine output state, is used for data cached bag and clock zone to isolate, and the data of memory output will be exported to output state machine and control logic.Memory data is exported to after the output detection check unit scrambling the scrambled data buffer memory simultaneously to memory cell and export to output state machine idle running logic, and to state machine and control logic output state.
Fig. 5 is the structured flowchart of network interface unit between sheet among the present invention.Its internal structure and local network interface unit class are like (basic identical in other words), to be output channel dissolve data based certain agreement and the rule that the string module transmits to string to its major function cuts apart, and changes into the used logic micro sheet structure data of network-on-chip transmission and output to network; Input channel is then opposite, is the used logic micro sheet structure data of network-on-chip transmission are changed into the outer data type of certain sheet according to the same rule.Between sheet the structure of network interface unit and local network interface unit class seemingly, but and the difference of local network interface unit be that the bus control unit of local network interface becomes outside third party's translation interface unit, this translation interface unit is configurable.Outer what connect is the chip of network interface unit between similar strap as chankings, then do not carry out input and output error detection verification by being configured in output, directly send at a high speed string to dissolve the string module at output packet and send, and form packet in the data that input is dissolved the input of string module to string at a high speed; As the outer connection of chankings is third-party chip, then use output error detection unit to carry out data check by being configured in output, and be converted into the protocol data of third-party chip, send at a high speed string to dissolve the string module through output and send, input at a high speed the string protocol data of dissolving the third-party chip of string module input be converted to the packet of network-on-chip.Therefore, the functional structure of network interface unit can connect the dissimilar transfer modes that are configured to the transfer mode of compatible third-party chip interface or are configured to compatible similar chip interface of chip according to sheet outward between sheet.The configurable structure of network interface unit between sheet has been simplified the interconnect extended of chip chamber.Because the interconnect extended agreement between similar chip adopts the route switching mode of same protocol, improved the efficient that data transmit simultaneously.
Fig. 6 carries out a kind of embodiment of expanding in the network topology sheet on two dimensional surface for route among the present invention and interface arrangement node.In this structure, logic microplate data can be carried out the transmission of 4 directions in all directions on the two dimensional surface by the router in each node, and expand in sheet.
A kind of embodiment that Fig. 7 expands between sheet for route among the present invention and interface arrangement.Network interface unit can link to each other with third-party chip sheet outside by the stringization/modules such as (Serdes) of unstringing at a high speed between sheet in this structure, also can link to each other by network interface unit between the sheet in the high speed stringization/modules such as (Serdes) of unstringing and sheet another piece NoC chip outward.By expanding between sheet, improved the flexibility and the versatility of NoC chip expansion.
Fig. 8 is another route device of the present invention, and this device is adapted at using in the 3 D stereo expansion.Mainly comprise a router and two network interface unit.Whole route device has 8 ports, and except 4 ports in east, south, west, north with two dimensional surface expansion, the upper and lower that has also increased 3 D stereo is to port.Also have 2 local interfaces in addition, each local interface all links to each other with node unit via a network interface unit, and is same, and this unit can be a communication interface but be not limited to these two kinds between on-chip processor unit or sheet, according to the difference of this unit, the configuration register content difference of network interface.If some local ports or two local ports have data to send, data are delivered to router after through the packing of network interface separately, send on the network by some in the East, West, South, North of router, upper and lower 6 ports or 2 again; Have data will deliver on the local node on same certain or certain 2 directions on 6 directions on the network, then data are delivered to corresponding network interface unit by router, are resolved by network interface and deliver to local on-chip processor or interface after unpacking.
Fig. 9 is for carrying out a kind of embodiment of stereoscopic grid topology expansion on three-dimensional planar based on the node described in Fig. 8, in this structure, logic microplate data can be carried out the transmission of three-dimensional planar Shang Dong, south, west, north, upper and lower 6 directions by the router in each node.Such structure makes network can carry out three-dimensional expansion, and the continuous development of integrated circuit technology has made three-dimensional wiring become possibility, and therefore so three-dimensional extended mode can improve integrated level greatly.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. one kind is applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that this device comprises:
Router, be used for to the logic microplate data that receive carry out that route is calculated, exchange and transmitting, this router has: a plurality of router interfaces, be used for other sheets on router directly be connected;
1 or 2 local network interface is used to isolate processing unit in network-on-chip and the sheet, carries out the conversion of data type, and connects processing unit in router and the sheet;
1 or a plurality of between network interface, its number is determined according to the needed maximum transmitted port number of expansion between sheet, be used for outer data of sheet and route network data are changed, and be connected by stringization/SerDes module of unstringing and sheet third-party chip outward at a high speed, perhaps with sheet outer network chip of the same type on sheet between network interface dock, realize extension of network between sheet.
2. according to claim 1ly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that,
Will send when local node has data, then data are delivered to router after packing through local network interface, send to network between network-on-chip or sheet by the some router interfaces in a plurality of router interfaces of router again;
Have data will deliver on the local node on several directions on the network-on-chip, then data are delivered to local network interface by router, are resolved by local network interface and deliver to processing unit in the local sheet after unpacking.
3. according to claim 1ly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that described router comprises a plurality of input channels, a plurality of tunnel, a plurality of arbitration unit, cross bar switch, a plurality of output channel, allocation units, route computing unit, router state register and controller and a credit computing unit; Wherein,
Router receives logic microplate data by a plurality of input channels, and in different tunnels, each input channel is assigned with several tunnels, is used to improve network efficiency with the logic microplate deposit data that receives;
Route computing unit uses certain routing algorithm that the logic microplate data in the tunnel are carried out route and calculates, and logic microplate forwarding of data in notice router state register and the controller control router;
The output of some tunnels that arbitration unit control is corresponding with each input channel, this output is connected with cross bar switch;
The logic microplate data that certain allocation algorithm exchange that cross bar switch is determined according to allocation units is imported are at last by a plurality of output channels outputs;
The credit computing unit is according to the information of router state register and controller, export credit amount data, and an input credit data processing of information offered routing state register and controller;
Router state register and controller receive the information of credit computing unit and the information of route computing unit, the behavior of control arbitration unit and allocation units.
4. according to claim 1ly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that, described local network interface is a bridge of local node data type and the conversion of network-on-chip wire data type, constitute by input channel and output channel, the transport layer data that output channel is used for on-chip processor is transmitted is cut apart according to certain agreement and rule, changes into the used logic microplate data of network-on-chip transmission and outputs to network; Input channel is used for that network-on-chip is transmitted used logic microplate data and changes into the local node data type according to the same rule.
5. according to claim 1ly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that described local network interface comprises:
Configuration and status register are used to deposit control information, protocol analysis information and interrupting information;
The input rank unit is used to carry out the isolation of data buffering and different clock-domains;
Import and dateout bag dual port memory unit, be used to store the data message of a complete data packet that need transmit;
Input and output state machine and control logic unit are used for analysis protocol and receive logic microplate type;
Input and output error detection verification unit are used for the data of output are carried out scrambling, and the data that receive are carried out the cyclic redundancy detection check; And
Bus control unit is used to finish total line traffic control.
6. according to claim 4ly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that, described input channel is by the input rank unit, input packet dual port memory cell, input error detection verification unit, input state machine and control logic unit, configuration and status register, and bus control unit constitutes, the logic microplate of importing into from network-on-chip passes through the data queue that channel selecting outputs to Virtual Channel, input state machine and the empty full signal of control logic output are given in formation, the read-write input signal is by input state machine and control logic output, the data input and output of control formation, and export to data memory input; Data memory input is asynchronous, be used for data cached bag and isolate different clock zones, storing process is by the output control of input state machine and control logic, input store is also exported to input state machine and control logic to the state of self, memory can also be exported to input error detection verification unit data simultaneously, carries out the verification of cyclic redundancy; After verification finished, input error detection verification meeting output status signal was given input state machine and control logic, and is correct or packet is wrong with the notice verification; Input state machine and control logic, receive the status signal of each module and control each module transmission data, when signal is finished in verification, will be by finishing total line traffic control with bus control unit, if receiving is control signal or operation acknowledge signal, then starts interrupt signal int_n and make the processor reading of data also operate; If chunk data receives back notice bus control unit and starts DMA transmission data; Input state machine and control logic can be given external routing unit to local network interface unit outside export credit amount signal according to the state of input rank simultaneously.
7. according to claim 4ly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that, described output channel is by bus control unit, dateout packet memory, output error detection unit, output state machine and control logic, and configuration and status register formation; Output state machine and control logic are received the input of bus control unit, when the order of transfer of data, if local network interface is idle at present, then can receive data, the output state machine control logic is packed to data according to protocol information and the state information imported in configuration and the status register, produce internal control signal and export to packet memory, control storage reads in data, the controller that input is initiated transmission command can continue to send transmission, output state machine and control logic also send according to the state of each module input and by the credit signal controlling Memory Controller that external routing unit is imported and allow read command, output state machine and control logic merge the data and the data of output detection check unit input that memory inputs to self and are converted into that router sends in the outside contact pin of logic microplate through the position in addition, and the significance bit that sends data is simultaneously set out on a journey by device to outer contact pin; Memory has the output to verification unit simultaneously, and to the output state machine output state, is used for data cached bag and clock zone to isolate, and the data of memory output will be exported to output state machine and control logic; Memory data is exported to after the output detection check unit scrambling the scrambled data buffer memory simultaneously to memory cell and export to output state machine idle running logic, and to state machine and control logic output state.
8. according to claim 1ly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that, network interface is made of input channel and output channel between described, output channel is cut apart the transport layer data that sheet transmits outward according to certain agreement and rule, change into the used logic microplate data of network-on-chip transmission and output to network; Input channel is transmitted used logic microplate data with network-on-chip and is transformed outer in flakes data type according to the same rule.
9. according to claim 8ly be applicable on the polycaryon processor sheet and route of expanding between sheet and interface arrangement, it is characterized in that, the internal structure of network interface and local network interface are basic identical between described, its output channel is dissolved string module data based certain agreement and the rule that transmit with string and is cut apart, and changes into the used logic micro sheet structure data of network-on-chip transmission and outputs to network; Input channel is then opposite, is network-on-chip to be transmitted used logic micro sheet structure data change into the outer data type of certain sheet according to the same rule; The difference of network interface and local network interface is that the bus control unit of local network interface becomes outside third party's translation interface unit between sheet, and this translation interface unit is configurable; Outer what connect is the chip of network interface unit between similar strap as chankings, then do not carry out input and output error detection verification by being configured in output, directly send at a high speed string to dissolve the string module at output packet and send, and form packet in the data that input is dissolved the input of string module to string at a high speed; As the outer connection of chankings is third-party chip, then use output error detection unit to carry out data check by being configured in output, and be converted into the protocol data of third-party chip, send at a high speed string to dissolve the string module through output and send, input at a high speed the string protocol data of dissolving the third-party chip of string module input be converted to the packet of network-on-chip; Therefore, the functional structure of network interface unit can connect the dissimilar transfer modes that are configured to the transfer mode of compatible third-party chip interface or are configured to compatible similar chip interface of chip according to sheet outward between sheet.
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