JP2012054422A - Light-emitting diode - Google Patents

Light-emitting diode Download PDF

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JP2012054422A
JP2012054422A JP2010196080A JP2010196080A JP2012054422A JP 2012054422 A JP2012054422 A JP 2012054422A JP 2010196080 A JP2010196080 A JP 2010196080A JP 2010196080 A JP2010196080 A JP 2010196080A JP 2012054422 A JP2012054422 A JP 2012054422A
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layer
light emitting
semiconductor
emitting diode
semiconductor light
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Tsunehiro Unno
恒弘 海野
Tomoya Mizutani
友哉 水谷
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting diode capable of downsizing while ensuring sufficient amount of emitted light and capable of providing excellent productivity and yield.SOLUTION: A light-emitting diode 100 comprises a substrate 30, a metal wiring layer 31 disposed on the substrate 30, and semiconductor light-emitting elements 10 provided on the metal wiring layer 31. Each of the semiconductor light-emitting elements 10 comprises: a semiconductor light-emitting layer 6 that has a side length of 100 μm or more to 250 μm or less and includes a first semiconductor layer 5, an active layer 4, and a second semiconductor layer 3 that are stacked in this order from the substrate 30 side; a transparent insulating film 7 provided on the substrate 30 side of the semiconductor light-emitting layer 6; and a first electrode 16 and a second electrode 17 that are provided on the substrate 30 side of the transparent insulating film 7 via separation regions 18 and 19 and are electrically connected to the metal wiring layer 31. The first electrode 16 is electrically connected to the first semiconductor layer 5 by a first contact portion 12 provided through the transparent insulating film 7. The second electrode 17 is electrically connected to the second semiconductor layer 3 by a second contact portion 11 provided through the transparent insulating film 7, the first semiconductor layer 5, and the active layer 4.

Description

本発明は、発光ダイオードに関し、更に詳しくは、半導体発光素子側の電極と基板側の配線とが、バンプを用いることなく貼り合せされた新規な構造を有する発光ダイオードに関する。   The present invention relates to a light emitting diode, and more particularly to a light emitting diode having a novel structure in which an electrode on a semiconductor light emitting element side and a wiring on a substrate side are bonded together without using bumps.

近年、半導体発光素子である発光ダイオード（以下、ＬＥＤ）は、結晶品質の向上によって高い光・電気変換効率が実現されている（例えば、特許文献１〜３参照）。発光効率が高くなり、発熱の影響も少なくなって、大電流での使用が可能となったことから、表示用ＬＥＤに比べて高輝度が要求される照明用の光源への応用が広がっている。
一方、表示用ＬＥＤに対しては、照明用ＬＥＤで要求される大電流での使用や高輝度に代わって、わずかな電力での駆動、発光を実現する、いわゆる小型・省電力化が求められている。 In recent years, light-emitting diodes (hereinafter referred to as LEDs), which are semiconductor light-emitting elements, have achieved high light-electric conversion efficiency due to improved crystal quality (see, for example, Patent Documents 1 to 3). Since the luminous efficiency is high, the influence of heat generation is reduced, and it is possible to use it with a large current, the application to lighting light sources that require higher brightness than the LED for display is expanding. .
On the other hand, instead of using the high current required for lighting LEDs and the high luminance, display LEDs require so-called small size and low power consumption that realizes driving and light emission with a small amount of power. ing.

特開２００７−３２４２１３号公報JP 2007-324213 A 特開２００８−７８２２５号公報JP 2008-78225 A 特開２００９−２００１７８号公報JP 2009-200188 A

しかしながら、小型・省電力化を行うことと、ＬＥＤの十分な輝度・発光量を確保することとは、トレードオフの関係にあり、双方を実現することは困難であった。例えば、特許文献１のようなボンディングワイヤを用いた実装方法では、ＬＥＤの小型化に従い、ＬＥＤ上に占めるボンディングパッドのサイズが大きくなってしまい、ＬＥＤからの光取出し効率が低下するという問題がある。   However, there is a trade-off relationship between miniaturization and power saving and ensuring sufficient brightness and light emission amount of the LED, and it has been difficult to realize both. For example, in the mounting method using a bonding wire as in Patent Document 1, the size of the bonding pad occupying the LED increases as the size of the LED decreases, and the light extraction efficiency from the LED decreases. .

また、特許文献２のようなバンプを用いたフリップチップ実装では、ワイヤボンディング方式に比べＬＥＤを小型化しても光取出し効率の低下を抑えられる。しかし、フリップチップ実装では、１つのＬＥＤを実装するために、多数のバンプを形成する必要があり、バンプの量やバンプ高さの制御、バンプヘのＬＥＤ実装の位置合わせ及び接合は容易ではなく、生産性や歩留りの改善が難しいという問題がある。   Further, in flip chip mounting using bumps as in Patent Document 2, a decrease in light extraction efficiency can be suppressed even if the LED is downsized as compared with the wire bonding method. However, in flip chip mounting, in order to mount one LED, it is necessary to form a large number of bumps. Control of the amount of bumps and bump height, alignment and bonding of LED mounting to bumps is not easy, There is a problem that it is difficult to improve productivity and yield.

本発明の目的は、十分な発光量を確保しつつ小型化が図れるとともに、良好な生産性・歩留りを実現できる発光ダイオードを提供することにある。   An object of the present invention is to provide a light-emitting diode that can be reduced in size while ensuring a sufficient amount of light emission, and that can realize good productivity and yield.

本発明の第１の態様は、基板と、前記基板上に配設される金属配線層と、前記金属配線層上に設けられる半導体発光素子と、を有し、
前記半導体発光素子は、１辺が１００μｍ以上２５０μｍ以下であり、
前記基板側から順に、第１半導体層、活性層、第２半導体層を備えた半導体発光層と、前記半導体発光層の前記基板側に設けられる透明絶縁膜と、前記透明絶縁膜の前記基板側に離間領域を介して設けられ、前記金属配線層と電気的に接続される第１電極部及び第２電極部と、を有し、
前記第１電極部は、前記透明絶縁膜を貫通して設けられる第１コンタク卜部により前記第１半導体層と電気的に接続され、前記第２電極部は、前記透明絶縁膜、前記第１半導体
層、及び前記活性層を貫通して設けられる第２コンタクト部により前記第２半導体層と電気的に接続される、発光ダイオードである。 A first aspect of the present invention includes a substrate, a metal wiring layer disposed on the substrate, and a semiconductor light emitting element provided on the metal wiring layer.
The semiconductor light emitting element has one side of 100 μm to 250 μm,
In order from the substrate side, a semiconductor light emitting layer including a first semiconductor layer, an active layer, and a second semiconductor layer, a transparent insulating film provided on the substrate side of the semiconductor light emitting layer, and the substrate side of the transparent insulating film A first electrode part and a second electrode part that are electrically connected to the metal wiring layer.
The first electrode portion is electrically connected to the first semiconductor layer by a first contact hole provided through the transparent insulating film, and the second electrode portion includes the transparent insulating film and the first semiconductor. A light emitting diode electrically connected to the second semiconductor layer by a second contact portion provided through the layer and the active layer.

本発明の第２の態様は、第１の態様の発光ダイオードにおいて、前記金属配線層上には、複数の前記半導体発光素子が設けられている。   According to a second aspect of the present invention, in the light emitting diode according to the first aspect, a plurality of the semiconductor light emitting elements are provided on the metal wiring layer.

本発明の第３の態様は、第１又は第２の態様の発光ダイオードにおいて、前記第１電極部及び／又は前記第２電極部は、金属反射層を備えている。   According to a third aspect of the present invention, in the light-emitting diode according to the first or second aspect, the first electrode portion and / or the second electrode portion includes a metal reflective layer.

本発明の第４の態様は、第１〜第３の態様のいずれかの発光ダイオードおいて、前記第１電極部及び前記第２電極部は貼り合わせ層を有し、前記貼り合せ層を介して前記金属配線層と接合されている。   According to a fourth aspect of the present invention, in the light-emitting diode according to any one of the first to third aspects, the first electrode portion and the second electrode portion have a bonding layer, and the bonding layer is interposed therebetween. Are joined to the metal wiring layer.

本発明の第５の態様は、第１〜第４の態様のいずれかの発光ダイオードにおいて、前記第２半導体層の上記活性層側とは反対側の面は、粗面化加工された光取出し面である。   According to a fifth aspect of the present invention, in the light-emitting diode according to any one of the first to fourth aspects, the surface of the second semiconductor layer opposite to the active layer side is roughened. Surface.

本発明の第６の態様は、第１〜第５の態様のいずれかの発光ダイオードにおいて、前記第２コンタク卜部は、前記第２電極部上に設けられ、前記第１半導体層及び前記活性層に対して絶縁するための絶縁材料と、前記絶縁材料に覆われるように設けられるＡｕ系材料とからなる。   According to a sixth aspect of the present invention, in the light-emitting diode according to any one of the first to fifth aspects, the second contact part is provided on the second electrode part, and the first semiconductor layer and the active layer And an Au-based material provided so as to be covered with the insulating material.

本発明の第７の態様は、第１〜第６の態様のいずれかの発光ダイオードにおいて、前記金属配線層は、複数の前記半導体発光素子を直列接続するパターンに形成されている。   According to a seventh aspect of the present invention, in the light emitting diode according to any one of the first to sixth aspects, the metal wiring layer is formed in a pattern in which a plurality of the semiconductor light emitting elements are connected in series.

本発明の第８の態様は、第１〜第７の態様のいずれかの発光ダイオードにおいて、前記基板に貫通孔が形成され、前記貫通孔に導電性材料が設けられることで前記金属配線層に電気的に接続される裏面コンタクト部が形成されている。   According to an eighth aspect of the present invention, in the light-emitting diode according to any one of the first to seventh aspects, a through hole is formed in the substrate, and a conductive material is provided in the through hole, whereby the metal wiring layer is provided. A back contact portion to be electrically connected is formed.

本発明によれば、十分な発光量を確保しつつ小型化が図れるとともに、良好な生産性・歩留りを実現できる発光ダイオードを提供することができる。   According to the present invention, it is possible to provide a light emitting diode that can be reduced in size while ensuring a sufficient amount of light emission, and that can realize good productivity and yield.

本発明の一実施形態に係る発光ダイオードを示す断面図である。It is sectional drawing which shows the light emitting diode which concerns on one Embodiment of this invention. 本発明の一実施形態の発光ダイオードにおける複数の半導体発光素子の接続関係を示す図である。It is a figure which shows the connection relation of the some semiconductor light-emitting element in the light emitting diode of one Embodiment of this invention. 本発明の一実施形態に係る発光ダイオードを製造する製造工程の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing process which manufactures the light emitting diode which concerns on one Embodiment of this invention. 本発明の一実施形態に係る発光ダイオードを製造する製造工程の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing process which manufactures the light emitting diode which concerns on one Embodiment of this invention. 本発明の一実施形態に係る発光ダイオードを製造する製造工程の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing process which manufactures the light emitting diode which concerns on one Embodiment of this invention. 本発明の一実施形態に係る発光ダイオードを製造する製造工程の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing process which manufactures the light emitting diode which concerns on one Embodiment of this invention. 本発明の他の実施形態に係る発光ダイオードにおける複数の半導体発光素子の接続関係を示す図である。It is a figure which shows the connection relation of the some semiconductor light-emitting element in the light emitting diode which concerns on other embodiment of this invention. 本発明の他の実施形態に係る発光ダイオードを示す断面図である。It is sectional drawing which shows the light emitting diode which concerns on other embodiment of this invention. 本発明の他の実施形態に係る発光ダイオードを示す断面図である。It is sectional drawing which shows the light emitting diode which concerns on other embodiment of this invention. 本発明の一実施例の発光ダイオードにおける複数の半導体発光素子の接続関係を示す図である。It is a figure which shows the connection relation of the some semiconductor light-emitting element in the light emitting diode of one Example of this invention. 本発明の実施例及び比較例において、素子サイズと光束との関係を示すグラフである。In the Example and comparative example of this invention, it is a graph which shows the relationship between element size and a light beam. 本発明の実施例及び比較例において、素子サイズと光束との関係を示すグラフである。In the Example and comparative example of this invention, it is a graph which shows the relationship between element size and a light beam. 複数の半導体発光素子を有する比較例の構成を示す断面図である。It is sectional drawing which shows the structure of the comparative example which has several semiconductor light-emitting devices. 複数の半導体発光素子を有する比較例の構成を示す断面図である。It is sectional drawing which shows the structure of the comparative example which has several semiconductor light-emitting devices.

以下に、本発明に係る発光ダイオードの一実施形態を図面を用いて説明する。   Hereinafter, an embodiment of a light emitting diode according to the present invention will be described with reference to the drawings.

［第１の実施形態]
図１に、本発明の第１の実施形態に係る発光ダイオードを示す。
本実施形態の発光ダイオード１００は、基板３０と、基板３０上に配設される金属配線層３１と、金属配線層３１上に設けられる複数の半導体発光素子１０と、を有する。
半導体発光素子１０は、基板３０側から順に、第１半導体層５、活性層４、第２半導体層３を備えた半導体発光層６と、半導体発光層６の基板３０側に設けられる透明絶縁膜７と、透明絶縁膜７の基板３０側に離間領域１８を介して設けられる第１電極部１６及び第２電極部１７と、を有する。
第１電極部１６及び第２電極部１７は、基板３０側に貼り合せ層１５を備え、第１電極部１６及び第２電極部１７は貼り合せ層１５により金属配線層３１と接合されている。第１電極部１６は、透明絶縁膜７を貫通して設けられる第１コンタクト部１２により第１半導体層５と電気的に接続されている。第２電極部１７は、透明絶縁膜７、第１半導体層５、活性層４を貫通して設けられる第２コンタクト部１１により第２半導体層３と電気的に接続されている。
特に、半導体発光素子１０は、チップサイズが１００μｍ以上２５０μｍ以下の小型サイズとなっている。 [First embodiment]
FIG. 1 shows a light emitting diode according to a first embodiment of the present invention.
The light emitting diode 100 of this embodiment includes a substrate 30, a metal wiring layer 31 disposed on the substrate 30, and a plurality of semiconductor light emitting elements 10 provided on the metal wiring layer 31.
The semiconductor light emitting element 10 includes, in order from the substrate 30 side, a semiconductor light emitting layer 6 including a first semiconductor layer 5, an active layer 4, and a second semiconductor layer 3, and a transparent insulating film provided on the substrate 30 side of the semiconductor light emitting layer 6. 7 and a first electrode portion 16 and a second electrode portion 17 provided on the substrate 30 side of the transparent insulating film 7 via a separation region 18.
The first electrode portion 16 and the second electrode portion 17 include a bonding layer 15 on the substrate 30 side, and the first electrode portion 16 and the second electrode portion 17 are joined to the metal wiring layer 31 by the bonding layer 15. . The first electrode portion 16 is electrically connected to the first semiconductor layer 5 by a first contact portion 12 provided through the transparent insulating film 7. The second electrode portion 17 is electrically connected to the second semiconductor layer 3 by a second contact portion 11 provided through the transparent insulating film 7, the first semiconductor layer 5, and the active layer 4.
In particular, the semiconductor light emitting device 10 has a small size with a chip size of 100 μm to 250 μm.

本実施形態では、第１電極部１６及び第２電極部１７は、透明絶縁膜７側から反射金属層１３、拡散抑止層１４、貼り合せ層１５を順次積層して構成されている。また、金属配線層３１は、基板３０側から密着層３２、接合用金属層３３を順次積層して構成されている。
金属反射層１３は、活性層４で発光し透明絶縁膜７側に出射された光を半導体発光層６側に反射して、光取り出し効率を向上させるための層であり、発光波長の光に対して高い反射率を有する、例えばＡｕ、Ａｇ、Ｃｕ、Ａｌ等の金属、若しくはこれらの金属を少なくとも１つ含む合金が用いられる。
拡散抑止層１４は、金属反射層１３の基板３０側から貼り合せ層１５等を構成する材料が金属反射層１３に拡散することを抑制して、金属反射層１３の反射特性の低下を抑制する層であり、例えばＴｉ、Ｐｔなどが用いられる。 In the present embodiment, the first electrode portion 16 and the second electrode portion 17 are configured by sequentially laminating the reflective metal layer 13, the diffusion suppressing layer 14, and the bonding layer 15 from the transparent insulating film 7 side. The metal wiring layer 31 is formed by sequentially laminating an adhesion layer 32 and a bonding metal layer 33 from the substrate 30 side.
The metal reflection layer 13 is a layer for reflecting the light emitted from the active layer 4 and emitted to the transparent insulating film 7 side to the semiconductor light emitting layer 6 side to improve the light extraction efficiency. For example, a metal having high reflectivity, such as Au, Ag, Cu, Al, or an alloy containing at least one of these metals is used.
The diffusion suppression layer 14 suppresses the material constituting the bonding layer 15 and the like from the substrate 30 side of the metal reflection layer 13 from diffusing into the metal reflection layer 13 and suppresses the deterioration of the reflection characteristics of the metal reflection layer 13. For example, Ti, Pt or the like is used.

第１電極部１６及び第２電極部１７は貼り合わせ層１５を介して金属配線層３１に接合されている。第１電極部１６及び第２電極部１７の貼り合せ層（接合用金属層）１５と、金属配線層３１の接合用金属層３３とは、例えば、熱圧着接合や共晶接合などによって接合される。貼り合せ層１５及び接合用金属層３３の材料には、一例として、ＡｕやＡｕ共晶合金などが用いられる。ほぼ同一の平面上に位置する複数の第１電極部１６及び第２電極部１７の貼り合せ層１５の表面（貼り合せ面、接合面）と、ほぼ同一の平面上に位置する複数の金属配線層３１の接合用金属層３３の表面（貼り合せ面、接合面）とを、熱圧着などによって接合する面接合方式（貼り合せ方式）であるため、バンプを用いたフリップチップ実装（図１４参照）に比べて、接合は容易となり、接合不良の発生を抑えることができる。   The first electrode portion 16 and the second electrode portion 17 are bonded to the metal wiring layer 31 through the bonding layer 15. The bonding layer (joining metal layer) 15 of the first electrode part 16 and the second electrode part 17 and the joining metal layer 33 of the metal wiring layer 31 are joined by, for example, thermocompression bonding or eutectic bonding. The For example, Au or an Au eutectic alloy is used as the material for the bonding layer 15 and the bonding metal layer 33. A plurality of metal wirings positioned on substantially the same plane as the surface (bonding surface, bonding surface) of the bonding layer 15 of the plurality of first electrode portions 16 and second electrode portions 17 positioned on substantially the same plane. Flip chip mounting using bumps (see FIG. 14) because it is a surface bonding method (bonding method) in which the surface (bonding surface, bonding surface) of the bonding metal layer 33 of the layer 31 is bonded by thermocompression bonding or the like. ), The joining becomes easier and the occurrence of poor joining can be suppressed.

第２半導体層３の活性層４側とは反対側の面は、粗面化加工された光取出し面３ａとなっている。半導体発光素子１０の光取出し面３ａには、電極が形成されていないので、光取出し効率が高い。   The surface of the second semiconductor layer 3 opposite to the active layer 4 side is a light extraction surface 3a that has been roughened. Since no electrode is formed on the light extraction surface 3a of the semiconductor light emitting device 10, the light extraction efficiency is high.

本実施形態では、基板３０上に配設される金属配線層３１は、図２に示すように、複数の半導体発光素子１０を直列接続するパターンに形成されている。即ち、例えば、図２において、左右方向に並ぶ３個の半導体発光素子１０のうち、左端の半導体発光素子１０から、中央の半導体発光素子１０を経て、右端の半導体発光素子１０へと電流が流れる。具体的には、各半導体発光素子１０の第１電極部１６に接続された金属配線層３１から供給された電流は、第１電極部１６、第１コンタクト部１２を通じて第１半導体層５に供給され、第１半導体層５、活性層４及び第２半導体層３を通って第２コンタクト部１１より第２電極部１７に流れ、第２電極部１７から金属配線層３１を通じて当該半導体発光素子１０の右隣の半導体発光素子１０の第１電極部１６へと流れる。なお、基板３０上の金属配線層３１のパターンは、半導体発光素子１０の電極部・金属配線層構造を適宜変更することで、直列接続のみならず、並列接続、直列及び並列接続とすることもできる。   In the present embodiment, the metal wiring layer 31 disposed on the substrate 30 is formed in a pattern in which a plurality of semiconductor light emitting elements 10 are connected in series as shown in FIG. That is, for example, in FIG. 2, among the three semiconductor light emitting elements 10 arranged in the left-right direction, a current flows from the semiconductor light emitting element 10 at the left end to the semiconductor light emitting element 10 at the right end through the central semiconductor light emitting element 10. . Specifically, the current supplied from the metal wiring layer 31 connected to the first electrode portion 16 of each semiconductor light emitting element 10 is supplied to the first semiconductor layer 5 through the first electrode portion 16 and the first contact portion 12. The semiconductor light emitting element 10 flows through the first semiconductor layer 5, the active layer 4, and the second semiconductor layer 3 from the second contact portion 11 to the second electrode portion 17, and from the second electrode portion 17 through the metal wiring layer 31. Flows to the first electrode portion 16 of the semiconductor light emitting element 10 adjacent to the right side of. The pattern of the metal wiring layer 31 on the substrate 30 can be changed not only in series connection but also in parallel connection, series and parallel connection by appropriately changing the electrode part / metal wiring layer structure of the semiconductor light emitting element 10. it can.

本実施形態の発光ダイオード１００によれば、面接合方式（貼り合せ方式）により、半導体発光素子１０の第１電極部１６及び第２電極部１７を基板３０上の金属配線層３１に貼り合せているため、光取出し面３ａ側に影となる電極（遮蔽物）が存在せず、光取出し効率が高い。また、上記面接合方式によって第１電極部１６及び第２電極部１７と金属配線層３１とを接合する構成を採用することで、複数の半導体発光素子１０を有する発光ダイオード１００であっても、接合不良の発生を抑えることができると共に、接合の容易化が図れ、発光ダイオードの生産性・歩留りの向上を実現できる。さらに、半導体発光素子１０で発生した熱を第１電極部１６及び第２電極部１７から金属配線層３１を介して基板３０側に効率よく逃がすことができ、半導体発光素子１０への通電量を増加して輝度・発光量の増大を図ることも可能である。また、複数個の半導体発光素子１０を直列に設けることで、容易に電流値と輝度とを調節することができる。また、本実施形態の発光ダイオードは、光取出し効率が高く、放熱性も良好であるので、小型・省電力で、しかも十分な輝度・発光量を確保でき、表示用の発光ダイオードとして好適である。   According to the light emitting diode 100 of the present embodiment, the first electrode portion 16 and the second electrode portion 17 of the semiconductor light emitting element 10 are bonded to the metal wiring layer 31 on the substrate 30 by a surface bonding method (bonding method). Therefore, there is no shadow electrode (shielding object) on the light extraction surface 3a side, and the light extraction efficiency is high. Moreover, even if it is the light emitting diode 100 which has the some semiconductor light-emitting device 10 by employ | adopting the structure which joins the 1st electrode part 16 and the 2nd electrode part 17, and the metal wiring layer 31 by the said surface bonding system, The occurrence of defective bonding can be suppressed, the bonding can be facilitated, and the productivity and yield of the light emitting diode can be improved. Furthermore, the heat generated in the semiconductor light emitting device 10 can be efficiently released from the first electrode portion 16 and the second electrode portion 17 to the substrate 30 side via the metal wiring layer 31, and the amount of current supplied to the semiconductor light emitting device 10 can be reduced. It is also possible to increase the luminance and the amount of emitted light. Further, by providing a plurality of semiconductor light emitting elements 10 in series, the current value and the luminance can be easily adjusted. Further, the light emitting diode of this embodiment has high light extraction efficiency and good heat dissipation, so that it is small and power-saving, and can secure sufficient luminance and light emission, and is suitable as a light emitting diode for display. .

上記実施形態の半導体発光素子１０の素子サイズを、１辺が１００μｍ以上２５０μｍ以下の小型サイズとしたのは、次の理由からである。素子サイズを１００μｍより小さくすると、素子分離・貼り合せ工程において、高い精度が要求され、現状の技術では、工程時間が長くなり、コスト増を招く。一方、素子サイズを２５０μｍより大きくすることも勿論可能であるが、従来の上下電極タイプのＬＥＤ（図１３参照）との優位性などを考慮すると、貼り合わせを用いた本発明の構成が光取出し効率の向上等の観点から、より有効な範囲とするために、素子サイズの上限を２５０μｍとした。   The element size of the semiconductor light emitting element 10 of the above embodiment is a small size with one side being 100 μm or more and 250 μm or less for the following reason. If the element size is smaller than 100 μm, high accuracy is required in the element separation / bonding process, and the current technology increases the process time and causes an increase in cost. On the other hand, it is of course possible to make the element size larger than 250 μm. However, considering the superiority with the conventional upper and lower electrode type LED (see FIG. 13), the configuration of the present invention using bonding is a light extraction. From the viewpoint of improving efficiency, the upper limit of the element size is set to 250 μm in order to make the range more effective.

以下に、本実施形態の発光ダイオードの製造工程と共に、本実施形態の発光ダイオードを更に詳細に説明する。図３〜図６に本実施形態に係る発光ダイオード１００を製造する製造工程の一例を示す。   Below, the light emitting diode of this embodiment is demonstrated in detail with the manufacturing process of the light emitting diode of this embodiment. 3 to 6 show an example of a manufacturing process for manufacturing the light emitting diode 100 according to this embodiment.

（基板上への金属配線層の形成工程）
基板（支持基板）３０としては、光に対する透明性は必要としない。例えば、サファイア、Ｓｉ、ＧａＮ、ＡｌＮ、ＺｎＯ、ＳｉＣ、ＢＮ、ＺｎＳなどの単結晶基板、Ａｌ２Ｏ３、ＡＩＮ、ＢＮ、ＭｇＯ、ＺｎＯ、ＳｉＣ、Ｃ等のセラミクスやこれらの混合物などからなる基板を用いることができる。特に、基板３０の材料には、高抵抗で熱伝導性が高い材料が望ましい。
金属配線層３１は、図３（ａ）に示すように、基板３０上に密着層３２と接合用金属層３３とを順次形成し、フォトリソグラフィ法、エッチング法により配線パターンを形成す
ることが望ましい。密着層３２としては、ＴｉやＰｔを１ｎｍ以上５０ｎｍ以下の厚さで形成するのがよい。接合用金属層３３としては、ＡｕやＡｕ共晶合金などを用い、０.５
μｍ〜２.０μｍの厚さに形成するのがよい。 (Process for forming a metal wiring layer on a substrate)
The substrate (support substrate) 30 does not need transparency to light. For example, single crystal substrates such as sapphire, Si, GaN, AlN, ZnO, SiC, BN, ZnS, substrates made of ceramics such as Al 2 O 3 , AIN, BN, MgO, ZnO, SiC, C, and mixtures thereof. Can be used. In particular, the material of the substrate 30 is desirably a material having high resistance and high thermal conductivity.
As shown in FIG. 3A, the metal wiring layer 31 is preferably formed by sequentially forming an adhesion layer 32 and a bonding metal layer 33 on a substrate 30 and forming a wiring pattern by photolithography and etching. . The adhesion layer 32 is preferably formed of Ti or Pt with a thickness of 1 nm to 50 nm. As the bonding metal layer 33, Au, an Au eutectic alloy or the like is used, and 0.5.
It is good to form in thickness of micrometer-2.0micrometer.

（成長用基板上へのエピタキシャル層の形成工程）
半導体発光素子１０は、III−Ｖ族化合物半導体であるＡｌＧａＩｎＰ系のエピタキシ
ャル層を形成する場合、図３（ｂ）に示すように、まず、成長用基板として、例えば厚さ３００μｍ、Ｓｉドープのｎ型ＧａＡｓ基板１を用い、ｎ型ＧａＡｓ基板１上に、ＭＯＶＰＥ（有機金属気相成長）法により、ＧａＩｎＰエッチングストップ層２と、第２半導体層としてのＳｉドープのｎ型ＡｌＧａＩｎＰクラッド層３と、活性層としての量子井戸構造を含んで形成されるアンドープのＡｌＧａＩｎＰ活性層４と、第１半導体層としてのＭｇドープのｐ型ＡｌＧａＩｎＰクラッド層５とを順次成長させ、エピタキシャルウェハを形成する。なお、上記エピタキシャル層以外にも、例えば、ｐ型ＡｌＧａＩｎＰクラッド層５上にｐ型ＧａＰ等からなるｐ型コンタクト層を形成するなどしてもよい。
更に具体的には、ピーク波長が６３０ｎｍ付近の赤色光を発するＡｌＧａＩｎＰ系の半導体発光素子では、活性層４は、一例として、アンドープの（Ａｌ０.１Ｇａ０.９）０.
５Ｉｎ０.５Ｐ層を形成する。また、ｎ型クラッド層３は、Ｓｉ、Ｓｅ等のｎ型ドーパン
トを所定の濃度含む、ｎ型（Ａｌ０.７Ｇａ０.３）０.５Ｉｎ０.５Ｐ層を形成し、ｐ型クラッド層５は、Ｚｎ、Ｍｇ等のｐ型ドーパントを所定の濃度含む、ｐ型（Ａｌ０.７Ｇａ
０.３）０.５Ｉｎ０.５Ｐ層を形成する。 (Epitaxial layer formation process on growth substrate)
When forming an AlGaInP-based epitaxial layer that is a III-V group compound semiconductor, the semiconductor light emitting device 10 is first formed as a growth substrate, for example, with a thickness of 300 μm and Si-doped n as shown in FIG. A GaInP etching stop layer 2 and a Si-doped n-type AlGaInP cladding layer 3 as a second semiconductor layer on the n-type GaAs substrate 1 by a MOVPE (metal organic chemical vapor deposition) method. An undoped AlGaInP active layer 4 formed including a quantum well structure as an active layer and an Mg-doped p-type AlGaInP cladding layer 5 as a first semiconductor layer are sequentially grown to form an epitaxial wafer. In addition to the above epitaxial layer, for example, a p-type contact layer made of p-type GaP or the like may be formed on the p-type AlGaInP cladding layer 5.
More specifically, in an AlGaInP semiconductor light emitting device that emits red light having a peak wavelength of around 630 nm, the active layer 4 is, for example, undoped (Al 0.1 Ga 0.9 ) 0.9 .
A 5 In 0.5 P layer is formed. The n-type cladding layer 3 forms an n-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P layer containing an n-type dopant such as Si and Se at a predetermined concentration, and is p-type. The cladding layer 5 is p-type (Al 0.7 Ga) containing a predetermined concentration of p-type dopant such as Zn or Mg.
0.3 ) 0.5 In 0.5 P layer is formed.

（第１コンタクト部、第２コンタクト部の形成工程）
次に、図３（ｃ）に示すように、フォトリソグラフィ法およびエッチング法を用いて、第２コンタクト部としてのｎ型コンタクト部１１を形成するために、ｐ型ＡｌＧａＩｎＰクラッド層５及びＡｌＧａＩｎＰ活性層４を貫通する孔８を形成するとともに、エピタキシャルウェハの全面に透明絶縁膜として、例えばＳｉＯ２膜７を形成する。透明絶縁膜の材料には、ＳｉＯ２以外に、ＳｉＮなどを用いてもよい。
更に、透明絶縁膜であるＳｉＯ２膜７に対して、ｎ型コンタクト部１１、第１コンタクト部としてのｐ型コンタクト部１２を形成するための孔９がそれぞれ形成される。このとき、ｎ型コンタクト部１１用の孔８の側面に、ｐ型クラッド層５及び活性層４に対し絶縁をとるための絶縁膜を形成する。
なお、孔８が形成されるエピタキシャル層の厚さ１μｍ程度であるのに対し、孔８の直径は５〜１０μｍ程度（孔８のアスペクト比が０.１〜０.２程度）の大きさを有するので、ｎ型コンタクト部１１を形成する金属等の導電層の周囲に絶縁膜を形成しなくても、ｎ型コンタクト部１１を形成する導電層とｐ型クラッド層５及び活性層４との間の短絡を防止することは可能である。 (Formation process of a 1st contact part and a 2nd contact part)
Next, as shown in FIG. 3C, a p-type AlGaInP cladding layer 5 and an AlGaInP active layer are formed to form an n-type contact portion 11 as a second contact portion by using a photolithography method and an etching method. 4 is formed, and for example, a SiO 2 film 7 is formed as a transparent insulating film on the entire surface of the epitaxial wafer. As a material for the transparent insulating film, SiN or the like may be used in addition to SiO 2 .
Further, holes 9 for forming an n-type contact portion 11 and a p-type contact portion 12 as a first contact portion are formed in the SiO 2 film 7 which is a transparent insulating film. At this time, an insulating film for insulating the p-type cladding layer 5 and the active layer 4 is formed on the side surface of the hole 8 for the n-type contact portion 11.
The thickness of the epitaxial layer in which the hole 8 is formed is about 1 μm, whereas the diameter of the hole 8 is about 5 to 10 μm (the aspect ratio of the hole 8 is about 0.1 to 0.2). Therefore, the conductive layer forming the n-type contact portion 11, the p-type cladding layer 5, and the active layer 4 can be formed without forming an insulating film around the conductive layer such as a metal forming the n-type contact portion 11. It is possible to prevent a short circuit between them.

次に、ｎ型コンタクト部１１によるｎ型クラッド層３への電気的接続、及びｐ型コンタクト部１２によるｐ型クラッド層５への電気的接続は、図４（ａ）に示すように、これらの孔８，９にＡｕ系の金属を設けることで行う。ｎ型コンタクト部１１は、一例として、ｎ型クラッド層３側からＡｕＧｅ層（オーミックコンタクト層）／Ｎｉ層（拡散防止層）／Ａｕ層（接合層）が積層されて形成される。ｐ型コンタクト部１２は、一例として、ｐ型クラッド層５側からＡｕＢｅ層（オーミックコンタクト層）／Ｎｉ層（拡散防止層）／Ａｕ層（接合層）が積層されて形成される。
透明絶縁膜７と、ｎ型コンタクト部１１、ｐ型コンタクト部１２とにより、電流狭窄構造が形成される。ｎ型コンタクト部１１、ｐ型コンタクト部１２は、図２に示すようにドット状に複数個形成しても、或いは、環状や枝状に連続して形成しても良い。 Next, the electrical connection to the n-type cladding layer 3 by the n-type contact portion 11 and the electrical connection to the p-type cladding layer 5 by the p-type contact portion 12 are as shown in FIG. This is done by providing Au-based metal in the holes 8 and 9. As an example, the n-type contact portion 11 is formed by laminating an AuGe layer (ohmic contact layer) / Ni layer (diffusion prevention layer) / Au layer (bonding layer) from the n-type cladding layer 3 side. As an example, the p-type contact portion 12 is formed by laminating an AuBe layer (ohmic contact layer) / Ni layer (diffusion prevention layer) / Au layer (bonding layer) from the p-type cladding layer 5 side.
The transparent insulating film 7, the n-type contact portion 11, and the p-type contact portion 12 form a current confinement structure. The n-type contact portion 11 and the p-type contact portion 12 may be formed in a plurality of dots as shown in FIG. 2, or may be continuously formed in a ring shape or a branch shape.

（第１電極部、第２電極部の形成工程）
次に、透明絶縁膜７、ｎ型コンタクト部１１及びｐ型コンタクト部１２の上に、図４（
ｂ）に示すように、第１電極部であるｐ側電極部１６及び第２電極部であるｎ側電極部１７を構成するための電極層として、例えばＡｕからなる反射金属層１３と、Ｔｉからなる拡散抑止層１４と、Ａｕからなる接合用金属層１５とを蒸着法などで形成する。
更に、エピタキシャルウェハの透明絶縁膜７上において、ｐ側電極部１６となる領域とｎ側電極部１７となる領域とが導通しないように、反射金属層１３、拡散抑止層１４及び接合用金属層１５に対して、離間領域となる電極分離用溝１８と素子分離用溝１９を形成する。これにより、ｐ側電極部１６とｎ側電極部１７が分離されて形成される。
なお、ＳｉＯ２からなる透明絶縁膜７とＡｕからなる反射金属層１３との間には、密着層を形成しても良い。密着層としてはＮｉ層やＡｌ層がよく、例えば、厚さ１〜１０ｎｍに形成される。
また、本実施形態のように複数の半導体発光素子１０を直列に設ける場合は、隣り合う半導体発光素子１０の間の反射金属層１３、拡散抑止層１４及び接合用金属層１５を残すように素子分離を行うこともできる。半導体発光素子１０間の反射金属層１３や接合用金属層１５を残すことで、導電性や放熱性の向上が得られる。一方で、半導体発光素子１０間の反射金属層１３や接合用金属層１５を残す箇所と、除去する箇所を有することで、フォトリソグラフィ工程において工数が増加する。これらは、求められる発光ダイオードの特性により適宜選択すればよい。 (Formation process of a 1st electrode part and a 2nd electrode part)
Next, on the transparent insulating film 7, the n-type contact portion 11, and the p-type contact portion 12, FIG.
As shown in b), as an electrode layer for constituting the p-side electrode portion 16 as the first electrode portion and the n-side electrode portion 17 as the second electrode portion, for example, a reflective metal layer 13 made of Au, and Ti A diffusion suppression layer 14 made of and a bonding metal layer 15 made of Au are formed by vapor deposition or the like.
Further, on the transparent insulating film 7 of the epitaxial wafer, the reflective metal layer 13, the diffusion suppressing layer 14, and the bonding metal layer are formed so that the region serving as the p-side electrode portion 16 and the region serving as the n-side electrode portion 17 do not conduct. 15, an electrode isolation groove 18 and an element isolation groove 19 are formed as separation regions. Thereby, the p-side electrode portion 16 and the n-side electrode portion 17 are formed separately.
An adhesion layer may be formed between the transparent insulating film 7 made of SiO 2 and the reflective metal layer 13 made of Au. The adhesion layer is preferably a Ni layer or an Al layer, and is formed to have a thickness of 1 to 10 nm, for example.
Further, when a plurality of semiconductor light emitting elements 10 are provided in series as in the present embodiment, the elements are provided so as to leave the reflective metal layer 13, the diffusion suppression layer 14, and the bonding metal layer 15 between the adjacent semiconductor light emitting elements 10. Separation can also be performed. By leaving the reflective metal layer 13 and the bonding metal layer 15 between the semiconductor light emitting elements 10, the conductivity and heat dissipation can be improved. On the other hand, the number of man-hours increases in the photolithography process by having a portion where the reflective metal layer 13 and the bonding metal layer 15 between the semiconductor light emitting elements 10 are left and a portion where the metal layer 15 is removed. These may be appropriately selected depending on the required characteristics of the light emitting diode.

（貼り合せ工程）
図３（ａ）に示す金属配線層３１を形成した基板（支持基板）３０と、図４（ｂ）に示すｐ側電極部１６及びｎ側電極部１７を有する半導体発光素子１０が形成されたエピタキシャルウェハとを、図５（ａ）に示すように、張り合わせて貼り合せウェハを作製する。
具体的には、マイクロマシーン用の位置合わせ機能付きの貼り合せ装置を用い、金属配線層３１とｐ側電極部１６及びｎ側電極部１７との位置合わせを行い、金属配線層３１の接合用金属層３３とｐ側電極部１６及びｎ側電極部１７の接合用金属層１５とを密接させて熱圧着により張り合わせる。具体的には、貼り合せ装置内に支持基板３０とエピタキシャルウェハをそれぞれセットし、高真空下において、３５０℃まで昇温するとともに加圧して密着状態にする。この状態を１時間保持した後、室温まで降温するとともに、加圧を開放し、大気圧まで戻すことで、貼り合せウェハを得る。なお、基板３０とエピタキシャルウェハとの貼り合せは、熱圧着による接合以外にも、共晶接合などで行っても良い。 (Lamination process)
The substrate (support substrate) 30 on which the metal wiring layer 31 shown in FIG. 3A was formed, and the semiconductor light emitting element 10 having the p-side electrode portion 16 and the n-side electrode portion 17 shown in FIG. 4B were formed. As shown in FIG. 5A, an epitaxial wafer is bonded to produce a bonded wafer.
Specifically, using a bonding apparatus with an alignment function for a micromachine, the metal wiring layer 31 is aligned with the p-side electrode portion 16 and the n-side electrode portion 17 to bond the metal wiring layer 31. The metal layer 33 and the bonding metal layer 15 of the p-side electrode part 16 and the n-side electrode part 17 are brought into close contact and bonded together by thermocompression bonding. Specifically, the support substrate 30 and the epitaxial wafer are set in a bonding apparatus, respectively, heated to 350 ° C. and pressurized to be in a close contact state under high vacuum. After maintaining this state for 1 hour, the temperature is lowered to room temperature, the pressure is released, and the pressure is returned to atmospheric pressure, whereby a bonded wafer is obtained. The bonding of the substrate 30 and the epitaxial wafer may be performed by eutectic bonding or the like in addition to bonding by thermocompression bonding.

（成長用基板の除去、粗面化加工の工程）
貼り合せウェハの成長用基板１を除去するために、貼り合せウェハの成長用基板１側が表になるように研磨板に貼り付け、ラッピングにより成長用基板１を研磨していく。そして成長用基板１の残り厚さが所定の厚さ、例えば３０μｍとなったところで研磨をやめ、貼り合せウェハを研磨板から取り外し、貼り合せウェハから貼り付け用のワックスを除去後、エッチングに拠り完全に成長用基板１を除去する。なお、成長用基板１の除去は、上記のようにラッピングとエッチングとを組み合わせて行う方法に限らず、ラッピングのみによって行うこともできるし、エッチングのみによって行っても良い。
成長用基板１としてＧａＡｓを用いている場合、ＧａＡｓ用のエッチング液にはアンモニア水と過酸化水素水との混合液などを用いることができる。エッチングストップ層２を成長用基板１との界面に形成しておくことで、複雑な管理を必要とすることなく成長用基板１を完全に除去することができる。成長用基板であるＧａＡｓ基板１を除去した後、エッチング液を代えてエッチングストップ層２を除去する（図５（ｂ））。エッチングストップ層２がＧａＩｎＰにより形成される場合、塩酸系のエッチング溶液を用いると良い。 (Growth substrate removal, roughening process)
In order to remove the growth substrate 1 of the bonded wafer, the growth substrate 1 is bonded to a polishing plate so that the growth substrate 1 side of the bonded wafer is facing, and the growth substrate 1 is polished by lapping. Then, when the remaining thickness of the growth substrate 1 reaches a predetermined thickness, for example, 30 μm, polishing is stopped, the bonded wafer is removed from the polishing plate, the wax for bonding is removed from the bonded wafer, and then etching is performed. The growth substrate 1 is completely removed. The removal of the growth substrate 1 is not limited to the method of combining lapping and etching as described above, but can be performed only by lapping or only by etching.
When GaAs is used as the growth substrate 1, a mixed liquid of ammonia water and hydrogen peroxide water or the like can be used as an etching solution for GaAs. By forming the etching stop layer 2 at the interface with the growth substrate 1, the growth substrate 1 can be completely removed without requiring complicated management. After removing the GaAs substrate 1 as a growth substrate, the etching solution is changed and the etching stop layer 2 is removed (FIG. 5B). When the etching stop layer 2 is formed of GaInP, a hydrochloric acid-based etching solution may be used.

ＧａＡｓ基板１及びエッチングストップ層２を除去後、露出したｎ型クラッド層３の表面である光取出し面３ａに対して粗面化を行う。粗面化には、例えば、フォトリソグラフィ技術を用いて、図６（ａ）に示すように、ｎ型クラッド層３の光取出し面３ａに鋭角の先端部を有する錐伏の凹凸を形成するとよい。これにより半導体発光素子１０の外部への
光取出し効率の向上が図れる。なお、ｎ型クラッド層３の錐伏の凹凸を有する光取出し面３ａ上に、ｎ型クラッド層３の屈折率よりも低い屈折率を有するＳｉＯ２等の透明膜を形成してもよい。ＳｉＯ２等の透明膜を設けることで、光取出し面３ａが保護されると共に、光取出し面３ａの最表面がなだらかな波型の曲面になるので、レンズ効果による光取出し効率も向上する。 After removing the GaAs substrate 1 and the etching stop layer 2, the light extraction surface 3a which is the surface of the exposed n-type cladding layer 3 is roughened. For roughening, for example, as shown in FIG. 6A, concavity and convexity having an acute tip portion may be formed on the light extraction surface 3a of the n-type cladding layer 3 by using a photolithography technique. . Thereby, the light extraction efficiency to the outside of the semiconductor light emitting element 10 can be improved. A transparent film such as SiO 2 having a refractive index lower than that of the n-type cladding layer 3 may be formed on the light extraction surface 3 a having the concavity and convexity of the n-type cladding layer 3. By providing a transparent film such as SiO 2 , the light extraction surface 3a is protected, and the outermost surface of the light extraction surface 3a is a gently wavy curved surface, so that the light extraction efficiency due to the lens effect is improved.

（素子分離及びダイシング工程）
次に、第１電極部１６と第２電極部１７との間に形成された素子分離用溝１９の上方に位置する、半導体発光層６及び透明絶縁膜７をフォトリソグラフィ法およびエッチング法により除去し、素子分離用溝２０を形成して、所定サイズの複数の半導体発光素子１０に素子分離する。また、金属配線層３１上に、パッド電極を形成する場合には、パッド電極を形成する領域の半導体発光層６等もエッチングして金属配線層３１を露出させる。
各半導体発光素子１０に分離した後、所定個数の半導体発光素子１０を有する発光ダイオードとなるように、エッチングにより、所定の形状に半導体発光層６等に切断用の溝（図示せず）を形成し、この切断用の溝の位置でダイシングブレードによって基板３０等の切断を行い、所定サイズの発光ダイオードに切り分ける。なお、半導体発光素子１０の側面に低屈折率の透明絶縁膜を形成することで、半導体発光素子１０の側面を保護すると共に、光取出し効率の向上を図るようにしてもよい。この透明絶縁膜には、例えば、ＳｉＯ２、ＳｉＮなどが用いられる。
その後、発光ダイオードをステム等に搭載する際に確実に固定できるようにするために、基板３０の裏面にダイボンディング用の密着層３４を形成する。 (Element isolation and dicing process)
Next, the semiconductor light emitting layer 6 and the transparent insulating film 7 located above the element isolation groove 19 formed between the first electrode portion 16 and the second electrode portion 17 are removed by photolithography and etching. Then, element isolation trenches 20 are formed to isolate the plurality of semiconductor light emitting elements 10 having a predetermined size. When a pad electrode is formed on the metal wiring layer 31, the semiconductor light emitting layer 6 and the like in the region where the pad electrode is formed are also etched to expose the metal wiring layer 31.
After separating into each semiconductor light emitting element 10, a groove (not shown) for cutting is formed in the semiconductor light emitting layer 6 or the like in a predetermined shape by etching so as to become a light emitting diode having a predetermined number of semiconductor light emitting elements 10. Then, the substrate 30 or the like is cut by a dicing blade at the position of the cutting groove, and is cut into light-emitting diodes of a predetermined size. Note that a transparent insulating film having a low refractive index may be formed on the side surface of the semiconductor light emitting device 10 to protect the side surface of the semiconductor light emitting device 10 and improve the light extraction efficiency. For example, SiO 2 or SiN is used for the transparent insulating film.
Thereafter, an adhesion layer 34 for die bonding is formed on the back surface of the substrate 30 so that the light emitting diode can be securely fixed when mounted on the stem or the like.

［他の実施形態]
上記第１の実施形態では、複数の半導体発光素子１０を直列に接続した発光ダイオード１００について説明したが、複数の半導体発光素子１０を並列に接続したり、或いは直列と並列を組み合わせて接続したりしても良い。図７（ａ）には、３個の半導体発光素子１０が並列に接続された電極部・配線構造の例を示す。また、図７（ｂ）には、図中、右側の直列接続の２つの半導体発光素子１０と、左側の直列接続の２つの半導体発光素子１０とが、並列に接続された電極部・配線構造の例を示す。 [Other Embodiments]
In the first embodiment, the light emitting diode 100 in which a plurality of semiconductor light emitting elements 10 are connected in series has been described. However, a plurality of semiconductor light emitting elements 10 are connected in parallel, or a combination of series and parallel is connected. You may do it. FIG. 7A shows an example of an electrode portion / wiring structure in which three semiconductor light emitting elements 10 are connected in parallel. FIG. 7B shows an electrode portion / wiring structure in which two semiconductor light emitting elements 10 connected in series on the right side and two semiconductor light emitting elements 10 connected in series on the left side are connected in parallel. An example of

上記実施形態では、複数の半導体発光素子１０を直列や並列に接続した発光ダイオードについて説明したが、本発明の発光ダイオードは、図８に示すように、基板３０上に１個の半導体発光素子１０が形成された１素子タイプの発光ダイオードでも勿論よい。   In the above embodiment, a light emitting diode in which a plurality of semiconductor light emitting elements 10 are connected in series or in parallel has been described. However, the light emitting diode of the present invention has one semiconductor light emitting element 10 on a substrate 30 as shown in FIG. Of course, a one-element type light emitting diode in which is formed may be used.

また、図９に示すように、基板３０に貫通孔（スルーホール）を形成し、当該貫通孔に導電性材料を充填することで、金属配線層３１に電気的に接続される裏面コンタクト部３５を形成しても良い。裏面コンタクト部３５を採用することで、金属配線層３１にパッド電極の領域を設ける必要がなくなり、発光ダイオードの小型化に寄与する。また、発光ダイオードを小型化すると精度の良いワイヤボンディングが必要となるが、裏面コンタクト部３５を有する構造では、ワイヤボンディングの工程が不要となり、電極部や配線の構造・接続のさらなる簡略化が可能となり、１素子タイプの発光ダイオードでも、その取り扱いが容易となる。   Further, as shown in FIG. 9, a back contact portion 35 that is electrically connected to the metal wiring layer 31 by forming a through hole (through hole) in the substrate 30 and filling the through hole with a conductive material. May be formed. By employing the back contact portion 35, it is not necessary to provide a pad electrode region in the metal wiring layer 31, which contributes to downsizing of the light emitting diode. In addition, when the light emitting diode is downsized, accurate wire bonding is required. However, in the structure having the back contact portion 35, the wire bonding step is not required, and the structure and connection of the electrode portion and wiring can be further simplified. Thus, even a single element type light emitting diode can be handled easily.

また、上記実施形態の発光ダイオードは、基板上にＡｌＧａＩｎＰ系の半導体発光素子が形成されたものであったが、窒化ガリウム系の半導体発光素子が形成された発光ダイオードにも適用できる。この場合、例えば、成長用基板にサファイアを用いて、窒化ガリウム系の半導体発光層を形成する。
また、上記実施形態において、半導体発光層６のｎ型、ｐ型の導電型を逆にして構成しても良い。 Further, although the light emitting diode of the above embodiment has an AlGaInP semiconductor light emitting element formed on a substrate, it can also be applied to a light emitting diode in which a gallium nitride semiconductor light emitting element is formed. In this case, for example, sapphire is used as a growth substrate to form a gallium nitride based semiconductor light emitting layer.
In the above embodiment, the n-type and p-type conductivity types of the semiconductor light emitting layer 6 may be reversed.

次に、本発明の実施例を説明する。   Next, examples of the present invention will be described.

本発明の上記第１の実施形態に係る発光ダイオードの構造に基づいて、実施例に係る発光ダイオードを製造した。
図１０に、実施例の発光ダイオードにおける複数の半導体発光素子の接続関係を示す。実施例では、支持基板３０上に形成された金属配線層３１に対して、７個の半導体発光素子１０を直列接続に配置した。具体的には、図１０に示すように、矩形状の支持基板３０上の対角配置にある２つの金属配線層３１にパッド電極４０を形成し、この２つのパッド電極４０、４０間に電圧を加え、金属配線層３１を通じて、７個のＳ字状に直列接続された半導体発光素子１０に電流が流れるように構成した。 Based on the structure of the light emitting diode according to the first embodiment of the present invention, the light emitting diode according to the example was manufactured.
FIG. 10 shows a connection relation of a plurality of semiconductor light emitting elements in the light emitting diode of the example. In the example, seven semiconductor light emitting elements 10 are arranged in series with respect to the metal wiring layer 31 formed on the support substrate 30. Specifically, as shown in FIG. 10, a pad electrode 40 is formed on two metal wiring layers 31 in a diagonal arrangement on a rectangular support substrate 30, and a voltage is applied between the two pad electrodes 40, 40. In addition, a current is allowed to flow through the metal wiring layer 31 to the seven semiconductor light emitting devices 10 connected in series in an S shape.

半導体発光素子１０は、ｎ型のＡｌＧａＩｎＰからなるｎ型クラッド層と、量子井戸構造からなる活性層（発光層）と、ｐ型のＡｌＧａＩｎＰからなるｐ型クラッド層とを有し、透明絶縁膜は、ＳｉＯ２膜から形成した。また、ｐ型コンタクト部には、ｐ型クラッド層側からＡｕＢｅ層／Ｎｉ層／Ａｕ層を設けて形成した。ｎ型コンタク卜部としては、ｎ型クラッド層側から、ＡｕＧｅ層／Ｎｉ層／Ａｕ層を設けて形成した。なお、ｎ型コンタク卜部は、ｐ型クラッド層及び活性層との側面側にＳｉＯ２による絶縁膜を備えることで、ｐ型クラッド層、活性層との絶縁を実現している。ｎ側電極部及びｐ側電極部は、金属反射層としてはＡｕ層を用い、拡散防止層（合金化抑止層）としてＴｉ層を用い、接合用金属層としてＡｕ層を用いた。
上記半導体発光素子１０と接合された、金属配線層３１を有する支持基板３０としては、１００μｍ厚の高抵抗の絶縁性Ｓｉ基板を用いた。また、金属配線層３１の密着層としてＴｉ層を用い、接合用金属層としてＡｕ層を用いた。 The semiconductor light emitting device 10 has an n-type cladding layer made of n-type AlGaInP, an active layer (light-emitting layer) made of a quantum well structure, and a p-type cladding layer made of p-type AlGaInP. , Formed from a SiO 2 film. Further, the p-type contact portion was formed by providing an AuBe layer / Ni layer / Au layer from the p-type cladding layer side. The n-type contact flange was formed by providing an AuGe layer / Ni layer / Au layer from the n-type cladding layer side. Note that the n-type contact flange portion is provided with an insulating film made of SiO 2 on the side surface side of the p-type cladding layer and the active layer, thereby realizing insulation from the p-type cladding layer and the active layer. In the n-side electrode portion and the p-side electrode portion, an Au layer was used as the metal reflection layer, a Ti layer was used as the diffusion prevention layer (alloying suppression layer), and an Au layer was used as the bonding metal layer.
As the support substrate 30 having the metal wiring layer 31 bonded to the semiconductor light emitting element 10, a high resistance insulating Si substrate having a thickness of 100 μm was used. Further, a Ti layer was used as the adhesion layer of the metal wiring layer 31, and an Au layer was used as the bonding metal layer.

半導体発光素子１０の素子サイズと発光出力などの関係を調べるために、半導体発光素子１０の素子サイズが異なる４種の発光ダイオード（実施例１〜実施例４）を作製した。実施例１の半導体発光素子１０の素子サイズは、１００μｍ×１００μｍとし、実施例２の半導体発光素子１０の素子サイズは、１５０μｍ×１５０μｍとし、実施例３の半導体発光素子１０の素子サイズは、２００μｍ×２００μｍとし、実施例４の半導体発光素子１０の素子サイズは、２５０μｍ×２５０μｍとした。実施例１〜実施例４の発光ダイオードにおいて、半導体発光素子１０に流れる電流密度が同じになるように通電電流を設定し、発光出力を測定した。   In order to investigate the relationship between the element size of the semiconductor light emitting element 10 and the light emission output, four types of light emitting diodes (Example 1 to Example 4) having different element sizes of the semiconductor light emitting element 10 were produced. The element size of the semiconductor light emitting element 10 of Example 1 is 100 μm × 100 μm, the element size of the semiconductor light emitting element 10 of Example 2 is 150 μm × 150 μm, and the element size of the semiconductor light emitting element 10 of Example 3 is 200 μm. The element size of the semiconductor light emitting element 10 of Example 4 was 250 μm × 250 μm. In the light emitting diodes of Examples 1 to 4, the energization current was set so that the current density flowing in the semiconductor light emitting element 10 was the same, and the light emission output was measured.

（比較例１〜４）
実施例の発光ダイオードと比較するために、図１３に示すような、上部電極２１１、下部電極２１２を有する上下電極構造の７個の半導体発光素子（ＬＥＤチップ）２１０を、ワイヤボンディング２１３により直列接続した比較例１〜４の発光ダイオードを作製した。
比較例１〜４の半導体発光素子２１０の各素子サイズは、実施例１〜４に合わせて、それぞれ１００μｍ×ｌ００μｍ（比較例１）、１５０μｍ×１５０μｍ（比較例２）、２００μｍ×２００μｍ（比較例３）、２５０μｍ×２５０μｍ（比較例４）とした。また、実施例１〜４と同様に、これら比較例１〜４の半導体発光素子２１０に流れる電流密度が同じになるように通電電流を設定し、発光出力を測定した。 (Comparative Examples 1-4)
For comparison with the light emitting diode of the example, as shown in FIG. 13, seven semiconductor light emitting elements (LED chips) 210 having upper and lower electrode structures having an upper electrode 211 and a lower electrode 212 are connected in series by wire bonding 213. The light emitting diodes of Comparative Examples 1 to 4 were manufactured.
The device sizes of the semiconductor light emitting devices 210 of Comparative Examples 1 to 4 are 100 μm × 100 μm (Comparative Example 1), 150 μm × 150 μm (Comparative Example 2), and 200 μm × 200 μm (Comparative Example), respectively, in accordance with Examples 1 to 4. 3), 250 μm × 250 μm (Comparative Example 4). Similarly to Examples 1 to 4, the energization current was set so that the current densities flowing in the semiconductor light emitting devices 210 of Comparative Examples 1 to 4 were the same, and the light emission output was measured.

図１１に、各素子サイズの実施例１〜４及び比較例１〜４に対し、測定された光束（ｌｍ）の測定結果を示す。また、表１に、実施例１〜４及び比較例１〜４における通電電流（ｍＡ）、光束（ｌｍ）、動作電圧（Ｖ）、および発光効率（ｌｍ／Ｗ）を示す。

Figure 2012054422
In FIG. 11, the measurement result of the measured light beam (lm) is shown with respect to Examples 1 to 4 and Comparative Examples 1 to 4 of each element size. Table 1 shows the energization current (mA), the luminous flux (lm), the operating voltage (V), and the luminous efficiency (lm / W) in Examples 1 to 4 and Comparative Examples 1 to 4.
Figure 2012054422

図１１及び表１に示すように、素子サイズ２５０μｍの半導体発光素子１０を用いた実施例４では、半導体発光素子１０の表面に上部電極が無いことで、上部電極２１１を有する半導体発光素子２１０の比較例４に比べて、光束のアップ率は約２０％向上した。この光束増大の効果は、発光素子サイズが小さくなるにつれて大きくなり、素子サイズ２００μｍの実施例３では、比較例３よりも５８％アップし、素子サイズ１５０μｍの実施例２では、比較例２よりも１００％アッブし、更に素子サイズ１００の実施例１では、比較例１よりも４３０％アップと顕著な効果を示した。また同様に、表１に示すように比較例１〜４に比べて、実施例１〜４では、発光効率が大幅に向上した。   As shown in FIG. 11 and Table 1, in Example 4 using the semiconductor light-emitting element 10 having an element size of 250 μm, the semiconductor light-emitting element 210 having the upper electrode 211 has no upper electrode on the surface of the semiconductor light-emitting element 10. Compared with Comparative Example 4, the luminous flux increase rate was improved by about 20%. The effect of increasing the luminous flux increases as the light emitting element size is reduced. In Example 3 with an element size of 200 μm, the effect is 58% higher than in Comparative Example 3, and in Example 2 with an element size of 150 μm, it is higher than in Comparative Example 2. In Example 1 where the element size was 100%, and the element size was 100, a remarkable effect of 430% over the Comparative Example 1 was obtained. Similarly, as shown in Table 1, the light emission efficiency was significantly improved in Examples 1 to 4 as compared to Comparative Examples 1 to 4.

（比較例５〜８）
また、実施例の発光ダイオードと比較するために、図１４に示すような、チップ片面に設けられた２つの電極２２１，２２２上にバンプ２２３が形成されたフリップチップ構造の半導体発光素子（ＬＥＤチップ）２２０を用い、金属配線２２４上にバンプ２２３を介して半導体発光素子２２０を実装し、７個の半導体発光素子２２０を直列接続とした比較例５〜８の発光ダイオードを作製した。
比較例５〜８の半導体発光素子２２０の各素子サイズは、実施例１〜４に合わせて、それぞれ１００μｍ×ｌ００μｍ（比較例５）、１５０μｍ×１５０μｍ（比較例６）、２００μｍ×２００μｍ（比較例７）、２５０μｍ×２５０μｍ（比較例８）とした。また、実施例１〜４と同様に、これら比較例５〜８の半導体発光素子２２０に流れる電流密度が同じになるように通電電流を設定し、発光出力を測定した。 (Comparative Examples 5 to 8)
Further, for comparison with the light emitting diode of the embodiment, as shown in FIG. 14, a semiconductor light emitting element (LED chip) having a flip chip structure in which bumps 223 are formed on two electrodes 221 and 222 provided on one side of the chip. ) 220, the semiconductor light emitting element 220 was mounted on the metal wiring 224 via the bump 223, and the light emitting diodes of Comparative Examples 5 to 8 in which the seven semiconductor light emitting elements 220 were connected in series were manufactured.
The device sizes of the semiconductor light emitting devices 220 of Comparative Examples 5 to 8 are 100 μm × 100 μm (Comparative Example 5), 150 μm × 150 μm (Comparative Example 6), and 200 μm × 200 μm (Comparative Example), respectively, in accordance with Examples 1 to 4. 7), 250 μm × 250 μm (Comparative Example 8). Further, similarly to Examples 1 to 4, the energization current was set so that the current densities flowing in the semiconductor light emitting elements 220 of Comparative Examples 5 to 8 were the same, and the light emission output was measured.

図１２に、各素子サイズの実施例１〜４及び比較例５〜８に対し、測定された光束（光束の平均値及びばらつき）の測定結果を示す。また、表２に、実施例１〜４及び比較例５〜８における光束の平均値、最大値及び最小値を示す。

Figure 2012054422
In FIG. 12, the measurement result of the measured light beam (average value and dispersion | variation of a light beam) is shown with respect to Examples 1-4 and Comparative Examples 5-8 of each element size. Table 2 shows the average value, maximum value, and minimum value of the luminous fluxes in Examples 1-4 and Comparative Examples 5-8.
Figure 2012054422

同一の素子サイズの実施例１〜４及び比較例５〜８を比較すると、図１２、表２に示すように、測定された光束の値は、実施例１〜４よりも比較例５〜８の方が低くなっているが、どちらも半導体発光素子の表面に上部電極が無いことから、上下電極構造の半導体発光素子２１０を用いた比較例１〜４に比べて、大幅な差は生じなかった。しかし、光束のばらつきに関しては、バンプを用いたフリップチップ構造の比較例５〜８の方が光束が小さい半導体発光素子２２０が発生し、半導体発光素子２２０の光束のばらつきが大きくなっていることがわかった。光束の低い半導体発光素子２２０を調べてみると、発光にムラが生じており、バンプ接続が良好でないことがわかった。   When Examples 1 to 4 and Comparative Examples 5 to 8 having the same element size are compared, as shown in FIG. 12 and Table 2, the measured light flux values are Comparative Examples 5 to 8 rather than Examples 1 to 4. Although both are lower, since there is no upper electrode on the surface of the semiconductor light emitting device, there is no significant difference compared to Comparative Examples 1 to 4 using the semiconductor light emitting device 210 with the upper and lower electrode structures. It was. However, regarding the variation in the luminous flux, the comparative examples 5 to 8 having the flip chip structure using the bumps generate the semiconductor light emitting element 220 having a smaller luminous flux, and the variation in the luminous flux of the semiconductor light emitting element 220 is larger. all right. When the semiconductor light emitting device 220 having a low luminous flux was examined, it was found that light emission was uneven and the bump connection was not good.

１ 成長用基板
３ 第２半導体層（ｎ型クラッド層）
３ａ 光取出し面
４ 活性層
５ 第１半導体層（ｐ型クラッド層）
６ 半導体発光層
７ 透明絶縁膜（ＳｉＯ２膜）
１０ 半導体発光素子
１１ 第２コンタクト部（ｎ型コンタクト部）
１２ 第１コンタクト部（ｐ型コンタクト部）
１３ 金属反射層
１４ 拡散防止層
１５ 貼り合せ層（接合用金属層）
１６ 第１電極部（ｐ側電極部）
１７ 第２電極部（ｎ側電極部）
１８ 離間領域（電極分離用溝）
１９ 離間領域（素子分離用溝）
３０ 基板
３１ 金属配線層
３３ 接合用金属層
３５ 裏面コンタクト部
１００ 発光ダイオード 1 Growth substrate 3 Second semiconductor layer (n-type cladding layer)
3a Light extraction surface 4 Active layer 5 First semiconductor layer (p-type cladding layer)
6 Semiconductor light emitting layer 7 Transparent insulating film (SiO 2 film)
10 Semiconductor Light Emitting Element 11 Second Contact Part (n-type Contact Part)
12 First contact part (p-type contact part)
13 Metal reflection layer 14 Diffusion prevention layer 15 Bonding layer (metal layer for bonding)
16 1st electrode part (p side electrode part)
17 2nd electrode part (n side electrode part)
18 Separation area (electrode separation groove)
19 Separation region (element isolation groove)
30 Substrate 31 Metal wiring layer 33 Bonding metal layer 35 Back contact portion 100 Light emitting diode

Claims (8)

基板と、
前記基板上に配設される金属配線層と、
前記金属配線層上に設けられる半導体発光素子と、を有し、
前記半導体発光素子は、
１辺が１００μｍ以上２５０μｍ以下であり、
前記基板側から順に、第１半導体層、活性層、第２半導体層を備えた半導体発光層と、
前記半導体発光層の前記基板側に設けられる透明絶縁膜と、
前記透明絶縁膜の前記基板側に離間領域を介して設けられ、前記金属配線層と電気的に接続される第１電極部及び第２電極部と、を有し、
前記第１電極部は、前記透明絶縁膜を貫通して設けられる第１コンタク卜部により前記第１半導体層と電気的に接続され、
前記第２電極部は、前記透明絶縁膜、前記第１半導体層、及び前記活性層を貫通して設けられる第２コンタクト部により前記第２半導体層と電気的に接続される、
ことを特徴とする発光ダイオード。 A substrate,
A metal wiring layer disposed on the substrate;
A semiconductor light emitting device provided on the metal wiring layer,
The semiconductor light emitting element is
One side is 100 μm or more and 250 μm or less,
In order from the substrate side, a semiconductor light emitting layer including a first semiconductor layer, an active layer, and a second semiconductor layer;
A transparent insulating film provided on the substrate side of the semiconductor light emitting layer;
A first electrode portion and a second electrode portion that are provided on the substrate side of the transparent insulating film via a separation region and are electrically connected to the metal wiring layer;
The first electrode part is electrically connected to the first semiconductor layer by a first contact part provided through the transparent insulating film,
The second electrode part is electrically connected to the second semiconductor layer by a second contact part provided through the transparent insulating film, the first semiconductor layer, and the active layer.
A light emitting diode characterized by that. 前記金属配線層上には、複数の前記半導体発光素子が設けられていることを特徴とする請求項１に記載の発光ダイオード。   The light emitting diode according to claim 1, wherein a plurality of the semiconductor light emitting elements are provided on the metal wiring layer. 前記第１電極部及び／又は前記第２電極部は、金属反射層を備えていることを特徴とする請求項１または２に記載の発光ダイオード。   The light emitting diode according to claim 1 or 2, wherein the first electrode part and / or the second electrode part includes a metal reflective layer. 前記第１電極部及び前記第２電極部は貼り合わせ層を有し、前記貼り合せ層を介して前記金属配線層と接合されていることを特徴とする請求項１〜３のいずれかに記載の発光ダイオード。   The said 1st electrode part and the said 2nd electrode part have a bonding layer, and are joined to the said metal wiring layer via the said bonding layer. Light emitting diode. 前記第２半導体層の上記活性層側とは反対側の面は、粗面化加工された光取出し面であることを特徴とする請求項１〜４のいずれかに記載の発光ダイオード。   5. The light emitting diode according to claim 1, wherein a surface of the second semiconductor layer opposite to the active layer is a roughened light extraction surface. 前記第２コンタク卜部は、前記第２電極部上に設けられ、前記第１半導体層及び前記活性層に対して絶縁するための絶縁材料と、前記絶縁材料に覆われるように設けられるＡｕ系材料とからなることを特徴とする請求項１〜５のいずれかに記載の発光ダイオード。   The second contact hole part is provided on the second electrode part, and is provided with an insulating material for insulating from the first semiconductor layer and the active layer, and an Au-based material provided so as to be covered with the insulating material. The light-emitting diode according to claim 1, wherein 前記金属配線層は、複数の前記半導体発光素子を直列接続するパターンに形成されていることを特徴とする請求項１〜６のいずれかに記載の発光ダイオード。   The light emitting diode according to claim 1, wherein the metal wiring layer is formed in a pattern in which a plurality of the semiconductor light emitting elements are connected in series. 前記基板に貫通孔が形成され、前記貫通孔に導電性材料が設けられることで前記金属配線層に電気的に接続される裏面コンタクト部が形成されていることを特徴とする請求項１〜７のいずれかに記載の発光ダイオード。   8. A back contact portion that is electrically connected to the metal wiring layer is formed by forming a through hole in the substrate and providing a conductive material in the through hole. The light emitting diode in any one of.
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