JP2011252218A - Method for fabricating electronic component and electro-plating apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method that controls dissolution of a seed film and reduces undeposition of a plating film and generation of defects after electro-plating is performed.SOLUTION: A method for fabricating an electronic component according to an embodiment, includes a seed film forming process S110 and a plating process S114. In the seed film forming process S110, the seed film is formed above a substrate. In the plating process S114, electro-plating is performed by soaking the seed film in a plating solution in a plating bath to which the plating solution being bubbled by a nitrogen gas is supplied, using the seed film as a cathode.

Description

  Embodiments described herein relate generally to an electronic component manufacturing method and an electrolytic plating apparatus.

  In recent years, new microfabrication techniques have been developed along with higher integration and higher performance of semiconductor integrated circuits (LSIs). In particular, recently, in order to achieve high speed LSI, the wiring material is changed from a conventional aluminum (Al) alloy to a low resistance copper (Cu) or Cu alloy (that is, a copper-containing material, hereinafter collectively referred to as Cu). ) Is moving forward. Since Cu is difficult to be finely processed by dry etching methods such as RIE (reactive ion etching) frequently used in the formation of Al alloy wiring, a Cu film is deposited on the insulating film subjected to the groove processing. The so-called damascene method, in which the Cu film other than the portion embedded in the groove is removed by a chemical mechanical polishing (CMP) method to form a buried wiring, is mainly used. Has been. The Cu film is generally formed by forming a thin Cu seed layer by sputtering or the like and then forming a laminated film having a thickness of about several hundreds of nanometers by electrolytic plating. Further, when forming a multilayer Cu wiring, a wiring forming method called a dual damascene structure can be used. In such a method, after depositing an insulating film on the lower layer wiring and forming a predetermined via hole (hole) and a trench for upper layer wiring (wiring groove), Cu serving as a wiring material is simultaneously buried in the via hole and the trench, Further, unnecessary wiring in the upper layer is removed by CMP and planarized to form a buried wiring.

  Here, the Cu seed film formed by the sputtering method has a particularly thin sidewall, and is easily dissolved in the plating solution. Since no current flows even if electrolytic plating is attempted in the portion where the Cu seed film is dissolved, the Cu film is not formed. For this reason, even when the Cu film is completely filled with the Cu film grown from the surroundings, there is a problem in that the adhesion between the side wall and the Cu film is low and a defect occurs.

JP 2004-210808 A

  An object of the present invention is to provide a method for overcoming the above-described problems, suppressing the dissolution of a seed film, and reducing the occurrence of undeposited or defective plating film after electrolytic plating.

  The electronic component manufacturing method of the embodiment includes a seed film forming step and a plating step. In such a seed film formation step, a seed film is formed on the substrate. In this plating step, the seed film is immersed in the plating solution in the plating tank supplied with the plating solution bubbled with nitrogen gas, and electrolytic plating is performed using the seed film as a cathode.

  The electrolytic plating apparatus according to the embodiment includes a plating tank, a supply tank, a nitrogen gas supply unit, and a current supply apparatus. An anode member is disposed in the plating tank. In such a supply tank, a plating solution that is bubbled with nitrogen gas is supplied to the plating tank. In the nitrogen gas supply unit, the nitrogen gas is supplied into the supply tank. Such a current supply device passes a current between the anode and the substrate to be plated.

3 is a flowchart illustrating a main part of a method for manufacturing a semiconductor device according to the first embodiment. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is a conceptual diagram which shows an example of a structure of the plating apparatus with which the board | substrate was hold | maintained in the stand-by position in 1st Embodiment. FIG. 3 is a conceptual diagram showing an example of a configuration of a plating apparatus in which a substrate is held at a plating position in the first embodiment. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is a figure which shows the relationship between the number of defects in 1st Embodiment, and an etching rate. It is a conceptual diagram of a cross section of a substrate for explaining the effect of N ₂ bubbling in the first embodiment. 6 is a flowchart illustrating a main part of a method for manufacturing a semiconductor device according to a second embodiment. It is a conceptual diagram which shows an example of a structure of the plating apparatus with which the board | substrate was hold | maintained in the standby position in 2nd Embodiment. It is a conceptual diagram which shows an example of a structure of the plating apparatus with which the board | substrate was hold | maintained in the plating position in 2nd Embodiment. It is a conceptual diagram which shows an example of the bathing method of the board | substrate in 3rd Embodiment.

(First embodiment)
In the first embodiment, a case where Cu damascene wiring is formed in an insulating layer of a low-k film will be described below with reference to the drawings.

FIG. 1 is a flowchart showing the main part of the semiconductor device manufacturing method according to the first embodiment. In FIG. 1, in this embodiment, a low-k film forming step (S102) for forming a low-k thin film made of an insulating material having a low dielectric constant, a cap film forming step (S104) for forming a cap film, As an opening forming step for forming an opening (S106), a conductive material film forming step for forming a conductive material film using a conductive material, a barrier metal film forming step (S108), a seed film forming step (S110). A series of steps of nitrogen (N ₂ ) bubbling and electrolytic plating step (S114) and polishing step (S116) are performed.

  FIG. 2 is a process sectional view showing a process performed corresponding to the flowchart of FIG. FIG. 2 shows the low-k film formation step (S102) to the opening formation step (S106) in FIG. Subsequent steps will be described later.

In FIG. 2A, as a low-k film forming step (S102), a low-k film 220 made of a porous low dielectric constant insulating material is formed on a substrate 200 as an example of a base, for example, 300 nm. The thickness is formed. By forming the low-k film 220, an interlayer insulating film having a relative dielectric constant k of 3.0 or less can be obtained. As a material of the low-k film 220, porous silicon carbonate (SiOC) is preferably used. By using the porous SiOC film, an interlayer insulating film having a relative dielectric constant k of, for example, 2.6 or less can be obtained. As a forming method, for example, it can be formed using PECVD. For example, methyl diethoxy silane (Methyl-di-ethoxy-silane ), alpha-terpinene _{(alpha-terpinene: C 10 H} 16), oxygen _(O 2), into the chamber (not shown) a mixed gas of helium (He) The substrate 200 is heated to, for example, 250 ° C. in a state where the pressure in the chamber is maintained at, for example, 1.3 × 10 ³ Pa (10 Torr) or less, and high-frequency power is applied to a lower electrode and an upper electrode (not shown) in the chamber. Supply and generate plasma. Methyldiethoxysilane is a gas for forming a main skeleton component, and alpha terpinene is a gas for forming a porogen component. Then, the porogen contained in the SiOC film is removed by heating and vaporizing. Then, curing is performed by ultraviolet (UV) irradiation in a nitrogen atmosphere at, for example, 450 ° C., which is higher than the porogen removal temperature. Thereby, the low-k film 220 which becomes a porous insulating film can be formed. The formation method is not limited to the CVD method, and an SOD (spin on dielectric coating) method in which a thin film is formed by spin-coating a solution and performing heat treatment is also suitable. As a material of the low-k film 220, for example, a film having a siloxane skeleton such as polymethylsiloxane mainly composed of methylsiloxane, polysiloxane, hydrogen silsesquioxane, or methyl silsesquioxane is preferably used. is there. Further, it is preferable that a base film (not shown) is formed below the low-k film 220. As the base film, for example, silicon oxide (SiO ₂ ), silicon carbonitride (SiCN), silicon carbide (SiC), or non-porous silicon carbonate (denseSiCO) is preferable. The formation method can be formed by PECVD, but is not limited thereto, and other methods may be used. The base film is formed with a film thickness of 20 nm, for example. As the substrate 200, for example, a silicon wafer having a diameter of 300 mm is used. Here, illustration of a contact plug layer, a device part, etc. is omitted. Then, layers having various semiconductor elements or structures (not shown) such as other metal wirings may be formed on the substrate 200. Alternatively, other layers may be formed.

In FIG. 2B, as a cap film forming step (S104), silicon carbonate (SiOC) is deposited on the low-k film 220 as a cap insulating film by a CVD method, for example, to a film thickness of 50 nm, for example. A thin film is formed. By forming the SiOC film 222, it is possible to protect the low-k film 220 that is difficult to directly perform lithography, and to form a pattern in the low-k film 220. As a material of the cap insulating film, in addition to SiOC, at least one specific dielectric selected from the group consisting of silicon oxide (SiO ₂ ), SiC, silicon carbide (SiCH), silicon carbonitride (SiCN), and SiOCH An insulating material having a rate of 2.5 or more may be used. Here, the film is formed by the CVD method, but other methods may be used.

  In FIG. 2C, as the opening forming step (S106), the opening 150, which is a wiring trench structure for producing a damascene wiring in the lithography process and the dry etching process, is formed in the SiOC film 222 and the low-k film 220. Form. For example, a wiring groove having a width of 5 μm is formed. An exposed SiOC film 222 and a low-k film 220 positioned therebelow are exposed to a substrate 200 on which a resist film is formed on the SiOC film 222 through a lithography process such as a resist coating process and an exposure process (not shown). By removing by an anisotropic etching method, the opening 150 can be formed substantially perpendicular to the surface of the substrate 200. For example, as an example, the opening 150 may be formed by a reactive ion etching method. In addition, when the above-described base film is formed under the low-k film 220, the base film may be removed by anisotropic etching.

FIG. 3 is a process sectional view showing a process performed corresponding to the flowchart of FIG. FIG. 3 shows from the barrier metal film formation step (S108) to the N ₂ bubbling and electroplating step (S114) in FIG. Subsequent steps will be described later.

  In FIG. 3A, as a barrier metal film forming step (S108), a barrier metal film 240 using a barrier metal material is formed on the surface of the opening 150 and the SiOC film 222 formed in the opening forming step. A barrier metal film 240 is formed by depositing a thin film of a tantalum (Ta) film, for example, with a thickness of 30 nm in a sputtering apparatus using a sputtering method which is one of physical vapor deposition (PVD) methods. The deposition method of the barrier metal material is not limited to the PVD method, and an atomic layer deposition (ALD or atomic layer chemical vapor deposition: ALCVD) method, a CVD method, or the like can be used. The coverage can be improved as compared with the case of using the PVD method. As the material of the barrier metal film, in addition to Ta, a tantalum-based tantalum-containing material such as tantalum nitride (TaN), a titanium-based titanium-containing material such as titanium (Ti) or titanium nitride (TiN), tungsten nitride ( WN) and the like, or a laminated film using a combination of Ta and TaN such as Ta and TaN may be used.

  In FIG. 3B, as a seed film formation step (S110), a Cu thin film serving as a cathode electrode in the subsequent electroplating step is formed as a seed film 250 (copper copper) by a physical vapor deposition (PVD) method such as sputtering. As an example of the contained film, the film is deposited (formed) on the inner wall of the opening 150 where the barrier metal film 240 is formed and on the surface of the substrate 200. Here, the seed film 250 is deposited to a thickness of 20 nm on the surface of the substrate 200, for example.

Here, in the first embodiment, in order to prevent the seed film 250 from being dissolved and lost in the plating solution, in the next electrolytic plating step (S114), N ₂ bubbling is performed from the start of plating to at least the start of plating. Electrolytic plating is performed using the plating solution.

In FIG. 3C, as the N ₂ bubbling and electrolytic plating step (S114), the seed film 250 is immersed in a plating solution in a plating tank supplied with a plating solution that is bubbled with nitrogen gas. As a cathode, a Cu film 260 (an example of a copper-containing film) is deposited in the opening 150 and on the surface of the substrate 200 by an electrochemical growth method using electrolytic plating. Here, for example, a Cu film 260 having a thickness of 800 nm is deposited, and after the deposition, annealing is performed at a temperature of 150 ° C. for 30 minutes, for example.

FIG. 4 is a conceptual diagram showing an example of the configuration of the plating apparatus in which the substrate is held at the standby position in the first embodiment. In the electrolytic plating apparatus, an N ₂ tank 620 (nitrogen gas supply unit), a nozzle 632, a supply tank 610, a plating tank 650, an anode electrode 654, a current supply device 612, and a holder 652 are arranged. . Nitrogen (N ₂ ) gas supplied from the N ₂ tank 620 is supplied into the plating solution 670 from the tip of the nozzle 632 extending into the plating solution 670 in the supply tank 610 through the valve 630 and the pipe 631 ( Released). A part of the N ₂ gas is dissolved in the plating solution 670, the remainder is discharged from the top to the atmosphere. Thus, in the supply tank 610, the plating solution 670 is bubbled with the N ₂ gas. Then, the plating solution 670 bubbled with N ₂ gas as described above is supplied to the plating tank 650 by the pump 640. The plating solution 670 is continuously supplied to the plating tank 650 by the pump 640 from before the start of electrolytic plating to the end of plating. The plating solution 670 overflowing from the plating tank 650 is returned to the supply tank 610 through the pipe. Thus, the plating solution 670 circulates through the supply tank 610 and the plating tank 650. As the plating solution 670, a solution containing copper sulfate as a main component and an additive may be used. The plating tank 650 is formed in a substantially cylindrical shape, and contains the plating solution 670 supplied from the supply tank 610 inside. An anode electrode 654 made of an anode member whose upper surface is exposed to the plating solution 670 is disposed at the bottom of the plating solution 670 in the plating tank 650. As the anode electrode 654, for example, a soluble anode such as phosphorous copper may be used. The holder 652 is disposed above the plating tank 650 and detachably holds the substrate 200 with the plating surface facing downward. Then, the current supply device 612 causes a current to flow between the anode electrode 654 and the substrate 200 that is the substrate to be plated.

FIG. 4 shows a state in which the holder 652 holds the substrate 200 at a position raised from the liquid surface of the plating solution 670. For example, the substrate 200 is held at a standby position for transporting the substrate 200 by a robot (not shown). A cathode-side contact is connected to the outer peripheral portion of the surface of the substrate 200 on which the seed layer is formed in a region not touching the plating solution 670. On the other hand, a contact on the anode side is connected to the anode electrode 654. It should be noted that the constituent equipment until the N ₂ gas is supplied to the supply tank 610, for example, the constituent equipment such as the N ₂ tank 620, the valve 630, the pipe 631, and the nozzle 632, is not a part constituting the electrolytic plating apparatus, It may be arranged as a supply facility.

FIG. 5 is a conceptual diagram showing an example of the configuration of the plating apparatus in which the substrate is held at the plating position in the first embodiment. In the first embodiment, when the surface of the substrate 200 is placed in the plating bath 650 containing the plating solution 670, the bath is rotated into the plating solution 670 that is bubbled with N ₂ gas while rotating the substrate 200. As a result, the seed film 250 is immersed in the plating solution 670 in the plating tank 650 supplied with the plating solution 670 bubbled with N ₂ gas. By immersing the seed film 250 in the plating solution 670 bubbled with N ₂ gas, dissolution of the seed film 250 can be suppressed. In order to suppress the dissolution of the seed film 250, the plating solution 670 that has been N ₂ bubbled from before the start of electroplating to at least the start of electroplating is supplied to the plating tank 650. Then, the surface of the substrate 200 is immersed in the plating solution 670 while being rotated, and the anode electrode 654 is anode (anode) from the current supply device 612, and the seed film 250 of the substrate 200 to be the plating surface is the cathode (cathode). Then, the electroplating is performed. Further, when entering the bath, it is more preferable to enter the bath in a state where the substrate is inclined at a predetermined angle so that no air remains between the substrate 200 and the plating solution 670.

  Then, from this state, the extra Cu film 260 and the barrier metal film 240 deposited on the opening 150 are removed by CMP to form a damascene wiring.

  FIG. 6 is a process sectional view showing a process performed corresponding to the flowchart of FIG. FIG. 6 shows the polishing step (S116) of FIG.

  In FIG. 6, as a polishing process, the surface of the substrate 200 is polished by a CMP method, and a Cu film 260 and a barrier metal film 240 including a seed film 250 serving as a wiring layer as a conductive portion deposited on the surface other than the opening. Is removed by polishing and planarized as shown in FIG. As described above, damascene wiring can be formed.

FIG. 7 is a diagram showing the relationship between the number of defects and the etching rate in the first embodiment. In FIG. 7, the etching rate indicates the Cu dissolution rate in the plating solution. The number of defects indicates the number of defects embedded in the wiring after polishing. The etching rate can be reduced by performing N ₂ bubbling. Then, by reducing the etching rate, dissolution of the seed film 250 can be suppressed, and a region where the seed film 250 is lost can be prevented. As a result, it is possible to reduce embedding defects in the wiring.

The reason why the Cu dissolution rate could be reduced by performing N ₂ bubbling is thought to be because Cu dissolution in the plating solution is generated by the following reaction formula.
^{_{Cu + O 2 + 2H + →}} Cu 2+ + H 2 O

Cu reacts with dissolved oxygen and acid in the plating solution and is eluted in the plating solution. By performing N ₂ bubbling, dissolved oxygen in the plating solution is driven out, and the reaction amount of the above reaction formula is reduced. Thereby, it is considered that elution of Cu into the plating solution was reduced.

FIG. 8 is a conceptual diagram of a substrate cross section for explaining the effect of N ₂ bubbling in the first embodiment. As shown in FIG. 8A, when N ₂ bubbling is not performed, a void due to the disappearance of the seed Cu layer that occurs remarkably on the side wall of the opening occurs. On the other hand, as described above, by entering the plating solution 670 in which N _{2 is} bubbling, as shown in FIG. It is possible to prevent plating undeposited due to the disappearance of the seed Cu layer that occurs remarkably on the side walls.

Here, when performing electroplating, the seed film 250 may be immersed in the plating solution 670 while applying a voltage to the seed film 250 while performing N ₂ bubbling. In particular, in the first embodiment, it is more preferable to apply a voltage lower than the voltage at the start of electrolytic plating after immersion in the plating solution 670 to the seed film 250 when immersing in the plating solution 670. Such a configuration can further suppress dissolution of the Cu seed film.

Here, in order to completely prevent the dissolution of the Cu seed film without performing N ₂ bubbling, it is necessary to set the voltage at which Cu plating occurs, but when entering the plating tank 650, Since a certain period of time is required until all the surfaces of the substrate 200 come into contact with the liquid, the plating time differs between the first wetted portion and the last wetted portion. As a result, plating growth occurs on the surface of the substrate 200. The embedded uniformity of the Cu film 260 is deteriorated. Further, if the voltage applied to the substrate 200 is reduced without performing N ₂ bubbling, Cu undeposited or defects are generated on the thin side wall of the Cu seed film. Therefore, in the first embodiment, while N ₂ bubbling is performed, the seed film 250 is immersed in the plating solution 670 at a voltage lower than the voltage at the start of electrolytic plating after being immersed in the plating solution 670. Apply. Thereby, dissolution of the Cu layer can be further suppressed while maintaining the filling uniformity.

(Second Embodiment)
In the second embodiment, in addition to the contents of the first embodiment, the case of further cooling the substrate will be described below with reference to the drawings.

FIG. 9 is a flowchart showing a main part of a method for manufacturing a semiconductor device according to the second embodiment. 9, this embodiment is the same as FIG. 1 except that a cooling step (S112) is added between the seed film formation step (S110) and the N ₂ bubbling and electrolytic plating step (S114). The following is the same as in the first embodiment except for the contents specifically described. Each process up to the seed film forming process (S110) is the same as that of the first embodiment.

  As a cooling step (S112), the seed film 250 is cooled. In the cooling method, the seed film 250 is cooled through the back surface of the substrate 200 by cooling the back surface of the substrate 200 using a gas.

FIG. 10 is a conceptual diagram showing an example of the configuration of the plating apparatus in which the substrate is held at the standby position in the second embodiment. In FIG. 10, the holder 652 is processed so that a space is formed on the back surface side of the substrate 200, and the space serves as a gas (gas) flow path 601. A part of the nitrogen (N ₂ ) gas supplied from the N ₂ tank 620 is supplied to the supply tank 610 through the valve 630 and the pipes 631 and 634, and the remaining part is supplied through the valve 630 and the pipes 631 and 636. , Supplied to the flow path 601 of the holder 652. Then, the substrate temperature is controlled by causing the N ₂ gas to flow to the back surface of the substrate 200 held at the standby position. Since the silicon wafer as the substrate 200 has good heat conduction, the substrate temperature can be made comparable to the gas temperature if such a gas is allowed to flow on the back surface of the substrate 200 for a sufficient time. Other configurations are the same as those in FIG. Thus, the seed film 250 is cooled by cooling the back surface of the substrate 200 using N ₂ gas supplied from the N ₂ tank 620 that is the same supply source as the N ₂ gas used for bubbling.

  Here, the substrate temperature is desirably cooled by 10 ° C. or more than the temperature of the plating solution 670. For example, when the temperature of the plating solution 670 is 25 ° C., the substrate temperature may be controlled in a range from a temperature at which the substrate 200 does not condense (for example, 5 ° C.) to 15 ° C. When the dissolution rate of the seed film 250 in the plating solution 670 at 25 ° C. is 100%, the dissolution rate of the seed film 250 in the plating solution 670 is reduced to about 56% by setting the substrate temperature to 15 ° C. Can be suppressed. If the substrate temperature is set to 5 ° C., the dissolution rate of the seed film 250 in the plating solution 670 can be suppressed to about 30%. That is, by setting the substrate temperature to 15 ° C. or lower, the dissolution rate can be slowed to nearly half. The cooling position is preferably as close to the plating solution 670 as possible. By setting the position as close to the plating solution 670 as possible, the time until the substrate 200 comes into contact with the plating solution 670 after cooling can be shortened, and the cooling effect can be maintained.

In FIG. 3 (c), _N as ₂ bubbling and electrolytic plating process (S114), the plating solution in the plating solution 670 plating bath 650 is supplied, which is bubbled with _{N 2} gas, it was cooled in _{N 2} gas The seed film 250 is immersed, and electroplating is performed using the seed film 250 as a cathode.

FIG. 11 is a conceptual diagram illustrating an example of a configuration of a plating apparatus in which a substrate is held at a plating position in the second embodiment. In the second embodiment, when the surface of the substrate 200 is placed in the plating tank 650 containing the plating solution 670 in which N _{2 is} bubbled, the substrate 200 on which the seed film 250 is cooled in the cooling step described above is rotated. While entering the tank. Then, the surface of the substrate 200 is immersed in the plating solution 670 while being rotated, and the anode electrode 654 is anode (anode) from the current supply device 612, and the seed film 250 of the substrate 200 to be the plating surface is the cathode (cathode). Then, the electroplating is performed. In addition, as described above, it is preferable that the substrate is placed in a state where the substrate is inclined at a predetermined angle so that air does not remain between the substrate 200 and the plating solution 670 when entering.

Here, when performing electroplating, the cooled seed film 250 may be immersed in the plating solution 670 while applying a voltage to the seed film 250 while performing N ₂ bubbling. At this time, as described above, it is more preferable to apply a voltage lower than the voltage at the start of electrolytic plating after being immersed in the plating solution 670 to the seed film 250 when the voltage is immersed in the plating solution 670.

As described above, when the surface of the substrate 200 is placed in the plating tank 650, the dissolution of the seed film 250 can be further suppressed by cooling the substrate in addition to N ₂ bubbling with respect to the plating solution 670.

(Third embodiment)
In the second embodiment, before entering the plating tank 650 into the plating tank 650, for example, cooling is performed at the standby position shown in FIG. 10 and cooling is stopped at the time of entering the tank, but this is not restrictive.

FIG. 12 is a conceptual diagram illustrating an example of a substrate tank entry method according to the third embodiment. As shown in FIG. 12 (a), before the substrate 200 is placed in the plating tank 650, flowing the N ₂ gas supplied from the N ₂ tank 620 against the back surface of the substrate 200 is the second implementation. It is the same as the form. In the third embodiment, as shown in FIG. 12B, the substrate 200 is placed in the plating tank 650 while cooling. By comprising in this way, a cooling effect can be maintained more. Further, the substrate 200 may be continuously cooled during actual plating.

The embodiment has been described above with reference to specific examples. However, the present invention is not limited to these specific examples. In the above-described embodiment, the low-k film 220 is used as the insulating film. However, the present invention is not limited to this, and other insulating materials may be used. For example, a silicon oxide film (SiO ₂ ) may be used. Further, the back surface of the substrate 200 may not be directly cooled, but indirectly cooled. In the embodiment, the damascene wiring is described. However, the dual damascene wiring can exhibit the same effect. In particular, it is suitable for filling Cu into a via hole in forming a dual damascene wiring. In the above-described example, the N ₂ gas supplied from the N ₂ tank 620 is branched to the holder 652 side and the plating solution supply tank 610 side, but this is not restrictive. For example, N ₂ bubbling may be performed by supplying N ₂ gas supplied to the holder 652 side and exhausted from the holder 652 to the supply tank 610 side.

  In addition, the film thickness of the interlayer insulating film and the size, shape, number, and the like of the opening can be appropriately selected from those required for the semiconductor integrated circuit and various semiconductor elements.

  In addition, a method of manufacturing an electronic component represented by all methods of manufacturing a semiconductor device that includes elements of the present invention and whose design can be appropriately changed by those skilled in the art is included in the scope of the present invention.

  Further, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as a photolithography process, cleaning before and after processing, are omitted, but it goes without saying that these techniques may be included.

150 Opening 200 Substrate 220 Low-k film 250 Seed film 260 Cu film 610 Supply tank 612 Current supply device 620 N ₂ tank 650 Plating tank 654 Anode electrode 670 Plating solution

Claims (5)

A seed film forming step of forming a seed film on the substrate;
A plating step of immersing the seed film in the plating solution in a plating tank supplied with a plating solution bubbled with nitrogen gas, and performing electrolytic plating using the seed film as a cathode;
A method for manufacturing an electronic component, comprising:   The method of manufacturing an electronic component according to claim 1, wherein the seed film is cooled by cooling the back surface of the substrate using nitrogen gas supplied from the same supply source as the nitrogen gas used for the bubbling.   3. The method of manufacturing an electronic component according to claim 1, wherein when performing the electrolytic plating, the seed film is immersed in a plating solution while a voltage is applied to the seed film.   The electronic component according to any one of claims 1 to 3, wherein a voltage lower than a voltage at the time of starting electrolytic plating after being immersed in the plating solution is applied to the seed film when immersed in the plating solution. Manufacturing method. A plating tank in which an anode member is disposed;
A supply tank for supplying a plating solution bubbling with nitrogen gas to the plating tank;
A nitrogen gas supply unit for supplying the nitrogen gas into the supply tank;
A current supply device for passing a current between the anode member and the substrate to be plated;
An electrolytic plating apparatus comprising:

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