JP2011120115A - Image processing apparatus and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that, in the case of the division of boundaries of tiles into tiles while overlapping them, a bandwidth of a memory may cause a problem and required performance cannot be obtained. <P>SOLUTION: An image processing apparatus has a buffer 504 having such a storage capacity as to store pixel data for at least one of a plurality of tiles obtained by dividing image data and the prescribed number of pixels around the relevant tile, and pixel data of tiles adjacent vertically and horizontally are stored in the buffer 504 while overlapping the tiles by shifting addresses by an amount of at least the prescribed number of pixels (S607). Each time pixel data of overlapped tiles are stored in the buffer 504, in accordance with an order of arraying a plurality of tiles, pixel data of the tiles and pixel data for the prescribed number of pixels are read from the buffer 504 and image processing is performed to the read-out pixel data. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus that processes image data and a control method thereof.

  When the image data is printed, image processing is performed on the image data. In such image processing, for example, peripheral pixels are referred to like filter processing. In such processing, a line buffer for holding image data of the previous line in addition to data of the current line is provided. Necessary. When the print resolution is 600 dpi and 1200 dpi, the size of the line buffer for storing the necessary image data increases. Therefore, a method of dividing one page of image data into tile units and processing has been proposed. In such tile division, in order to deal with image processing that refers to surrounding pixels, image data is overlapped and divided at tile boundary portions instead of simply being divided into tile units. And the method of removing the overlap part after image processing is completed is proposed (refer patent document 1).

JP-A-2005-198121

  In this way, when the tile boundary is overlapped and divided into tiles, for example, uncompressed raster data is developed in a memory, and overlapping tiles can be created while reading the raster data. . In this case, however, the bandwidth of the memory becomes a problem and the required performance cannot be obtained. On the other hand, when the compressed data is expanded in the memory, there is a problem in what unit the raster data is compressed and which compressed data is read to create the overlap tile.

  An object of the present invention is to solve the above-mentioned problems of the prior art.

  A feature of the present invention is to provide a technique capable of creating an overlap tile without considering the memory bandwidth.

In order to achieve the above object, an image processing apparatus according to an aspect of the present invention has the following arrangement. That is,
Means for dividing the image data into a plurality of tiles;
Storage means having a storage capacity capable of storing pixel data for at least one tile and a predetermined number of pixels around the tile;
Address generating means for generating an address for storing the pixel data of the tile adjacent to the left or right in the upward or downward direction at least by the predetermined number of pixels while shifting the address to overlap the storage means; ,
Each time pixel data of the overlapped tile is stored in the storage unit, the pixel data of the tile and the pixel data for the predetermined number of pixels are stored from the storage unit according to the arrangement order of the plurality of tiles. Reading means for reading; and
And image processing means for executing image processing on the pixel data read by the reading means.

  According to the present invention, overlapping tiles can be created without considering the memory bandwidth. In addition, there is an effect that a line buffer for creating an overlap tile becomes unnecessary.

1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. FIG. 5 is a view for explaining image data drawn by RIP according to the embodiment. The figure explaining a mode that the packet which the packet preparation part produced is preserve | saved at the main memory. The figure which shows the order from which a packet transmission part reads a packet (A), The flowchart which shows the process in which a packet transmission part reads a packet (B). The block diagram which shows the structure of the packet receiver which concerns on this embodiment. The flowchart explaining operation | movement of the packet receiving part which concerns on this embodiment. The figure explaining the process which writes the MCU which the JPEG decoder decoded into the MCU buffer. The flowchart explaining the process in which raster DMAC produces an overlap tile. It is a figure explaining the example of a filter process, (A) is a figure which shows an example of a 7 * 7 filter process, (B) is a flowchart explaining a filter process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the present invention. .

  FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention.

  The PC 101 transmits page description language (PDL) data to the image processing apparatus 100 according to the present embodiment via the network 102. In the image processing apparatus 100, a network controller (NIC) 110 controlled by the CPU 114 receives the PDL data and stores it in the main memory 111 via the bus switch 113. When the storage of the PDL data ends, the CPU 114 converts the PDL data into a display list (DL). Thereafter, a RIP (Raster Image Processor) 115 reads DL from the main memory 111 and draws it in image data in units of pixels.

  2A and 2B are diagrams for explaining image data drawn by the RIP 115 according to the present embodiment.

  As shown in FIG. 2A, one page of image data 201 is drawn in units of divided tiles 202. For example, drawing is performed in the order of tile (0, 0), tile (1, 0),..., Tile (x, y). The RIP 115 outputs the drawn tile to the packet creation unit 116. In the present embodiment, an overlap tile is created in which the tile size is 32 × 32 (pixels) and 8 pixels are added around the tile.

  The packet creation unit 116 JPEG compresses the tile received via the bus switch 113. In this JPEG compression, compression is performed in units of 8 × 8 (pixel) image data called a minimum encoding unit (MCU) 203.

  As shown in FIG. 2A, the tile 202 is divided into (4 × 4 = 16) MCUs and JPEG compressed. As shown in FIG. 2B, the packet 205 created by the packet creation unit 116 includes a packet header 207 and packet data 206. The packet header 207 stores packet information, and the packet data 206 stores JPEG compressed data.

  FIG. 3 is a diagram for explaining how a packet created by the packet creation unit 116 is stored in the main memory 111.

  The packet table 301 has elements for the number of packets constituting the page, and each element indicates where each packet is on the main memory 111. Each tile has a unique ID (identifier) consisting of (x, y) coordinates in the page as shown in FIG. 2A, and each tile has the same ID as the corresponding tile storing the packet. The packet table 301 is used when reading a packet including an arbitrary tile in the page.

  When the packet creation unit 116 finishes creating a packet for one page in this way, the packet transmission unit 112 next reads the packet with reference to the packet table 301 and transmits the packet to the packet reception unit 120.

  FIG. 4A shows the order in which the packet transmission unit 112 reads packets. FIG. 4B is a flowchart illustrating processing in which the packet transmission unit 112 reads a packet.

  Here, the operation of the packet transmission unit 112 will be described with reference to the flowchart of FIG. The following steps are all processing of the packet transmission unit 112.

  In S402, variables x and y specifying the ID of the packet to be read are both initialized to “0” (upper left packet). In step S <b> 403, the packet (x, y) is read from the main memory 111 and transmitted to the packet receiving unit 120. In S404, the packet (x, y + 1) (the packet below the packet transmitted in S403) is read from the main memory 111 and transmitted to the packet receiving unit 120. In step S405, it is determined whether or not the value of x is the maximum value (x_max) (whether it is a rightmost packet). If it is not the rightmost packet, the process proceeds to S406, x is incremented (+1), and the process returns to S403. If it is determined in S405 that the packet is the rightmost packet, the process proceeds to S407, and it is determined whether the value of y is the maximum value (y_max) -1 or not (the packet of the lowermost value-1). If it is not the lower end packet, the process proceeds to S408, x is initialized to 0, y is incremented, and the process returns to S403. In S407, if the packet is at the lower end -1, this processing ends.

  FIG. 5 is a block diagram illustrating a configuration of the packet receiving unit 120 according to the present embodiment.

  The DMAC 501 receives the packet, extracts the JPEG code from the packet, and writes it in the code buffer 502. Thereafter, the JPEG decoder (decompressor) 503 reads the JPEG code from the code buffer 502, decodes it in MCU units, and writes the resulting image data to the MCU buffer 504. Here, the MCU buffer 504 is shown in the case of storing pixel data (48 × 48 pixels) for 6 × 6 MCUs. When the data necessary for creating the overlap tile is prepared in the MCU buffer 504, the raster DMAC 505 reads the image data from the MCU buffer 504 and creates the overlap tile.

  FIG. 6 is a flowchart for explaining the operation of the packet receiving unit 120 according to the present embodiment.

  In step S602, variables x, y, and offset for controlling the operation are initialized to x = 0, y = 0, and offset = 2. Next, when the two packets transmitted in S403 and S404 in FIG. 4 are received in S603 and S604, it is determined whether or not x = 0 (leftmost tile) in S605. If it is the leftmost tile, an overlap tile cannot be created yet, so the process proceeds to S606, x is incremented, and the process returns to S603. If it is not the leftmost tile in S605, the process proceeds to S607 to create an overlap tile. In step S608, it is determined whether x is the maximum value (x_max) (whether it is the rightmost tile). If it is not the rightmost tile, the process proceeds to S609, x is incremented, offset = offset + 4 is set, and the process returns to S603. Here, the variable offset is a variable for controlling where the MCU decoded by the JPEG decoder 503 is written in the MCU buffer 504. The variable offset changes as 0 → 1 → 2 → 3 → 4 → 5 → 0 → 1,. For example, when the offset value is “2”, if it is +4, it becomes “0” (module 6 is calculated). The operation of the MCU buffer 504 will be described in detail later. If it is determined in step S608 that the tile is the rightmost tile, the process advances to step S610, and it is determined whether y is the maximum value (y_max) -1 (the tile of (lower end-1)). If it is not the tile of (lower end-1), the process proceeds to S611, y is incremented, x = 0, offset = offset + 2, and the process returns to S603. On the other hand, if it is determined in step S610 that the tile is (lower end-1), this process ends.

  FIG. 7 is a diagram for explaining processing for writing the MCU decoded by the JPEG decoder 503 into the MCU buffer 504.

  The writing location in the MCU buffer 504 differs depending on whether the variable x, offset calculated in the flowchart of FIG. 6 is the tile of the packet received in S603 or the tile of the packet received in S604. FIG. 7A shows a case where a tile having a variable x “0” (leftmost tile) is received in S603, and FIG. 7B shows a case where the variable x is received in S604. FIG. 7C shows a case where a tile whose variable x is not “0” is received in S603, and FIG. 7D shows a case where a tile is received in S604. The MCU numbers shown in FIG. 7 correspond to the MCU numbers shown in FIG.

  Next, referring to FIGS. 7E, 7F, 7G, 7H, the first 10 tiles (tiles (0, 0) to (4, 0), (0, 1) to (4, 4)) are displayed. The operation will be described by taking an example of processing when the tile 1)) is received.

  The first tile (0, 0) corresponds to the case of FIG. 7A, and as shown in FIG. 7E, the right half of the tile (MCU 2, 3, 6, 7, 10 of FIG. 2A). , 11, 14, 15) are written in the rectangular area 700 of (0, 0) to (1, 3) of the MCU buffer 504. The second tile (0, 1) corresponds to the case of FIG. 7B, and as shown in FIG. 7E, the upper right 16 × 16 pixels (MCUs 2, 3, 6, 7 in FIG. 2A). ) Only in the rectangular area 701 of (0, 4) to (1, 5) of the MCU buffer 504. Next, the third tile (1, 0) corresponds to the case of FIG. 7C, and all the tiles of (2, 0) to (5, 3) of the MCU buffer 504 as shown in FIG. Write to the rectangular area 703. The fourth tile (1, 1) with offset = 2 corresponds to the case of FIG. 7D, and the upper half of the tile is moved to (2, 4) to (2) of the MCU buffer 504 as shown in FIG. Write to the rectangular area 704 of (5, 5). Create the first overlap tile at this stage. A method of creating an overlap tile by reading data from the MCU buffer 504 will be described in the operation of the raster DMAC 505 described later.

  The fifth tile (2, 0) corresponds to the case of FIG. 7C, and all the tiles are rectangles (0, 0) to (3, 3) of the MCU buffer 504 as shown in FIG. 7F. Write to area 705 (offset = 0). The sixth tile (2, 1) corresponds to the case of FIG. 7D, and the upper half of the tile is placed in the MCU buffer 504 at (0, 4) to (3, 5) as shown in FIG. Is written in the rectangular area 706 (offset = 0). As a result, the left half rectangular area corresponding to the rectangular areas 705 and 706 of the previous two tile data is overwritten with these tiles (2, 0) and tiles (2, 1) and disappears. However, the data of FIG. 7E remains in (4, 0) to (5, 5) corresponding to the rectangular regions 707 and 708 in the right half. At this stage, a second overlap tile is created.

  The seventh tile (3, 0) corresponds to the case of FIG. 7C. As shown in FIG. 7G, the left half of the tile is the rectangular area (4, 0) to (5, 3). In the rectangular area 709, the right half is written into the rectangular area 710 of the rectangular areas (0, 0) to (1, 3) (offset = 4). The eighth tile (3, 1) corresponds to the case of FIG. 7D, and the upper left half of the tile is a rectangle of regions (4, 4) to (5, 5) as shown in FIG. 7G. In the area 711, the upper right half is written into the rectangular areas 712 of the rectangular areas (0, 4) to (1, 5) (offset = 4). As a result, the data of the tiles (3, 0) and (3, 1) are written in the rectangular areas 709 to 712. In the areas indicated by Tile (2, 0) and Tile (2, 1), the data shown in FIG. The data remains intact. At this stage, a third overlap tile is created.

  The ninth tile (4, 0) corresponds to the case of FIG. 7C, and all the tiles are rectangles (2, 0) to (5, 3) of the MCU buffer 504 as shown in FIG. Write to area 713 (offset = 2). The tenth tile (4, 1) corresponds to the case of FIG. 7D, and the upper half of the tile is placed in the MCU buffer 504 at (2, 4) to (5, 5) as shown in FIG. ) In the rectangular area 714 (offset = 2). Again, in the areas indicated by Tile (3, 0) and Tile (3, 1), the data of the rectangular areas 710 and 712 in FIG. At this stage, a fourth overlap tile is created.

  Here, the shape of FIG. 7 (H) is the same as the shape of FIG. 7 (E), and the MCU buffer 504 is used by repeating FIG. 7 (E) to (H) in S603 to S608, and in S610 the initial state. Returning to FIG.

  FIG. 8 is a flowchart for explaining processing in which the raster DMAC 505 reads data from the MCU buffer 504 and creates an overlap tile in step S607 of FIG. Variables a and b are variables for designating the MCU buffer 504 from which data is read, and variables i and j are variables for designating pixels to be read from the MCU buffer 504 (a, b). The raster DMAC 505 reads one pixel designated by the variables a, b, i, and j in step S806. It is determined whether the variables i, j, a, and b have reached predetermined values in S807, S809, S811, and S813, respectively. If not, the variables i, j, a, and b are incremented in S808, S810, S812, and S814, respectively. In each of these steps (S), if a predetermined value is reached, the process proceeds to the next step. Variables a, b, i, j are incremented in multiple loops in the order of a, j, b. The increment of the variable i is for reading the 8th pixel in the jth line of the MCU buffer 504 (a, b). The increment of the variable a is for moving the MCU buffer 504 to be read to the right every time 8 pixels are read.

  The change of the variable a will be described with reference to FIGS. 7E, 7F, 7G, and 7H, taking as an example processing for creating the first four overlap tiles. When the first overlap tile is created in S607 of FIG. 6 (the MCU buffer 504 is in the state of FIG. 7E), the variable a changes to 0, 1, 2, 3, 4, and 5. When creating the second overlap (MCU buffer 504 is in the state shown in FIG. 7F), variable a changes to 4, 5, 0, 1, 2, and 3. When the third overlap is created (MCU buffer 504 is in the state shown in FIG. 7G), the variable a changes to 2, 3, 4, 5, 0, 1. When the fourth overlap is created (MCU buffer 504 is in the state of FIG. 7H), variable a is 0, 1, 2, 3, 4 as in the case of creating the first overlap. , 5 will change. The first and last values of this variable a are controlled by start_muc_x and last_mcu_x updated in S816. The increments of the variables j and b are for reading out one line of the overlap tile of 48 pixels in total, each of 8 pixels from the 6 MCU buffers 504, and then shifting to reading of the next line. The variables start_mcu and last_mcu are variables for controlling the transition of the variable a, and are initialized every time an overlap tile is created in S816 after being initialized in S802. As a result of the processing of S802 to S816 in FIG. 8, the pixel data stored in the MCU buffer 504 as an overlap tile in which 8 pixels are added to the periphery of each tile as shown in FIGS. Read out.

  In this way, each pixel of the overlap tile created by the packet reception unit 120 is sent to the color conversion unit 121, converted into CMYK, and sent to the filter processing unit 122. The filter processing unit 122 performs a process of fattening the object in order to prevent white spots from occurring due to displacement of the C, M, Y, and K plates. The process is realized by a filter process.

  FIG. 9A is a diagram illustrating an example of 7 × 7 filter processing. In FIG. 9A, d (*, *) indicates one pixel, the target pixel 900 is d (0,0), and its peripheral pixels are reference pixels. In the filter processing, a result obtained by adding the values obtained by multiplying each pixel d (*, *) by the coefficient c (*, *) is output. FIG. 9B is a flowchart for explaining the filter processing.

  In S902 and S903, the variables i and j are both initialized to "-3". In step S904, the result obtained by multiplying the pixel d (i, j) by the coefficient c (i, j) is added to out_data as the final output. In S905 and S907, it is determined whether or not the variables i and j have reached a predetermined value (“3”). If the variables i and j have not reached the predetermined value, the process increments in S906 and S908. The filter processing unit 122 performs 7 × 7 filter processing that refers to these peripheral pixels. The filter processing unit 122 transmits the processed pixel to the gradation processing unit 123.

  The gradation processing unit 123 converts the pixel received from the filter processing unit 122 into halftone data and transmits the halftone data to the smoothing processing unit 124. The smoothing processing unit 124 performs processing for smoothing edge portions such as characters. This process is also realized by the filter process similar to the process of the filter processing unit 122. In the filter process, various processes can be performed by adjusting the coefficient. The smoothing processing unit 124 transmits the processed pixels to the output unit 125. The output unit 125 discards the overlapping portion of the pixels received from the smoothing processing unit 124 and stores only the other portion in the spool memory 126. When the output unit 125 receives all the tiles constituting the page, the output unit 125 reads out the pixels from the spool memory 126 in the page raster order and transmits them to the printer unit 130. Then, the printer unit 130 prints on the paper.

  As described above, according to the present embodiment, one page of image data is divided into a plurality of tiles, each tile is divided into a plurality of MCUs, encoded, and stored in a memory. The JPEG decoder decodes the JPEG code in MCU units, and stores the resulting image data in the MCU buffer. Here, the MCU buffer has a storage capacity capable of storing pixel data for at least one tile and a predetermined number of pixels around it. Then, every time pixel data of a tile that overlaps at least in the upward or downward direction and left or right is stored, the pixel data stored in the MCU buffer is read out and an image is referenced with reference to surrounding pixels. The data is output to the image processing unit that performs processing. Further, when storing tile pixel data in this MCU buffer, a write address is generated by shifting the write address (position) of each tile data by the predetermined number of pixels (address generation). As a result, the pixel data of the next tile is written in a state where a part of the pixel data of the tile previously stored in the MCU buffer (the subsequent tile side) remains. Then, the pixel data of the tile currently stored in the MCU buffer can be read out in the order of the original tile arrangement in a state including the peripheral pixels of the previously stored tile pixel data. Accordingly, there is an effect that overlap tiles can be created without considering the memory bandwidth. In addition, there is an effect that a line buffer for creating an overlap tile becomes unnecessary.

(Other examples)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

Claims (8)

Means for dividing the image data into a plurality of tiles;
Storage means having a storage capacity capable of storing pixel data for at least one tile and a predetermined number of pixels around the tile;
Address generating means for generating an address for storing the pixel data of the tile adjacent to the left or right in the upward or downward direction at least by the predetermined number of pixels while shifting the address to overlap the storage means; ,
Each time pixel data of the overlapped tile is stored in the storage unit, the pixel data of the tile and the pixel data for the predetermined number of pixels are stored from the storage unit according to the arrangement order of the plurality of tiles. Reading means for reading; and
Image processing means for performing image processing on the pixel data read by the reading means;
An image processing apparatus comprising:   The address generation means stores the pixel data of the subsequent tile in the storage means so that the pixel data located on the subsequent tile side among the pixel data of the tile stored previously is left in the storage means. The image processing apparatus according to claim 1, wherein the address is generated.   The image processing apparatus according to claim 1, wherein the image processing unit executes image processing that refers to a target pixel and peripheral pixels of the target pixel. Compression means for compressing image data in units of tiles;
A memory for storing the image data compressed by the compression means;
4. The image processing apparatus according to claim 1, further comprising an expansion unit configured to expand the compressed image data stored in the memory in units of tiles. 5. A control method for an image processing apparatus, comprising:
Dividing the image data into a plurality of tiles;
In a memory having a storage capacity capable of storing at least one pixel data of the tile and a predetermined number of pixels around the tile, the pixel data of the tile adjacent to the upper or lower direction and the left or right is at least the predetermined An address generation step for generating addresses for storing by shifting and overlapping addresses by the number of pixels;
Each time pixel data of the overlapped tile is stored in the memory, reading out the pixel data of the tile and the pixel data of the predetermined number of pixels from the memory according to the arrangement order of the plurality of tiles Process,
An image processing step of performing image processing on the pixel data read in the reading step;
A control method for an image processing apparatus, comprising:   The address generating step is an address for storing the pixel data of the subsequent tile in the memory so that the pixel data located on the subsequent tile side among the pixel data of the tile stored previously is left in the memory. The method of controlling an image processing apparatus according to claim 5, wherein:   The method of controlling an image processing apparatus according to claim 5, wherein the image processing step executes image processing that refers to a target pixel and peripheral pixels of the target pixel. A compression step of compressing image data in units of tiles;
Storing the image data compressed in the compression step in a memory;
8. The method of controlling an image processing apparatus according to claim 5, further comprising a decompressing step of decompressing the compressed image data stored in the memory in units of the tiles. .

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