JP2011081695A - Control circuit of data operation unit and data operation unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate processing by achieving the parallel execution of a single operation and a data path operation. <P>SOLUTION: The control circuit includes a main control part 12 for outputting a data transfer command, also executing the single operation and outputting the operation result and a data path operation indication, and a data transfer control part 13 for making data stored in an external storage device 2 be transferred to a data path circuit 4 by controlling a DMA controller 3 according to the data transfer command. When data transfer by the DMA controller 3 is completed, a data path control part 15 supplies the operation result of the single operation and a data path operation instruction which is the execution command of operation contents indicated by the data path operation indication to the data path circuit 4, and the data path operation is executed by the data path circuit 4. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a data arithmetic device that performs high-speed data arithmetic and a control circuit that controls data path arithmetic and the like in the data arithmetic device.

For example, some data arithmetic devices that process a plurality of data at high speed, such as video signal processing, have a data path circuit that performs data path arithmetic.
At this time, in order to realize high-speed data processing, for example, a data path circuit is configured using a general-purpose accelerator such as a SIMD (Single Instruction Multiple Data) arithmetic unit.
Such a general-purpose accelerator is controlled by a processor. However, a processor as a conventional control means executes a program in a built-in instruction memory, thereby performing input / output control for an external memory and arithmetic for an arithmetic unit. The contents are instructed (see, for example, Patent Document 1).

FIG. 4 is an explanatory diagram showing an example of data path control timing by a processor mounted on a conventional data arithmetic apparatus.
However, in addition to the processor, the data arithmetic unit includes a data path circuit that performs data path arithmetic and a DMA (Direct Memory Access) controller that transfers data to a storage device in the data path circuit under the instruction of the processor. And are implemented.
Note that the processor executes not only data path circuit arithmetic control and data transfer control but also single control operations such as data transfer address arithmetic and conditional branching.

First, the processor performs an address calculation or the like necessary for DMA transfer as preprocessing for transferring data to the storage device in the data path circuit (indicated as “DMA transfer 0 preprocessing” in FIG. 4). (For example, a transfer source address, a transfer destination address, a transfer data size, etc. are calculated).
When the processor performs an address calculation or the like necessary for the DMA transfer, it sets the result of the address calculation or the like in the DMA controller (indicated as “DMA transfer 0 setting” in FIG. 4), and instructs the DMA controller to perform the DMA transfer. To do.

When receiving a DMA transfer instruction from the processor, the DMA controller executes data transfer corresponding to “DMA transfer 0 setting” (indicated as “DMA transfer 0” in FIG. 4) in parallel with the processing of the processor.
When the data transfer is completed, the DMA controller outputs a DMA transfer completion notification to the processor.

While the DMA controller is executing “DMA transfer 0”, the processor performs preprocessing necessary for the next data transfer (indicated as “DMA transfer 1 preprocessing” in FIG. 4) and the next data path operation ( In FIG. 4, a single operation (denoted as “single operation 0” in FIG. 4) for calculating parameters and the like necessary for “data path operation 0” is executed.
After that, the processor waits until a DMA transfer completion notification is output from the DMA controller. When the DMA transfer completion notification is received from the DMA controller, the processor sets the result of address calculation or the like in “DMA transfer 1 preprocessing” to the DMA controller. (Indicated as “DMA transfer 1 setting” in FIG. 4), the DMA controller is instructed to perform DMA transfer.
Further, the processor outputs the calculation result of the parameter or the like in “single operation 0” to the data path circuit, and instructs the data path circuit to execute “data path operation 0”.

When the data path circuit receives an instruction to execute “data path operation 0” from the processor, the data path circuit reads the data DMA-transferred to the storage device by the DMA controller (data transferred by “DMA transfer 0”) and outputs it from the processor The “data path calculation 0” is executed using the calculated result of the parameter or the like in the “single calculation 0” and the data transferred by the “DMA transfer 0”.
When receiving a DMA transfer instruction from the processor, the DMA controller executes data transfer corresponding to “DMA transfer 1 setting” (indicated as “DMA transfer 1” in FIG. 4) in parallel with the data path calculation of the data path circuit. To do.
When the data transfer is completed, the DMA controller outputs a DMA transfer completion notification to the processor.

When the “data path calculation 0” by the data path circuit is completed, the processor executes post-processing (“data path calculation 0 post-processing” in FIG. 4) using the calculation result of “data path calculation 0”. When the “data path calculation 0 post-processing” is completed, the pre-processing necessary for the next data transfer (indicated as “DMA transfer 2 pre-processing” in FIG. 4) and the next data path calculation (in FIG. A single operation (denoted as “single operation 1” in FIG. 4) for calculating a parameter or the like necessary for the operation 1 ”is executed.
When the processor executes “DMA transfer 2 preprocessing” and “single operation 1”, the processor sets the result of the address operation or the like in “DMA transfer 2 preprocessing” in the DMA controller (“DMA transfer 2 in FIG. 4). Instructs DMA transfer to the DMA controller.
Further, the processor outputs the calculation result of the parameter or the like in “single operation 1” to the data path circuit, and instructs the data path circuit to execute “data path operation 1”.

When the data path circuit receives an instruction to execute “data path calculation 1” from the processor, the data path circuit reads the data DMA-transferred to the storage device by the DMA controller (data transferred by “DMA transfer 1”) and outputs it from the processor The “data path calculation 1” is executed using the calculated result of the parameter or the like in the “single calculation 1” and the data transferred by the “DMA transfer 1”.
When receiving a DMA transfer instruction from the processor, the DMA controller executes data transfer corresponding to “DMA transfer 2 setting” (indicated as “DMA transfer 2” in FIG. 4) in parallel with the data path calculation of the data path circuit. To do.
When the data transfer is completed, the DMA controller outputs a DMA transfer completion notification to the processor.

When the “data path calculation 1” by the data path circuit is completed, the processor performs post-processing (“data path calculation 1 post-processing” in FIG. 4) using the calculation result of “data path calculation 1”. Completion of “data path calculation 1 post-processing” calculates pre-processing necessary for the next data transfer (indicated as “DMA transfer 3 pre-processing” in FIG. 4) and parameters required for the next data path calculation. A single operation (indicated as “single operation 2” in FIG. 4) is executed.
Thereafter, since the same processing is repeated, description thereof is omitted.

JP 2009-15556 A

  Since the conventional data operation circuit is configured as described above, a single operation by the processor and a data path operation by the data path circuit can be executed in parallel even if a data path circuit is mounted in addition to the processor. There is a problem that it is impossible to increase the processing speed.

  The present invention has been made to solve the above-described problems, and realizes a control circuit and data for a data arithmetic apparatus capable of realizing a parallel execution of a single arithmetic operation and a data path arithmetic operation to increase the processing speed. An object is to obtain an arithmetic unit.

  The control circuit of the data operation device according to the present invention outputs a data transfer command used for data path operation, executes a predetermined single operation, and the operation result of the single operation and the operation content of the data path operation The data used for the data path calculation stored in the storage device is controlled by controlling the DMA controller in accordance with the data transfer instruction output from the main control section that outputs a data path calculation instruction indicating A data transfer control unit to be transferred to the path circuit, and when the data transfer by the DMA controller is completed, the data path control unit displays the calculation result of the single calculation output from the main control unit and the data path calculation instruction A data path operation instruction, which is an execution command of the single operation, is given to the data path circuit, and the operation result of the single operation and the DMA controller are Chromatography is obtained so as to perform data path calculation to the data path circuit according to the data path operation instruction using the transferred data by la.

  According to the present invention, a data path calculation instruction for outputting a data transfer command used for data path calculation, executing a predetermined single calculation, and indicating the calculation result of the single calculation and the calculation contents of the data path calculation The main control unit for outputting the data and the data for transferring the data used for the data path calculation stored in the storage device to the data path circuit by controlling the DMA controller according to the data transfer command output from the main control unit When the data transfer by the DMA controller is completed, the data path control unit is a data that is an instruction to execute the calculation contents indicated by the calculation result of the single calculation and the data path calculation instruction output from the main control unit. A path operation instruction is given to the data path circuit, and the operation result of the single operation is transferred to the data transferred by the DMA controller. Since the data path operation related to the data path operation instruction using the data is executed by the data path circuit, the main control unit performs the next single operation in parallel when the data path circuit is executing the data path operation. As a result, the processing speed can be increased.

It is a block diagram which shows the data arithmetic device by Embodiment 1 of this invention. It is explanatory drawing which shows the example of control timing of the data arithmetic unit by Embodiment 1 of this invention. It is a block diagram which shows the data arithmetic device by Embodiment 2 of this invention. It is explanatory drawing which shows the example of a control timing of the data path by the processor mounted in the conventional data arithmetic unit.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a data operation apparatus according to Embodiment 1 of the present invention.
In FIG. 1, the control circuit 1 executes a predetermined single operation (for example, calculation of parameters and the like by performing addition, subtraction, logical sum, etc.) necessary for data path calculation, and also performs data transfer in the DMA controller 3. This is a circuit for performing control and control of data path calculation in the data path circuit 4.
The external storage device 2 is, for example, a storage medium such as a memory or a hard disk that stores data used when the data path circuit 4 performs a data path calculation.

  The DMA controller 3 converts the data stored in the external storage device 2 (or the internal storage device 16 of the control circuit 1) into data according to the data transfer command (DMA transfer setting + DMA transfer start instruction) output from the control circuit 1. While performing DMA transfer to the storage device 4 a in the path circuit 4, the operation result of the data path calculation stored in the storage device 4 a in the data path circuit 4 is transferred to the internal storage device 16 or the external storage device 2 of the control circuit 1. When the DMA transfer is completed, a process of outputting a DMA transfer completion notification to the control circuit 1 is performed.

In accordance with the data path operation instruction output from the control circuit 1, the data path circuit 4 outputs the operation result of the single operation output from the control circuit 1 and the data stored in the storage device 4a (DMA transferred by the DMA controller 3). The data path calculation using the data).
The control circuit 1, the external storage device 2, the DMA controller 3, and the data path circuit 4 are connected to the bus 5.

The main instruction memory 11 of the control circuit 1 is a storage medium that stores a program executed by the main control unit 12.
The program stored in the main command memory 11 is a command related to a data transfer instruction output from the main control unit 12 to the data transfer control unit 13, and a data path calculation instruction output from the main control unit 12 to the data path control unit 15. , A command related to a single operation executed by the main control unit 12, a read / write command to the internal storage device 16, a command related to sequence control in the main control unit 12 (for example, jump, comparison jump, etc.), and the like.

  The main control unit 12 of the control circuit 1 executes a program stored in the main instruction memory 11 to execute a data transfer instruction (for example, a transfer source address, a transfer destination address, In addition to the transfer data size, a data transfer start instruction is output to the data transfer control unit 13 and a predetermined single operation (for example, addition, subtraction, logical sum, etc.) required for the data path operation is performed. A process of outputting a data path calculation instruction indicating the calculation result of the single calculation and the calculation contents of the data path calculation to the data path control unit 15 is executed.

The data transfer control unit 13 of the control circuit 1 performs DMA transfer setting (for example, setting a transfer source address, a transfer destination address, a transfer data size, etc.) in the DMA controller 3 in accordance with the data transfer instruction output from the main control unit 12. By outputting a DMA transfer start instruction to the DMA controller 3, the data stored in the external storage device 2 (or the internal storage device 16 of the control circuit 1) is transferred to the storage device 4a in the data path circuit 4. Performs the DMA transfer process.
When the data transfer control unit 13 receives a DMA transfer completion notification from the DMA controller 3, the data transfer control unit 13 performs processing to output the DMA transfer completion notification to the main control unit 12 and the data path control unit 15.
Further, the data transfer control unit 13 controls the DMA controller 3 so that the calculation result of the data path calculation by the data path circuit 4 (the calculation result stored in the storage device 4a) is the internal storage device 16 or the external storage device. 2 is also executed.

The data path instruction memory 14 of the control circuit 1 is a storage medium that stores a program executed by the data path control unit 15.
When the data path control unit 15 of the control circuit 1 receives a DMA transfer completion notification from the data transfer control unit 13 by executing a program stored in the data path instruction memory 14, the data path control unit 15 outputs it from the main control unit 15. In accordance with the data path calculation instruction, a calculation result of a single calculation and a data path calculation instruction are given to the data path circuit 4, and the data path calculation related to the data path calculation instruction is executed by the data path circuit 4.
The internal storage device 16 of the control circuit 1 is a recording medium accessible by the main control unit 12 and stores the calculation results of the data path circuit 4, data used for data path calculation, and the like.

Next, the operation will be described.
The main control unit 12 of the control circuit 1 reads a program stored in the main instruction memory 11 and executes the program.
If the program stored in the main instruction memory 11 is, for example, an instruction related to a data transfer instruction to the data transfer control unit 13, DMA transfer setting (for example, setting a transfer source address, a transfer destination address, a transfer data size, etc.) The contents of the control for issuing the DMA transfer start instruction to the DMA controller 3 are described.

  For example, if the program stored in the main instruction memory 11 is an instruction related to a data path calculation instruction to the data path control unit 15, the data path calculation setting (for example, in the program stored in the data path instruction memory 14, The start address, the end address, the next data transferable address, etc. for starting execution are set) and the single operation result in the main control unit 12 is set to the data path circuit 4 to issue a data path operation start instruction. Control details are described.

For example, if the program stored in the main instruction memory 11 is an instruction related to a single operation, the operation content of a single operation (operation content for obtaining parameters or the like) is described.
If the program stored in the main instruction memory 11 is, for example, a read / write command for the internal storage device 16 or an internal register (not shown), the address and data size indicating the read source and write destination of data etc. are described. Yes.
For example, if the program stored in the main instruction memory 11 is an instruction related to sequence control, control contents such as jump and comparison jump are described.

FIG. 2 is an explanatory diagram showing an example of control timing of the data arithmetic device according to the first embodiment of the present invention.
In the first embodiment, a description will be given assuming that the main instruction memory 11 stores a program for the main control unit 12 to execute processing according to the control timing example of FIG.
FIG. 2 shows an example in which data path calculation 0 to data path calculation 3 are executed.

The main control unit 12 of the control circuit 1 performs DMA transfer as pre-processing for transferring data to the storage device 4a in the data path circuit 4 (indicated as “DMA transfer 0 pre-processing” in FIG. 2). Necessary address calculation or the like is performed (for example, transfer source address, transfer destination address, transfer data size, etc. are calculated).
When the main control unit 12 performs an address calculation or the like necessary for DMA transfer, the main control unit 12 sends a data transfer instruction (indicated as “DMA transfer 0 instruction” in FIG. 2) including the result of the address calculation to the data transfer control unit 13. Output.

  When the data transfer control unit 13 receives the “DMA transfer 0 instruction” from the main control unit 12, if the data transfer enable notification is output from the data path control unit 15 (the data transfer enable notification will be described later), With reference to the result of the address calculation or the like included in the “DMA transfer 0 instruction”, the DMA transfer setting (for example, setting the transfer source address, the transfer destination address, the transfer data size, etc.) is performed on the DMA controller 3, and the DMA A transfer start instruction is issued to the DMA controller 3.

When the DMA controller 3 receives a DMA transfer start instruction from the data transfer control unit 13, in parallel with the processing of the main control unit 12 of the control circuit 1, the data transfer suitable for the DMA transfer setting by the data transfer control unit 13 (see FIG. 2, “DMA transfer 0” is executed).
For example, if the transfer source address in the DMA transfer setting is an address in the external storage device 2 and the transfer destination address is an address in the storage device 4a in the data path circuit 4, data corresponding to the transfer data size is transferred from the external storage device 2. Is transferred to the storage device 4a in the data path circuit 4 by DMA.
When the DMA transfer of data is completed, the DMA controller 3 outputs a DMA transfer completion notification to the data transfer control unit 13, and the data transfer control unit 13 sends the DMA transfer completion notification to the main control unit 12 and the data transfer unit 13. Transfer to the path control unit 15.

While the DMA controller 3 is executing “DMA transfer 0”, the main control unit 12 performs preprocessing necessary for the next data transfer (indicated as “DMA transfer 1 preprocessing” in FIG. 2), A single operation (denoted as “single operation 0” in FIG. 2) for calculating parameters and the like necessary for the data path operation (denoted as “data path operation 0” in FIG. 2) is executed.
When executing “single calculation 0”, the main control unit 12 outputs a data path calculation instruction including the calculation result of “single calculation 0” to the data path control unit 15.

FIG. 2 shows an example in which the data path calculation 0 to the data path calculation 3 are executed. Before the data path circuit 4 starts the execution of the data path calculation 0, the main control unit 12 gives the data path calculation instruction 1 If it is output to the data path control unit 15 only once, the data path calculation 0 to the data path calculation 3 can be executed.
That is, the data path calculation instruction output from the main control unit 12 includes a description for instructing “loop execution” of the specified range in the program stored in the data path instruction memory 14 (repeating the specified range of the program four times). If the data path calculation instruction is output to the data path control unit 15 only once, the data path calculation 0 to the data path calculation is performed. 3 can be executed.
However, when the data path calculation is repeated a plurality of times, the main control unit 12 may output a data path calculation instruction to the data path control unit 15 every time the data path circuit 4 performs the data path calculation.

Thereafter, the main control unit 12 stands by until the transfer completion notification of “DMA transfer 0” output from the DMA controller 3 is transferred from the data transfer control unit 13.
The data path control unit 15 also waits until the transfer completion notification “DMA transfer 0” output from the DMA controller 3 is transferred from the data transfer control unit 13.

  When the data path control unit 15 receives a data path calculation instruction from the main control unit 12 and receives a transfer completion notification of “DMA transfer 0” from the data transfer control unit 13, the data path control unit 15 performs the data path calculation according to the data path calculation instruction. Calculation setting (for example, in the program stored in the data path instruction memory 14, the start address, the end address, the transferable address of the next data, etc. are set) and the calculation result of “single calculation 0” The setting is performed to the data path circuit 4 and a data path calculation start instruction is issued to the data path circuit 4.

  When the data path circuit 4 receives a data path calculation start instruction from the data path control unit 15, in parallel with the processing of the main control unit 12 and the DMA controller 3, the calculation result of "single calculation 0" and the storage device 4a “Data path calculation 0” related to the data path calculation setting is executed using the data stored in (data transferred by the DMA controller 3).

Here, the data path control unit 15 controls the data path calculation of the data path circuit 4 by executing the program stored in the data path instruction memory 14, but the program is configured to execute the data path in one instruction per cycle. If stored in the instruction memory 14, the data path control unit 15 issues a data path calculation instruction every cycle, so that the calculation status of the data path circuit 4 is always grasped.
Therefore, when the data path control unit 15 issues an end address command as a data path calculation command, the data path calculation completion notification is output to the main control unit 12 as the data path calculation of the data path circuit 4 is completed. To do.
Further, the data path control unit 15 determines that the acquisition completion timing of the data (data necessary for the data path calculation) acquired from the storage device 4a is the next data when the data path circuit 4 is executing the data path calculation. If it is specified by the transferable address, a data transfer enable notification is output to the data transfer control unit 13 when the data path calculation instruction reaches the transferable address instruction of the next data.

When the main control unit 12 receives a transfer completion notification of “DMA transfer 0” from the data transfer control unit 13, the data transfer instruction including the result of the address calculation or the like in “DMA transfer 1 preprocessing” (in FIG. Output to the data transfer control unit 13.
When the data transfer control unit 13 receives the “DMA transfer 1 instruction” from the main control unit 12, if the data transfer enable notification is output from the data path control unit 15, it is included in the “DMA transfer 1 instruction”. Referring to the result of address calculation, etc., DMA transfer setting (for example, setting of transfer source address, transfer destination address, transfer data size, etc.) is made to the DMA controller 3 and a DMA transfer start instruction is issued to the DMA controller 3 To do.

When the DMA controller 3 receives a DMA transfer start instruction from the data transfer control unit 13, in parallel with the processing of the main control unit 12 and the data path circuit 4, the data transfer suitable for the DMA transfer setting by the data transfer control unit 13 ( In FIG. 2, “DMA transfer 1” is executed.
For example, if the transfer source address in the DMA transfer setting is an address in the external storage device 2 and the transfer destination address is an address in the storage device 4a in the data path circuit 4, data corresponding to the transfer data size is transferred from the external storage device 2. Is transferred to the storage device 4a in the data path circuit 4 by DMA.
When the DMA transfer of data is completed, the DMA controller 3 outputs a DMA transfer completion notification to the data transfer control unit 13, and the data transfer control unit 13 sends the DMA transfer completion notification to the main control unit 12 and the data transfer unit 13. Transfer to the path control unit 15.

While the DMA controller 3 is executing “DMA transfer 1”, the main control unit 12 performs preprocessing necessary for the next data transfer (indicated as “DMA transfer 2 preprocessing” in FIG. 2), A single operation (denoted as “single operation 1” in FIG. 2) for calculating parameters and the like necessary for the data path operation (denoted as “data path operation 1” in FIG. 2) is executed.
Thereafter, the main control unit 12 waits until the transfer completion notification of “DMA transfer 1” output from the DMA controller 3 is transferred from the data transfer control unit 13.

When the main control unit 12 receives the transfer completion notification of “DMA transfer 1” from the data transfer control unit 13, the data transfer instruction including the result of address calculation or the like in “DMA transfer 2 pre-processing” (in FIG. Output to the data transfer control unit 13.
Thereafter, the main control unit 12 waits until a completion notification of “data path calculation 0” is output from the data path control unit 15.

  When receiving the “DMA transfer 2 instruction” from the main control unit 12, the data transfer control unit 13 waits until a data transfer enable notification is output from the data path control unit 15, and the data transfer control unit 15 notifies the data transfer enable notification. The DMA controller 3 sets the DMA transfer setting (for example, sets the transfer source address, the transfer destination address, the transfer data size, etc.) with reference to the result of the address calculation or the like included in the “DMA transfer 2 instruction”. Then, a DMA transfer start instruction is issued to the DMA controller 3.

When the DMA controller 3 receives a DMA transfer start instruction from the data transfer control unit 13, in parallel with the processing of the main control unit 12 of the control circuit 1, the data transfer suitable for the DMA transfer setting by the data transfer control unit 13 (see FIG. 2, “DMA transfer 2” is executed.
For example, if the transfer source address in the DMA transfer setting is an address in the external storage device 2 and the transfer destination address is an address in the storage device 4a in the data path circuit 4, data corresponding to the transfer data size is transferred from the external storage device 2. Is transferred to the storage device 4a in the data path circuit 4 by DMA.
When the DMA transfer of data is completed, the DMA controller 3 outputs a DMA transfer completion notification to the data transfer control unit 13, and the data transfer control unit 13 sends the DMA transfer completion notification to the main control unit 12 and the data transfer unit 13. Transfer to the path control unit 15.

When the main control unit 12 receives the completion notification of “data path calculation 0” from the data path control unit 15, the post-processing of “data path calculation 0” is performed while the DMA controller 3 is executing “DMA transfer 2”. (For example, a process for counting the number of data path calculations or a predetermined calculation process using the calculation result of the data path calculation 0 transferred by the DMA controller 3) is executed.
The data transfer control unit 13 controls the DMA controller 3 under the instruction of the main control unit 12 so that the calculation result of the data path calculation by the data path circuit 4 (the calculation result stored in the storage device 4a) is stored internally. The data is transferred to the storage device 16. This calculation result transfer process is performed as necessary, and is not performed every time the data path calculation is executed. However, since the transfer process itself is the same as the transfer process of data used for the data path calculation, the description thereof is omitted.

Further, the main control unit 12 performs preprocessing necessary for the next data transfer (indicated as “DMA transfer 3 preprocessing” in FIG. 2) and the next data path calculation (in FIG. 2, “data path calculation 2”). A single operation (denoted as “single operation 2” in FIG. 2) for calculating parameters and the like necessary for the above is executed.
Thereafter, the main control unit 12 waits until the transfer completion notification of “DMA transfer 2” output from the DMA controller 3 is transferred from the data transfer control unit 13.

  When the execution of “data path calculation 0” is completed, the data path circuit 4 stores the calculation result of “single calculation 1” and the storage device 4a in parallel with the processing of the main control unit 12 and the DMA controller 3. “Data path calculation 1” related to the data path calculation setting is executed using the existing data (data DMA-transferred by the DMA controller 3).

  Thereafter, the processing contents of “DMA transfer 3”, “DMA transfer 4” in the DMA controller 3 and “data path calculation 2” and “data path calculation 3” in the data path circuit 4 are “DMA transfer 2” and data in the DMA controller 3. Since the processing contents of the “data path calculation 1” in the path circuit 4 are the same as those in FIG.

  As apparent from the above, according to the first embodiment, a data transfer command used for data path calculation is output, a predetermined single calculation is executed, and the calculation result and data path of the single calculation are executed. The data is stored in the external storage device 2 by controlling the DMA controller 3 in accordance with the data transfer command output from the main control unit 12 that outputs a data path calculation instruction indicating the calculation contents of the calculation. A data transfer control unit 13 for transferring data used for the data path calculation to the storage device 4a in the data path circuit 4, and when the data transfer by the DMA controller 3 is completed, the data path control unit 15 Data path calculation instruction that is the execution result of the calculation result indicated by the data path calculation instruction and the calculation result of the single calculation output from The data path circuit 4 is configured to execute the data path calculation related to the data path calculation instruction using the calculation result of the single calculation and the data transferred by the DMA controller 3. When the circuit 4 is executing a data path operation, the main control unit 12 can execute the next single operation in parallel, and as a result, the processing speed can be increased. Play.

Embodiment 2. FIG.
In the first embodiment, the main control unit 12 outputs the data path calculation instruction indicating the calculation result of the single calculation and the calculation contents of the data path calculation, and the data path control unit 15 is output from the main control unit 12. The data path calculation instruction which is the execution result of the calculation result indicated by the single calculation result and the data path calculation instruction is given to the data path circuit 4, and the single calculation result and the data transferred by the DMA controller 3 Although the data path calculation related to the data path calculation instruction using the data path is executed by the data path circuit 4, the main control unit 12 indicates the data indicating the calculation contents of the data path calculation corresponding to the calculation result of the single calculation. A path calculation instruction is output, and the data path control unit 15 is an execution command for the calculation content indicated by the data path calculation instruction output from the main control unit 12. The above data using the data transferred by the DMA controller 3 by giving a data path calculation instruction (data path calculation instruction for executing the calculation contents of the data path calculation reflecting the calculation result of the single calculation) to the data path circuit 4 The data path circuit 4 may be caused to execute a data path calculation related to the path calculation instruction.

  Here, as the calculation contents of the data path calculation reflecting the calculation result of the single calculation, for example, if the calculation result of the single calculation is equal to or greater than the threshold value, the data path calculation of “A + B” is executed, and the single calculation If the result of the calculation is less than the threshold value, a data path calculation of “A + 2B” may be executed.

Embodiment 3 FIG.
In the first embodiment, when the data path control unit 15 issues an end address instruction as a data path calculation instruction, it is assumed that the data path calculation of the data path circuit 4 has been completed, and the data path calculation completion notification is sent to the main path. Although what is output to the control unit 12 has been shown, the timing (for example, address, program counter) at which the main control unit 12 outputs a data path calculation completion notification in response to a data path calculation instruction output to the data path control unit 15. The data path control unit 15 may output the completion notification of the data path calculation to the main control unit 12 at the above timing.
In this case, the main control unit 12 can start post-processing of the data path calculation before the instruction of the end address of the data path calculation is executed (for example, before the instruction of the end address is executed). In a situation where the calculation result of the data path calculation is fixed), the timing for starting the post-processing can be freely set.

Embodiment 4 FIG.
3 is a block diagram showing a data operation apparatus according to Embodiment 4 of the present invention. In the figure, the same reference numerals as those in FIG.
The upper control circuit 6 is a circuit that controls the processing content of the control circuit 1.
The higher-level control circuit communication I / F 17 receives the control signal output from the higher-level control circuit 6 and performs a process of transmitting the data path calculation result and the like to the higher-level control circuit 6. The upper control circuit communication I / F 17 constitutes a communication interface.

Next, the operation will be described.
For example, when controlling the processing content of the main control unit 12 of the control circuit 1, the upper control circuit 6 sends a control signal including a control instruction indicating the processing content of the main control unit 12 and control parameters to the control circuit 1. Output.
The upper control circuit communication I / F 17 of the control circuit 1 includes a communication storage device (for example, a register), and includes control instructions and control parameters included in the control signal output from the upper control circuit 6. Are written in the communication storage device.

When the main control unit 12 reads a program stored in the main instruction memory 11 in the same manner as in the first embodiment, the main control unit 12 executes the program to store the communication for the communication I / F 17 between the upper control circuits. Reads control instructions and control parameters written in the apparatus.
In the fourth embodiment, at the head of the program stored in the main instruction memory 11, there is an instruction for reading out a control instruction, a control parameter, etc. from the communication storage device of the upper control circuit communication I / F 17. It shall be described.

When the main control unit 12 reads a control instruction, a control parameter, and the like, the main control unit 12 performs a single operation in consideration of the control instruction, the control parameter, and the like, and transfers data to the data transfer control unit 13. An instruction and a data path calculation instruction to the data path control unit 15 are performed.
That is, the main control unit 12 executes a program stored in the main instruction memory 11, thereby executing a single operation, a data transfer instruction to the data transfer control unit 13, and a data path to the data path control unit 15. For example, if the control instruction indicates the addition or change of a program, the added or changed program is executed to execute a single operation or transfer data to the data transfer control unit 13. An instruction and a data path calculation instruction to the data path control unit 15 are performed.
If the control parameter indicates a branch condition or threshold value of the program, the program is executed so as to satisfy the branch condition or threshold value.

If the control instruction read from the communication storage device instructs transmission of the data path calculation or single calculation result, the main control unit 12 displays the data path calculation or single calculation result. A process of writing to the communication storage device of the upper control circuit communication I / F 17 is performed.
When the main control unit 12 writes the data path calculation or single calculation result into the communication storage device, the upper control circuit communication I / F 17 controls the data path calculation or single calculation result. Transmit to circuit 6.

  As is apparent from the above, according to the fourth embodiment, the inter-higher control circuit communication I / F 17 that receives the control signal output from the upper control circuit 6 is provided, and the main control unit 17 is connected between the upper control circuits. Processing is performed in accordance with the control signal received by the communication I / F 17 (for example, execution of a single operation, data transfer instruction to the data transfer control unit 13, data path operation instruction to the data path control unit 15, etc.) Therefore, it becomes possible for the upper control circuit 6 to control the processing of the control circuit 1, and as a result, there is an effect that data calculation can be performed in cooperation with other circuits.

  1 control circuit, 2 external storage device, 3 DMA controller, 4 data path circuit, 4a storage device, 5 bus, 6 upper control circuit, 11 main command memory, 12 main control unit, 13 data transfer control unit, 14 data path command Memory, 15 data path control unit, 16 internal storage device, 17 communication interface (communication interface) between upper control circuits.

Claims (9)

  A main control unit that outputs a data transfer command used for data path calculation, executes a predetermined single calculation, and outputs a data path calculation instruction indicating a calculation result of the single calculation and a calculation content of the data path calculation And a data transfer control unit for transferring data used for data path calculation stored in the storage device to the data path circuit by controlling the DMA controller according to the data transfer command output from the main control unit, When the data transfer by the DMA controller is completed, a data path calculation instruction, which is an execution instruction of the calculation result indicated by the calculation result of the single calculation output from the main control unit and the data path calculation instruction, is given to the data path circuit. The data path using the calculation result of the single calculation and the data transferred by the DMA controller. The control circuit of the data processing apparatus to a data path computation according to the operation instruction and a data path controller to be executed in the data path circuit.   Outputs a data transfer command used for data path calculation, executes a predetermined single calculation, and outputs a data path calculation instruction indicating the calculation contents of the data path calculation corresponding to the calculation result of the single calculation main A data transfer control unit for transferring data used for data path calculation stored in the storage device to the data path circuit by controlling the DMA controller according to the data transfer command output from the main control unit; When the data transfer by the DMA controller is completed, a data path calculation instruction which is an execution instruction of the calculation contents indicated by the data path calculation instruction output from the main control unit is given to the data path circuit, and the DMA controller The data path operation related to the data path operation instruction using the transferred data is The control circuit of the data processing apparatus that includes a data path controller to be executed by the pass circuit.   3. The data transfer control unit controls the DMA controller to transfer the calculation result of the data path calculation by the data path circuit to an internal storage device accessible by the main control unit. A control circuit of the data operation device described. When the data transfer by the DMA controller is completed, the data transfer control unit outputs a data transfer completion notification to the main control unit and the data path control unit,
When receiving the data transfer completion notification from the data transfer control unit, the main control unit outputs a data transfer command used for the next data path calculation, and executes a predetermined single calculation,
4. The data path control unit according to claim 1, wherein when the data transfer control unit receives a data transfer completion notification from the data transfer control unit, the data path control unit starts execution of a data path calculation by a data path circuit. A control circuit for the data arithmetic device according to claim 1. The data path control unit grasps the execution status of the data path calculation by the data path circuit, and when the data path circuit can transfer the data used for the next data path calculation, the data transfer enable notification is transferred to the data path circuit. Output to the control unit,
When the data transfer control unit receives a data transfer enable notification from the data path control unit, the data transfer control unit controls the DMA controller in accordance with the data transfer command output from the main control unit, thereby storing the next data stored in the storage device. 5. The control circuit for a data arithmetic device according to claim 1, wherein data used in the data path arithmetic is transferred to the data path circuit. 6. When outputting the data path calculation instruction, the main control unit specifies the timing for outputting the data path calculation completion notification,
5. The data path control unit outputs a data path calculation completion notification by a data path circuit to the main control unit at a timing specified by the main control unit. The control circuit of the data arithmetic unit of any one of Claims.   7. A communication interface for receiving a control signal output from a host control circuit is provided, and the processing content of the main control unit is controlled by a control signal received by the communication interface. The control circuit of the data arithmetic unit of any one of these.   Outputs a storage device that stores data, a DMA controller that transfers data, a data path circuit that executes data path calculation, a data transfer command used for data path calculation, and executes a predetermined single calculation The main controller that outputs the data path calculation instruction indicating the calculation result of the single calculation and the data path calculation, and the DMA controller is controlled according to the data transfer command output from the main control unit. Thus, when the data transfer control unit for transferring the data used for the data path calculation stored in the storage device to the data path circuit and the data transfer by the DMA controller are completed, the data is output from the main control unit. Data path operation, which is the execution instruction for the operation result indicated by the operation result of the single operation and the data path operation instruction A data path control unit that gives an instruction to the data path circuit and causes the data path circuit to execute a data path operation related to the data path operation instruction using the operation result of the single operation and the data transferred by the DMA controller And a data operation device.   Outputs a storage device that stores data, a DMA controller that transfers data, a data path circuit that executes data path calculation, a data transfer command used for data path calculation, and executes a predetermined single calculation A main control unit that outputs a data path calculation instruction indicating the calculation contents of the data path calculation corresponding to the calculation result of the single calculation, and the DMA controller according to a data transfer command output from the main control unit The data transfer control unit for transferring the data used in the data path calculation stored in the storage device to the data path circuit, and when the data transfer by the DMA controller is completed, the data is output from the main control unit. The data path calculation instruction, which is the execution instruction of the calculation content indicated by the data path calculation instruction Giving the pass circuit, data processing apparatus that includes a data path controller for the data path computation according to the data path operation instruction using the data transferred by the DMA controller executes the data path circuit.

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