JP2010245157A - Component for wiring and method of manufacturing the same, and electronic device package used by incorporating the component for wiring and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To integrate additional processes as components, of vertical wiring for forming a structure of an electronic device package, and to produce very simply and inexpensively by using conventionally-used normal manufacturing technique using die pressing. <P>SOLUTION: The component for wiring is used by being incorporated in an electronic device package including a circuit element containing a semiconductor chip arranged on a substrate with a wiring layer formed on an upper surface. The component for wiring includes a post electrode formed by half-punching a metal plate having a thickness equal to a height of the post electrode, and a half-punch plate connected to the post electrode via a joint part. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a wiring component having a post electrode, a method of manufacturing the wiring component, and a circuit element in which the wiring component is incorporated and disposed on a substrate having a wiring layer formed on the upper surface and an external electrode. The present invention relates to an electronic device package and a manufacturing method thereof.

  When the electrode is taken away from the LSI chip mounting substrate as in the electronic device package structure in which the external electrode is arranged on the front surface, or away from the active surface of the LSI chip as in the wafer level chip size package On the other hand, when an electrode is taken out, a structure including at least a vertical wiring for taking out the electrode apart from the substrate is necessary.

  For this purpose, Patent Document 1 discloses a technique for wiring by connecting a component for wiring to a predetermined position on a semiconductor substrate. 13 and 14 are diagrams for explaining the electronic device package disclosed in Patent Document 1, FIG. 13 is a cross-sectional view in the middle of its manufacture, and FIG. 14 is a cross-sectional view shown in a completed state. As shown in FIG. 13, horizontal wiring parts (rewiring) and post electrodes are grown on a support plate made of a conductive material by electroforming, thereby forming wiring components integrally connected to the support plate. Then, this wiring component is connected to a predetermined position on the wiring layer formed on the front surface of the semiconductor substrate (multilayer organic substrate). Thereafter, as shown in FIG. 14, after filling the resin covering the circuit element (LSI chip) and sealing the resin, the support plate is peeled off to electrically separate the individual horizontal wiring portion and the post electrode. Configure. As a result, it is possible to manufacture an electronic device package in which external electrodes are arranged on the front surface in a simple and inexpensive manner.

  In this way, the cost reduction can be realized by integrating the additional process of the vertical wiring for forming the electronic device package structure as a part, simplifying the process, and leaving the part to a specialized manufacturer. This componentization allows wafer level chip size packages and the like to consolidate processes that require equipment close to the previous process into parts offline, and this allows post-process manufacturers to enter without a large investment.

  However, although the electroforming method for manufacturing the illustrated wiring component is a very excellent method, there is a problem that the electroforming method itself has a lot of know-how and the number of manufacturers is limited at present.

  Patent Document 2 discloses an example in which a conventional manufacturing technique using a conventionally used mold press is applied to manufacturing a terminal land frame.

International Publication WO2008 / 065896 A1 Japanese Patent No. 3422276

  An object of the present invention is to solve such problems and to integrate vertical wiring additional steps for forming an electronic device package structure as parts.

  In addition, the present invention makes it possible to produce wiring parts used in electronic device packages very simply and at low cost by using a conventional manufacturing technique using a conventionally used die press without using an electroforming method. The purpose is to do.

  The wiring component of the present invention is used by being incorporated in an electronic device package in which a circuit element including a semiconductor chip is arranged on a substrate having a wiring layer formed on an upper surface, and a post electrode connected to the circuit element and an external electrode is used. Have. The wiring component includes a post electrode formed by punching a metal plate having a thickness equal to the height of the post electrode, and a half punched plate connected to the post electrode via a connecting portion. .

  In the electronic device package of the present invention, a circuit element including a semiconductor chip is arranged on a substrate having a wiring layer formed on the upper surface, and a post electrode connected to the circuit element and an external electrode is included. This substrate is a glass substrate having a wiring layer or a transparent resin substrate having good light transmittance, and a semiconductor chip mounted on and connected to the substrate is an image sensor chip. One end of the post electrode formed by punching out from a metal plate having a thickness equal to the height of the post electrode is connected to the wiring layer on the substrate, and the other end of the post electrode is connected to the external electrode. To function as an image sensor chip package.

  In the electronic device package of the present invention, the substrate is a high heat dissipation substrate functioning as a heat sink, and the semiconductor chip mounted and connected on the substrate is a high heat dissipation LSI chip. One end of the post electrode formed by punching out from a metal plate having a thickness equal to the height of the post electrode is connected to the wiring layer on the substrate, and the other end of the post electrode is connected to the external electrode. And function as a high heat dissipation type chip package.

  Further, the method for manufacturing an electronic device package of the present invention includes forming a wiring layer on a substrate and punching the post electrode halfway from a metal plate having a plate thickness equal to the height of the post electrode. Then, after forming a wiring component composed of a half-cut plate connected to the post electrode through a connecting portion, connecting the post electrode of the wiring component to the wiring layer on the substrate, the half-cut plate is peeled off.

  According to the present invention, it is possible to consolidate the additional process of the vertical wiring for forming the electronic device package as a part.

  In addition, the present invention makes it possible to produce wiring components used in electronic device packages extremely simply and at low cost by using a normal manufacturing technique using a conventionally used die press without using an electroforming method. Can do.

  In addition, according to the present invention, it is possible to manufacture a semiconductor package that requires an electrode to be taken out on the opposite side of the substrate, such as an image sensor or a high heat dissipation package, by a simple method. There is no need for through wiring technology in which a through hole is formed in a semiconductor substrate and filled with a metal material, and an electrode can be easily taken out and wired on the opposite side of the semiconductor substrate.

It is a figure which shows the 1st example of the electronic device package comprised based on this invention. It is a figure which shows the components for wiring, (A) is a perspective view, (B) has shown sectional drawing cut | disconnected by line X-X ', respectively. It is a microscope picture of the section which shows a half punching state. 2A and 2B are diagrams showing a state in which a semiconductor chip (LSI chip) is bonded and connected as an electronic component on a substrate, FIG. 3A is a cross-sectional view, and FIG. It is a figure shown in the state which connected the above-mentioned wiring component on the board | substrate with which the semiconductor LSI chip was mounted | worn. It is a figure shown in the state sealed with resin. It is a figure which shows the 2nd example of the electronic device package comprised based on this invention. FIG. 3 is a view showing a state in which an electronic component such as an image sensor or a high heat dissipation type LSI chip is mounted and connected on a glass substrate having a wiring layer or a high heat dissipation substrate functioning as a heat sink. It is a figure shown in the state which connected and fixed the components for wiring on the board | substrate. It is a figure which shows the completed image sensor chip package (or high heat dissipation type | mold chip package). (A) is an upper-layer electronic device package, (B) is a lower-layer electronic device package, (C) is a two-layer structure in which both electronic device packages shown in (A) and (B) are connected vertically. It is a figure which illustrates the semiconductor package of a structure. (A) is a substrate, (B) is a middle-layer electronic device package, (C) is a lower-layer electronic device package, and (D) is a vertical connection of the configurations shown in (A) to (C). It is a figure which illustrates the semiconductor package of the 3 layer structure comprised in this way. It is a figure explaining the electronic device package disclosed by patent document 1, and is sectional drawing in the middle of the manufacture. It is a figure explaining the electronic device package disclosed by patent document 1, and is sectional drawing shown in the completed state.

  Hereinafter, the wiring component and the manufacturing method thereof according to the present invention will be described step by step based on examples. FIG. 1 is a diagram showing a first example of an electronic device package configured according to the present invention. A semiconductor chip (LSI chip) is bonded and connected as an electronic component on a substrate having a wiring layer formed on the upper surface. The wiring layer is connected to a post electrode formed by punching out a half-cut plate after being punched out from a metal plate (copper plate) having a plate thickness equal to the height of the post electrode. If necessary, the top surface of the substrate is resin-sealed, and the tip of the post electrode exposed outside the resin seal is used as the external electrode. Also, through wiring that penetrates the substrate is provided, one end of which is connected to the wiring layer on the top surface of the substrate, and the other end is led to the back surface of the substrate. (Not shown) can be formed.

  Next, the manufacture of the first example of such an electronic device package will be sequentially described with reference to FIGS. 2A and 2B are diagrams showing wiring components, where FIG. 2A shows a perspective view and FIG. 2B shows a cross-sectional view taken along line X-X ′. FIG. 2 illustrates a single unit pattern. In actual manufacturing, a single unit pattern is formed in a state of being connected to one another, manufactured in an electronic device package in that state, and then cut into individual chips. After being cut into individual pieces, it is completed as a final product. In this wiring component, a post electrode is punched out from a metal plate (copper plate) having a plate thickness equal to the height of the post electrode. That is, it is stopped by partial punching without completely punching. At this stage, the post electrode is still connected to the half-cut plate through the connecting portion. Metal plate portions other than the post electrodes (hereinafter referred to as “half-cut plates”) function to integrally couple a plurality of horizontal wiring portions and post electrodes during the manufacture of the electronic device package. The half punched plate is peeled off and removed after the resin sealing step for manufacturing the electronic device package.

  FIG. 3 is a cross-sectional photomicrograph showing the half-blanked state. The step portion shown on the upper side in the figure is further enlarged and shown on the lower side. It can be seen that there is a break at the joint between the post electrode and the half-cut plate, and it can be easily peeled off.

  4A and 4B are diagrams showing a state in which a semiconductor chip (LSI chip) is bonded and connected as an electronic component on a substrate, where FIG. 4A shows a cross-sectional view and FIG. 4B shows a perspective view. The illustrated substrate is exemplified as a silicon substrate (semiconductor substrate) having a wiring layer formed on the upper surface.

  In order to form a wiring layer on the semiconductor substrate, a metal seed layer to be a wiring pattern is formed on the entire surface of the semiconductor substrate (for example, a sputtered layer or a nano metal material is coated). As the seed layer, for example, gold, silver, copper, or palladium foil that enables copper plating can be used. The wiring layer pattern is completed by applying a resist on the seed layer, exposing and developing the pattern, further etching, removing the resist. A wiring layer is grown on the seed layer by plating. Alternatively, the lithography process can be omitted by patterning the seed layer directly with nano metal particles. This direct patterning is a method in which nano metal particles such as copper are contained in an organic solvent and a desired pattern is drawn by an ink jet method which is practically used in a printer.

  The semiconductor LSI chip is illustrated as being flip-chip bonded to the wiring layer on the substrate. Instead of this flip chip bond connection, it is also possible to form a bonding metal pad portion to be a bonding wire connection electrode on the wiring layer on the substrate and connect it by a bonding wire. In this case, the metal pad portion on the wiring layer and the semiconductor LSI chip are connected by, for example, an Au bonding wire.

  FIG. 5 is a diagram showing a state in which the above-described wiring components are connected to a substrate on which a semiconductor LSI chip is mounted. A post electrode of a wiring component is fixed and electrically connected to a predetermined position of the wiring layer formed on the upper surface of the substrate. As a method for fixing and connecting the post electrode, (1) ultrasonic bonding, (2) connection using a conductive paste such as silver paste, (3) solder connection, (4) connection electrode provided on the semiconductor substrate side While the metal pad portion is provided with a concave portion, the wiring component side can be formed by a method of providing a convex portion and inserting / crimping or inserting and crimping.

  FIG. 6 is a diagram showing the resin-sealed state. After the integrally connected post electrodes are fixed at predetermined positions on the wiring layer, the upper surface of the substrate is transfer-molded to the lower surface of the half-cut plate, or a liquid resin (material is used) in this state as necessary. For example, epoxy-based).

  Thereafter, the electronic device package shown in FIG. 1 is shown in a state after the half-cut plate is peeled off. The half-cut plate can be simply peeled off, but an entire surface etching process can be added to reduce the peeling force. By etching the entire surface of the wiring component from above in FIG. 6, the thickness of the connecting portion between the post electrode and the half-cut plate can be further reduced. Other parts are also etched because it is a full-surface etching, but the thickness of the connecting part with the half-cut plate is the thinnest, and the thin part is further thinned by etching from both sides, It becomes easy to peel off. On the front surface side, an upper surface wiring is provided at the tip of the post electrode or on the sealing resin on the front surface side, and the external electrode is located at a position different from the tip of the post electrode through the upper surface wiring. (Bump electrode) can be provided.

  FIG. 7 is a diagram showing a second example of an electronic device package configured according to the present invention. In the second example, external electrodes (bump electrodes) are provided on the back surface of the substrate of the electronic device package (see FIG. 1) of the first example. The bump electrode is connected to the wiring layer on the upper surface of the substrate through a through wiring penetrating the substrate. Alternatively, the through wiring can be connected to a land which is an end surface electrode portion formed on the back surface side without providing a bump electrode.

  As described with reference to FIG. 4, the first example (and the second example) has been described using an example in which a semiconductor silicon substrate is used as the substrate. It is also possible to use a multilayer organic substrate as disclosed or a lead frame. When a multilayer organic substrate is used, the external electrode connected to the wiring layer on the upper surface of the substrate via the conductor layer inside the through hole can be easily formed on the back surface side of the substrate. The multilayer organic substrate is a substrate in which a wiring pattern is formed on each layer of a substrate composed of a plurality of layers, and then these substrates are bonded together, and through holes for connecting the wiring patterns of each layer are formed as necessary. A conductor layer is formed inside the through hole, and the conductor layer is connected to a land which is an end face electrode portion formed on the back surface side.

  As described above, the present invention forms an external electrode connected to the front surface side post electrode (or a horizontal wiring portion connected thereto) by using the exemplified wiring component, It is possible to easily form an external electrode also on the back side.

  Next, the case where the electronic device package of the present invention is used for an image sensor chip package or a high heat dissipation type chip package will be described with reference to FIGS. In FIG. 8, an electronic component such as an image sensor or a high heat dissipation type LSI chip is mounted on a glass substrate having a wiring layer (or a transparent resin substrate having good light transmission) or a high heat dissipation substrate functioning as a heat sink. FIG. In the case of an image sensor, the light receiving surface is arranged facing downward. The wiring layer on the transparent glass substrate can be formed by the same method as the wiring layer on the semiconductor substrate described above with reference to FIG. An electronic component such as an image sensor (semiconductor LSI chip) is fixed and electrically connected using a wiring layer formed on a glass substrate as a bonding pad region.

  FIG. 9 is a diagram showing a state in which wiring components are connected and fixed on the substrate. This connection is performed as described above with reference to FIG.

  FIG. 10 is a view showing a completed image sensor chip package (or a high heat dissipation type chip package). After the resin sealing, the half-cut plate is peeled off, and then the external electrode is formed at the tip of the post electrode. As described above, transfer molding is performed so as to fill the space between the glass substrate and the half-cut plate, or resin sealing is performed using a liquid resin (a material is, for example, an epoxy type). Thereafter, the half-cut plate is peeled off. Further, on the front surface side, an external electrode (bump electrode) is provided at the tip of the post electrode. Alternatively, an upper surface wiring is provided on the front surface side, and an external electrode (bump electrode) is provided at a position different from the tip of the post electrode via the upper surface wiring. Thereafter, after being cut into individual chips and separated into individual pieces, an image sensor chip package or a high heat dissipation type chip package is completed as a product. As a result, an electronic component such as an image sensor or a high heat dissipation type LSI chip is mounted on a glass substrate having a wiring layer (or a transparent resin substrate with good light transmission) or a high heat dissipation substrate functioning as a heat sink. An image sensor chip package or a high heat dissipation type chip package in which external electrodes are formed on the front surface opposite to the substrate without the need for through electrodes is completed.

  Next, the case where the electronic device package of the present invention is used for a semiconductor package having a two-layer structure will be described with reference to FIG. 11A shows an upper-layer electronic device package, FIG. 11B shows a lower-layer electronic device package, and FIG. 11C shows a configuration in which both electronic device packages shown in FIGS. A two-layer semiconductor package is illustrated. The electronic device package illustrated in FIG. 11A has a configuration illustrated in FIG. External electrodes are not formed on the back surface of the substrate, but end face electrode portions connected to the post electrodes of the lower layer electronic device package are provided. The end face electrode portion penetrates the substrate and is connected to the wiring layer on the upper surface of the substrate. The lower layer electronic device package shown in (B) is an electronic device package (see FIG. 7) of a type having an external electrode on the back surface of the substrate. By connecting both electronic device packages shown in (A) and (B) above and below, a semiconductor package having a two-layer structure as shown in (C) is formed. As described above, when the electronic device package of the present invention is used, a two-layered semiconductor package can be easily configured.

Next, the case where the electronic device package of the present invention is used in a three-layer semiconductor package will be described with reference to FIG. 12A shows the substrate, FIG. 12B shows the middle-layer electronic device package, FIG. 12C shows the lower-layer electronic device package, and FIG. 12D shows the configuration shown in FIGS. A semiconductor package having a three-layer structure formed by connecting is illustrated. The substrate shown in FIG. 12A can include an upper surface wiring layer, a through wiring connected to the wiring layer, and the like. Further, like the electronic device package shown in FIG. An electronic circuit element can also be connected. In addition, the middle-layer electronic device package shown in FIG. 12B has the configuration illustrated in FIG. 1 but is illustrated as not being resin-sealed. Although no external electrode is formed on the back surface of the substrate, an end face electrode portion (not shown) connected to the post electrode of the lower layer electronic device package is provided. The end face electrode portion penetrates the substrate and is connected to the wiring layer on the upper surface of the substrate. Moreover, a resistor and an IC are provided as examples of electronic components. The lower layer electronic device package shown in (C) is an electronic device package (see FIG. 7) of a type having an external electrode on the back surface of the substrate. As described above, if the electronic device package of the present invention is used, a three-layer semiconductor package can be easily configured.

Claims (11)

In a wiring component having a post electrode connected to the circuit element and an external electrode, which is used by being incorporated in an electronic device package in which a circuit element including a semiconductor chip is arranged on a substrate having a wiring layer formed on the upper surface,
A wiring component comprising a post electrode formed by punching out from a metal plate having a thickness equal to the height of the post electrode, and a half punched plate connected to the post electrode through a connecting portion. In a method for manufacturing a wiring component having a post electrode connected to an external electrode and used in an electronic device package in which a circuit element including a semiconductor chip is disposed on a substrate having a wiring layer formed on an upper surface ,
A wiring component comprising: forming a post electrode and a half punched plate connected to the post electrode through a connecting portion by punching in half from a metal plate having a thickness equal to the height of the post electrode. Manufacturing method. In an electronic device package in which a circuit element including a semiconductor chip is disposed on a substrate having a wiring layer formed on an upper surface, and a post electrode connected to the circuit element and an external electrode is present,
The substrate is a glass substrate having a wiring layer or a transparent resin substrate with good light transmission, and a semiconductor chip mounted and connected on the substrate is an image sensor chip,
One end of a post electrode formed by punching in half from a metal plate having a thickness equal to the height of the post electrode is connected to the wiring layer on the substrate, and the other end of the post electrode is connected to the external An electronic device package that functions as an image sensor chip package consisting of being connected to electrodes. In an electronic device package in which a circuit element including a semiconductor chip is disposed on a substrate having a wiring layer formed on an upper surface, and a post electrode connected to the circuit element and an external electrode is present,
The substrate is a high heat dissipation substrate that functions as a heat sink, and the semiconductor chip mounted and connected on the substrate is a high heat dissipation LSI chip,
One end of a post electrode formed by punching in half from a metal plate having a thickness equal to the height of the post electrode is connected to the wiring layer on the substrate, and the other end of the post electrode is connected to the external An electronic device package that functions as a high heat dissipation chip package consisting of being connected to electrodes. In a method for manufacturing an electronic device package, in which a circuit element including a semiconductor chip is arranged on a substrate having a wiring layer formed on an upper surface, and a post electrode connected to the circuit element and an external electrode is present,
A wiring layer is formed on the substrate,
From a metal plate having a thickness equal to the height of the post electrode, a post electrode is punched out in half, thereby forming a wiring component comprising a post electrode and a half punched plate connected to the post electrode through a connecting portion. Forming,
After connecting the post electrode of the wiring component to the wiring layer on the substrate, the half-cut plate is peeled off,
An electronic device package manufacturing method comprising: 6. The method of manufacturing an electronic device package according to claim 5, wherein after the post electrode of the wiring component is connected to the wiring layer on the substrate, the upper surface of the substrate is resin-sealed to the lower surface of the half-cut plate. The electronic device according to claim 6, wherein a top surface wiring is provided at the tip of the post electrode or on the sealing resin, and an external electrode is provided at a position different from the tip of the post electrode through the top surface wiring. Package manufacturing method. The method for manufacturing an electronic device package according to claim 7, further comprising an external electrode connected to a wiring layer on an upper surface of the substrate through a through wiring penetrating the substrate on a back surface of the substrate. The substrate is a glass substrate having a wiring layer or a transparent resin substrate having good light transmission, and an image sensor chip package is configured by mounting and connecting an image sensor chip on the substrate. Item 6. A method for manufacturing an electronic device package according to Item 5. 6. The substrate according to claim 5, wherein the substrate is a high heat dissipation substrate that functions as a heat sink, and a high heat dissipation type LSI package is mounted on and connected to the substrate. Manufacturing method of electronic device package. 6. The method of manufacturing an electronic device package according to claim 5, wherein a semiconductor package having a multi-layer structure is configured by connecting a plurality of the electronic device packages vertically.

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