JP2010218661A - Recording and reproducing apparatus, control apparatus, and formatting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly detect and correct a bit slipping area. <P>SOLUTION: Block sizes are changed to be smaller as it goes to the latter half toward 1 to 81 of the indices of each block constituting a data sector. As the error detecting and correcting capability of each block, parity bits are assigned by one bit to each block and a parity area integrating the parity bits is disposed to the heading part of the data sector. Since the block sizes are reduced as it goes to the latter half of each block constituting the data sector, a ratio of the error detecting and correcting capability to be assigned are larger. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a recording / reproducing apparatus, a control apparatus, and a formatting method.

  2. Description of the Related Art Conventionally, there are information recording devices that record information on a recording medium such as a magnetic disk device and an optical disk device. Records continuously in the circumferential direction.

  Then, as an information recording method adopted for the next-generation type magnetic disk device or the like, a bit patterned recording (BPR) method is being studied. In this BPR method, an information recording device such as a magnetic disk device records dots of 1 bit per dot by controlling the dots physically arranged on the medium and the recording clock with high accuracy. Here, if the recorded data is shifted by 1 bit, all the data after the shifted position are erroneous. This is called a bit slip.

  Bit slip occurs due to a shift between the dot and the recording clock, but the main factor of the shift between the dot and the recording clock is the eccentricity of the medium. Eccentricity can be generally grasped at the stage when the medium is incorporated in the apparatus, and a recording clock following the eccentricity can be generated. Data is recorded for each sector, and a preamble and sync for adjusting the recording frequency and phase are embedded at the head of the sector. Therefore, although there is no large frequency or phase shift in the data sector, the phase shift is integrated toward the second half in the data sector, and bit slip is likely to occur.

  Thus, since bit slip is a fatal problem in information recording devices such as magnetic disk devices, optical disk devices, and tape devices, many countermeasures have been studied.

  For example, Patent Document 1 proposes a technique for dealing with bit slip by correcting all erasure errors of data blocks after bit slip has occurred. Further, Patent Document 2 proposes a technique for dealing with bit slip by inserting or deleting 1 bit in reproduction data and shifting the insertion or deletion position repeatedly until correct data is obtained.

JP 62-158282 A JP-A-63-157371

  However, the technique proposed in the above patent document requires a large amount of additional information or processing time to detect a bit slip and correct an error caused by the bit slip. It is difficult to apply to disk devices.

  Further, if a strong error correction code is used to detect a bit slip and correct an error due to the bit slip, additional information increases and the recording density decreases.

  Therefore, the present invention has been made to solve the above-described problems of the prior art, and by detecting the bit slip and adjusting the distribution of the detection correction capability for correcting the detected error portion, An object of the present invention is to provide a recording / reproducing apparatus, a control apparatus, and a formatting method capable of quickly detecting and correcting a slip portion.

  In order to solve the above-described problems and achieve the object, the disclosed apparatus has a larger ratio of error detection and correction capability allocated in the data sector in the second half of each block constituting the data sector provided on the recording medium. As described above, a format unit for reducing the block size is provided.

  According to the disclosed apparatus, a bit slip portion can be detected and corrected quickly.

FIG. 1 is a diagram for explaining the magnetic disk device according to the first embodiment. FIG. 2 is a functional block diagram of the configuration of the magnetic disk device according to the first embodiment. FIG. 3 is a functional block diagram illustrating configurations of the HDC and the RDC according to the first embodiment. FIG. 4 is a diagram for explaining the concept of the recording clock frequency measurement process according to the first embodiment. FIG. 5 is a conceptual diagram illustrating an example of a recording clock frequency in the data sector according to the first embodiment. FIG. 6 is a conceptual diagram illustrating a relationship between a block index to which a parity is added and a data bit position according to the first embodiment. FIG. 7 is a diagram for explaining the block size calculation process in the data sector according to the first embodiment. FIG. 8 is a functional block diagram illustrating the configuration of the parity adder according to the first embodiment. FIG. 9 is a functional block diagram illustrating the configuration of the post processor according to the first embodiment. FIG. 10 is a diagram for explaining the bit slip detection according to the first embodiment. FIG. 11 is a functional block diagram illustrating the configuration of the bit slip corrector according to the first embodiment. FIG. 12 is a flowchart illustrating a recording clock frequency measurement process according to the first embodiment. FIG. 13 is a diagram illustrating a flow of block size variable amount initial value calculation processing according to the first embodiment.

  Hereinafter, an embodiment of a recording / reproducing apparatus, a control apparatus, and a formatting method will be described in detail. A magnetic disk device is taken up as an example of the information recording / reproducing device.

  FIG. 1 is a diagram for explaining the magnetic disk device according to the first embodiment. The outline of the magnetic disk apparatus according to the first embodiment is to cope with a bit slip that occurs during information recording using a bit patterned recording (BPR) method. The essence of the magnetic disk device according to the first embodiment is that the block of the error detection / correction capability allocated in each block increases in the second half of each block constituting the data sector provided on the recording medium. The point is to reduce the size.

  That is, as shown in FIG. 1, the block size is changed so that the block size decreases in the latter half of the index of each block constituting the data sector from 1 to 81. Then, as error detection / correction capability of each block, one parity bit is allocated to each block, and a parity part in which the parity bits are integrated is arranged at the head of the data sector. In this way, the block size becomes smaller in the second half of each block constituting the data sector, so that the ratio of the error detection / correction capability (parity) to be assigned increases. The magnetic disk device according to the first embodiment will be described in detail below.

[Configuration of Magnetic Disk Device (Example 1)]
FIG. 2 is a functional block diagram of the configuration of the magnetic disk device according to the first embodiment. As shown in the figure, the magnetic disk device 100 includes a medium 110, a head 120, a head amplifier 130, an SPM (spindle motor) 140, a VCM (voice coil motor) 150, a servo control unit 160, an MPU (microprocessor) 170, It has a memory (non-volatile) 180, an HDC (hard disk controller) 200, and an RDC (read / write channel) 300. The head amplifier 130, the servo control unit 160, the MPU 170, the HDC 200, and the RDC 300 are connected to each other via a data bus.

  The medium 110 is a recording medium in which a magnetic material is coated on a thin disk made of aluminum or glass. The head 120 reads data from the medium 110 and writes data to the medium 110. The head amplifier 130 amplifies and converts the signal from the head 120 and also amplifies and converts the signal to the head. The SPM 140 rotates the medium 110 based on the control voltage from the servo control unit 160. The VCM 150 moves the head amplifier 130 on which the head 120 is mounted based on the control voltage from the servo control unit 160.

  The servo controller 160 controls the SPM 140 or the VCM 150 so as to operate with a predetermined control voltage. The MPU 170 sends a control signal to the servo control unit 160 to execute servo control, and also executes control of the HDC 200 and RDC 300 described later. The memory (nonvolatile) 180 records data such as setting values used by the HDC 200 described later.

  FIG. 3 is a functional block diagram illustrating configurations of the HDC and the RDC according to the first embodiment.

  As shown in the figure, the HDC 200 includes a CRC encoder 210, an RLL encoder 220, an error correction encoder 230, an error correction decoder 240, an RLL decoder 250, and a CRC decoder 260. The HDC 200 implements I / F control, buffer control, format control, and error correction functions for exchanging user data with a host computer.

  As shown in FIG. 3, the RDC 300 includes a parity adder 310, a recording compensator 320, a CTF / ADC 330, an equalizer 340, a Viterbi decoder 350, and a post processor 360. The RDC 300 realizes functions of recording synchronization, PRML (Partial Response Maximum Likelihood), data encoding, and data decoding.

  Then, the HDC 200 calculates the recording clock frequency that changes for each data sector according to the eccentricity amount on the medium 110 using the servo mark interval measured by the RDC 300, and calculates the block size corresponding to the recording clock frequency. .

[Measurement of recording clock frequency]
First, the measurement of the recording clock frequency performed between the HDC 200 and the RDC 300 at the time of shipment from the factory or at the first write time will be described. The recording clock frequency is a clock frequency for accurately recording data on dots provided in a target data sector in the BPR recording method.

  FIG. 4 is a diagram for explaining the concept of the recording clock frequency measurement process according to the first embodiment. The upper part of the figure shows the arrangement of data areas and servo areas in the medium 110. Servo areas are arranged radially, and servo marks (addresses on the medium) are recorded in advance. The data area is arranged between the servo areas, and data is recorded in the circumferential (track) direction. The lower part of the figure shows a timing chart of the reproduction signal output from the head 120 and the head amplifier 130 and a fixed clock (N clock). The reproduction signal is composed of servo marks and data sectors (data areas) which are data portions between the servo marks. HDC 200 and RDC 300 cooperate to measure the number of clocks oscillated in the data sector, which is the data portion between servo marks, as the number of recording clocks.

Hereinafter, the measurement of the recording clock frequency will be specifically described. First, the HDC 200 performs a seek to a target data sector. Next, the RDC 300 detects a servo mark recorded in advance on the medium 110 from the reproduction signal, and measures the servo mark interval. Next, the HDC 200 calculates the recording clock frequency of the target data sector from the specified value between the servo marks and the measured value between the servo marks measured by the RDC 300 using the following formula, and calculates the recording clock frequency. It is stored in the memory (nonvolatile) 180 as a preset value. Note that the preset value may be written in the system area on the medium 110.

Note that f _w represents the recording clock frequency, f _r represents the fixed clock frequency, N represents the number of dots (the number of recording bits) arranged between the servo marks, and n was measured by the RDC 300. Indicates the number of counts between servo marks.

  Then, the HDC 200 determines whether measurement has been completed for all target data sectors. As a result of the determination, if the measurement has not been completed for all the target sectors, the process returns to the seek process and the next target data sector is measured. If the measurement has been completed for all the sectors to be processed, the measurement of the recording clock frequency is terminated.

[Calculation of block size]
Subsequently, calculation of the block size by the HDC 200 will be described.

  FIG. 5 is a conceptual diagram illustrating an example of a recording clock frequency in the data sector according to the first embodiment. The recording clock can be set to an optimum recording clock frequency following the eccentricity of each data sector by measuring the recording clock frequency described above. However, since the adjustment of the recording clock frequency is performed for each data sector as shown in the figure, the phase error of the recording clock increases in the second half of the data sector. This phase error causes a bit slip.

  Next, the concept of changing the block size will be described. FIG. 6 is a conceptual diagram illustrating a relationship between a block index to which a parity is added and a data bit position (bit integrated value from the head of a data sector) according to the first embodiment.

  If the recording clock frequency is constant between data sectors, the error correction coded data sector is equally divided into 81 blocks, and 1-bit parity is added every 60 bits. At this time, as shown in FIG. 6A, the relationship between the block index and the data bit position is a linear function. However, if it is considered that the phase error of the recording clock is large in the second half of the data sector due to the eccentricity of the medium 110, as shown in FIG. 6B, for example, from a maximum of 100 bits to a minimum of 20 bits. The block size is changed so that the block size becomes smaller in the latter half of the index of the data sector.

  The calculation of the block size executed in the HDC 200 will be described. FIG. 7 is a diagram for explaining the block size calculation process in the data sector according to the first embodiment. The upper part of the figure shows the relationship between the block index to which parity is added and the data bit position, and the lower part of the figure shows the relationship between the block index and the block size.

  The broken line shown in FIG. 7 shows the case where the block size is fixed at 60 bits (block size reference value), and the block size indicated by the broken line at the bottom of the figure is also fixed at 60 bits. On the other hand, the solid line shown in the figure shows, for example, that the block size reference value is 60, the block size variable amount initial value is 40, the final value is −40, and the data sector from the beginning of the data sector where the block size is 100 The block size is gradually reduced toward the second half of the sector, and the block size is set to 20 in the final block. Also, the alternate long and short dash line shown in the figure is an example in which the initial value of the block size variable amount is 50 and 30. An example of a calculation method for calculating the block size is shown below.

(Block size) = (Block size reference value) + (Block size variable amount initial value)
+ (Block size variable amount) x (block index -1)
Here, the variable block size is
(Block size variable amount) = − (Block size variable amount initial value) × 2
÷ (Total number of blocks-1)
However, (block size variable amount initial value) <(block size reference value), the block index is 1 to m, and the block size is an integer value obtained by rounding off the decimal point. If there is a difference between the total sum of all the blocks obtained here and the number of recording bits, adjustment is made with the head block (block index “1”).
(Correction size of block 1) = (size of block 1) + (number of recording bits)
-Σ (block size)

  Here, using the calculation method described above, the block size reference value is 60, the block size variable amount initial value is 40, and the final value is −40 (see the solid line in FIG. 7). A calculation example will be described.

  First, the block size variable amount can be calculated as “−1” from the block size variable initial value “40” and the total number of blocks “81”. Therefore, the block size of the block index 21 is calculated by using the above calculation method: block size reference value (60) + block size variable initial value (40) + block size variable (−1) × (21-1) = 80.

[Determine initial value of variable block size]
The determination of the block size variable amount initial value used in the block size calculation process described above will be specifically described below. The HDC 200 determines a block size by determining a block size variable amount initial value in advance based on a frequency difference of recording clocks between adjacent data sectors.

  For example, when the frequency difference of the recording clock between the adjacent data sector A and data sector B is 0.02%, if the number of recording bits of the data sector is 5000 bits, 1 in the last bit of the data sector A Bit errors will occur. Therefore, the block size variable amount initial value is determined according to the number of error bits of the final bit due to the frequency difference of the recording clock. For example, when the number of error bits of the last bit is 1 or more, the block size at the last block index is set to 1. That is, as shown in FIG. 7 above, when the block size reference value is 60, the block size variable amount initial value is set to 59. An example of a method for calculating the block size variable initial value will be described below.

(Block size variable amount initial value) = (Block size reference value)
−1 / {(number of recording bits) × (frequency difference)}
However, the initial value of the block size variable amount is an integer satisfying 0 to (block size reference value-1), and the decimal part is rounded off.

  Hereinafter, the calculation operation of the block size variable amount initial value by the HDC 200 will be described. The HDC 200 calculates the block size variable amount initial value after the recording clock frequency measurement process is completed at the time of factory shipment or at the time of the first write. First, the HDC 200 calculates a frequency difference between data sectors with reference to recording clock frequencies of a desired data sector and an adjacent data sector. After calculating the frequency difference, the HDC 200 calculates a block size variable amount initial value by using the above-described calculation method, and the calculated block size variable amount initial value is stored in a memory (nonvolatile) 180 together with a preset value of the recording clock frequency. To record. The HDC 200 determines whether all the calculation of the block size variable amount initial value has been completed for the data sector to which the recording clock frequency is preset. If the HDC 200 is not completed, the HDC 200 performs the uncompleted calculation. The process ends for the calculation of the initial value of the variable size.

[Data recording]
The data recording process of the magnetic disk device 100 that generates the parity of the recording data by the RDC 300 for each block size calculated by the HDC 200 and records and formats the recording data and the parity on the medium 110 will be briefly described below. To do.

  First, a data recording process in the magnetic disk device 100 will be briefly described. As shown in FIG. 3, the HDC 200 performs cyclic check (CRC) encoding on user data input in units of sectors using a CRC encoder 210. Next, HDC 200 performs run length constraint (RLL) coding on the data after cyclic check coding from RLL encoder 220, and error correction coding on the data after run length constraint coding by error correction encoder 230. The encoded data is output to the RDC.

  The RDC 300 adds parity for each block to the encoded data input from the HDC 200 by the parity adder 310, adjusts the recording position by the recording compensator 320, and then passes through the “Write Amp (write amplifier)” 131. To be recorded on the medium 110.

  As described above, the operations of the HDC 200 and the RDC 300 in the recording / reproduction process (data sector format) using the block size obtained by the HDC 200 will be specifically described below. FIG. 8 is a functional block diagram illustrating the configuration of the parity adder according to the first embodiment. As shown in the figure, the parity adder 310 includes a block size formatter 311, a parity generator 312, a memory 313, and a multiplexer 314.

  The HDC 200 seeks to a data sector to be recorded during data recording. At this time, the block size formatter 311 included in the parity adder 310 of the RDC 300 reads from the memory (nonvolatile) 180 the zone / track block size variable amount initial value to be recorded. Then, the block size formatter 311 calculates the block size by the above-described calculation method using the block size variable amount initial value read from the memory (non-volatile) 180, and calculates the block size corresponding to the data position to the parity generator 312. Send to.

  As described in the data recording process in the magnetic disk device 100 described above, the parity generator 312 of the RDC 310 receives encoded data (recorded data) in which user data is error correction encoded by the HDC 200 from the HDC 200.

  Then, the parity generator 312 divides the encoded data (recorded data) received from the HDC 200 in order from the beginning with a predetermined block size sent from the block size formatter 311 and generates an error detection parity for each block size. Calculate each. For example, it is calculated as a parity to which an odd / even parity is added that is “1” if the number of “1” s in a block divided by a predetermined block size is odd, and “0” if it is even. The parity generator 312 records the data and the parity in association with each other in the memory 313 until the generation of the parity is completed for all the blocks obtained by dividing the encoded data with a predetermined block size.

  The multiplexer 314 reads parity data and recording data from the memory 313 and sends the parity data and recording data to the recording compensator 320 in this order. The recording compensator 320 records the parity data and the recording data on the medium 110 in this order. The recording data recorded on the medium 110 has a format configuration as shown in FIG. 1, the parity of the block 1 corresponds to 1 of the parity part, and the parity of the block 81 corresponds to 81 of the parity part. The error detection parity can be detected more reliably by using a cyclic check (CRC) code or a BCH code, and can easily distinguish between a random error and a burst error.

[Data playback]
Data reproduction processing of the magnetic disk device 100 that reproduces data from the medium 110 will be briefly described below.

  The HDC 200 seeks to a data sector to be reproduced during data reproduction. At this time, the RDC 300 reads out the block size variable amount initial value of the zone / track to be reproduced from the memory (non-volatile) 180. As shown in FIG. 3, the RDC 300 reads out data recorded on the medium 110 via a “Read Amp” 132 by a reproducing head, and an analog filter (CTF) 330, an analog-digital converter (ADC) ) 330 and the Viterbi decoder 350 determine the binary data via the equalizer 340.

  The RDC 300 performs error detection and correction on the binary data determined by the Viterbi decoder 350 by the post processor 360 based on the data block and the parity corresponding to the data block. Next, the RDC 300 outputs data and an erasure flag to the HDC 200. HDC 200 performs error correction decoding, RLL decoding, and CRC decoding using the data from RDC 300 and the erasure flag, and outputs user data.

  Hereinafter, the internal operation of the post processor 360 will be described. FIG. 9 is a functional block diagram illustrating the configuration of the post processor according to the first embodiment. As shown in the figure, the post processor 360 includes a demultiplexer 361, a block size formatter 362, a parity regenerator 363, an error detector 364, a bit slip detector 365, a bit slip corrector 366, a selector 367, and a parity error correction. A container 368.

  The demultiplexer 361 divides the Viterbi decoder output data into a data part and a parity part, sends the data part to the parity regenerator 363, and sends the parity part to the error detector 364. The parity regenerator 363 generates parity by the same operation as the parity generator 312 of the parity adder 310 according to the block size read from the nonvolatile memory 180 by the block size formatter 362 regarding the data portion of the Viterbi decoder output data. To the error detector 364.

  The error detector 364 performs error detection using the parity sent from the parity regenerator 363 and the data of the parity part divided from the Viterbi decoder output data, and detects the error detected detection information as a bit slip. The data is sent to the detector 365 and the selector 367, respectively.

  When the occurrence of bit slip is not detected in the bit slip detector 365 described later, the selector 367 converts the error detection information sent from the error detector 364 together with the data portion of the Viterbi decoder output data to the parity error corrector. To 368. The parity error corrector 368 performs error correction using the equalizer output data with respect to the block in which there is an error from the error detection information. As a method of parity error detection and parity error correction, for example, the method shown in the reference document (IEEE Trans.Magn.VOL.31, NO.6, Nov. 1995), or Viterbi decoding instead of the equalizer output data The method using the likelihood information obtained in JP-A-2008-136166 can be used.

[Bit slip detection]
Hereinafter, the bit slip detection in the post processor 360 will be described. FIG. 10 is a diagram for explaining the bit slip detection according to the first embodiment. As shown in the figure, at the time of error detection in the post processor 360, bit slip detection is performed from the continuity of error blocks. When error correction becomes impossible in the error correction decoder 240 of the HDC 200, it is assumed that a bit slip has occurred in the block 77 since the parity error continues in the block 77 and the subsequent comparison with the bit slip detection result. I can assume.

  A bit slip detection operation in the post processor 360 will be described. As shown in FIG. 10, the bit slip detector 365 determines the index of the burst start block when the error is in a burst state (burst error) from the error detection result for each block received from the error detector 364. Information (eg, block 77) is sent to the bit slip corrector 366. The bit slip detector 365 is used when a predetermined number (for example, 3 blocks) of blocks in which an error has occurred continues, when an error exceeding 3 blocks in 5 consecutive blocks has occurred, or from a block in which an error has occurred. Up to the last error block below the above condition is detected as a burst state (burst error).

[Bit slip correction]
FIG. 11 is a functional block diagram illustrating the configuration of the bit slip corrector according to the first embodiment. As shown in the figure, the bit slip corrector 366 includes a bit inserter / deleter 366a, a parity regenerator 366b, an error detector 366c, and a bit slip detector 366d.

  The bit slip corrector 366 assumes that a bit slip has occurred in the block 77 from the index information of the burst start block sent from the bit slip detector 365. Then, the bit inserter / deleter 366 a inserts 1 bit “1” into the block 78. The parity regenerator 366b performs parity regeneration for the block 78 and subsequent blocks, and the error detector 366c performs error detection using the parity regenerated by the parity regenerator 366b. If there is no continuous error as a result of the error detection, the bit slip detector 366d gives an erasure flag only to the block 77, and together with the data portion of the Viterbi decoder output data and the error detection information of the error detector 366c, a selector 367. Send to.

  The HDC 200 that has received the error correction result via the selector 367 and the parity error corrector 368 outputs user data after performing error correction decoding.

  The bit slip direction can be determined in advance based on the difference in recording clock frequency from the adjacent track. For example, when the frequency of the next data sector is high, the possibility of bit deletion is high, and when the frequency is opposite, the possibility of bit insertion is high. The above-described bit insertion / deletion by the bit insertion / deletion unit 366a is performed in consideration of the difference in recording clock frequency. Also, if a parity error is detected by insertion or deletion, an erasure correction flag is given to the burst error block (for example, blocks 77 to 81) and output to the error correction decoder 240 to perform erasure error correction. When the error correction decoder 240 performs processing in 10-bit units (called symbols) such as Reed-Solomon, the erasure correction flag is shaped into a symbol (if there is an erasure flag even in one bit in the symbol, the symbol is Disappear.

[Processing by Magnetic Disk Device (Example 1)]
Hereinafter, processing by the magnetic disk device will be described. FIG. 12 is a flowchart illustrating a recording clock frequency measurement process according to the first embodiment. FIG. 13 is a diagram illustrating a flow of block size variable amount initial value calculation processing according to the first embodiment.

[Recording clock frequency measurement processing]
First, the flow of the recording clock frequency measurement process will be described with reference to FIG. As shown in the figure, the HDC 200 performs a seek to the target data sector (step S1). The RDC 300 detects a servo mark recorded in advance on the medium 110 from the reproduction signal, and measures the servo mark interval (step S2). The HDC 200 calculates the recording clock frequency of the target data sector from the specified value between the servo marks and the measured value between the servo marks measured by the RDC 300 (step S3), and stores the recording clock frequency as a preset value in the memory ( The data is stored in non-volatile (180) (step S4).

  Then, the HDC 200 determines whether measurement has been completed for all target data sectors (step S5). As a result of the determination, if the measurement has not been completed for all the target sectors (No at Step S5), the process returns to the seek process at Step S1 described above, and the next target data sector is measured. If the measurement has been completed for all the sectors to be processed (Yes at step S5), the measurement of the recording clock frequency is terminated.

[Block size variable amount initial value calculation processing]
Next, the flow of block size variable amount initial value calculation processing will be described with reference to FIG. As shown in the figure, the HDC 200 refers to the recording clock frequencies of the desired data sector and the adjacent data sector (step S1) and calculates the frequency difference between the data sectors (step S2). After calculating the frequency difference, the HDC 200 calculates a block size variable amount initial value (step S3), and records the calculated block size variable amount initial value in the memory (nonvolatile) 180 together with a preset value of the recording clock frequency ( Step S4). Then, the HDC 200 determines whether or not all the calculations of the block size variable amount initial value have been completed for the data sector to which the recording clock frequency is preset (step S5). If the result of the determination is that the process has not been completed (No at Step S5), the process returns to Step S1 described above to perform an uncompleted calculation. On the other hand, if it is determined that the process is completed (Yes at step S5), the process for calculating the block size variable amount initial value is terminated.

[Effects of Example 1]
As described above, according to the first embodiment, as shown in FIG. 1, the block size is changed so that the block size becomes smaller in the second half of the index of each block constituting the data sector toward 1 to 81. Thus, the same number of parities are allocated to each block. That is, the data sector is formatted so that the ratio of the error detection / correction ability to be assigned increases in the second half of each block constituting the data sector. For this reason, the ratio of error detection / correction capability increases in the latter half of the block, where the probability of bit slip occurrence is high, and as a result, the bit slip location can be detected and corrected quickly.

  In addition, according to the first embodiment, the block size variable amount for changing the block size is set according to the difference in the recording frequency between the data sectors, so that the block size can be adjusted appropriately.

  Further, according to the first embodiment, since the parity part corresponding to each block constituting the data sector is arranged at the head of the data sector, errors in the parity part can be prevented and the error detection and correction capability can be maintained.

  Hereinafter, other embodiments of the recording / reproducing apparatus, the control apparatus, and the formatting method will be described.

(1) Device Configuration, etc. For example, each component of the magnetic disk device 100 shown in FIG. 2 is functionally conceptual and does not necessarily need to be physically configured as shown. That is, the specific form of distribution / integration of the magnetic disk device 100 is not limited to that shown in the figure. For example, the HDC 200 and the memory (nonvolatile) 180 are integrated. As described above, all or a part of the magnetic disk device 100 can be configured to be functionally or physically distributed and integrated in arbitrary units according to various loads and usage conditions. Furthermore, each processing function (for example, see FIG. 11 and FIG. 12, etc.) performed in the magnetic disk device 100 is realized by a program in which all or an arbitrary part is analyzed and executed by the MPU or MCU, Alternatively, it can be realized as hardware by wired logic.

(2) Formatting Method The following formatting method is realized by the magnetic disk device 100 described in the above embodiment.

  That is, the steps of formatting the data sector so that the ratio of the error detection / correction ability to be assigned becomes larger in the latter half of each block constituting the data sector provided on the medium 110 (for example, steps S1 to S4 in FIG. 12). Format method including a reference) is realized.

  As described above, the disclosed recording / reproducing apparatus, control apparatus, and formatting method are useful for dealing with bit slips that occur during information recording using the bit patterned recording (BPR) method. Particularly, it is suitable for quickly detecting and correcting a bit slip portion.

DESCRIPTION OF SYMBOLS 100 Magnetic disk apparatus 110 Medium 120 Head 130 Head amplifier 140 SPM (spindle motor)
150 VCM (voice coil motor)
160 Servo Control Unit 170 MPU (Microprocessor)
180 memory 200 HDC (hard disk controller)
210 CRC encoder 220 RLL encoder 230 Error correction encoder 240 Error correction decoder 250 RLL decoder 260 CRC decoder 300 RDC (read / write channel)
310 Parity adder 320 Recording compensator 330 CTF / ADC
340 equalizer 350 Viterbi decoder 360 post processor

Claims (5)

  It has a format part that reduces the block size so that the ratio of error detection and correction capability allocated in the data sector increases in the second half of each block constituting the data sector provided on the recording medium. Recording / playback device.   The format unit sets a block size variable amount for changing the block size so that the block size becomes smaller in the latter half of the index of the block constituting the data sector according to the difference in recording frequency between the data sectors. The recording / reproducing apparatus according to claim 1.   The recording / reproducing apparatus according to claim 1, wherein the format unit arranges a bit string corresponding to an error correction capability assigned to each block at the head of a data sector. Applied to recording and playback devices,
It has a format part that reduces the block size so that the ratio of error detection and correction capability allocated in the data sector increases in the second half of each block constituting the data sector provided on the recording medium. Control device. Applied to recording and playback devices,
A format step for reducing the block size is included so that the ratio of the error detection and correction capability allocated in the data sector increases in the latter half of each block constituting the data sector provided on the recording medium. How to format.

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