JP2010191672A - Data storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data storage system achieving improved response performance of a disk system, etc., having one or more HDDs, without a large cost increase. <P>SOLUTION: A disk subsystem includes a read control means. When a control unit 21 is requested from a host system 1 to read out a data stored in a logical HDD 22, if the data to be read out is stored in an SSD 23 (having higher readout speed than the logical HDD 22), the read control means reads out the data stored in the SSD 23, so as to transfer the data to the host system 1, while if the data to be read out is not stored in the SSD 23, the read control means reads out the data to be read out from the logical HDD 22, so as to transfer the data to the host system 1, and stores the readout data into the SSD 23. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for improving response performance suitable for application to, for example, a disk system including one or more HDDs (Hard Disk Drives).

  In recent years, various types of personal computers such as notebook type and desktop type have been widely used. Many personal computers of this type use an HDD as an external storage device.

  Recently, in order to improve the response performance of the HDD, various proposals have been made regarding so-called hybrid HDDs in which a nonvolatile memory is built in the HDD and the nonvolatile semiconductor memory is used as a cache (for example, Patent Document 1). Etc.).

JP 2003-167781 A

  By the way, in offices where a large number of employees work by using personal computers, it is common to install a LAN (Local Area Network) for connecting these personal computers to each other. In addition, for the purpose of data sharing and unified data management, a large capacity disk system is installed so as to be accessible via the LAN.

  The disk system, for example, includes a plurality of HDDs, thereby realizing an increase in capacity at a low cost. If a hybrid HDD (each of which incorporates a nonvolatile semiconductor memory as a cache) is applied in place of a normal HDD in order to improve the response performance, a significant cost increase will be caused.

  The present invention has been made in consideration of such circumstances, and for example, a data storage that can improve the response performance of a disk system or the like having one or more HDDs without causing a significant cost increase. The purpose is to provide a system.

  In order to achieve the above-described object, a data storage system of the present invention controls one or more first storage devices, a second storage device, the first storage device, and the second storage device. And when the control device is requested to read the data stored in the first storage device, the data to be read is stored in the second storage device. When the data stored in the second storage device is read and transferred to the request source, and the data to be read is not stored in the second storage device, the data to be read is stored in the first storage device. It has a read control means for reading from the storage device and transferring it to the request source, and storing the read data in the second storage device.

  According to the present invention, for example, it is possible to improve the response performance of a disk system including one or more HDDs without causing a significant cost increase.

1 is a diagram showing a configuration of a data storage system (disk subsystem) according to a first embodiment of the present invention. The figure which shows the logical allocation example of the storage area of SSD in the disk subsystem of the said 1st Embodiment. The figure which shows an example of the cache area ensured on SSD in the disk subsystem of the said 1st Embodiment. The figure which shows an example of the management data area ensured on SSD in the disk subsystem of the said 1st Embodiment. The figure which shows an example of the bitmap in the management data area ensured on SSD in the disk subsystem of the said 1st Embodiment. The figure which shows an example of the data cache directory in the management data area ensured on SSD in the disk subsystem of the said 1st Embodiment. The figure for demonstrating the meaning of each combination of the Entire bit and Dirty bit of the data cache directory in the management data area ensured on SSD in the disk subsystem of the said 1st Embodiment. The figure for demonstrating the operation | movement procedure when the disk subsystem of the said 1st Embodiment receives the read command from a host system. The figure for demonstrating the operation | movement procedure when the disk subsystem of the said 1st Embodiment receives the write command from a host system. The figure which shows an example of the bitmap cache directory in the management data area ensured on SSD in the disk subsystem of the said 1st Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a data storage system according to the first embodiment of the present invention. This data storage system is realized as a disk subsystem 2 for storing a large amount of data used by the host system 1. The connection form between the host system 1 and the disk subsystem 2 is arbitrary. For example, in an environment connected via a LAN (Local Area Network), a plurality of host systems 1 may exist. In addition, naturally, a form in which the host system 1 and the disk subsystem 2 exist on the same computer and are connected via a data bus can be considered.

  As shown in FIG. 1, the disk subsystem 2 includes a control unit 21, a memory 21 </ b> A, a plurality of logical HDDs (hard disk drives) 22, and SSDs (solid state drives) 23.

  The control unit 21 is a central unit that controls the operation of the disk subsystem 2, and a data write request (write command) to the logical HDD 22 issued by the host system 1 or a data read request (read command) from the logical HDD 22. ), And drives and controls the memory 21A, the logical HDD 22, and the SSD 23 in order to efficiently process the requested data access to the logical HDD 22. When the disk subsystem 2 is externally connected to the host system 1, the control unit 21 includes, for example, a microcontroller and a control program, and when the disk subsystem 2 exists on the same computer as the host system 1. For example, it is composed of a basic input / output system (BIOS), a device driver, and the like.

  The disk subsystem 2 configures a high-speed SSD 23 as a shared cache of these logical HDDs 22 while configuring a large-capacity storage area with low-cost and low-speed logical HDDs 22 and makes the SSD 23 efficient as a shared cache. By providing the control unit 21 with a mechanism for using it in an effective manner, it is possible to improve response performance without incurring a significant cost increase. This point will be described in detail below.

  The memory 21A is, for example, a DRAM or the like for temporarily storing various data used as a work area by the control unit 21. The logical HDD 22 is a single HDD, a RAID (Redundant Array of Inexpensive Disks) or the like in which a plurality of HDDs are connected in parallel to improve fault tolerance. As the logical HDD 22 in the disk subsystem 2, a single HDD and RAID may be mixed. The host system 1 individually recognizes each logical HDD 22 and issues a data access request for each to the control unit 21 of the disk subsystem 2. The SSD 23 is a storage device equipped with a flash memory that is a nonvolatile semiconductor memory as a storage unit. As described above, this disk subsystem is equipped with this SSD 23 to be used as a shared cache of the logical HDD 22, but the surplus area other than the area allocated as the shared cache is one logical drive as in the logical HDD 22. As described above, an access request from the host system 1 may be accepted.

  FIG. 2 is a diagram showing a logical allocation example of the storage area of the SSD 23 in the disk subsystem 2.

  Here, it is assumed that the SSD 23 has a storage capacity of 32 GB. On the other hand, the maximum number of logical HDDs 22 is 16, and the capacity of each is maximum 2T bytes. In addition, the control unit 21 executes writing of data to the logical HDD 22 and reading of data from the logical HDD 22 in units of 128 Kbytes. Hereinafter, this is referred to as a block size. A sector that is a unit of use of the logical HDD 22 is 512 bytes, and therefore one block is 256 sectors. As shown in FIG. 2, the control unit 21 uses the storage area of the SSD 23 having a size of 32 GB in three ways: a cache area a1, a management data area a2, and a surplus area a3.

  The cache area a1 is an area that holds a part of the data of the logical HDD 22, that is, an area that is used as the aforementioned shared cache. Here, 16 Gbytes, which is half of the total storage capacity of the SSD 23, is allocated as the cache area a1. Data of the logical HDD 22 is held in the cache area a1 in block size units. In other words, the cache area a1 is divided into areas for each block size.

  The management data area a2 is an area for holding various management data for managing a part of the data of the logical HDD 22 existing on the cache area a1.

  The surplus area a3 is a remaining area after securing the cache area a1 and the management data area a2 on the SSD 23, and the control unit 21 uses the surplus area a3 as one logical drive in the same manner as the logical HDD 22. Then, an access request from the host system 1 to the logical drive is accepted.

  FIG. 3 is a diagram showing an example of the cache area a1 secured on the SSD 23. As shown in FIG.

  As described above, the cache area a1 is divided into block sizes, that is, areas of every 128 Kbytes. Then, the control unit 21 stores a part of the data of the logical HDD 22 in the cache area a1 by the 4-way set associative method. More specifically, in the present disk subsystem 2, since the maximum number of logical HDDs 22 is 16, the identifier of the logical HDD 22 can be expressed by 4 bits. Further, since the maximum capacity of each logical HDD 22 is 2 Tbytes, an LBA (Logical Block Address) indicating a sector position in each logical HDD 22 can be expressed by 32 bits. Therefore, the sector position (sector address) in the entire disk subsystem 2 can be expressed by 36 bits of upper 4 bits + lower 32 bits. The control unit 21 stores four addresses for each group, with the addresses having the same 22-8 digit values in the 36-bit sector address as one group.

  Therefore, as shown in FIG. 3, the control unit 21 arranges (EA: 22-8 digit value in the aforementioned 36-bit sector address, way: 0 to 3) from the top in the cache area a1. , (0000, 0), (0000, 1),... (7FFF, 3) are allocated. Then, the control unit 21 assumes that the data read out from the logical HDD 22 for each group is four in the order in which the data is read out, on the assumption that the data read out more recently has a higher probability of being read out again. Data is exchanged in the cache area a1 so as to be stored in the cache area a1.

  Note that the control unit 21 determines that the data requested to be written from the host system 1 to the logical HDD 22 is free in the cache area a1 (the number of other data in the same group stored in the cache area a1 is four). If not, storage in the cache area a1 using the free way is executed. Also, if there is no free space, when the data read in the past in the same group (lowest storage priority) does not include write data not reflected in the logical HDD 22, the data is replaced with this data. The target data is stored in the cache area a1. That is, even if the access time is closer to the write data, the read data having a higher possibility of re-access is preferentially present in the cache area a1.

  Since the SSD 23 is faster than the logical HDD 22, the response performance can be improved. Further, since the SSD 23 is a non-volatile storage device, when the disk subsystem 2 is started after, for example, periodic inspection, the data read immediately before the previous stop of the disk subsystem 2 is stored. Since it is in a state, the effect of improving the response performance appears immediately after startup. Since one unit is applied as a shared cache for a plurality of logical HDDs 22, there is no significant cost increase.

  FIG. 4 is a diagram showing an example of the management data area a2 secured on the SSD 23.

  Bit map a21 (hereinafter sometimes referred to as BM) is the sector position of data stored in the cache area a1 for each block of the data in the logical HDD 22 due to a write request from the host system 1 for each block. Is a data group for storing. FIG. 5 shows an example of this bitmap a1.

  As described above, in this embodiment, since one block has 256 sectors, 256 bits, that is, 32 bytes of information are required to store the write sector position in each block. Since one sector is 512 bytes, 16 blocks of bitmap can be stored in one sector. Therefore, the control unit 21 saves the bitmap in the same arrangement as each cache area having the block size allocated to the cache area a1.

  The control unit 21 executes data writing to the logical HDD 22 and data reading from the logical HDD 22 in a block size. Therefore, the control unit 21 divides the write request (write command) issued by the host system 1 into blocks, and executes data writing to the logical HDD 22 for each of the divided blocks. Considering the case where the size of the data requested to be written by the host system 1 is not an integral multiple of the block size, it is necessary to write data less than the block size at the end (the size of the data requested to be written). The same is true if is less than the block size). In preparation for such a case, by managing the bitmap, it becomes possible to execute data merging necessary when reflecting the cache 23 from the SSD 23 to the logical HDD 22. For example, when the host system 1 requests writing of data in units of sectors, the control unit 21 converts this writing into writing in units of blocks including the sector, and internally executes writing in units of blocks. However, in this case as well, the bitmap is used when data is merged between the sector in the block data cached in the SSD 23 and the other sectors stored in the logical HDD 23.

  Further, the data cache directory a22 (hereinafter sometimes referred to as DCD) is a 4-way set associative directory employed by the disk subsystem 2 in order to cache a part of the data of the logical HDD 22 in the SSD 23. FIG. 6 shows an example of this data cache directory.

  In FIG. 6, LD is an identifier of the logical HDD 22. In this disk subsystem 2, there are 4 bytes as described above, and the LBA is 32 bits. As described above, the sector address of the disk subsystem 2 is composed of 36 bits of the upper 4 bits and the lower 32 bits. The 35-23 digits of the sector address are defined as an FA (Frame Address) portion, and the 22-8 digits are defined as an EA (Entry Address) portion.

  The data cache directory a22 is a table of EA (row) × way (column). Each way field includes an FA, an LRU (Least Resently used) counter, an Entire bit, and a Dirty bit.

  The FA stores the FA part of the sector address. Thus, for example, with respect to the read target data, the directory is referenced using the EA part of the sector address as a search key, and if any way FA in the same line matches the FA part of the sector address, a hit (on the SSD 23) Exists), it can be determined as a miss hit (not present on the SSD 23) when they do not match any of them.

  The LRU counter is a counter area that takes a value from the initial value 0 to the number of ways. A larger value indicates that reading has been performed recently.

  The Entire bit is a flag area indicating whether or not the entire block is recorded in the SSD 23. “1” indicates that there is a whole, and “0” indicates that there is a part.

  The Dirty bit is a flag area indicating whether or not write data exists in the block. “1” indicates that there is write data, and “0” indicates that there is no write data.

  From the Entire bit and the Dirty bit, it is found that the location of the block data when hitting the data cache directory a22 is as shown in FIG. More specifically, when the Entire bit is “0” and the Dirty bit is “1”, a part of the data of the SSD 23 is the latest, and the position of this latest data is recorded in the bitmap. When the Entire bit is “1” and the Dirty bit is “0”, the same data exists in the SSD 23 and the logical HDD 22. When both the Entire bit and the Dirty bit are “1”, the data in the SSD 23 is the latest and the data in the logical HDD 22 is old. When the Entire bit is “0”, the write data is included in at least a part of the block, so the Dirty bit is inevitably “1”, so theoretically both the Entire bit and the Dirty bit are “ There is no 0 ”combination.

  The bitmap a21 and the data cache directory a22 of the management data area a2 described above are expanded in the memory 21A managed by the control unit 21 when the disk subsystem 2 is started, and at a predetermined timing such as when the disk subsystem 2 is shut down. Will be written back.

  Next, an operation principle executed by the control unit 21 of the disk subsystem 2 when reading data from / writing data to the logical HDD 22 using the SSD 23 as a shared cache will be described.

  First, an operation procedure when a read command is received from the host system 1 will be described with reference to FIGS.

  When receiving a data read command from the host system 1, the control unit 21 divides the read command into blocks and executes data read processing for each of the divided blocks.

  In the data read processing for each block after the division, the control unit 21 first uses the sector address EA portion and FA portion to determine whether or not there is a hit in the data cache directory a22, that is, the read target block is the SSD 23. Whether it exists in the cache area a1.

  If there is a hit, the control unit 21 checks whether or not the Entire bit of the way holding the read target block is “1”. If the Entire bit is “1” (Case R1), the control unit 21 reads the block data existing in the cache area a1 of the SSD 23 and acquires the read target data. At this time, as post-processing, the control unit 21 sets the LRU counter of the way to the maximum value and decrements the value of the LRU counter of another way having a value larger than the value before the update by one. By this operation, the value of 4 → 3 → 2 → 1 or the initial value of 0 is held in the LRU counter in ascending order of time.

  When the Entire bit is “0”, the control unit 21 subsequently refers to the bit map a21 corresponding to the block data to determine whether everything is occupied by the write sector, that is, all the data is cached in the SSD 23. It is checked whether it exists in the area a1. If all the data exists in the cache area a1 of the SSD 23 (case R2), the control unit 21 reads the block data existing in the cache area a1 of the SSD 23 and acquires the read target data. Also at this time, the control unit 21 updates the LRU counter as the post-processing described above.

  On the other hand, when the Entire bit is “0” and all data does not exist in the cache area a1 of the SSD 23 (case R3), the control unit 21 reads the data of the block to be read from both the cache area a1 of the SSD 23 and the logical HDD 22. And based on the bit map a21, data merging is performed to form the latest block data, and the read target data is acquired. Then, the control unit 21 performs writing to the cache area a1 of the SSD 23 in order to update the block data stored in the cache area a1 of the SSD 23 to the formed block data of the latest state. At this time, in addition to the above-described updating of the LRU counter, the control unit 21 executes a process for setting the Entire bit of the way to “1” as a post-process.

  In addition, when the block to be read does not exist in the cache area a1 of the SSD 23, that is, when there is no hit in the data cache directory a22 (case R4), the control unit 21 performs reading by reading from the logical HDD 22. Get the target data. The control unit 21 also writes the read block data to the cache area a1 of the SSD 23.

  If there is an empty way in the same group, this writing is executed for that way. If there is no free way, the process is executed to replace the data of the way having the smallest value of the LRU counter. If the Dirty bit of the way to be replaced is “1”, the data is reflected on the logical HDD 22 and then executed. At this time, if the Entire bit is “0”, data merging is executed with reference to the bitmap a21. When the reflection to the logical HDD 22 is finished, the control unit 21 executes initialization of the corresponding portions of the Entire bit, the Dirty bit, and the bitmap a21.

  Then, as post-processing (in the case of the case R4), the control unit 21 sets the value of the LRU counter of the way to the maximum value and decrements the value of the LRU counter of the other way one by one, and sets the Entire bit to “ The process of setting to 1 ″ is executed.

  Next, an operation procedure when a write command is received from the host system 1 will be described with reference to FIGS. 6 and 9.

  When receiving a data read command from the host system 1, the control unit 21 divides the read command into blocks and executes data write processing for each of the divided blocks.

  In the data writing process for each block after the division, the control unit 21 first uses the sector address EA part and the FA part to determine whether or not there is a hit in the data cache directory a22, that is, the write target block is the SSD 23. Whether it exists in the cache area a1.

  If there is a hit, the control unit 21 checks whether or not this writing is a block size, that is, 256 sectors worth. If writing is in block units (case W1), the control unit 21 executes writing to the SSD 23 to overwrite the write target data on the block data existing in the cache area a1 of the SSD 23. At this time, as post-processing, the control unit 21 sets the Entire bit and Dirty bit to “1”, and if necessary, initializes the corresponding part of the bitmap a21. If the writing is less than 256 sectors (Case W2), as a post-processing, a bitmap update for further storing the position of the writing sector is executed.

  On the other hand, when the block to be written does not exist in the cache area a1 of the SSD 23, that is, when there is no hit on the data cache directory a22, the control unit 21 determines whether there is an empty way in the same group, and When there is no empty way, it is checked whether the dirty bit of the way having the smallest value of the LRU counter is “0”.

  When there is an empty way in the same group, or when the dirty bit of the way having the smallest LRU counter value is “0”, the control unit 21 determines that the writing is in units of blocks (case W3 ), The data to be written is stored in the way where the value of the empty way or the LRU counter is the smallest, and, as post-processing, the Entire bit and Dirty bit of the way are set to “1”. If the writing is less than 256 sectors (Case W4), update of the bitmap for storing the position of the writing sector is further executed as post-processing.

  When there is no free way in the same group and the dirty bit of the way having the smallest LRU counter value is “1” (case W5), the control unit 21 uses the SSD 23 of the write target data. Writing to the logical HDD 23 is executed without caching.

  Further, the control unit 21 receives the read command from the host system 1 and receives the write command, or when the host system 1 does not generate a command for a certain time or more, the data cache directory a22 The write-back process for reflecting the block data whose Dirty bit is “1” to the logical HDD 22 and making the cache area a1 of the SSD 23 and the logical HDD 22 in the same state is executed for each line of the data cache directory a22. This write-back process is executed by the Spread First method. That is, the process proceeds in the order in which the number of Dirty bits “1” is equal between the lines in the data cache directory a22. If no command is sent from the host system 1 during the write-back process for one line, the control unit 21 continues this write-back process.

  As described above, in the present disk subsystem 1, the control unit 21 manages the cache area a1 of the SSD 23 by using the data cache directory a22 and the bitmap a21, so that a plurality of low-speed logical HDDs 22 are controlled. Data reading can be replaced with high-speed reading from one high-speed SSD 23 with high probability, and the response performance can be improved without causing a significant cost increase.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.

  In the first embodiment described above, it is assumed that the control unit 21 expands the bitmap a21 held in the management data area a2 of the SSD 23 to the memory 21A managed by itself when the disk subsystem 2 is started. did.

  The bitmap a21 is a huge table of 4M bytes when the cache area a1 secured on the SSD 23 is 16G bytes. Therefore, it is necessary to mount a large capacity memory 21A. Therefore, in the second embodiment, not all of the bitmap a21 is expanded in the memory 21A, but the bitmap a21 is also cached in the memory 21A by the 4-way set associative method. The required capacity of the memory 21A is reduced and further cost reduction is realized.

  FIG. 10 is a diagram illustrating an example of a bitmap cache directory for caching a part of the bitmap a21 in the memory 21A. This bitmap cache directory is stored in the SSD 23 as other management data of the management data area a2 shown in FIG. 4, and this disk subsystem 2 is used together with the data cache directory a22 instead of the bitmap a21 in the first embodiment. Is expanded in the memory 21A at the time of activation, and written back at a predetermined timing such as when the disk subsystem 2 is shut down.

  In the disk subsystem 2 of the present embodiment, the 22-19 digits of the 36-bit sector address obtained by connecting the LD4 bit and the LBA32 bit are used as the BMFA (Bit Map Frame Address) portion, and the 18-13 digits are used as the BMEA (Bit Map). Entry Address) part. The bitmap cache directory is a table of BMEA (rows) × way (columns). Each way field includes a BMFA, an LRU counter, and a dirty bit.

  The BMFA stores the BMFA part of the sector address. Thus, for example, with respect to a bitmap related to data to be read, a directory is referenced using the BMEA part of the sector address as a search key, and a hit (when the BMFA of any way in the same line matches the BMFA part of the sector address ( It can be determined that there is a mis-hit (does not exist on the memory 21A) when it does not match any of them.

  The LRU counter is a counter area that takes a value from the initial value 0 to the number of ways. Larger values indicate more recently cached.

  The Dirty bit is a flag area indicating whether or not the bitmap has position information of write data. “1” indicates that the position information of the write data exists, and “0” indicates that the position information of the write data does not exist.

  Next, the cache processing of the bitmap a21 executed by the control unit 21 of the second embodiment will be described.

  The control unit 21 checks whether or not there is a hit in the bitmap cache directory, that is, whether or not the access target bitmap portion exists in the memory 21A, using the sector address BMEA and BMFA portions.

  If there is a hit, the control unit 21 uses the bitmap portion existing on the memory 21A. If the bitmap portion is updated, the control unit 21 sets the dirty bit to “1”. At this time, as in the case of the data cache directory a22, the control unit 21 sets the LRU counter of the way to the maximum value as post-processing and sets the LRU counter of another way having a value larger than the value before the update. Decrement the value by one. By this operation, the value of 4 → 3 → 2 → 1 or the initial value of 0 is held in the LRU counter in ascending order of time.

  On the other hand, if there is no hit, if there is an empty way in the same group, the control unit 21 reads the bitmap part to be accessed from the SSD 23 and stores it in the empty way. Further, if there is no free way, replacement with the bitmap portion of the way having the smallest LRU counter value is executed. At this time, if the Dirty bit of the way to be exchanged is “1”, the bitmap portion before the exchange is written back to the SSD 23, and the Dirty bit is initialized. If the Dirty bit is not “1”, this write back is not necessary. And the control part 21 performs the update of the above-mentioned LRU counter as post-processing.

  In the disk subsystem according to the second embodiment in which a part of the bitmap a21 is cached on the memory 21A by such a procedure, the 4-Mbyte bitmap a21 can be used in a work area of about 1 Mbyte. The required capacity of the memory 21A can be reduced, and further cost reduction can be realized.

  As described above, according to the present disk subsystem 2, it is possible to improve the response performance of a disk system or the like including, for example, one or more HDDs without causing a significant cost increase.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine a component suitably in different embodiment.

DESCRIPTION OF SYMBOLS 1 ... Host system, 2 ... Disk subsystem, 21 ... Control part, 21A ... Memory, 22 ... Logical HDD, 23 ... SSD.

Claims (12)

One or more first storage devices;
A second storage device;
A control device for controlling the first storage device and the second storage device;
Comprising
The control device includes:
When reading of data stored in the first storage device is requested, if data to be read is stored in the second storage device, the data stored in the second storage device is When the data to be read is read and transferred to the request source and the data to be read is not stored in the second storage device, the data to be read is read from the first storage device and transferred to the request source. Read control means for storing the stored data in the second storage device,
A data storage system characterized by that.   The control device sets, as a group, an address where the values of bit strings located in a predetermined range in a bit string indicating an address designated at the time of reading data stored in the first storage device match as one group. Data management for exchanging data in the second storage device so that a predetermined number of data to be read are stored in the second storage device in order of close time when requested to read The data storage system of claim 1, further comprising means.   When the control device is requested to write data to the first storage device and the data corresponding to the address specified at the time of writing is stored in the second storage device, the control device 3. The data storage system according to claim 2, further comprising write control means for executing writing to the second storage device.   When the data corresponding to the address specified at the time of writing is not stored in the second storage device, the write control means of the control device is data belonging to a group specified from the address specified at the time of writing. 4. The data storage according to claim 3, wherein if the number stored in the second storage device does not reach a predetermined number, the writing of the write target data is executed to the second storage device. 5. system.   The write control means of the control device does not store the data corresponding to the address specified at the time of writing in the second storage device, and the group is specified from the address specified at the time of writing. When the number of stored data in the second storage device reaches a predetermined number, the data farthest in time when reading is requested in the data belonging to the group does not include write data 4. The data storage system according to claim 3, wherein if the write data is not included, the write of the write target data is executed on the second storage device so as to replace the data. . The control device includes:
Writing data to the first storage device and data from the first storage device in a second unit in which a plurality of first units, which are units of use of storage areas in the first storage device, are collected. Read
For the data on the first storage device existing on the second storage device, bitmap information indicating whether or not data is written by the write control means in the first unit is managed for each second unit. 6. The data storage system according to claim 3, further comprising a bitmap management means.   The read control means indicates that a part of data read in the second unit based on an address designated at the time of reading is written in the second storage device by the write control means. Indicates that the bit map information managed by is merged with a part of the data written in the second storage device and the other part of the data stored in the first storage device 7. The data storage system according to claim 6, wherein the data storage system is transferred to a request source. The control device includes:
A memory capable of storing a part of the bitmap information;
The bitmap management means stores the entire bitmap information in the second storage device, and the values of bit strings located in a predetermined range in a bit string indicating an address designated at the time of reading or writing coincide with each other The memory is configured so that each part of the bitmap information related to the data to be read is stored in the memory by a predetermined number in order from the time closest to the time when the read is requested for each group. Execute the swap of bitmap information in
7. The data storage system according to claim 6, wherein:   The controller controls the second control unit by the write control unit when neither reading of data from the first storage device nor writing of data to the first storage device is requested for a predetermined time or more. 6. The data storage system according to claim 4, further comprising write back means for storing data written in a storage device in the first storage device.   10. The write-back unit of the control device preferentially stores data in the first storage device with priority given to a group having a large number of data including a portion written by the write control unit. The data storage system described.   The control device uses a first area in a storage area provided in the second storage device as a storage area for data to be read from the first storage device, and a storage area provided in the second storage device 2. The data storage system according to claim 1, wherein the second area is used as an area for storing data to be written to the second storage device. The first storage device is composed of one or more magnetic disk devices,
The second storage device includes a nonvolatile semiconductor memory device.
The data storage system according to claim 1.

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