CN111625477A

CN111625477A - Method and device for processing read request for accessing erase block

Info

Publication number: CN111625477A
Application number: CN202010652412.9A
Authority: CN
Inventors: 袁戎; 路向峰
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2020-09-04
Anticipated expiration: 2036-07-01
Also published as: CN107562639A; CN111625477B; CN107562639B

Abstract

A method and apparatus for processing a read request to access an erase block are provided. The disclosed method for processing IO requests comprises: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; if the physical block or the block stripe containing the first physical address is in an erasing state, replaying the first read request; and acquiring the first physical address recorded by the first FTL table entry even if the first FTL table entry is locked.

Description

Method and device for processing read request for accessing erase block

Technical Field

The present application relates to solid state storage devices, and more particularly, to the handling of read requests to access an erase block while the solid state storage device handles IO requests.

Background

Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host and the storage device 102 by, for example, SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The storage device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105 and optionally a firmware Memory 110. The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc. The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the firmware memory 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in a variety of ways including software, hardware, firmware, or a combination thereof. The control unit 104 may be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller. Control unit 104 loads firmware from firmware memory 110 at runtime. Firmware memory 110 may be NOR flash, ROM, EEPROM, or may be part of NVM chip 105.

In the solid-state storage device, mapping information from logical addresses to physical addresses is maintained using FTL (Flash Translation Layer). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented in the prior art using an intermediate address modality. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.

The FTL table includes a plurality of FTL table entries (or table entries). In one embodiment, each FTL table entry records a correspondence relationship between a logical page address and a physical page. In another example, each FTL table entry records the correspondence between consecutive logical page addresses and consecutive physical pages. In another embodiment, each FTL table entry records the corresponding relationship between the logical block address and the physical block address. In still another embodiment, the FTL table records the mapping relationship between logical block addresses and physical block addresses, and/or the mapping relationship between logical page addresses and physical page addresses.

Fig. 2 is a schematic diagram of a prior art control component accessing an FTL table. The control section 204 includes a plurality of CPUs (CPU210, CPU 212, and CPU 214) and a flash interface through which the CPU of the control section accesses the NVM chip in the solid-state storage device. The FTL table is stored in a memory external to control component 204 and includes a plurality of entries (entry 220, entry 222, and entry 224). Each of the plurality of CPUs can independently access the FTL table. Since FTL entries may be accessed by multiple CPUs simultaneously, to achieve data consistency, a lock is provided for each FTL entry. Referring to fig. 2, to update the FTL entry 224, the CPU210 checks the lock 234 of the FTL entry 224, and in case the lock 234 indicates that the FTL entry 224 is not locked, the CPU210 obtains the lock 234 (e.g., sets the lock 234 to the locked state) and acquires the FTL entry 224 (time t 1). Next, the CPU210 operates on the retrieved FTL entry 224 and updates the FTL entry 224 at time t4 and releases the lock 234 (e.g., sets the lock 234 to an unlocked state). During times t1-t4, the other CPUs (CPU 212 and CPU 214) retrieve the presence of lock 234 and temporarily relinquish access to the FTL entry 224. In FIG. 2, at time t2, the CPU 212 attempts to access the FTL entry 224, but finds that the lock 234 cannot be obtained, and then relinquishes access to the FTL entry 224. Similarly, the CPU214 may also relinquish access to the FTL entry 224 at time t3 because the lock 234 is not available. After time t4, however, CPU210 releases lock 234 and the CPU 212 and the CPU214 that preempted lock 234 will access FTL entry 234. In another example, during the time period t1-t4, one task of the CPU210 acquires the lock 234, while another task in the CPU210 temporarily relinquishes access to the FTL entry 224 because the lock 234 was not acquired.

The lock of the FTL entry may be stored in the same location of the corresponding FTL entry, or the locks of a plurality of FTL entries may be collectively stored in another storage space.

Disclosure of Invention

In the solid-state storage device, a plurality of IO requests are processed simultaneously, and almost every IO request needs to access the FTL table. And the locking mechanism enables the access to the FTL table entry to be serialized, reduces the parallel processing capacity of solid-state storage, and increases the processing delay of the IO request.

In this application, a first method for processing an IO request according to a first aspect of the present application is provided, including: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; and if the physical block containing the first physical address is in an erasing state, replaying the first read request.

According to the first method for processing an IO request of the first aspect of the present application, there is provided a second method for processing an IO request of the first aspect of the present application, further including: if the first physical block containing the first physical address is in a written state, reading data from the first physical address in response to the first read request.

According to the first or second method for processing an IO request of the first aspect of the present application, there is provided a third method for processing an IO request of the first aspect of the present application, further including: in response to receiving an erase request for a first physical block, setting a state of the first physical block to an erased state; and setting a state of the first physical block to a written state in response to receiving a program request for the first physical block.

According to one of the first to third methods of processing an IO request of the first aspect of the present application, there is provided the fourth method of processing an IO request of the first aspect of the present application, wherein the replaying the read request includes: accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; if the first physical block containing the first physical address is in an erasing state, replaying the first read request; and reading data from the first physical address in response to the first read request if the first physical block including the first physical address is in a written state.

According to a second aspect of the present application, there is provided a first method for processing an IO request, including: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; and if the large block containing the first physical address is in an erasing state, replaying the first read request.

According to the second aspect of the present application, there is provided a method for processing an IO request, further comprising: if the large block containing the first physical address is in a written state, data is read from the first physical address in response to the first read request.

According to the second aspect of the present application, there is provided a method for processing an IO request, further comprising: in response to receiving an erase request for the first chunk, setting a state of the first chunk to an erased state; and setting a state of the first large block to a written state in response to receiving a program request for the first large block.

According to the first to third methods of processing an IO request of the second aspect of the present application, there is provided a method of processing an IO request of the fourth aspect of the present application, wherein the replaying the read request includes: accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; if the first large block containing the first physical address is in an erasing state, replaying the first read request; and reading data from the first physical address in response to the first read request if the first chunk containing the first physical address is in a written state.

According to the method for processing an IO request in the first or second aspect of the present application, there is provided a fifth method for processing an IO request in the first or second aspect of the present application, wherein even if the first FTL entry is locked, the first physical address recorded in the first FTL entry is obtained.

According to a third aspect of the present application, there is provided a first method for processing an IO request, including: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; data is read from the first physical address.

According to the first method for processing an IO request in the third aspect of the present application, there is provided a second method for processing an IO request in the third aspect of the present application, further including: and if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is in an erasing state, replaying the first read request.

According to the second method for processing an IO request in the third aspect of the present application, there is provided a third method for processing an IO request in the third aspect of the present application, further including: and responding to replay of the first read request, and if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is still in an erasing state, indicating that the first read request operation fails.

According to the second method for processing an IO request in the third aspect of the present application, there is provided a fourth method for processing an IO request in the third aspect of the present application, further including: and responding to replay of the first read request, if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is still in an erasing state, and if the physical block containing the first physical address is in the erasing state, replaying the first read request.

According to a fourth method for processing an IO request in the third aspect of the present application, there is provided a fifth method for processing an IO request in the third aspect of the present application, further including: in response to replaying the first read request, if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, if the first physical block including the first physical address is in a written state, reading data from the first physical address in response to the first read request.

According to a fourth method for processing an IO request in the third aspect of the present application, there is provided a sixth method for processing an IO request in the third aspect of the present application, further including: and responding to the replay of the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erasing state, and if the large block containing the first physical address is in the erasing state, replaying the first read request.

According to a sixth method for processing an IO request in the third aspect of the present application, there is provided a seventh method for processing an IO request in the third aspect of the present application, further comprising: in response to replaying the first read request, if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, if the large block containing the first physical address is in a written state, reading data from the first physical address in response to the first read request.

According to a fourth aspect of the present application, there is provided a first method for processing an IO request, including: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; responding to a received read request, accessing a first FTL table entry corresponding to the read request, and if the first FTL table entry is locked and a physical block containing a first physical address is in an erasing state, replaying the first read request; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to the first method for processing an IO request of the fourth aspect of the present application, there is provided a second method for processing an IO request of the fourth aspect of the present application, further including: in response to receiving a read request, accessing a first FTL entry corresponding to the read request, if the first FTL entry is locked, and if a first physical block including a first physical address is in a written state, reading data from the first physical address in response to the first read request.

According to the fourth aspect of the present application, there is provided a third method for processing an IO request, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is suspended until the lock of the first FTL entry is released.

According to a third method for processing an IO request in a fourth aspect of the present application, there is provided the fourth method for processing an IO request in the fourth aspect of the present application, wherein after the lock of the first FTL entry is released, the first FTL entry is obtained and locked.

According to the first or second method for processing an IO request of the fourth aspect of the present application, there is provided the fifth method for processing an IO request of the fourth aspect of the present application, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is finished.

According to a fifth aspect of the present application, there is provided a first method for processing an IO request, including: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; responding to a received read request, accessing a first FTL table entry corresponding to the read request, and if a physical block containing a first physical address is in an erasing state, replaying the first read request; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to the first method for processing an IO request of the fifth aspect of the present application, there is provided a second method for processing an IO request of the fifth aspect of the present application, further including: and responding to the received read request, accessing a first FTL table entry corresponding to the read request, and reading data from a first physical address to respond to the first read request if a first physical block containing the first physical address is in a written state.

According to the first or second method for processing an IO request in the fifth aspect of the present application, there is provided the third method for processing an IO request in the fifth aspect of the present application, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is suspended until the lock of the first FTL entry is released.

According to a third method for processing an IO request in a fifth aspect of the present application, there is provided the fourth method for processing an IO request in the fifth aspect of the present application, wherein after the lock of the first FTL entry is released, the first FTL entry is obtained and locked.

According to the first or second method for processing an IO request of the fifth aspect of the present application, there is provided the method for processing an IO request of the fifth aspect of the present application, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is ended.

According to a sixth aspect of the present application, there is provided a first method for processing an IO request, including: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; responding to a received read request, accessing a first FTL table entry corresponding to the read request, and if a first large block containing a first physical address is in an erasing state, replaying the first read request; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to the first method for processing an IO request of the sixth aspect of the present application, there is provided a second method for processing an IO request of the sixth aspect of the present application, further including: and responding to the received read request, accessing a first FTL table entry corresponding to the read request, and reading data from the first physical address to respond to the first read request if the first large block containing the first physical address is in a written state.

According to the first or second method for processing an IO request in the sixth aspect of the present application, there is provided the third method for processing an IO request in the sixth aspect of the present application, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is suspended until the lock of the first FTL entry is released.

According to a third method for processing an IO request in a sixth aspect of the present application, there is provided the fourth method for processing an IO request in the sixth aspect of the present application, wherein after the lock of the first FTL entry is released, the first FTL entry is obtained and locked.

According to the first or second method for processing an IO request in the sixth aspect of the present application, there is provided the fifth method for processing an IO request in the sixth aspect of the present application, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is finished.

According to a seventh aspect of the present application, there is provided an apparatus for processing an IO request according to the seventh aspect of the present application, including: the FTL entry obtaining module is configured to, in response to receiving the first read request, access a first FTL entry corresponding to the first read request to obtain a first physical address recorded in the first FTL entry; and the read request replay module is used for replaying the first read request if the physical block containing the first physical address is in an erasing state.

According to an eighth aspect of the present application, there is provided an apparatus for processing an IO request according to the eighth aspect of the present application, including: the FTL entry obtaining module is configured to, in response to receiving the first read request, access a first FTL entry corresponding to the first read request to obtain a first physical address recorded in the first FTL entry; and the read request replay module is used for replaying the first read request if the large block containing the first physical address is in an erasing state.

According to a ninth aspect of the present application, there is provided an apparatus for processing an IO request according to the ninth aspect of the present application, including: the FTL entry obtaining module is configured to, in response to receiving the first read request, access a first FTL entry corresponding to the first read request to obtain a first physical address recorded in the first FTL entry; and the reading module is used for reading data from the first physical address.

According to a tenth aspect of the present application, there is provided an apparatus for processing an IO request according to the tenth aspect of the present application, including: the FTL entry obtaining module is configured to, in response to receiving the write request, access a first FTL entry corresponding to the write request, and lock the first FTL entry if the first FTL entry is not locked; a read request replay module, configured to respond to a received read request, access a first FTL entry corresponding to the read request, and replay the first read request if the first FTL entry is locked and if a physical block including a first physical address is in an erased state; and the write request processing module is used for allocating a first physical address to the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

According to an eleventh aspect of the present application, there is provided an apparatus for processing an IO request according to the eleventh aspect of the present application, including: the FTL entry obtaining module is configured to, in response to receiving the write request, access a first FTL entry corresponding to the write request, and lock the first FTL entry if the first FTL entry is not locked; a read request replay module, configured to respond to a received read request, access a first FTL entry corresponding to the read request, and replay the first read request if a physical block including a first physical address is in an erased state; and the write request processing module is used for allocating a first physical address to the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

According to a twelfth aspect of the present application, there is provided an apparatus for processing an IO request according to the twelfth aspect of the present application, including: the FTL entry obtaining module is configured to, in response to receiving the write request, access a first FTL entry corresponding to the write request, and lock the first FTL entry if the first FTL entry is not locked; the read request processing module is used for responding to the received read request, accessing a first FTL table entry corresponding to the read request, and replaying the first read request if a first large block containing a first physical address is in an erasing state; and the write request processing module is used for allocating a first physical address to the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

According to a thirteenth aspect of the present application, there is provided a computer program comprising computer program code to, when loaded into a computer system and executed thereon, cause said computer system to perform a method of handling IO requests as provided in accordance with the first to sixth aspects of the present application.

According to a fourteenth aspect of the present application, there is provided a program comprising program code which, when loaded into and executed on a storage device, causes the storage device to perform the method of handling IO requests as provided in accordance with the first to sixth aspects of the present application.

Drawings

The application, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a prior art storage device;

FIG. 2 is a schematic diagram of a control component of a prior art storage device accessing an FTL table;

fig. 3A is a schematic diagram of a control component of a storage device accessing an FTL table according to an embodiment of the present application;

fig. 3B is a schematic diagram of a control component of a storage device accessing an FTL table according to another embodiment of the present application;

fig. 3C is a schematic diagram of a control component of a storage device accessing an FTL table according to still another embodiment of the present application; and

FIG. 4A is a flow diagram of accessing an FTL table for handling write commands according to an embodiment of the present application;

FIG. 4B is a flow diagram of accessing an FTL table for handling read commands according to an embodiment of the present application;

fig. 5A is a schematic diagram of a control component of a storage device accessing an FTL table according to yet another embodiment of the present application;

FIG. 5B is a sequence diagram for handling IO requests according to yet another embodiment of the present application;

FIG. 6 is a schematic diagram of the organization of physical blocks of an NVM into a block stripe according to an embodiment of the present application;

fig. 7 is a schematic diagram of a control component of a storage device accessing an FTL table according to yet another embodiment of the present application;

FIG. 8A is a flow diagram of accessing an FTL table for handling write commands according to yet another embodiment of the present application;

FIG. 8B is a flow diagram of accessing an FTL table for handling read commands according to yet another embodiment of the present application;

FIG. 9A is a flow diagram of accessing an FTL table for processing IO commands according to an embodiment of the present application;

FIG. 9B is a flow diagram of accessing FTL tables for processing IO commands according to yet another embodiment of the present application; and

fig. 9C is a flow diagram of accessing FTL table for processing IO commands according to still another embodiment of the present application.

Detailed Description

In the NVMe (Non-Volatile Memory express) protocol, different IO command types are defined. For some IO commands, no requirements are made on the sequentiality between the IO commands. For example, if a read command for logical address x is submitted and a write command for logical address x is also submitted, although the execution result of the write command may affect the execution result of the read command, if the sequentiality between the two IO commands is not required, the NVMe protocol allows the solid-state storage device to execute the two IO commands in any order.

Aiming at the characteristic of the NVMe protocol, in the embodiment according to the application, the processing mode of the IO request is improved, so that the IO command processing capacity of the solid-state storage device is improved, and the processing delay of the IO command is reduced. Those skilled in the art will appreciate that while embodiments according to the present application are described in the NVMe protocol as an example, embodiments according to the present application may be implemented in other protocols that do not require an execution order between IO commands.

Referring to fig. 3A, a schematic diagram illustrating control components of a storage device accessing FTL tables according to an embodiment of the present application is shown. The control unit 304 of the solid state disk includes a plurality of CPUs (CPU 310, CPU 312, and CPU 314), each of which is capable of accessing the FTL table external to the control unit 304. The FTL table is stored in, for example, a DRAM (Dynamic Random Access Memory). The CPU of the control unit also accesses the NVM chip through a flash interface (not shown). By way of example, the CPU310 processes a write command from the host, accesses the FTL entry 324 (indicated by W-t1 of FIG. 3A) at time t1 in accordance with the logical address indicated by the write command to assign a physical address to the write command. To avoid multiple write commands writing the same logical address at the same time, a lock corresponding to an entry is also requested when accessing the FTL entry. In the example of FIG. 3A, the CPU310 accesses the lock 334 corresponding to the FTL entry 324. In the example of FIG. 3, the lock 334 indicates that the FTL entry 324 is not locked, and the CPU310 modifies the lock 334 to indicate a lock on the FTL entry 324. In an embodiment according to the present application, when a write command is processed, a lock of an FTL entry to be modified by the write command is acquired. When the lock cannot be acquired, processing of the write command is temporarily suspended and release of the lock is awaited. In the example of FIG. 3A, after time t1, the CPU310 obtains a lock for the FTL entry 324. At this time, when other CPUs access the FTL entry 324 for processing the write command, since the lock 334 is found to indicate that the FTL entry 324 is locked, the processing of the write command accessing the FTL entry 324 is terminated.

Still referring to fig. 3A, the CPU314 processes a read command from the host and accesses the FTL entry 324 at time t2 according to the logical address of the read command. Although FTL entry 324 is locked, in the embodiment according to the present application, CPU314 ignores the lock of FTL entry 324, still obtains FTL entry 324, and obtains the physical address to be accessed according to FTL entry 324. Further, the CPU314 or other CPUs read data by the physical address and provide the read data to the host as a response to the read command. Because the read command is processed without checking whether the FTL entry 324 is locked, the write command accessing the FTL entry 324 and one or more read commands accessing the FTL entry 324 can be executed simultaneously, thereby improving the parallel processing capability of the IO command. And reduces read command processing time since there is no need to wait for the lock of FTL entry 324 to be released when processing read commands.

In the example of FIG. 3A, to process a write command, the CPU310 assigns a new physical address to the write command and updates the FTL entry 324 with the new physical address, and at time t3, the CPU310 completes the update of the FTL entry 324 (indicated in FIG. 3 by W-t 3). And also writes data to the new physical address in response to the write command. The data may be written to the new physical address by CPU310 or other CPU. Thus, at time t2, which is before time t3, the CPU314 obtains the old physical address from the FTL entry 324, and after time t3, the new physical address (updated by the CPU310 in processing write commands) is obtained from the FTL entry 324 in response to a read command. Therefore, when processing the read command, if the CPU314 accesses the FTL entry 324 before the time t3, a different physical address is obtained by accessing the FTL entry 324 after the time t3, and different data is read. Such results conform to protocols such as NVMe protocol that do not require the order of processing of IO commands.

In one example, the lock 334 and the FTL entry 324 are stored separately from each other. To process a read command, the CPU314 accesses the FTL entry 324 without accessing the lock 334. In another example, the lock 334 is stored in the same storage location as the FTL entry 324. While processing read commands, the CPU314 will obtain the contents of the lock 334 while accessing the FTL entry 324, but the CPU314 need not process the contents of the lock 334, but instead only care about the physical address provided by the FTL entry 324.

With continued reference to fig. 3A, the granularity of the lock is for each FTL entry. In response to the IO command, CPU 312 accesses FTL entry 328. For read commands, the CPU 312 ignores the lock 338 corresponding to the FTL entry 328; for write commands, CPU 312 checks lock 338 corresponding to FTL entry 328, and continues processing write commands only if lock 338 indicates that FTL entry 328 is not locked, and suspends processing write commands or defers updating FTL entry 328 if lock 338 indicates that FTL entry 328 is locked.

Fig. 3B is a schematic diagram of a control component of a storage device accessing an FTL table according to another embodiment of the present application. Read or write commands from the host access different lengths of data and different numbers of FTL entries. In an embodiment according to the present application, the granularity of locking is per FTL entry. By way of example, the CPU310 processes a write command from the host, the write command accessing 3 logical addresses, and the CPU310 accesses the FTL entry 320, the FTL entry 322, and the FTL entry 324 (indicated by W1-t1, W2-t1, and W3-t1 of FIG. 3B) at time t1 to allocate a physical address for the write command. CPU310 also requests locks corresponding to the entries when accessing FTL entries, by accessing lock 330, lock 332, and lock 334 to request locks corresponding to FTL entries 320, FTL entries 322, and FTL entries 324. When the corresponding lock is acquired, the CPU310 performs subsequent operations, allocates a new physical address and updates the corresponding FTL entry with the new physical address, and when the corresponding lock cannot be acquired, the CPU310 stops the operation on the corresponding FTL entry and waits for the corresponding lock to be released. For example, the CPU310 obtains the lock of the FTL entry 320 and the FTL entry 322, but does not obtain the lock of the FTL entry 324, the CPU310 continues to update the FTL entry 320 and the FTL entry 322 by subsequent processing, and suspends the operation on the FTL entry 324 until the lock 334 of the FTL entry 324 is released and obtained by the CPU310, and the CPU310 continues to update the FTL entry 324. In response to the FTL entry being updated, data is also written to the new physical address in response to the write command. And when the new physical addresses of the three FTL table entries corresponding to the write command are all written with data, completing the write command processing.

Still referring to FIG. 3B, the CPU314 processes the read command from the host, and accesses the FTL entry 324 (denoted as R-t2 in FIG. 3B) at time t2 according to the logical address of the read command. Although the FTL entry 324 has been locked by the CPU310 when processing the write command, in the embodiment according to the present application, the CPU314 ignores the lock of the FTL entry 324, still acquires the FTL entry 324, and acquires the physical address to be accessed according to the FTL entry 324. Further, the CPU314 or other CPUs read data by the physical address and provide the read data to the host as a response to the read command. Because the read command is processed without checking whether the FTL entry 324 is locked, the write command accessing the FTL entry 324 and one or more read commands accessing the FTL entry 324 can be executed simultaneously, thereby improving the parallel processing capability of the IO command. And reduces read command processing time since there is no need to wait for the lock of FTL entry 324 to be released when processing read commands.

Fig. 3C is a schematic diagram of a control component of a storage device accessing an FTL table according to still another embodiment of the present application. In the illustrated embodiment, FIG. 3C is an illustration of how multiple IO commands may be processed in parallel on the same CPU. By way of example, the CPU310 processes a write command from the host, and the CPU310 accesses the FTL entry 324 (indicated by W1-t2 of FIG. 3C) at time t1 to assign a physical address for the write command based on the logical address indicated by the write command. The CPU310 also requests a lock corresponding to the entry when accessing the FTL entry, and requests a lock corresponding to the FTL entry 324 by accessing the lock 334. Upon acquiring the corresponding lock, the CPU310 performs subsequent operations, allocates a new physical address and updates the corresponding FTL entry 324 with the new physical address at time t3 (the updating of the FTL entry 324 is indicated by W3-t3 of fig. 3C). Between times t1 and t3, the CPU310 also accesses the FTL entry 324 at time t2 in response to a host read command. Although at time t2, the lock 334 indicates that the FTL entry 324 is locked, for a read command, the CPU310 still accesses and uses the FTL entry 324 to read data using the physical address provided by the FTL entry 324 even though there is a lock on the FTL entry 324. In further embodiments, the CPU310 caches the FTL entry 324 retrieved at time t1, and retrieves the contents of the FTL entry 324 from the CPU310 cache at time t 2. And for processing read commands, whether or not the FTL entry 324 cached by the CPU310 is updated, reading data using the physical address provided by the cached FTL entry 324. At time t2, the CPU314 accesses the FTL entry 324 (shown in FIG. 3C as R3-t 2) in response to the logical address of another read command. Because of the read command, although the lock 334 indicates that the FTL entry 324 is locked, the CPU314 still accesses and uses the FTL entry 324 and reads data with the physical address provided by the FTL entry 324.

Fig. 4A is a flow diagram of accessing an FTL table for processing a write command according to an embodiment of the present application. In an embodiment according to the present application, in response to receiving a write command (410) to access a logical address of a first FTL entry, it is checked (420) whether the first FTL entry is locked. If the first FTL table entry is locked, stopping the subsequent processing of the first FTL table entry and waiting for the lock of the first FTL table entry to be released. Subsequent processing of the first FTL entry is part of the processing of the write command. If the first FTL entry is not locked or the lock of the first FTL entry is released, to process the write command, the first FTL entry is locked (430) so that other write commands accessing the first FTL entry are temporarily suspended. To process the write command, a first physical address is assigned to the write command, the first FTL entry is updated with the first physical address, the updated FTL entry is written into the FTL table, and the first FTL entry is unlocked (440). Assigning a new physical address for a write command may utilize a variety of means known in the art. And writing data corresponding to the write command to the first physical address (450).

In another example, when the first FTL entry corresponding to the logical address of the write command is accessed in response to receiving the second write command, and the first FTL entry is found to be locked, the processing of the second write command is completed without allocating a physical address for the second write command and without writing data corresponding to the second write command to the nonvolatile memory.

Fig. 4B is a flow diagram of accessing an FTL table for processing a read command according to an embodiment of the present application. In response to receiving the read command, the logical address of the read command corresponds to the first FTL entry (432). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command (see step 430 of fig. 4A), the locked first FTL entry is obtained from the FTL table and used when processing the read command (434). And reading the data (436) in response to the read command based on the first physical address.

In another example, when a first FTL entry is obtained for processing a read command, if the first FTL entry is locked, it indicates that there is a write command in execution accessing the first FTL table, and the data to be written by the write command is in the cache. And searching data to be written by the write command accessing the first FTL table from the cache as read data of the read command. The speed of obtaining data from the cache is far faster than the speed of obtaining data from the nonvolatile memory chip, so that the processing time of the read command is further reduced by using the cached data to be written as a response to the read command.

Fig. 5A is a schematic diagram of a control component of a storage device accessing an FTL table according to yet another embodiment of the present application.

The control section 504 of the solid state disk includes a plurality of CPUs (CPU 510, CPU 512, CPU 514), each of which is capable of accessing the FTL table external to the control section 504. The CPU of the control unit also accesses the NVM chip 505 through the flash interface. NVM chip 505 includes a plurality of memory cells, such as memory cell 550, memory cell 552, memory cell 560, and memory cell 562. By way of example, CPU 510 processes a write command from a garbage collection task and accesses FTL entry 524 (indicated by Wg-t1 of FIG. 5A) at time t1 in accordance with the logical address indicated by the write command to assign a physical address to the write command. To avoid multiple write commands writing the same logical address at the same time, a lock corresponding to an entry is also requested when accessing the FTL entry. In the example of FIG. 5A, CPU 510 accesses lock 534 corresponding to FTL entry 524. In the example of FIG. 5A, CPU 510 modifies lock 534 to indicate a lock on FTL entry 524.

Still referring to FIG. 5A, the CPU 514 processes the read command from the host, accessing the FTL entry 524 (indicated by R-t2 in FIG. 5A) at time t2 based on the logical address of the read command. Although FTL table 524 is locked, in the embodiment according to the present application, CPU 514 ignores the lock of FTL table entry 524 when processing the read command, still acquires FTL table entry 524, and acquires the physical address to be accessed according to FTL table entry 524. The CPU 514 accesses the physical address of the NVM chip 505 through the flash interface according to the acquired physical address and acquires data to be read.

In the example of FIG. 5A, to process a write command from a garbage collection task, CPU 510 assigns a new physical address to the write command and updates FTL entry 524 with the new physical address, and at time t3, CPU 510 completes the update to FTL entry 524 (indicated in FIG. 5A by Wg-t 3). And also writes data to the new physical address in response to the write command.

In some cases, the physical address accessed when the CPU 514 processes the read command is a physical block in the NVM chip 505 that is in an erased state. The physical block in the erased state has no valid data and should not be read. FIG. 5B is a sequence diagram illustrating the reason that the CPU 514 reads an erase block in the NVM chip 505 for processing an IO request according to yet another embodiment of the present application. In fig. 5B, the time axis shows the direction of the passage of time. In response to Garbage Collection (GC) write command 560, CPU 510 accesses FTL entry 524 (indicated by Wg-t1 of FIG. 5A) at time t1 according to the logical address indicated by write command 560, FTL entry 524 is locked, and the physical address of FTL table 524 indicates memory location 550 of NVM chip 505. In processing the GC write command (560), FTL entry 524 is next updated by CPU 510, and the updated physical address of FTL entry 524 indicates storage unit 560.

After FTL entry 524 is locked, a user read command is received (570), CPU 514 processes the user read command (570) and obtains FTL entry 524. Since the lock 534 of the FTL entry 524 is ignored when the CPU 514 acquires the FTL entry 524, and the timing of acquiring the FTL entry 524 is before the FTL entry 524 is updated by the CPU 510, the physical address acquired from the FTL entry 524 indicates the storage unit 550.

With continued reference to fig. 5B, the GC write command 560 is followed by a GC erase command 562, and the affected old physical address (memory location 550) of the GC write command 560 is erased in response to the GC erase command 562. So that the memory cells 550 of the NVM chip are in an erased state. And CPU 514 obtains old FTL entry 524 for processing user read command 570 and issues the read command to storage unit 550 through the flash interface. The two operations, i.e., the CPU 514 issuing a read command to the memory unit 550 and the CPU 510 issuing an erase command to the memory unit 550, may occur in any order, so that when the CPU 514 issues a read command, the memory unit 550 may be in an erased state, and thus the read command may not be correctly processed.

In an embodiment according to the present application (see fig. 5A), to solve the above problem, the control section 504 also maintains a block status table 540. In the block state table 540, it is recorded whether each physical block of the NVM chip 550 is in an erased state or in an already written state. In one example, when a physical block is erased, block status table 540 is updated to identify that the physical block is in an erased state. When the physical block is written for the first time, block status table 540 is updated to identify that the physical block is in a written state. Before the CPU 514 issues a read command to the NVM chip 505 through the flash interface, the physical block where the physical address is located is obtained by using the physical address obtained from the FTL entry 524, and the state of the physical block is looked up in the block state table 540. If the physical block is in a written state, the CPU 514 issues a read command to the NVM chip 505 through the flash interface; if the physical block is in the erased state, the CPU 514 instructs to replay the read command. By way of example, replaying a read command means that the control section 504 treats the read command as a newly received read command and reprocesses it. Because of the time required for re-processing, when FTL entry 524 is re-acquired, its contents have been updated with a high probability, and newly acquired FTL entry 524 will provide an updated physical address in which valid data is stored. In a few cases, for example, when FTL entry 524 is obtained again, the update of FTL entry 524 is still not completed, and the obtained FTL entry is still the old physical address in the erased state. In this case, in one example, the read command is replayed again to retrieve the FTL entry 524; in yet another example, CPU 514 further identifies lock 534 corresponding to FTL entry 524. If the lock 534 indicates that the FTL entry 524 is locked, the CPU 514 waits for the release of the lock 534 to obtain the updated FTL entry 524, and then accesses the NVM chip 505 with the physical address provided by the updated FTL entry 524; if lock 534 indicates that FTL entry 524 is not locked, NVM chip 505 is immediately accessed with the physical address provided by FTL entry 524.

FIG. 6 is a schematic diagram of the organization of physical blocks of an NVM into block stripes according to an embodiment of the present application. In the solid-state storage device shown in FIG. 6, a block stripe is constructed on every 16 logical units (LUN0, LUN1, … … LUN15), and physical blocks of the same physical address within each logical unit constitute a "block stripe".

In FIG. 6, block B0 with address 0 in LUN0-LUN15 constitutes block stripe 0, where physical blocks B0 of LUN0 through LUN14 are used to store user data, and physical block B0 of LUN15 is used to store parity data calculated from user data within the block stripe. The physical blocks of the NVM include a plurality of pages, the physical pages in a block stripe having the same address constitute a page stripe, and check data is calculated for each page stripe. For example, each physical page in physical block B0 of LUN15 stores check data calculated from all user data of the page stripe in which the physical page resides.

Similarly, in FIG. 6, physical block B2, address 2, of LUN0-LUN15 is block stripe 2. Alternatively, the physical block used to store the check data may be located in any LUN in the block stripe. In the example of fig. 6, when the data of 1 physical page of a block stripe is damaged by the parity data in the block stripe, the data of the damaged page can be recovered from the other pages of the page stripe where the physical page is located.

Those skilled in the art will appreciate that the block strips may be constructed in a variety of other data organization manners. Multiple physical blocks are included in a block stripe, and data protection is provided in the block stripe through redundancy or RAID techniques. So that in case one or several physical blocks in a block stripe are corrupted, the data of the corrupted physical blocks can be reconstructed by the other blocks of the block stripe. Erasing is performed in units of block stripes. When an erase operation is performed, all physical blocks belonging to a stripe of blocks are erased together.

Fig. 7 is a schematic diagram of a control component of a storage device accessing an FTL table according to still another embodiment of the present application. In contrast to fig. 5A, in the embodiment of fig. 7, control unit 504 further includes CPU516, and block stripes 750, 752, 754, 756, and block stripe status table 740 for recording the status of each block stripe on NVM 705. In block stripe state table 740, a plurality of entries (entry 760, entry 762, entry 764, and entry 766) are included, each recording whether a corresponding block stripe of NVM705 is in an erased state or in an already written state. In one example, when a block stripe is erased, the block stripe state table 740 is updated to identify that the block stripe is in an erased state. When the block stripe is written for the first time, block stripe status table 740 is updated to identify that the physical block is in a written state.

In the FIG. 7 embodiment, to process a read command, CPU 514 accesses FTL entry 524 and provides the physical supply provided by FTL entry 524 to CPU 516. CPU516 issues a read command to NVM705 through the flash interface. Before the CPU516 issues a read command to the NVM705 through the flash interface, the physical address obtained from the FTL entry 524 is used to obtain the block stripe where the physical address is located, and the state of the block stripe is looked up in the block stripe state table 740. If the block is in the written state, CPU516 issues a read command to NVM705 via the flash interface; if the physical block is in the erased state, the CPU516 instructs to replay the read command. In rare cases, for example, when FTL entry 524 is retrieved, the update of FTL entry 524 is still not completed, and the retrieved FTL entry provides the old physical address in the erased state. In this case, in one example, the read command is replayed again to retrieve the FTL entry 524; in yet another example, CPU516 further identifies lock 534 corresponding to FTL entry 524. If lock 534 indicates that FTL entry 524 is locked, CPU 614 waits for release of lock 534 to obtain updated FTL entry 524, and then provides the physical address provided by updated FTL entry 524 to CPU 516; if lock 534 indicates that FTL entry 524 is not locked, the physical address provided by FTL entry 524 is immediately provided to CPU 516.

Fig. 8 is a flow diagram of accessing FTL table for processing IO commands according to yet another embodiment of the present application. In the embodiment according to fig. 8, in response to receiving a write command to access a logical address of a first FTL entry (802), it is checked whether the first FTL entry is locked (804). If the first FTL table entry is locked, stopping the subsequent processing of the first FTL table entry and waiting for the lock of the first FTL table entry to be released. Subsequent processing of the first FTL entry is part of the processing of the write command. If the first FTL entry is not locked or the lock of the first FTL entry is released, to process the write command, the first FTL entry is locked (806) so that other write commands accessing the first FTL entry are temporarily suspended. To process the write command, a first physical address is allocated for the write command, the first FTL entry is updated with the first physical address, the updated FTL entry is written into the FTL table, and the first FTL entry is unlocked (808). Assigning a new physical address for a write command may utilize a variety of means known in the art. And writing data corresponding to the write command to the first physical address (809).

With continued reference to fig. 8, in response to receiving the read command, the logical address of the read command also corresponds to the first FTL entry (810). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command (see step 806 of fig. 8), the first physical address provided by the first FTL entry is obtained from the FTL table and used when processing the read command (820). Next, the corresponding physical block or block stripe is obtained according to the first physical address, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5A, 540) or the block stripe state table (see fig. 7, 740). If the retrieved status indicates that the physical block or block stripe in which the first physical address is located is in an erased state (830), the read command is replayed, in other words, the read command is reprocessed, via step 810. If the retrieved status indicates that the physical block or block stripe in which the first physical address is located is in a written state 830, data is read from the first physical address in response to the read command 840.

Fig. 9A is a flow diagram of accessing FTL tables for processing IO commands according to an embodiment of the present application. In the embodiment of FIG. 9A, in response to receiving a read command, the logical address of the read command corresponds to the first FTL entry (910). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command, the first physical address provided by the first FTL entry is obtained 920 from the FTL table and used when processing the read command. Next, a read command is sent to the NVM in accordance with the first physical address to read data from the first physical address (925). Whether a physical page corresponding to the first address is in an erased state is indicated in the result of reading the data 930. In one example, the NVM chip provides such an indication in the results of reading the data to identify whether the physical page being read is in an erased state. In another example, the flash interface of the control unit determines whether the read data is from a physical page in an erased state based on the data read from the NVM chip.

With continued reference to FIG. 9A, if the result of reading the data indicates that the physical page corresponding to the first physical address is in the erased state, the step 910 is returned to replay the read command. If the read data result indicates that the physical page corresponding to the first physical address is not in the erased state, the read data is valid, and the read command processing is completed with the read data as a response to the read command (940).

In the embodiment of fig. 9A, after the first physical address is obtained, it is not first checked whether the physical block or block stripe where the first physical address is located is in an erased state. Since the probability that the physical block or block stripe where the first physical address is located is in the erased state is low, in most cases, the operation of checking whether it is in the erased state will introduce additional delay. In the embodiment of fig. 9A, after the first physical address is obtained, data is read out directly from the first physical address without first checking whether the physical block or block stripe where the first physical address is located is in an erased state, and it is determined whether the read physical page is in an erased state depending on an indication provided by the result of reading the data. Therefore, the additional processing is carried out only when the read physical page is in an erasing state, and the average processing delay of the read command is reduced.

Fig. 9B is a flow diagram of accessing FTL table for processing IO commands according to still another embodiment of the present application. The embodiment of fig. 9B is similar to the embodiment of fig. 9A, except that when data is read from the first physical address, and it is determined whether the physical page corresponding to the first address is in an erased state in the result of reading the data (980), if the result of reading the data indicates that the physical page corresponding to the first physical address is in an erased state, the corresponding physical block or block stripe is obtained according to the first physical address, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5A, 540) or the block stripe state table (see fig. 7, 740) (990). If the physical block or block stripe in which the first physical address is located is in a written state (990), then the result of reading data from the first physical address indicates that the physical page is in an erased state regardless of whether the first FTL entry is locked, but that the data stored at the first physical address is corrupted, indicating a failed read command processing as a response to the read command (995). If the physical block or block stripe where the first physical address is located is in an erased state (990), return to step 950 to replay the read command. If the data is read from the first physical address and the result of reading the data indicates that the physical page corresponding to the first physical address is not in an erased state (980), the read data is used as a response to the read command and the read command processing is completed (985).

Still referring to fig. 9B, in another example, when data is read from the first physical address for the first time through step 980 and it is determined that the physical page corresponding to the first address is in an erased state in the result of reading the data (980), the read command is directly replayed as indicated by a dotted line in fig. 9B. When the same read command is replayed and step 980 is passed for the second time, if it is determined again that the physical page corresponding to the first address is in the erased state in the result of reading the data (980), the process proceeds to step 990, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5A and 540) or the block stripe state table (see fig. 7 and 740).

In the embodiment of fig. 9B, when the read physical page is a physical page in an erased state, a different processing strategy is adopted to obtain better error processing efficiency.

Fig. 9C is a flow diagram of accessing FTL table for processing IO commands according to still another embodiment of the present application. The embodiment of FIG. 9B is similar to the embodiment of FIG. 9C, except that when data is read from the first physical address, and it is determined (980) whether the physical page corresponding to the first address is in an erased state, it is queried (992) whether the first FTL entry is locked. If the first FTL entry is not locked (992), the result of reading data from the first physical address indicates that the physical page is in an erased state regardless of whether the first FTL entry is locked, but that the data stored at the first physical address is corrupted, indicating a read command processing failure as a response to the read command (995). If the first FTL entry is locked (992), the data reading result from the first physical address indicates that the physical page is in the erase state and is related to the first FTL entry being locked, waits for the lock of the first FTL entry to be released, acquires the first FTL entry again and obtains the updated second physical address provided by the first FTL (994). And issuing an access command to the NVM at the second physical address, reading data (996) from the second physical address of the NVM in response to the read command.

Still referring to fig. 9C, in another example, when the data is read from the first physical address for the first time after step 980 is passed, and it is determined that the physical page corresponding to the first address is in the erased state in the result of reading the data (980), the process returns to step 950 to directly replay the read command, as indicated by the dotted line in fig. 9C. If the same read command passes through step 980 for the second time due to being replayed, if it is determined again that the physical page corresponding to the first address is in the erased state in the result of reading the data (980), the process proceeds to step 992, and it is queried whether the first FTL entry is locked, and the subsequent processing is performed.

In the embodiment of fig. 9C, when the read physical page is a physical page in an erased state, a different processing strategy is adopted to obtain better error processing efficiency.

Embodiments of the present application also provide a program comprising program code which, when loaded into a CPU and executed therein, causes the CPU to perform one of the methods provided above in accordance with embodiments of the present application.

Embodiments of the present application also provide a program comprising program code, which, when loaded into a storage device and executed thereon, causes a processor of the storage device to perform one of the methods according to embodiments of the present application as provided above.

It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions may be loaded onto a general purpose computer, special purpose computer, or other programmable data control apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data control apparatus create means for implementing the functions specified in the flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data control apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the function specified in the flowchart block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data control apparatus to cause a series of operational operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart block or blocks.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of operations for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Although the present invention has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the application, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the application.

Many modifications and other embodiments of the application set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the application is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A method of processing an IO request, comprising:

responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry;

if the physical block or the block stripe containing the first physical address is in an erasing state, replaying the first read request;

and acquiring the first physical address recorded by the first FTL table entry even if the first FTL table entry is locked.

2. A method of processing an IO request, comprising: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; responding to a received read request, accessing a first FTL table entry corresponding to the read request, and if a physical block containing a first physical address is in an erasing state, replaying the first read request; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

3. The method of claim 2, further comprising: and responding to the received read request, accessing a first FTL table entry corresponding to the read request, and reading data from a first physical address to respond to the first read request if a first physical block containing the first physical address is in a written state.

4. The method of claim 2 or 3, wherein while processing the write request, if the first FTL entry is locked, processing of the write request is suspended until the lock of the first FTL entry is released.

5. The method of any of claims 2-4, wherein after the lock on the first FTL entry is released, the first FTL entry is obtained and locked.

6. The method of claim 2 or 3, wherein when processing a write request, if the first FTL entry is locked, the processing of the write request is ended.

7. A method of processing an IO request, comprising:

reading data from a first physical address;

if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is in an erasing state, replaying the first read request;

responding to replay of the first read request, and if a result of reading data from the first physical address indicates that a physical page where the first physical address is located is still in an erasing state, indicating that the first read request operation fails; or responding to replay the first read request, if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is still in an erasing state, and if the physical block containing the first physical address is in the erasing state, replaying the first read request.

8. The method of claim 7, further comprising: in response to replaying the first read request, if a result of reading data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, if a first physical block containing the first physical address is in a written state, reading data from the first physical address in response to the first read request; or

And responding to the replay of the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erasing state, and if the large block containing the first physical address is in the erasing state, replaying the first read request.

9. The method of claim 8, further comprising: in response to replaying the first read request, if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, if the large block containing the first physical address is in a written state, reading data from the first physical address in response to the first read request.

10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to one of claims 1 to 9.