JP2010128604A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory access for efficiently processing data by switching a priority synchronized with a job, even when switching the priority in response to a processing content of a bus master and when a priority-switching grain size is fine. <P>SOLUTION: An access queue 1014 holds the plurality of received accesses, decodes an accessed descriptor, in case of the access to a descriptor area, and holds a data area indicated by the descriptor. The priority of the access to the area indicated by the descriptor is determined based on the access to the descriptor, and the determined priority is held in pairs with the data area. A data area determination circuit 1013 determines whether the access from the data master is corresponds to the held data area or not, and the access queue 1014 changes an order of the held accesses in response to the priority paired with the data area, when the access corresponds to the data area. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory system.

  Conventionally, in a memory system, a priority is determined by a bus master that performs memory access via a memory controller, a bus interface, and an address area.

Hereinafter, an example in which the priority is determined by the bus master will be described.
The memory controller holds priority information for each bus master, and a master identifier is added to access from the bus master. When the bus master accesses the memory controller, the memory controller identifies the bus master from the master identifier added to the access, determines the priority of the access, and registers the access in the access queue. The memory controller changes the access order in the access queue according to the access priority, and changes the access issue order to the memory device.

Next, an example in which the priority is determined by the bus interface will be described.
The memory controller holds priority information of each bus interface, and when accessing from the bus interface, the memory controller determines the priority of the access depending on which bus interface is accessed, and registers the access in an access queue. . The memory controller changes the access order in the access queue according to the access priority, and changes the access issue order to the memory device.

Next, an example in which the priority is determined by the address area is shown.
The memory controller holds priority information for access to each address area specified. When accessing from the bus master or the bus interface, the access priority is determined from the accessed address area, and the access is registered in the access queue. The memory controller changes the access order in the access queue according to the access priority, and changes the access issue order to the memory device.

JP 07-129500 A Japanese Patent Application Laid-Open No. 2000-20442

  However, when giving priority to each bus master, one bus master may process a plurality of jobs. When the bus master processes a job with a high priority and a job with a low priority, if the priority of the bus master is increased, a job with a lower priority is also processed with priority.

  Also, if the priority of the bus master is lowered, there is a problem that jobs with higher priority are not processed preferentially. When a priority is given to each bus interface, one bus interface is accessed from a plurality of bus masters, and the priority of the access may be different. When the priority of the bus interface is increased, a job with a low priority for accessing the bus interface is also processed with priority. When the priority of the bus interface is lowered, there is a problem that a job having a high priority for accessing the bus interface is not preferentially processed.

  In addition, when giving priority to each address area, jobs having different priorities may refer to the same address area. If the priority of the address area is increased, a job with a lower priority is also processed preferentially. If the priority of the address area is decreased, a job with a higher priority is not processed preferentially.

  In addition, although it is possible to change the priority for each job by software, when the granularity of priority switching is fine, overhead at the time of setting occurs. Therefore, it is difficult to switch the priority in synchronization with the job, and there is a problem that memory access for efficiently performing data processing cannot be realized.

  The memory system according to the present invention includes a bus master for fetching data, a memory controller, and a memory device connected to the memory controller, and specifies data used by the bus master and a data area on the memory space on the memory space. In the memory system that holds the descriptor to be accessed, the means for holding the received plurality of accesses, the means for determining access to the descriptor area from the bus master, and the access to the descriptor area if the access is to the descriptor area Means for decoding and holding the data area indicated by the descriptor; means for determining the priority of access from the access to the descriptor to the area indicated by the descriptor; and means for holding the determined priority in pairs with the data area Or bus master Means for determining whether or not the access corresponds to the data area held, and if the access corresponds to the data area, the order of the access held according to the priority of the data area and the pair And means for changing.

  According to the present invention, the priority can be switched according to the processing contents of the bus master, and even when the priority switching granularity is fine, switching the priority synchronized with the job is efficient. In addition, memory access for data processing can be realized.

<First Embodiment>
FIG. 1 is a configuration diagram illustrating a first embodiment of a memory system according to the present invention. In FIG. 1, reference numeral 101 denotes a memory controller. Reference numeral 102 denotes a memory device. Reference numeral 103 denotes a bus. The bus 103 arbitrates access from a plurality of bus masters and controls access to the memory controller 101.

  104 and 105 are bus masters. The bus masters 104 and 105 are connected to the bus 103 and issue access to the memory device 102. The bus masters 104 and 105 identify a data area on the memory space to be accessed by referring to the descriptor, and perform data fetch.

  Reference numeral 1011 denotes a descriptor area list. The descriptor area list 1011 holds addresses or address areas of a plurality of descriptors of the memory device 102.

  Reference numeral 1012 denotes an address discrimination circuit. When receiving an access from the bus masters 104 and 105, the address determination circuit 1012 determines whether or not the access address is a descriptor area. If it is a descriptor area, a flag indicating that the access is to the descriptor area is added and registered in the access queue 1014. If it is not a descriptor area, the access is transmitted to the data area determination circuit 1013.

  Reference numeral 1013 denotes a data area discrimination circuit. The data area determination circuit 1013 determines whether the access address received from the bus masters 104 and 105 is an address registered in the descriptor information registration list 1017. If it is a registered address, the priority of the corresponding address area is added to the access and registered in the access queue 1014. If the address is not registered, it is registered in the access queue 1014 without adding information to the access.

  Reference numeral 1014 denotes an access queue. The access queue 1014 is a queue that can hold a plurality of accesses from the bus masters 104 and 105. Further, the order of accesses to be transmitted to the command control circuit 1015 is changed according to the access priority.

  Reference numeral 1015 denotes a command control circuit. The command control circuit 1015 receives an access from the access queue 1014, converts it into a memory access command, and issues the command to the memory device 102. Further, the command control circuit 1015 determines whether or not a flag for accessing the descriptor area is added to the access from the access queue 1014. When the flag is added, the descriptor read from the memory device 102 is transmitted to the descriptor decoding circuit 1016.

  Reference numeral 1016 denotes a descriptor decoding circuit. The descriptor decoding circuit 1016 decodes the descriptor, reads the data area and priority indicated by the descriptor, and transmits them to the descriptor information registration list.

  Reference numeral 1017 denotes a descriptor information registration list. The descriptor information registration list 1017 holds a decoded descriptor data area and priority as a pair. Reference numeral 1018 denotes a return queue. The return queue 1018 holds read data and transmits the read data to the bus 103 at a timing at which the read data can be transmitted.

  Reference numeral 1021 denotes a descriptor. In the descriptor 1021, information indicating (specifying) the data area 1023 and priority information are set. Reference numeral 1022 denotes a descriptor. In the descriptor 1022, information indicating the data area 1024 and priority information are set. Reference numeral 1023 denotes a data area. In the data area 1023, data necessary for a job to be processed by the bus master accessing the descriptor 1021, in other words, data to be used is written. Reference numeral 1024 denotes a data area. In the data area 1024, data necessary for a job to be processed by the bus master accessing the descriptor 1022, in other words, data to be used is written.

  Next, the operation of the memory system in the first embodiment of the present invention will be described below. As shown in FIG. 2, it is assumed that the address of the descriptor 1021 is “0x0000010” and the address of the descriptor 1022 is “0x0000014”. Further, it is assumed that the address area 1023 pointed to by the descriptor 1021 is “0x00000100” to “0x00000200”, and the address area 1024 pointed to by the descriptor 1022 is “0x00000200” to “0x00000300”. Further, it is assumed that the priority set for the descriptor 1021 is “L” and the priority set for the descriptor 1022 is “H”. It is assumed that the priority is “H” higher than “L”. Here, it is assumed that all accesses are performed in units of words.

  In the descriptor area list 1011 of the memory controller 101, “0x00000010” and “0x00000014” are registered as descriptor address lists. In the descriptor area list 1011, address areas “0x00000010” to “0x00000014” may be registered.

  The bus master 104 reads the descriptor 1021 and fetches data from the data area 1023 indicated by the descriptor 1021. Assume that the bus master 105 is set to read the descriptor 1022 and fetch data from the data area 1024 indicated by the descriptor 1022.

  First, the bus master 104 issues an access for reading the descriptor 1021 (reading the address “0x00000010”). The address discrimination circuit 1012 discriminates whether or not the received access address is registered in the descriptor area list 1011. Since the address “0x00000010” is registered in the descriptor area list 1011, the address determination circuit 1012 adds a flag indicating that the access is to the descriptor area and registers it in the access queue 1014.

  The contents of the access queue 1014 are as shown in FIG. The command control circuit 1015 receives the access from the access queue 1014, issues a read command for the address “0x00000010” to the memory device 102, and reads the descriptor 1021. Since a flag indicating access to the descriptor area is added to the access, the command control circuit 1015 registers the read data in the return queue 1018 and transmits it to the descriptor decoding circuit 1016 at the same time.

  The descriptor decode circuit 1016 decodes the descriptor 1021, reads the data area (0x00000100 to 0x00000200) and priority (“L”) indicated by the descriptor 1021, and registers them in the descriptor information registration list 1017. The descriptor information registration list 1017 is as shown in FIG.

  The return queue 1018 transmits read data (descriptor 1021) to the bus master 104. The bus master 104 reads the data area (0x00000100 to 0x00000200) to be accessed from the descriptor 1021, and issues access for reading data from the data area in order. Although the data access order in the data area is arbitrary, in this embodiment, the bus master 104 issues 0x00000100, 0x00000104, 0x00000108,..., 0x000001FC in this order.

  When an access for reading data from the data area is issued from the bus master 104, the address determination circuit 1012 does not register the access address in the descriptor area list 1011. Therefore, the access is transmitted to the data area discrimination circuit 1013.

  The data area determination circuit 1013 determines whether or not the access is for a data area registered in the descriptor information registration list 1017. Since the address area corresponding to the access address is registered in the descriptor information registration list 1017, the priority registered in pairs with the address area is added to the access and registered in the access queue 1014.

  The contents of the access queue 1014 are as shown in FIG. When the bus master 104 accesses the data area a plurality of times, the access queue 1014 becomes as shown in FIG. In FIG. 3C, the first registered several accesses have already been processed.

  Next, the bus master 105 issues an access for reading the descriptor 1022 (reading the address “0x00000014”). The address discrimination circuit 1012 discriminates whether or not the received access address is registered in the descriptor area list 1011. Since the address “0x00000014” is registered in the descriptor area list 1011, the address determination circuit 1012 adds a flag indicating that the access is to the descriptor area and registers it in the access queue 1014. The contents of the access queue 1014 are as shown in FIG.

  The command control circuit 1015 receives the access from the access queue 1014, issues a read command for the address “0x00000014” to the memory device 102, and reads the descriptor 1022. Since a flag indicating access to the descriptor area is added to the access, the command control circuit 1015 registers the read data in the return queue 1018 and transmits it to the descriptor decoding circuit 1016 at the same time.

  The descriptor decode circuit 1016 decodes the descriptor 1022, reads the data area (0x00000200 to 0x00000300) and priority (“H”) indicated by the descriptor 1022, and registers them in the descriptor information registration list 1017. The descriptor information registration list 1017 is as shown in FIG.

  The return queue 1018 transmits read data (descriptor 1022) to the bus master 105. The bus master 105 reads the data area (0x00000200 to 0x00000300) to be accessed from the descriptor 1022, and issues access for reading data from the data area in order. In this embodiment, the bus master 105 issues 0x00000200, 0x00000204, 0x00000208, ..., 0x000002FC in this order.

  When an access for reading data from the data area is issued from the bus master 105, the address determination circuit 1012 does not register the access address in the descriptor area list 1011. Therefore, the access is transmitted to the data area discrimination circuit 1013.

  The data area determination circuit 1013 determines whether or not the access is for a data area registered in the descriptor information registration list 1017. Since the address area corresponding to the access address is registered in the descriptor information registration list 1017, the priority registered in pairs with the address area is added to the access and registered in the access queue 1014. The contents of the access queue 1014 are as shown in FIG.

  At this time, since the access has a higher priority than the previously registered access, it is rearranged so as to overtake the previously registered access so as to be issued to the command control circuit 1015 preferentially.

  When the bus master 105 accesses the data area a plurality of times, the access issued by the bus master 105 is issued to the command control circuit 1015 preferentially over the access issued by the bus master 104, so that the access queue 1014 is shown in FIG. It becomes like this.

  As described above, since the priority is set for the descriptor, the priority of the access to the area indicated by the descriptor can be determined when the descriptor is accessed, and the processing with the higher priority can be performed. Processing can be performed with priority over low processing.

  Further, if the same bus master accesses different descriptors and different priorities are set for the different descriptors, it is possible to switch the processing priorities even for the same bus master. For example, the bus master 104 reads the descriptor 1021, reads data from the data area 1023 indicated by the descriptor 1021, and executes the job.

  Next, the descriptor 1022 is read, data is read from the data area 1024 pointed to by the descriptor 1022, and the job is executed. If the priority is determined from the decoding results of the descriptor 1021 and the descriptor 1022 and the priority set in the descriptor 1021 descriptor 1022 is different, the priority is switched for each process even for the same bus master.

  Moreover, the priority is switched for each process even in the same bus interface as in the present embodiment. Furthermore, even if the access is in the same data area, different priorities are set for different descriptors, and if the different descriptors point to the same data area, the processing priorities can be switched.

  For example, if the descriptor 1021 and the descriptor 1022 indicate the same data area 1023, the bus master 104 and the bus master 105 read data from the same data area 1023 and execute the job. If the priorities set in the descriptor 1021 and the descriptor 1022 are different, the priorities are switched for each process even when accessing the same data area.

<Second Embodiment>
FIG. 5 is a block diagram showing a second embodiment of the memory system of the present invention. In FIG. 5, reference numeral 101 denotes a memory controller. Reference numeral 102 denotes a memory device. Reference numeral 103 denotes a bus. The bus 103 arbitrates access from a plurality of bus masters and controls access to the memory controller 101.

  104 and 105 are bus masters. The bus masters 104 and 105 are connected to the bus 103 and issue access to the memory device 102. The bus masters 104 and 105 identify the data area to be accessed by referring to the descriptor, and perform data fetch.

  Reference numeral 1011 denotes a descriptor address list. The descriptor address list 1101 holds addresses or address areas of a plurality of descriptors of the memory device 102.

  Reference numeral 1102 denotes a descriptor priority list. The descriptor priority list 1201 holds the priority for each address in the descriptor address list 1101.

  Reference numeral 1012 denotes an address discrimination circuit. When receiving an access from the bus masters 104 and 105, the address determination circuit 1012 determines whether or not the access address is a descriptor area.

  If it is a descriptor area, a flag indicating that the access is to the descriptor area is added and registered in the access queue 1014. If it is not a descriptor area, the access is transmitted to the data area determination circuit 1013.

  Reference numeral 1013 denotes a data area discrimination circuit. The data area determination circuit 1013 determines whether the access address received from the bus masters 104 and 105 is an address registered in the descriptor information registration list 1017. If it is a registered address, the priority of the corresponding address area is added to the access and registered in the access queue 1014. If the address is not registered, it is registered in the access queue 1014 without adding information to the access.

  Reference numeral 1014 denotes an access queue. The access queue 1014 is a queue that can hold a plurality of accesses from the bus masters 104 and 105. Further, the order of accesses to be transmitted to the command control circuit 1015 is changed according to the access priority.

  Reference numeral 1015 denotes a command control circuit. The command control circuit 1015 receives an access from the access queue 1014, converts it into a memory access command, and issues the command to the memory device 102. Further, the command control circuit 1015 determines whether or not a flag for accessing the descriptor area is added to the access from the access queue 1014. When the flag is added, the descriptor read from the memory device 102 is transmitted to the descriptor decoding circuit 1016.

  Reference numeral 1016 denotes a descriptor decoding circuit. The descriptor decoding circuit 1016 decodes the descriptor, reads the data area and priority indicated by the descriptor, and transmits them to the descriptor information registration list.

  Reference numeral 1017 denotes a descriptor information registration list. The descriptor information registration list holds a decoded data area and priority in pairs. Reference numeral 1018 denotes a return queue. The return queue 1018 holds read data and transmits the read data to the bus 103 at a timing at which the read data can be transmitted.

  Reference numeral 1121 denotes a descriptor. In the descriptor 1121, information indicating the data area 1023 is set. 1122 is a descriptor. In the descriptor 1122, information indicating the data area 1024 is set. Reference numeral 1023 denotes a data area. In the data area 1023, data necessary for a job to be processed by the bus master accessing the descriptor 1121 is written. Reference numeral 1024 denotes a data area. In the data area 1024, data necessary for a job to be processed by the bus master accessing the descriptor 1122 is written.

  Next, the operation of the memory system according to the second embodiment of the present invention will be described below. As shown in FIG. 2, it is assumed that the address of the descriptor 1121 is “0x0000010” and the address of the descriptor 1122 is “0x0000014”. Further, it is assumed that the address area 1023 pointed to by the descriptor 1121 is “0x00000100” to “0x00000200”, and the address area 1024 pointed to by the descriptor 1122 is “0x00000200” to “0x00000300”. Here, it is assumed that all accesses are performed in units of words.

  In the descriptor address list 1101 of the memory controller 101, 0x00000010 and 0x00000020 are registered as descriptor address lists. In the descriptor address list 1101, address areas 0x00000010 to 0x0000001C and 0x00000020 to 0x0000002C may be registered. In the descriptor priority list 1201, a priority “L” is registered for the address “0x00000010”, and a priority “H” is registered for the address “0x00000020”.

  The bus master 104 reads the descriptor 1121 and fetches data from the data area 1023 indicated by the descriptor 1121. Assume that the bus master 105 is set to read the descriptor 1122 and fetch data from the data area 1024 indicated by the descriptor 1122.

  First, the bus master 104 issues an access for reading the descriptor 1121 (reading the address “0x00000010”). The address determination circuit 1012 determines whether the received access address is registered in the descriptor address list 1101. Since the address “0x00000010” is registered in the descriptor address list 1101, the address determination circuit 1012 adds a flag indicating that the access is an access to the descriptor and registers it in the access queue 1014.

  The contents of the access queue 1014 are as shown in FIG. At this time, the priority “L” corresponding to the address “0x00000010” is registered in the descriptor information registration list 1017 from the descriptor priority list 1201.

  The command control circuit 1015 receives the access from the access queue 1014, issues a read command for the address “0x00000010” to the memory device 102, and reads the descriptor 1121. Since a flag indicating access to the descriptor area is added to the access, the command control circuit 1015 registers the read data in the return queue 1018 and transmits it to the descriptor decoding circuit 1016 at the same time.

  The descriptor decoding circuit 1016 decodes the descriptor 1121, reads the data area (0x00000100 to 0x00000200) indicated by the descriptor 1121, and registers it in the descriptor information registration list 1017. The descriptor information registration list 1017 is as shown in FIG.

  The return queue 1018 transmits read data (descriptor 1121) to the bus master 104. The bus master 104 reads the data area (0x00000100 to 0x00000200) to be accessed from the descriptor 1121, and issues access for reading data from the data area in order. Although the data access order in the data area is arbitrary, in this embodiment, the bus master 104 issues 0x00000100, 0x00000104, 0x00000108,..., 0x000001FC in this order.

  When an access for reading data from the data area is issued from the bus master 104, the address determination circuit 1012 does not register the access address in the descriptor address list 1101. Therefore, the access is transmitted to the data area discrimination circuit 1013.

  The data area determination circuit 1013 determines whether or not the access is for a data area registered in the descriptor information registration list 1017. Since the address area corresponding to the access address is registered in the descriptor information registration list 1017, the priority registered in pairs with the address area is added to the access and registered in the access queue 1014.

  The contents of the access queue 1014 are as shown in FIG. When the bus master 104 accesses the data area a plurality of times, the access queue 1014 becomes as shown in FIG. In FIG. 3C, the first registered several accesses have already been processed.

  Next, the bus master 105 issues an access for reading the descriptor 1122 (reading the address “0x00000020”). The address determination circuit 1012 determines whether the received access address is registered in the descriptor address list 1101. Since the address “0x00000020” is registered in the descriptor address list 1101, the address determination circuit 1012 adds a flag indicating that the access is an access to the descriptor area and registers it in the access queue 1014.

  The contents of the access queue 1014 are as shown in FIG. At this time, the priority “H” corresponding to the address “0x00000020” from the descriptor priority list 1201 is registered in the descriptor information registration list 1017.

  The command control circuit 1015 receives the access from the access queue 1014, issues a read command for the address “0x00000020” to the memory device 102, and reads the descriptor 1122. Since a flag indicating access to the descriptor area is added to the access, the command control circuit 1015 registers the read data in the return queue 1018 and transmits it to the descriptor decoding circuit 1016 at the same time.

  The descriptor decoding circuit 1016 decodes the descriptor 1122, reads the data area (0x00000200 to 0x00000300) pointed to by the descriptor 1122, and registers it in the descriptor information registration list 1017. The descriptor information registration list 1017 is as shown in FIG.

  The return queue 1018 transmits read data (descriptor 1122) to the bus master 105. The bus master 105 reads the data area (0x00000200 to 0x00000300) to be accessed from the descriptor 1022, and issues access for reading data from the data area in order. In this embodiment, the bus master 105 issues 0x00000200, 0x00000204, 0x00000208, ..., 0x000002FC in this order.

  When an access for reading data from the data area is issued from the bus master 105, the address determination circuit 1012 does not register the access address in the descriptor area list 1011. Therefore, the access is transmitted to the data area discrimination circuit 1013.

  The data area determination circuit 1013 determines whether or not the access is for a data area registered in the descriptor information registration list 1017. Since the address area corresponding to the access address is registered in the descriptor information registration list 1017, the priority registered in pairs with the address area is added to the access and registered in the access queue 1014. The contents of the access queue 1014 are as shown in FIG. At this time, since the access has a higher priority than the previously registered access, it is rearranged so as to overtake the previously registered access so as to be issued to the command control circuit 1015 preferentially.

  When the bus master 105 accesses the data area a plurality of times, the access issued by the bus master 105 is issued to the command control circuit 1015 preferentially over the access issued by the bus master 104, so that the access queue 1014 is shown in FIG. It becomes like this.

  As described above, when a descriptor is accessed, the priority of access to the area indicated by the descriptor can be determined, and processing with higher priority can be processed with priority over processing with lower priority. . If the same bus master accesses different descriptors and different priorities are set for the addresses of the different descriptors, it is possible to switch processing priorities even for the same bus master.

  For example, the bus master 104 reads the descriptor 1121, reads data from the data area 1023 indicated by the descriptor 1121, and executes the job.

  Next, the descriptor 1122 is read, data is read from the data area 1024 indicated by the descriptor 1122, and the job is executed. If the priority is determined from the addresses of the descriptor 1121 and the descriptor 1122, and the priority set for the address of the descriptor 1121 and the address of the descriptor 1122 is different, the priority is switched for each process even for the same bus master. .

  Moreover, the priority is switched for each process even in the same bus interface as in the present embodiment. Furthermore, even if the access is in the same data area, different priorities are set for the addresses of different descriptors. If the different descriptors point to the same data area, it is possible to switch the processing priority. is there.

  For example, if the descriptor 1121 and the descriptor 1122 point to the same data area 1023, the bus master 104 and the bus master 105 read data from the same data area 1023 and execute the job. However, if the priority set for the address of the descriptor 1121 and the address of the descriptor 1122 are different, the priority is switched for each process even when accessing the same data area.

It is a block diagram showing 1st Embodiment of the memory system of this invention. It is a figure showing the address of the memory device in 1st, 2nd embodiment of the memory system of this invention. It is a figure showing the content of the access queue in 1st, 2nd embodiment of the memory system of this invention. It is a figure showing the descriptor information registration content in the 1st, 2nd embodiment of the memory system of this invention. It is a block diagram showing 2nd Embodiment of the memory system of this invention.

Explanation of symbols

101 memory controller 102 memory device 103 bus 104, 105 bus master 1011 descriptor area list 1012 address discrimination circuit 1013 data area discrimination circuit 1014 access queue 1015 command control circuit 1016 descriptor decode circuit 1017 descriptor information registration circuit 1018 return queue 1021, 1022, 1121, 1122 Descriptor 1023, 1024 Data area 1101 Descriptor address list 1201 Descriptor priority list

Claims (3)

A memory that includes a bus master that performs data fetch, a memory controller, and a memory device that is connected to the memory controller, and that holds data used by the bus master in the memory space and a descriptor that specifies a data area in the memory space In the system,
Means for holding multiple received accesses;
Means for determining access to the descriptor area from the bus master;
If the access is to the descriptor area, means for decoding the accessed descriptor and holding the data area indicated by the descriptor;
Means for determining the priority of access to the area indicated by the descriptor from access to the descriptor;
Means for holding the determined priority in pairs with the data area;
Means for determining whether the access from the bus master corresponds to the held data area;
A memory system comprising: means for changing the order of accesses held in accordance with the priority of a pair with the data area when the access corresponds to a data area.   In the memory controller, as a means for determining the priority of access from the access to the descriptor to the area indicated by the descriptor, the priority is set for the descriptor, the descriptor is decoded, and the access to the data area indicated by the descriptor is performed. The memory system according to claim 1, wherein the priority is determined.   In the memory controller, as a means for determining the priority of access from the descriptor access to the area indicated by the descriptor, priority is set for each address of the descriptor, and the descriptor indicates by the address of access to the descriptor. 2. The memory system according to claim 1, wherein a priority of access to the data area is determined.

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