JP2010114834A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the flicker detection time, and to shorten the exposure time, by simplifying a configuration by making common a read line for flicker detection and a read line for display and increasing the frame rate of flicker detection. <P>SOLUTION: During a pixel read state in displaying recording image data onto an LCD display section 13, prior to photographing by a CMOS image sensor 10, the exposure time and the read time to flicker detection pixel blocks F00, ..., F11 in the CMOS image sensor 10 is set to the reciprocal of an integral multiple of the exposure time and the read time for displaying pixels D00, ..., D11. At the same time, stored charges read from the display pixels D00, ..., D11 and stored charges for flicker read from the flicker detection pixel blocks F00, ..., F11 are alternately output to one output read line W, in a time division manner. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention makes it possible to reduce the time required to detect the flicker frequency due to the influence of illumination light while displaying a live view of a captured image, particularly when shooting a subject in an illumination environment having a low lighting frequency. The present invention relates to an imaging apparatus.

  In general, an imaging apparatus such as a digital camera has an optical or electronic viewfinder function to adjust the angle of view of a captured image. Of these, the electronic viewfinder also includes a liquid crystal display for displaying live view images. In such an image pickup apparatus, an object is photographed and the photographed image is displayed as a live view, and automatic focus (AF), automatic exposure (AE), and automatic white balance (AWB) are used using image data of the live view. The detection for the control is performed.

  Such an imaging apparatus sometimes performs imaging in an illumination environment such as a fluorescent lamp that generates a low lighting frequency under the influence of a power supply frequency. In photographing under such an environment, it is generally known that an imaging device generates a blinking phenomenon called flicker. The imaging device includes an imaging device including a CCD that converts a light image from a subject into an electrical signal. For the readout to the image sensor, for example, the start and end of pixel exposure called a global shutter are the same regardless of the position of each pixel, and the readout to the image sensor is the start and end of pixel exposure called a rolling shutter, for example. There is a system in which is sequentially shifted at the pixel position. In the case of the global shutter method, flicker is observed as a blinking phenomenon in which the luminance level of each frame in the captured image varies. In the case of the rolling shutter system, it is observed as exposure unevenness in one frame of a photographed image.

Such an imaging apparatus sets exposure conditions that are not affected by flicker, but prior to this, it is necessary to detect the lighting frequency or flicker frequency of illumination. When the detection time of these lighting frequency or flicker frequency becomes long, the shutter lag time is extended, and a photo opportunity may be missed.
It is obvious from sampling theory that it is necessary to increase the exposure frame rate of the image sensor in order to complete the detection of the lighting frequency or flicker frequency in a short time. Further, the display image of the live view is required to have a small flicker component and not stand out. However, since the display image of the live view is generally acquired by photographing with a relatively long exposure, it takes time to detect the flicker frequency accordingly.

  If flicker components are included in image data to be detected for AF, AE, AWB, etc., such as live view image data, AF, AE, AWB, etc. are accurately controlled. Disappear. For example, in the AF control, if the luminance peak of the image data is erroneously detected due to the influence of the flicker component, the subject is not focused, that is, a false in-focus state (blur). For this reason, for example, reducing the influence of flicker on the detection target image information such as image data of live view, and eliminating the image quality deterioration of the captured image due to the influence of the flicker becomes a fundamental problem.

For example, Patent Document 1 (Patent No. 3826904: Japanese Patent Application Laid-Open No. 2005-33616), Patent Document 2 (Japanese Patent Application Laid-Open No. 2007-206606), and Patent Document 3 (Japanese Patent Application Laid-Open No. 2006-287361) have been taken as countermeasures against flicker. Gazette).
Japanese Patent Application Laid-Open No. H10-228561 discloses that flicker components are reduced by a combination of an imaging frame rate and an electronic shutter value. However, the imaging frame rate cannot be used in combinations other than 120/60/30 fps, and it takes time to detect the power supply frequency. In the meantime, the camera operator is aware of the flicker of the display image.
Patent Document 2 uses a high-speed imaging frame rate. When flicker frequency is checked before AF control and flicker is detected, the imaging frame rate is set to n times the flicker frequency L, and AF evaluation is performed from a plurality of images. It is disclosed that the value is calculated and sampling for contrast AF control is performed at a cycle shorter than the flicker frequency. This speeds up the imager AF and reduces the flicker component. However, since it takes time to recognize the power supply frequency 50/60 Hz, the operator of the camera feels flicker in the display image during that time. Actually, if exposure is performed for a short time in order to increase the sampling frequency, the image quality of the display image is degraded due to the sensitivity limit of the image sensor.

In the above Patent Documents 1 and 2, the following problems are not solved. First, since the exposure and readout conditions for flicker detection are determined by the exposure and readout conditions when the live view image is displayed on the electronic viewfinder, it is not possible to sufficiently speed up the flicker detection alone.
Secondly, to reduce the flicker component contained in the live view image displayed on the electronic viewfinder and to reduce the noise level that the live view image displayed on the electronic viewfinder can withstand. Since a sufficient exposure time is required, the exposure frame rate cannot actually be sufficiently increased.

  By the way, it is a known technique to perform sampling by increasing the imaging frame rate to be higher than the flicker frequency, detect a luminance peak in a plurality of captured image data, and detect the flicker frequency from these peaks. In order not to acquire captured image data including a flicker component, when acquiring captured image data by imaging with an image sensor, the shutter speed is appropriately selected from the detection result of the luminance peak of the captured image data. Yes. In order to shorten the flicker detection time, it is basically necessary to increase the sampling frequency by increasing the shutter speed and reading the image at a high frame rate.

  As another technique for detecting the flicker frequency, for example, there is a technique for performing normalization of luminance distribution of one screen, comparison between screens, and frequency analysis. However, the detection of the flicker frequency requires time until a plurality of frames of the display system are acquired, and thus cannot be said to be sufficiently fast, and flicker is observed within the flicker frequency detection period.

  When flicker components are detected from information of a live view image for display on an electronic viewfinder, if the frame frequency is increased, the flicker becomes more conspicuous in the live view image displayed on the viewfinder. However, when the frame frequency is increased, the detection time can be shortened and the accuracy can be improved, but there is a contradiction that it is not preferable for the observer.

For example, Patent Document 3 solves this contradiction. This Patent Document 3 improves detection accuracy by making a finder display system and a flicker detection system independent, and a vertical structure in which pixels that are not used in the finder display system are made independent and read out asynchronously is easy to detect. It is disclosed that detection accuracy is improved by driving at a frequency. Specifically, Patent Document 3 displays a video based on a display video signal output from a first pixel circuit group of an XY addressing type image sensor on a display device, while the first pixel circuit group and the second pixel circuit. A digital camera for recording image data based on a recording video signal output from a group on a recording device, wherein the first vertical synchronizing signal and the second pixel circuit when the first pixel circuit group outputs a display video signal A first vertical scanning circuit and a second pixel circuit that are asynchronous with a second vertical synchronization signal when the group outputs a flicker detection video signal and that control the output of the display video signal from the first pixel circuit group It discloses that it has a horizontal scanning circuit for outputting each video signal outputted from each different output terminal with the second vertical scanning circuit for controlling the output of the video signal for flicker detection from the group.
Japanese Patent No. 3826904 JP 2007-206606 A JP 2006-287361 A

  However, in Patent Document 3, the readout lines for the finder display system and the flicker detection system are secured by separate systems, that is, the display video signal output terminal and the flicker detection video signal output terminal are provided separately. Yes. For this reason, Patent Document 3 causes a wasteful increase in size and causes a dull movement of camera shake correction by the image sensor shift method.

  The object of the present invention is to simplify the configuration by making the readout line for flicker detection and the display readout line the same, increase the flicker detection frame rate to shorten the flicker detection time, and shorten the exposure time. An object of the present invention is to provide an imaging device capable of performing the above.

  An imaging device that performs imaging control based on a captured image while displaying the captured image according to the main aspect of the present invention, the display pixels of the captured image arranged at predetermined intervals, An image sensor having a pixel block for flicker detection composed of a plurality of pixels for detecting a flicker frequency separately from the display pixels, display information read from the display pixels, and read from the flicker detection pixel block The frame rate for reading out the flicker detection pixel block is independently controlled by the readout line for outputting the information for flicker on the same line and the exposure control for the display pixel and the exposure control for the flicker detection pixel block. And a control means for controlling the display pixel to be higher than the readout frame rate for the display pixels. To.

  According to the present invention, the flicker detection readout line and the display readout line are made the same to simplify the configuration, and the flicker detection frame rate is increased to shorten the flicker detection time, and the exposure time is shortened. An imaging device that can be provided can be provided.

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a system block diagram of an imaging apparatus such as a digital camera. The imaging apparatus includes a lens unit 1 and a camera body 2. The lens unit 1 adjusts the magnification, focus, and brightness of the optical information S that is reflected light from the subject and guides it to the camera body 2, and includes a zoom lens 3, a focus lens 4, and a diaphragm 5. The zoom lens 3, the focus lens 4, and the diaphragm 5 are disposed on the optical axis Q that guides the optical information S. The zoom lens 3 is movable along the optical axis Q by driving the zoom lens driving unit 6. The focus lens 4 is movable along the optical axis Q by driving the focus lens driving unit 7. The aperture diameter of the aperture 5 can be varied by driving the aperture drive unit 8.
The lens control microcomputer 9 drives and controls the zoom lens driving unit 6, the focus lens driving unit 7, and the diaphragm driving unit 8 in accordance with commands from the camera body 2.

  The camera body 2 includes an image sensor 10 as an image sensor. The image sensor 10 photoelectrically converts the incident optical information S and outputs it as a video signal. The image sensor 10 is made of, for example, a CMOS (hereinafter referred to as a CMOS image sensor). FIG. 2 shows an equivalent circuit of a pixel of a general CMOS image sensor 10. This CMOS image sensor 10 is formed by arranging a plurality of pixels 101-1 to 101-mn made of photodiodes (indicated by PD in the figure) and the like on a two-dimensional plane in the XY direction. Although the CMOS image sensor 10 has the number of pixels m × n, FIG. 2 shows the CMOS image sensor 10 with the number of pixels 4 × 4 because of the illustrated relationship.

The image sensor 10 is, for example, a global shutter in which the start and end of exposure for each pixel 101-1 to 101-mn are the same for each pixel position, or the start of exposure to each pixel 101-1 to 101-mn. And a rolling shutter that sequentially moves to and from the end.

The CMOS image sensor 10 reads stored charges by a method called an XY address scanning method, and includes a column-direction decoder (Row decoder) 102 and a vertical-direction decoder (Column decoder) 103. When the row drive signal G1 generated by the timing generator 20 is input, the row decoder 102 outputs a signal corresponding to the row drive signal G1 to each horizontal read selection signal line J00, J01,.
When the column drive signal G2 generated by the timing generator 20 is input, the column decoder 103 gives a signal corresponding to the column drive signal G2 to each of the switching elements T00, T01,. As a result, the switching elements T00, T01,..., T0m are selectively turned on to selectively store accumulated charges from the pixels 101-1 and 101-p in each column arranged in the vertical direction (Y direction). Is read out. Normally, the row decoder 102 outputs the row drive signal G1 to the horizontal read selection signal lines J00, J01,..., J0n, and the vertical read lines K00 through the switching elements T00, T01,. The output of the Column drive signal G2 to K01,..., K0m is performed in synchronism, and for example, each accumulated charge is read out for each pixel in one column in the horizontal direction (X direction).

  A video signal output from the CMOS image sensor 10 is sent to an analog front end (hereinafter referred to as AFE) 11. The AFE 11 adjusts the gain of the video signal from the CMOS image sensor 10, converts the gain-adjusted video signal from analog to digital, and thereby records an image in a subsequent digital signal processor (hereinafter referred to as DSP) 12. It is processed into easy-to-use image data.

  The DSP 12 is connected to an LCD display unit 13 composed of a liquid crystal panel used as a finder function, an external flash memory 14 for recording captured images, and a RAM 15. The DSP 12 displays the subject image in real time on the LCD display unit 13 based on the image data from the AFE 11, and records the main image data in the external flash memory 14 at the time of shooting when the release button is pressed. The main image data includes more pixels than the display image data. The LCD display unit 13 is provided on the back surface of the camera body 1.

  Specifically, the DSP 12 includes a pixel distribution unit 12-1, a display processing unit 12-2, a recording processing unit 12-3, and an accumulation processing unit 12-4. Among these, the pixel distribution unit 12-1 has image data from the AFE 11 before photographing as described later, data corresponding to the accumulated charge of each pixel of the pixel block for flicker detection in the CMOS image sensor 10, and the display pixel. Display image data corresponding to the accumulated charge is alternately arranged in a time-sharing manner. Therefore, the pixel distribution unit 12-1 uses the accumulated charge of the display pixel among the data corresponding to the accumulated charge of each pixel of the flicker detection pixel block and the display image data corresponding to the accumulated charge of the display pixel. The corresponding display image data is sent to the display processing unit 12-2, and the data corresponding to the accumulated charge of each pixel of the flicker detection pixel block is sent to the accumulation processing unit 12-4. Data corresponding to the accumulated charge of the pixel is sent to the recording processing unit 12-3. Note that the separation of the two systems of the data corresponding to the accumulated charge of each pixel of the flicker detection pixel block and the display image data corresponding to the accumulated charge of the display pixel makes the clock of the pixel output independent or the display period This is done by making the display signal indicating the display independent or assigning the effective polarity exclusively.

The display processing unit 12-2 performs resizing processing for matching display image data from the AFE 11 before photographing with the dot configuration of the LCD display unit 13 and frame rate matching processing.
The recording processing unit 12-3 generates recording image data by performing compression processing on the main image data from the AFE 11 at the time of shooting, and records the recording image data in the external flash memory 14. In the process of generating the recording image data, the image data and parameters are recorded in the RAM 15.
The accumulation processing unit 12-4 performs automatic focus (AF), automatic exposure (AE), and automatic white balance (AWB) using the display image data in parallel with the generation of the display image data by the display processing unit 12-2. ) And the like, and information on each pixel in the screen area for flicker detection, for example, the accumulated value of the luminance value of each pixel is obtained, and these accumulated values are sent to the system control microcomputer 19.

  The system control microcomputer 19 gives an instruction to the lens control microphone colon computer 9 of the lens unit 1, sets the operation mode of the CMOS image sensor 10, and generates the CMOS image sensor 10 generated by the timing generator (TG) 20. The drive timing mode is set, and has an exposure control unit 21 and a flicker detection unit 22. The system control microcomputer 19 performs setting and operation control on the CMOS image sensor 10, AFE 11, DSP 12, LCD display unit 13, external flash memory 14, RAM 15, and timing generator 20 in the camera body 2. The system control microcomputer 19 is connected to a user interface (not shown), and receives an operation command from the operator from the user interface.

The exposure control unit 21 includes display pixels D00 to Dki and flicker detection pixel blocks F00 to Fki among the plurality of pixels 11-1 to 11-mn of the CMOS image sensor 10 as shown in FIG. The exposure control for the display pixels D00 to Dki and the exposure control for the flicker detection pixel blocks F00 to Fki are performed independently.
That is, FIG. 3 shows a schematic diagram of a pixel readout state when the display image data is displayed on the LCD display unit 13 before recording and photographing by the CMOS image sensor 10. As described above, the CMOS image sensor 10 includes a plurality of pixels 101-1 to 101-mn arranged on a two-dimensional plane in the XY direction. These pixels 101-1 to 101-mn are pixels for displaying captured images D00 to Dki and for detecting flicker in a pixel readout state when displaying display image data on the LCD display unit 13 before recording and shooting. It is divided into pixel blocks F00 to Fki.

  The display pixels D00 to Dki are each composed of, for example, one pixel, and are arranged in plural at predetermined intervals, for example, every six pixels in the horizontal direction (X direction) and every seven pixels in the vertical direction (Y direction). Is done. On the other hand, each of the flicker detection pixel blocks F00 to Fki is composed of, for example, 5 × 6 pixels, and a plurality of flicker detection pixel blocks F00 to Fki are arranged between the display pixels D00 to Dki separately from the display pixels D00 to Dki.

  As the number of pixels of the CMOS image sensor 10 of the digital camera, for example, a total of 10 million pixels (approximately 3600 V × 2800 H pixels) or more in total of RGB colors is typically adopted. On the other hand, the rear LCD display unit 13 used as a finder function employs about 300,000 pixels (approximately 640 V × 480 H pixels). The LCD display unit 13 may use, for example, one pixel among the six pixels in the vertical and horizontal directions of the CMOS image sensor 10.

  Other pixels in one of the 6 pixels in the vertical and horizontal directions of the CMOS image sensor 10 may be mixed in order to increase sensitivity when the shooting environment is very dark. However, in an indoor fluorescent lamp illumination environment, In order to reduce flicker generated by illumination, it is necessary to set the exposure time to a long time that is an integral multiple of 1/120 seconds or 1/100 seconds, for example. In order to increase the sensitivity, pixel mixing may use neighboring pixels, for example, pixels between the display pixels D00 to Dki in the vertical direction in FIG. 3 for addition, but most of the pixels are not read out and are wasteful. It has become.

  In this apparatus, the pixels between the display pixels D00 to Dki, that is, the flicker detection pixel blocks F00 to Fki can be used for flicker detection and AE detection. The blocks F00 to Fki are mixed in charge, or the average value of the voltages is obtained to suppress the read information amount to be equal to or less than the number of display pixels, thereby preventing the frame rate from being lowered.

  As shown in FIG. 3, the exposure control unit 21 independently performs exposure control for the display pixels D00 to Dki and exposure control for the flicker detection pixel blocks F00 to Fki, and controls the flicker detection pixel blocks F00 to Fki. The exposure time and readout frame rate are controlled to be higher than the exposure time and readout frame rate for the display pixels D00 to Dki. Specifically, the exposure control unit 21 controls the Row drive signal G1 and the Column drive signal G2 generated by the timing generator 20, and sets the drive timing of the CMOS image sensor 10.

  The flicker detection unit 22 updates, for example, the cumulative value of the luminance value of each pixel as information of each pixel of the flicker detection pixel blocks F00 to Fki from the DSP 12 in order to examine the occurrence state of flicker due to illumination in the shooting environment. The flicker frequency and its level are obtained from the change in the accumulated value.

  FIG. 4 shows the relationship between the light source flicker and the unevenness in the screen at the time of the exposure of the rolling shutter method by the general XY address scanning readout in the CMOS image sensor 10. The figure shows the result of interval integration of the light amount of the light source, which fluctuates depending on the power supply frequency, for each exposure region by the exposure time based on the shutter speed, and the unit of the exposure region is a horizontal line. If the exposure time by the shutter speed control is an integral multiple of the light source flicker generated by the power supply frequency, the exposure is uniformly performed and the read image does not become uneven. On the other hand, if the exposure time by the shutter speed control is shorter or longer than the power supply frequency, unevenness occurs in the read image. It can be seen that the unevenness level difference is small because the low-pass filter effect by integration is larger when the exposure time is shorter than the shorter one.

Hereinafter, the Row drive signal G1 and the Column drive signal G2 generated by the CMOS image sensor 10 and the timing generator 20 will be described in detail.
FIG. 5 shows a method of sequentially reading the image information from the display pixels D00 to Dki and the image information from the flicker detection pixel blocks F00 to Fki in the CMOS image sensor 10 at 1: 1. That is, the flicker detection readout time ratio (= flicker detection readout pixel time / 1 frame readout time) is ½.

Similar to FIG. 3, the CMOS image sensor 10 is formed by arranging a plurality of pixels 101-1 to 101-mn on a two-dimensional plane in the XY direction, and among these pixels, the pixels D00 to Dki are used for display, and the pixel block F00 to Fki are used for flicker detection. In the relationship shown in the drawing, the display pixels D00 to Dki indicate only the four display pixels D00, D01, D10, and D11, and the flicker detection pixel blocks F00 to Fki include four flicker detection pixel blocks. Only F00, F01, F10, and F11 are shown. The display pixels D00,... D11 are composed of one pixel, for example, as described above. These display pixels D00,..., D11 are arranged in a plurality of lines in a line, and are set at predetermined intervals, for example, every six pixels in the horizontal direction (X direction) and six in the vertical direction (Y direction). A plurality of pixels are arranged for each pixel.
On the other hand, each of the flicker detection pixel blocks F00,..., F11 includes, for example, 5 × 6 pixels. These flicker detection pixel blocks F00,..., F11 are separate from the display pixels D00,..., D11, and are horizontally (X direction) and vertical (Y) between the display pixels D00,. Are arranged in each direction. That is, the flicker detection pixel blocks F00, F10 are at least one block for one column of display pixels D00,..., D11 arranged in a line, here the display pixels D00,. The blocks F00,..., F11 are arranged on a one-to-one basis.

A Row decoder 102 and a Column decoder 103 are provided in the horizontal direction (X direction) and the vertical direction (Y direction) in the vicinity of the display pixels D00,... D11 and the flicker detection pixel blocks F00,. It has been. A plurality of horizontal read selection signal lines J00, J01,..., J15 are connected to the Row decoder 102. The plurality of horizontal readout selection signal lines J00, J01,..., J15 are divided into, for example, horizontal readout selection signal lines J00 to J05 and horizontal readout selection signal lines J10 to J15, and among these, the horizontal readout selection signal lines J00 to J05. Are wired to the display pixels D00 and D01 and the flicker detection pixel blocks F00 and F01. The horizontal readout selection signal lines J10 to J15 are connected to the display pixels D10 and D11 and the flicker detection pixel blocks F10, It is wired to F11. These horizontal readout selection signal lines J00, J01,..., J15 are connected to the respective pixels 101-1, 101-2, etc. in each column arranged in the horizontal direction (X direction).
When the row drive signal G1 generated by the timing generator 20 is input, the row decoder 102 outputs a decode signal corresponding to the row drive signal G1 to each horizontal read selection signal line J00, J01,.

A plurality of vertical readout lines K00, K01,..., K15 are connected to the column decoder 103 via a plurality of switching elements T00, T01,. The plurality of vertical readout lines K00, K01,..., K15 are divided into, for example, vertical readout lines K00 to K05 and vertical readout lines K10 to K15, and among these, the vertical readout lines K00 to K05 are each the display pixel D00, D10 and flicker detection pixel blocks F00 and F10 are wired, and vertical readout lines K10 to K15 are wired to display pixels D01 and D11 and flicker detection pixel blocks F01 and F11. These vertical readout lines K00, K01,..., K15 are connected to the respective pixels 101-1 and 101-p in each column arranged in the vertical direction (Y direction).
Further, one output read line W is commonly connected to the plurality of switching elements T00, T01,.

  When the column drive signal G2 generated by the timing generator 20 is input to the column decoder 103, a decode signal corresponding to the column drive signal G2 is provided to each of the switching elements T00, T01,. As a result, when the switching elements T00, T01,..., T15 are turned on, the accumulated charges are converted into voltages from the pixels 101-1 and 101-p in each column arranged in the vertical direction (Y direction). Read out. Each read voltage is sequentially output through one output read line W.

  The exposure control unit 21 sets the exposure time and readout time for each flicker detection pixel block F00,..., F11 to be an integral number of the exposure time and readout time for each display pixel D00,. , D11 and the flicker detection pixel blocks F00,..., F11 are alternately output to one output read line W in a time-division manner. For this purpose, a Row drive signal G1 and a Column drive signal G2 are generated from the timing generator 20.

  Specifically, the exposure time and readout time of each flicker detection pixel block are set to be the same as the exposure time and readout time of each display pixel as shown in FIG. Only the exposure time and readout time of each flicker detection pixel block may be set short.

Next, the operation of the imaging device configured as described above will be described.
The optical information S, which is reflected light from the subject, is first adjusted in magnification by the zoom lens 3 in the lens unit 1, imaged on the surface of the CMOS image sensor 10 by the focus lens 4, and passed through the diaphragm 5 as desired. And is incident on the surface of the CMOS image sensor 10. The image sensor 10 photoelectrically converts the incident optical information S and outputs it as a video signal.
The AFE 11 adjusts the gain of the video signal from the CMOS image sensor 10, and acquires the image data by performing analog-digital conversion on the video signal after the gain adjustment.

  The DSP 12 displays image data from the AFE 11, for example, display image data before recording and shooting on the LCD display unit 13 in real time, and records this image data in the external flash memory 14 during recording and shooting. Specifically, the pixel distribution unit 12-1 of the DSP 12 includes a display pixel of the data corresponding to the accumulated charge of each pixel of the flicker detection pixel block and the display image data corresponding to the accumulated charge of the display pixel. The display image data corresponding to the accumulated charge is sent to the display processing unit 12-2, and sent to the data accumulation processing unit 12-4 according to the accumulated charge of each pixel of the flicker detection pixel block, and the CMOS image sensor 10 at the time of photographing. Is sent to the recording processing unit 12-3.

The display processing unit 12-2 performs resize processing for matching display image data from the AFE 11 before photographing with the dot configuration of the LCD display unit 13 and frame rate matching processing, and displays the display image data on the LCD display unit 13. Display in real time.
The recording processing unit 12-3 performs compression processing on the main image data from the AFE 11 at the time of shooting to generate recording image data, records the recording image data in the external flash memory 14, and records the recording data. Image data and parameters in the process of generating image data for use are temporarily recorded in the RAM 15.
In parallel with the generation of display image data by the display processing unit 12-2, the accumulation processing unit 12-4 includes a screen area for detecting AE, AF, and AWB in the display image data, and a screen area for detecting flicker. For example, the cumulative value of the luminance value of each pixel of the image data from the display pixels D00,... D11, and the luminance of each pixel of the image data from the flicker detection pixel blocks F00,. Each of the accumulated values is obtained, and these accumulated values are sent to the system control microcomputer 19.

The system control microcomputer 19 gives an instruction to the lens control microphone colon computer 9 of the lens unit 1, sets the operation mode of the CMOS image sensor 10, and generates the CMOS image sensor 10 generated by the timing generator (TG) 20. Is set to the flicker detection mode.
Here, the exposure control unit 21 of the system control microcomputer 19 determines the exposure time and readout time for each flicker detection pixel block F00,..., F11 shown in FIG. The accumulated charge read from the display pixels D00,..., D11 and the accumulated charges for flicker read from the flicker detection pixel blocks F00,. In order to alternately output to one output readout line W, a Row drive signal G1 and a Column drive signal G2 are generated from the timing generator 20, and for example, each of the Row and Column decode signals (drive signals) as shown in FIG. V10 to V15 and H10 to H15 are generated.

Here, with reference to FIG. 6, reading of each accumulated charge from the display pixels D00,..., D11 and the flicker detection pixel blocks F00,.
The decode signal of the Row drive signal G1 is divided into Row drive signals V00 to V05 and Row drive signals V10 to V15. Of these, each of the Row drive signals V00 to V05 is a horizontal readout selection signal line. The drive signals V10 to V15 of Row are supplied to J00 to J05, respectively, and are supplied to the horizontal readout selection signal lines J10 to J15, respectively. Accordingly, the row drive signals V00 to V05 are supplied to the display pixels D00 and D01 and the flicker detection pixel blocks F00 and F01 connected to the horizontal readout selection signal lines J00 to J05. The row drive signals V10 to V15 are supplied to the display pixels D10 and D11 and the flicker detection pixel blocks F10 and F11 connected to the horizontal readout selection signal lines J10 to J15.

  The row drive signals V00 to V05 are first set to a high level for a preset period for reading the accumulated charges from the pixels in the flicker detection pixel block F00, and then only the row drive signal V00 is displayed. It becomes a high level for a preset period for reading out the accumulated charge from the pixel D00. Next, the row drive signals V00 to V05 are at a high level for a period set in advance to read out accumulated charges from the pixels in the flicker detection pixel block F01, and then only the row drive signal V00. It becomes a high level for a period set in advance for reading out the accumulated charge from the display pixel D01. Next, the drive signals V00 to V05 of Row are set to a high level for a preset period in order to read out the accumulated charge from each pixel in the flicker detection pixel block F02 (not shown). Only the driving signal V00 becomes the high level for a preset period for reading out the accumulated charge from the display pixel D02.

  When the readout of the accumulated charges from the flicker detection pixel block and the display pixel in the horizontal direction (X direction) is completed, the row drive signals V10 to V15 are first supplied to the flicker detection pixel block F10. It becomes a high level for a period set in advance for reading out the accumulated charge from each of the pixels in the inside, and then it is set to a high level for a period set in advance for reading out the accumulated charge from the display pixel D10 only for the drive signal V10 for Row. Become. Next, the row drive signals V10 to V15 are at a high level for a period set in advance to read the accumulated charge from each pixel in the flicker detection pixel block F11, and then only the row drive signal V10. It becomes a high level for a period set in advance for reading the accumulated charge from the display pixel D11. Next, the drive signals V10 to V15 of Row are at a high level for a period set in advance to read out accumulated charges from the pixels in the flicker detection pixel block F12 (not shown). Only the driving signal V10 is set to the high level for a preset period for reading the accumulated charge from the display pixel D12.

  On the other hand, the Column drive signal G2 is divided into the Column drive signals H00 to H05 and the Column drive signals H10 to H15. First, among the Column drive signals H00 to H05, H00 to H04 are flicker detection. In order to read out the accumulated charge of each pixel in the pixel block F00, the drive signals V00 to V05 of Row are set to high level in synchronization with the high level for a preset period. As a result, the accumulated charge of each pixel in the flicker detection pixel block F00 is sent from the vertical read lines K00 to K04 to one output read line W through the switching elements T00 to T04.

Next, only the drive signal H05 of the column among the drive signals H00 to H05 of the column reads the stored charge of the display pixel D00, so that the drive signal V00 of the row becomes high for a preset period. Synchronously goes high. As a result, the accumulated charge of the display pixel D00 is sent from the vertical read line K05 to one output read line W through the switching element T05.
Next, among the drive signals H10 to H15 of the Column, the drive signals V00 to V05 of the Row are set in advance for the H10 to H14 to read out the accumulated charge of each pixel in the flicker detection pixel block F01. It becomes high level synchronously with the period becoming high level. As a result, the accumulated charge of each pixel in the flicker detection pixel block F01 is sent from the vertical read lines K10 to K14 to one output read line W through the switching elements T10 to T14.

  Next, only the drive signal H15 out of the drive signals H10 to H15 of the Column is synchronized with the drive signal V00 of the Row being at a high level for a preset period in order to read out the accumulated charge of the display pixel D01. High level for the period. As a result, the accumulated charge of the display pixel D01 is sent from the vertical read line K15 to one output read line W through the switching element T15.

  Similarly, H00 to H04 out of the column drive signals H00 to H05 are set in advance by the row drive signals V10 to V15 in order to read out the accumulated charges of the pixels in the flicker detection pixel block F10. It goes high in synchronism with the high level during the specified period. As a result, the accumulated charge of each pixel in the flicker detection pixel block F10 is sent from the vertical read lines K00 to K04 to one output read line W through the switching elements T00 to T04.

Next, among the drive signals H00 to H05 of the column, only the drive signal H05 of the column reads the accumulated charge of the display pixel D10, so that the drive signal V10 of the row becomes high level for a preset period. Synchronously goes high. As a result, the accumulated charge in the display pixel D10 is sent from the vertical read line K05 to one output read line W through the switching element T05.
Next, among the driving signals H10 to H15 of the Column, the driving signals V10 to V15 of the Row are preset in order to read out the accumulated charges of the pixels in the flicker detection pixel block F11. It becomes high level synchronously with the period becoming high level. As a result, the accumulated charge of each pixel in the flicker detection pixel block F11 is sent from the vertical read lines K10 to K14 to the single output read line W through the switching elements T10 to T14.

  Next, only the drive signal H15 out of the drive signals H10 to H15 of the Column is synchronized with the drive signal V10 of the Row being at a high level for a preset period in order to read out the accumulated charge of the display pixel D11. High level for the period. As a result, the accumulated charge of the display pixel D11 is sent from the vertical read line K15 to one output read line W through the switching element T15.

  As a result, the accumulated charge of each pixel in the flicker detection pixel block F00 is output as a video signal from one output readout line W of the CMOS image sensor 10, and then the accumulated charge of the display pixel D00, Accumulated charge of each pixel in the flicker detection pixel block F01, next accumulated charge of the display pixel D01,..., Next accumulated charge of each pixel in the flicker detection pixel block F11, and then accumulated in the display pixel D11 Like the charge, the accumulated charge of each pixel of the pixel block for flicker detection and the accumulated charge of the display pixel are output to one output readout line W alternately in a time division manner.

The AFE 11 adjusts the gain of the video signal from the CMOS image sensor 10, and acquires the image data by performing analog-digital conversion on the video signal after the gain adjustment.
The DSP 12 displays the image data from the AFE 11, for example, display image data before recording and shooting on the LCD display unit 13 in real time, and records the display image data and the main image data in the external flash memory 14 during recording and shooting. . Specifically, the pixel distributing unit 12-1 stores the accumulated charge of the display pixel among the data corresponding to the accumulated charge of each pixel of the flicker detection pixel block and the display image data corresponding to the accumulated charge of the display pixel. The display image data corresponding to the image data is sent to the display processing unit 12-2 and sent to the data accumulation processing unit 12-4 according to the accumulated charge of each pixel of the flicker detection pixel block. Data corresponding to the accumulated charge of the pixel is sent to the recording processing unit 12-3.

The display processing unit 12-2 performs a resizing process for matching display image data from the AFE 11 before recording and shooting with the dot configuration of the LCD display unit 13 and a frame rate matching process, and the display image data is displayed on the LCD display unit 13. Display in real time. As a result, a live view image of the subject is displayed on the LCD display unit 13.
The recording processing unit 12-3 performs compression processing on the main image data from the AFE 11 during recording shooting to generate recording image data, records the recording image data in the external flash memory 14, and The image data and parameters in the process of generating the recording image data are temporarily recorded in the RAM 15.

  In parallel with the generation of display image data by the display processing unit 12-2, the accumulation processing unit 12-4 includes a screen area for detecting AE, AF, and AWB in the display image data, and a screen area for detecting flicker. For example, the accumulated luminance value of each pixel of the display image data from the display pixels D00,... D11, and each pixel of each image data from the flicker detection pixel blocks F00,. The accumulated luminance values are obtained, and these accumulated values are sent to the system control microcomputer 19.

The system control microcomputer 19 uses the cumulative value of the luminance value of each pixel of each image data from the flicker detection pixel block F00,..., F11 from the DSP 12 in order to examine the occurrence state of flicker due to illumination in the photographing environment. Reading is performed every update, and the flicker frequency and its level are obtained from the change in the accumulated value.
The system control microcomputer 19 detects flicker in accordance with a flicker detection flowchart corresponding to the processing sequence at flicker detection shown in FIG. 7, for example. When shooting is started, the system control microcomputer 19 first sets the drive mode of the CMOS image sensor 10 to the flicker detection mode in order to detect flicker since the flicker state cannot be determined yet at the start of shooting. At the same time, the shutter speed control is switched to a high shutter speed.

  Prior to this, the system control microcomputer 19 obtains the luminance of the subject in step # 1 based on the display image data from the display pixels D00 to Dki for displaying the live view image on the LCD display unit 13. Then, it is determined whether or not the luminance is lower than a specified value, for example, a specified value 4BV. That is, it is determined whether or not the subject has brightness that cannot be room light, and is taken, for example, outdoors.

As a result of the determination, the luminance of the subject is obtained. If this luminance is higher than a predetermined value, for example, the predetermined value 4BV, the system control microcomputer 19 proceeds to step # 2 and uses the outdoor photographing P diagram parameter. Calculate exposure control parameters.
Next, in step # 3, the system control microcomputer 19 performs settings for performing exposure control such as the aperture diameter of the aperture 5, the shutter speed, and ISO sensitivity.

On the other hand, if the luminance of the subject is lower than a specified value, for example, a specified value 4BV, the system control microcomputer 19 moves to step # 4 and confirms the effective open value of the lens unit 1 and the aperture value of the aperture 5.
Next, in step # 5, the system control microcomputer 19 switches the CMOS image sensor 10 to the flicker detection mode as a pre-detection process of the light source flicker frequency, and sets it to a high shutter speed of, for example, 1/400 sec.
Next, in step # 6, the system control microcomputer 19 sequentially reads out the cumulative value of the luminance value of each pixel of each image data from the flicker detection pixel block F00,... The number of detected peaks, the peak interval, and the rate of change in the vicinity of the peak are obtained as the flicker conditions from the change in the accumulated value, and the flicker frequency and the level of the light source are obtained based on the number of detected peaks, the peak interval, and the rate of change in the vicinity of the peak.

  Next, in step # 7, the system control microcomputer 19 determines whether the flicker frequency of the light source is 50 Hz or 60 Hz. In determining the actual flicker frequency of the light source, it is confirmed that each peak has been obtained from the number of detected peaks, and the interval between these peaks is measured. Further, it is determined whether or not the flicker frequency of the light source is not affected by subject variation or noise based on the peak level difference and the repeatability of peak repetition.

As a result of the above determination, if the flicker frequency of the light source is 50 Hz, the system control microcomputer 19 proceeds to step # 8 and calculates the exposure control parameter using the 50-Hz P diagram parameter. Next, in step # 3, the system control microcomputer 19 performs settings for performing exposure control such as the aperture diameter of the aperture 5, the shutter speed, and ISO sensitivity.
On the other hand, if the flicker frequency of the light source is 60 Hz, the system control microcomputer 19 proceeds to step # 9 and calculates an exposure control parameter using the 60-Hz P diagram parameter. Next, in step # 3, the system control microcomputer 19 performs settings for performing exposure control such as the aperture diameter of the aperture 5, the shutter speed, and ISO sensitivity.

As described above, according to the first embodiment, when the CMOS image sensor 10 is in the pixel reading state when the recording image data is displayed on the LCD display unit 13 before photographing, The exposure time and readout time for the flicker detection pixel blocks F00,..., F11 are set to be an integral number of the exposure time and readout time for each display pixel D00,..., D11, and the display pixels D00,. , And flicker detection pixel blocks F00,..., F11 are alternately output to one output readout line W in a time-division manner.
As a result, the pixels that have been wasted between the display pixels D00,..., D11, that is, the flicker detection pixel blocks F00,..., F11 are conventionally used for flicker detection and AE detection. The accumulated charges from the pixel blocks F00,..., F11 are mixed with each other, or the average value of the voltage is obtained, so that the amount of read information can be suppressed to the number of display pixels or less to prevent the frame rate from being lowered. .
However, the image sensor 10 starts the exposure for each pixel 101-1 to 101-mn, for example, the global shutter in which the start and the end of the exposure for each pixel 101-1 to 101-mn are the same for each pixel position. Even when the camera has a rolling shutter that moves sequentially from the end to the end, it takes less time to detect the flicker frequency under the fluorescent light and reduces the time required to detect the flicker frequency. Never miss a photo opportunity. Flicker detection can be sped up without losing the live view display function and image quality. While the flicker is detected and the correction based on the shutter speed is performed, the photographer views the flicker in the live view image, but the time is sufficiently short, so that the flicker is not felt.

As a result, since the exposure time of the flicker detection pixel blocks F00,..., F11 is controlled independently of the exposure control of the display pixels D00,..., D11, the exposure of the display pixels D00,. It can be set for a long time, and the flicker level in the image can be kept low to make blinking and unevenness inconspicuous.
Also, if the frame rate is increased to increase the flicker detection speed, the shutter speed also increases, resulting in insufficient sensitivity. If the shutter speed is increased by, for example, two digits or more, the signal level of the image is buried in noise, and flicker detection There is a problem that the detection accuracy is too low. In order to solve this problem, Patent Document 3 tries to secure a level by gain correction, but a great improvement cannot be expected.
This device shortens the final readout time while improving noise by mixing pixels of the accumulated charges from each pixel of the flicker detection pixel blocks F00,..., F11, and shortens the final readout time. There is an improvement effect to raise.

  The accumulated charge of each pixel in the flicker detection pixel block F00, the accumulated charge of the display pixel D00, the accumulated charge of each pixel in the flicker detection pixel block F01 through one output read line W of the CMOS image sensor 10,... Since the accumulated charge of each pixel of the flicker detection pixel block and the accumulated charge of the display pixel are alternately output in a time-division manner like the accumulated charge of the display pixel D11, the output read line W of the CMOS image sensor 10 is output. One can be used for both the flicker detection pixel block and the display pixel, and an increase in the number of useless wirings can be avoided.

  The flicker detection pixel block F00,..., F11 has a large number of pixels. Since each accumulated charge is simultaneously read and mixed in units of flicker detection pixel blocks F00,. One output readout line W is a time-division switching between each accumulated charge read from the display pixels D00,..., D11 and each accumulated charge for flickers read from the flicker detection pixel blocks F00,. Therefore, it is driven in a band twice the read rate of each accumulated charge read from the display pixels D00,..., D11.

  The exposure time of the flicker detection pixel blocks F00,..., F11 can be controlled independently of the exposure control of the display pixels D00,. Thereby, compared with the case where the output of the accumulated charges of the display pixels D00,..., D11 is used for flicker detection, the flicker level difference can be increased and the flicker detection stability can be increased. Further, the flicker detection time can be shortened by increasing the image frame rate for flicker detection by expanding the pixel mixture area for flicker detection to be larger than the distribution ratio of display pixels and reducing the number of signals to be read independently.

As described above, according to the first embodiment, the CMOS image sensor 10 is divided into the flicker detection pixel blocks F00,..., F11 and the display pixels D00,. This increases the frame rate of the flicker detection block and shortens the flicker detection time.
In the flicker detection pixel blocks F00,..., F11, by increasing the sensitivity by pixel mixture addition, the exposure time can be further shortened, and the number of readout information can be reduced to reduce the frame rate.

Next, a second embodiment of the present invention will be described with reference to the drawings. 1 and 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
FIG. 8 shows the CMOS image sensor 10 with the same reading rate as the image information from the display pixels D00,..., D11 and the image information from the flicker detection pixel blocks F00,. Indicates the reading method. In this reading method, the reading ratio of the flicker detection pixel blocks F00,..., F11 for each line of the display pixels D00,. When the size is 640 pixels, it is improved to about 640: 1.

Specifically, the decode signal of the Row drive signal G1 generated by the CMOS image sensor 10 and the timing generator 20 and the decode signal of the Column drive signal G2 will be described.
In the relationship shown in the figure, the CMOS image sensor 10 has display pixels D00 to Dki as four display pixels D00,..., D11, and flicker detection pixel blocks F00 to Fki as two flicker detection pixel blocks F00, Let it be F10.
Each of the flicker detection pixel blocks F00 and F10 includes, for example, m × 5 pixels. m is the number of horizontal pixels. These flicker detection pixel blocks F00 and F10 are separate from the display pixels D00,..., D11, and in the horizontal direction (X direction) between the vertical directions (Y direction) of the display pixels D00,. It is arranged in a rectangular area of m × 5 pixels. Here, the flicker detection pixel blocks F00, F10 are arranged one block at a time for one row of display pixels D00,..., D11 arranged in a line.

A plurality of horizontal readout selection signal lines J00, J01,..., J15 are connected to the Row decoder 102. Among these, the horizontal readout selection signal line J00 is wired to each display pixel D00, D01, and the horizontal readout selection signal line. J01 to J05 are wired to one flicker detection pixel block F00, the horizontal readout selection signal line J10 is wired to each display pixel D10, D11, and the horizontal readout selection signal lines J11 to J15 are one flicker detection. It is wired to the pixel block F10.
When the row drive signal G1 generated by the timing generator 20 is input, the row decoder 102 outputs a decode signal corresponding to the row drive signal G1 to each horizontal read selection signal line J00, J01,.

A plurality of vertical readout lines K00, K01,..., K15 are connected to the column decoder 103 via a plurality of switching elements T00, T01,. These vertical readout lines K00, K01,..., K15 are wired to the display pixels D00,..., D11 and the flicker detection pixel blocks F00, F10.
In addition, a plurality of switching elements T00, T01,..., T15 are commonly connected to one output read line W, as described above.
When the column drive signal G2 generated by the timing generator 20 is input to the column decoder 103, a decode signal corresponding to the column drive signal G2 is provided to each of the switching elements T00, T01,. As a result, when the switching elements T00, T01,..., T15 are turned on, the accumulated charges are converted into voltages from the pixels 101-1 and 101-p in each column arranged in the vertical direction (Y direction). Read out. Each read voltage is sequentially output through one output read line W.

  However, the exposure control unit 21 reads the accumulated charges from the display pixels D00,..., D11 for each line and reads the accumulated charges from the flicker detection pixel blocks F00 and F10 in a time-sharing manner. A row drive signal G1 and a column drive signal G2 to be output to one output read line W are generated from the timing generator 20.

Next, reading of each accumulated charge from the display pixels D00,..., D11 and the flicker detection pixel blocks F00, F10 will be described with reference to FIG.
The decode signal of the Row drive signal G1 is divided into Row drive signals V00 to V05 and Row drive signals V10 to V15. Of these, each of the Row drive signals V00 to V05 is a horizontal readout selection signal line. The drive signals V10 to V15 of Row are supplied to J00 to J05, respectively, and are supplied to the horizontal readout selection signal lines J10 to J15, respectively. Accordingly, the drive signal V00 for Row is supplied to the display pixels D00 and D01 connected to the horizontal readout selection signal line J00, and the drive signals V01 to V05 are supplied to the horizontal readout selection signal lines J01 to J05. It is supplied to one connected flicker detection pixel block F00. Also, each drive signal V10 of Row is supplied to each display pixel D10, D11 connected to each horizontal readout selection signal line J10, and each drive signal V11-V15 is supplied to each horizontal readout selection signal line J11-J15. Is supplied to one flicker detection pixel block F10 connected to.

  The row drive signals V01 to V05 are first set to a high level for a period set in advance to read out accumulated charges from each pixel in one flicker detection pixel block F00, and then the row drive signal V00. Only when the accumulated charge is read out from the display pixel D00, it becomes high level for a preset period. Next, among the drive signals V00 to V05 of Row, only the drive signal V00 is at a high level for a preset period for reading the accumulated charge from the display pixel D01, and then the accumulated charge is read from the display pixel D02. Therefore, it becomes a high level for a period set in advance, and becomes a high level for a period set in advance to read out the accumulated charge from the display pixel D03.

  When the readout of the accumulated charges from the flicker detection pixel block and the display pixel in the horizontal direction (X direction) is completed, each of the drive signals V10 to V15 of Row continues with one flicker detection pixel block F10. It becomes a high level for a period set in advance for reading out the accumulated charge from each of the pixels in the inside, and then it is set to a high level for a period set in advance for reading out the accumulated charge from the display pixel D10 only for the row drive signal V10. Subsequently, only the drive signal V10 for Row is set to a high level for a preset period for reading the accumulated charge from the display pixel D11, and subsequently, a preset period for reading the accumulated charge from the display pixel D12. It becomes a high level, and becomes a high level for a period set in advance for reading out the accumulated charge from the display pixel D13.

  On the other hand, the decode signal of the Column drive signal G2 is divided into each of the drive signals H00 to H05 of the Column and each of the drive signals H10 to H15 of the Column. First, the drive signals H00 to H05 and H10 to H15 of the Column are In order to read out a signal in which the accumulated charge of each pixel in the flicker detection pixel block F00 is voltage-converted, the drive signals V01 to V05 of the Row are set to a high level in synchronization with a high level for a preset period. become. As a result, the accumulated charge of each pixel in the flicker detection pixel block F00 is voltage-converted and sent from the vertical read lines K00 to K15 to one output read line W through the switching elements T00 to T15.

  Next, only the drive signal H05 of the column among the drive signals H00 to H05 of the column reads the stored charge of the display pixel D00, so that the drive signal V00 of the row becomes high for a preset period. Synchronously goes high. As a result, a signal obtained by converting the voltage of the accumulated charge in the display pixel D00 is sent from the vertical read line K05 to one output read line W through the switching element T05.

Next, only the drive signal H15 of the column among the drive signals H00 to H05 of the column reads the accumulated charge of the display pixel D01, so that the drive signal V00 of the row becomes high for a preset period. Synchronously goes high. As a result, a signal obtained by converting the voltage of the accumulated charge in the display pixel D01 is sent from the vertical read line K15 to one output read line W through the switching element T15.
Similarly, the accumulated charge of the display pixel D02 is sent from the vertical read line to one output read line W through the switching element, and the accumulated charge of the display pixel D03 is sent to one output read line from the vertical read line through the switching element. Sent to W.

  Next, each of the drive signals V11 to V15 of Row becomes a high level for a preset period in order to read out the accumulated charge from each pixel in one flicker detection pixel block F10, and then the drive signal of Row. Only V10 is at a high level for a period set in advance to read out the accumulated charge from the display pixel D10. Next, only the row drive signal V10 is at a high level for a period set in advance for reading out the accumulated charge from the display pixel D11, and then the period for a period set in advance for reading out the accumulated charge from the display pixel D12. The level becomes a high level for a preset period for reading out the accumulated charge from the display pixel D13.

  On the other hand, the decoded drive signals H00 to H05 and H10 to H15 of the Column drive signal G2 read the accumulated charge of each pixel in the flicker detection pixel block F10, so that the drive signals V11 to V15 of the Row are The high level is synchronized with the high level for a preset period. As a result, the accumulated charge of each pixel in the flicker detection pixel block F10 is converted into a voltage and sent from the vertical read lines K00 to K15 to one output read line W through the switching elements T00 to T15.

  Next, only the column drive signal H05 reads the accumulated charge of the display pixel D10 as a voltage signal, so that the row drive signal V10 goes high in synchronism with the high level for a preset period. . As a result, the accumulated charge in the display pixel D10 is sent as a voltage signal from the vertical read line K05 to one output read line W through the switching element T05.

Next, only the column drive signal H15 reads the accumulated charge of the display pixel D11 as a voltage signal, so that the row drive signal V10 becomes high level in synchronization with the high level for a preset period. . As a result, the accumulated charge of the display pixel D11 is sent as a voltage signal from the vertical read line K15 to one output read line W through the switching element T15.
Similarly, the accumulated charge of the display pixel D12 is sent as a voltage signal from the vertical readout line to one output readout line W through the switching element, and the accumulated charge of the display pixel D13 is sent from the vertical readout line to the single output readout line W through the switching element. It is sent to the output readout line W.

  As a result, from one output readout line W of the CMOS image sensor 10, a video signal is output as a voltage signal obtained by averaging the accumulated charges of each pixel in the flicker detection pixel block F00, and then the display pixel. The accumulated charges of D00, D01, D02, D03,... Are read out in a time-sharing manner as voltage signals, and the accumulated charges of each pixel in the flicker detection pixel block F10 are output as voltage signals. The accumulated charges of D00, D01, D02, D03,... Are read out in a time division manner as voltage signals.

  As described above, according to the second embodiment, each pixel in the CMOS image sensor 10 is in the pixel readout state when the display image data is displayed on the LCD display unit 13 before the recording and photographing of the CMOS image sensor 10. The exposure time and readout time for the flicker detection pixel blocks F00, F10 and the exposure time and readout time for each display pixel D00,..., D11 are controlled independently to form one line of display pixels D00,. On the other hand, the readout of the flicker detection pixel blocks F00 and F10 is set to about 640: 1, and the signals read from the display pixels D00,..., D11 and the flicker detection signals read from the flicker detection pixel blocks F00 and F10. Are output to one output readout line W in a time-sharing manner. Needless to say, the same effect as that of the first embodiment can be obtained, and the number of pixel blocks to be individually read is reduced by expanding the area of each flicker detection pixel block F00, F10 in the CMOS image sensor 10. The read rate of the flicker detection pixel blocks F00 and F10 can be increased compared to the embodiment.

Next, a third embodiment of the present invention will be described with reference to the drawings. The same parts as those in FIG. 1 and FIG.
FIG. 10 shows a readout method in which the readout rates of the image information from the display pixels and the image information from the flicker detection pixel block in the CMOS image sensor 10 are further increased than those in the second embodiment. This reading method obtains one flicker information (Fxx) averaged over the entire screen for one display screen line. Specifically, the flicker detection read time ratio (= flicker detection read pixel time / 1 frame read time) is 1/307200.

  Specifically, the decode signal of the Row drive signal G1 generated by the CMOS image sensor 10 and the timing generator 20 and the decode signal of the Column drive signal G2 will be described.

In the relationship shown in the figure, the CMOS image sensor 10 has display pixels D00 to Dki as four display pixels D00,..., D11, and flicker detection pixel blocks F00 to Fki as two flicker detection pixel blocks F00, Let it be F10.
Each of the flicker detection pixel blocks F00 and F10 includes, for example, m × 5 pixels. These flicker detection pixel blocks F00 and F10 are separate from the display pixels D00,..., D11, and in the horizontal direction (X direction) between the vertical directions (Y direction) of the display pixels D00,. It is arranged in a rectangular area of m × 5 pixels.

  The exposure controller 21 reads each accumulated charge from each display pixel D00,..., D11 for each line and reads each accumulated charge from each flicker detection pixel block F00, F10 in a time-sharing manner. The row drive signal G1 and the column drive signal G2 to be output to the output read line W are generated from the timing generator 20.

Next, reading of accumulated charges from the display pixels D00,..., D11 and the flicker detection pixel blocks F00, F10 will be described with reference to FIG.
The drive signals V01 to V05 and V11 to V05 of Row are first set to a high level for a preset period for reading out the accumulated charges from all the pixels in the flicker detection pixel blocks F00 and F10 in the CMOS image sensor 10, respectively. Become a level. Next, only the row drive signal V00 is set to the high level for a preset period for reading the accumulated charge from the display pixel D00, and then only the row drive signal V00 receives the accumulated charge from the display pixel D01. It becomes a high level for a period set in advance for reading, and then only each drive signal V00 for Row becomes a high level for a period set in advance for reading accumulated charge from the display pixel D02, and then each drive for Row Only the signal V00 is at a high level for a period set in advance for reading the accumulated charge from the display pixel D03.

  When the readout of the accumulated charges from all the flicker detection pixel blocks and the display pixels D00,..., D0i in the horizontal direction (X direction) is completed, the drive signals V01 to V05, V11 to V15 of Row are continued. Becomes a high level for a period set in advance for reading the accumulated charge from each of the pixels in all the flicker detection pixel blocks F00 and F10, and then only the row drive signal V10 is accumulated from the display pixel D10. Then, the drive signal V10 of the row is set to the high level for a preset period for reading the accumulated charge from the display pixel D11, and then the display pixel is displayed. It becomes high level for a preset period for reading the accumulated charge from D12, and then the accumulated charge is read from the display pixel D13. It becomes the preset period a high level in order to get.

  On the other hand, the drive signals H00 to H05 and H10 to H15 of the Column are used for voltage conversion and reading out the accumulated charge of each pixel in all the flicker detection pixel blocks Fxx including the flicker detection pixel blocks F00 and F10. The drive signals V01 to V05 and V11 to V15 of the Row become high level in synchronization with the high level for a preset period. As a result, the accumulated charge of each pixel in all the flicker detection pixel blocks Fxx including the flicker detection pixel blocks F00 and F10 is converted into a voltage, and 1 is transmitted from each vertical readout line K00 to K15 through each switching element T00 to T15. It is sent to the output read line W of the book.

  Next, since only the column drive signal H05 converts the accumulated charge of the display pixel D00 into a voltage and reads it, the row drive signal V00 is set to the high level in synchronization with the high level for a preset period. Become. As a result, the accumulated charge of the display pixel D00 is converted into a voltage and sent from the vertical read line K05 to one output read line W through the switching element T05.

Next, since only the column drive signal H15 converts the accumulated charge of the display pixel D01 into a voltage and reads it, the row drive signal V00 is set to the high level in synchronization with the high level for a preset period. Become. As a result, the accumulated charge of the display pixel D01 is converted into a voltage and sent from the vertical readout line K15 to one output readout line W through the switching element T15.
Similarly, the accumulated charge of the display pixel D02 is voltage-converted and sent from the vertical readout line to one output readout line W through the switching element, and the accumulated charge of the display pixel D03 is voltage-converted and switched from the vertical readout line. It is sent to one output read line W through the element.
Again, the drive signals H00 to H05 and H10 to H15 of the Column are used to drive the above-mentioned row in order to convert and read out the accumulated charge of each pixel in all the flicker detection pixel blocks Fxx including F00 and F10. The signals V01 to V05 and V11 to V15 become high level in synchronization with the high level for a preset period. As a result, the accumulated charge of each pixel in all flicker detection pixel blocks Fxx including F00 and F10 is converted into a voltage, and one output readout line is passed from each vertical readout line K00 to K15 through each switching element T00 to T15. Sent to W.

  Next, only the Column drive signal H05 is converted to a high level in synchronization with the Row drive signal V10 being at a high level for a preset period in order to convert the stored charge from the display pixel D10 by voltage conversion. Become. As a result, the accumulated charge in the display pixel D10 is sent from the vertical read line K05 to one output read line W through the switching element T05.

Next, only the Column drive signal H15 is converted to a high level in synchronization with the drive signal V10 of the Row being at a high level for a preset period in order to read out the stored charge from the display pixel D11 by voltage conversion. Become. As a result, the charge stored in the display pixel D11 is converted into a voltage and sent from the vertical read line K15 to one output read line W through the switching element T15.
Subsequently, the accumulated charge of the display pixel D12 is voltage-converted and sent from the vertical read line to one output read line W through the switching element. Next, the accumulated charge of the display pixel D13 is voltage-converted and converted to the vertical read line. To the output read line W through the switching element.
Thereafter, the same operation as described above is repeated.

  As a result, the accumulated charge of each pixel in the flicker detection pixel block Fxx is output as a video signal from one output readout line W of the CMOS image sensor 10, and then the display pixels D00, D01, D02, The accumulated charges of D03, ... are read out in a time-sharing manner, and the accumulated charges of each pixel in all the flicker detection pixel blocks Fxx are output again, and then the display pixels D10, D11, D12, D13, ..., Are repeatedly read out in a time-sharing manner.

  As described above, according to the third embodiment, all of the CMOS image sensor 10 is in the pixel readout state when the display image data is displayed on the LCD display unit 13 before the recording and photographing of the CMOS image sensor 10. The exposure time and readout time for the flicker detection pixel blocks F00, F10 and the exposure time and readout time for each display pixel D00,..., D11 are controlled independently to read out the flicker detection pixel blocks F00, F10. In addition to speeding up, each accumulated charge read from the display pixels D00,..., D11 and each accumulated charge for flickers read from all the flicker detection pixel blocks F00, F10 are time-divided into one output readout line. Since it is output to W, the same effect as the first embodiment can be obtained. Needless to say, since one piece of flicker information averaged over the entire screen is obtained for one display screen line, the flicker detection pixel blocks F00 and F10 of the first embodiment are compared with those in the first embodiment. The read rate can be increased.

The light source flicker frequency detection process will be supplementarily described.
FIG. 12 shows transient flicker detection sampling in which light source flicker frequency detection processing is performed, that is, readout of accumulated charges from the CMOS image sensor 10. This light source flicker frequency detection processing is performed by reading each accumulated charge from the display pixels D00,..., D11 in the third embodiment and reading accumulated charges from all the flicker detection pixel blocks F00, F10. Is the flicker detection time when performing in a time-sharing manner.

  The flicker detection unit 22 of the system control microcomputer 19 sequentially reads the accumulated value of the luminance value of each pixel of each image data from all the flicker detection pixel blocks F00 and F10 from the DSP 12 every update, and The fluctuation level of the illumination light quantity is detected from the change. Then, the flicker detection unit 22 finds the high peak and the low peak of the illumination light amount, measures the time between the high peak and the low peak, and obtains the lighting frequency of the illumination light amount from this measurement time.

By the way, the emission luminance change curve of an actual light source such as a fluorescent lamp does not appear as a power supply curve similar to a clean sine curve, but includes noise due to uneven discharge. In order to avoid the influence of this noise, an average value of the measured values before and after is obtained, and a low-pass filter is applied to obtain a sampling value of the illumination light quantity.
Since the maximum value of the illumination light quantity cannot be determined in advance, a level of 100% of the signal level corresponding to the maximum value of the illumination light quantity cannot be defined. Therefore, during the measurement of the illumination light quantity, the sampling value of the illumination light quantity is sequentially stored. At this time, the maximum value and the minimum value of the sampling value of the illumination light quantity are sequentially updated and stored.

  In this way, the maximum value is obtained on the condition that the sampling value of the level that has decreased by 10% or more is obtained before and after the maximum value as the threshold value of the maximum value level while updating the maximum value and minimum value of the sampling value of the illumination light quantity. Are detected, and the sampling position is obtained. The detection of such maximum sampling is performed in order to improve not only the low-pass filter but also the detection position accuracy because the noise component is larger than the change in the amount of illumination light particularly near the high peak.

  The low peak is less susceptible to noise than the high peak, but sampling of the minimum value is performed on the condition that sampling values that are 10% or more higher than the minimum value before and after the low peak are obtained before and after the minimum value. Detect and determine the sampling position.

  When one high peak and one low peak are detected, the time difference between the high peak sampling position and the low peak sampling position is obtained. Then, it is determined whether the time difference between the sampling positions is close to 1/100 seconds or 1/120 seconds, and it is determined from this determination result whether the flicker frequency of the light source is 100 Hz or 120 Hz.

  Note that when the flicker waveform is a sine wave and the detection threshold of each of the high peak and the low peak is set to 10%, theoretically, it is possible to determine the flicker frequency of the light source with the information of the sampling period of about 17 milliseconds. . In the case of a light source such as an incandescent bulb or a high-frequency inverter fluorescent lamp, the flicker level is small, the peak is not detected because the frequency is different, and the peak interval may be completely different from the criterion. In these cases, the detection process is repeated several times, but if it is still not found, it is determined that there is no light source flicker.

Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.
In the display pixels D00 to Dki and the flicker detection pixel blocks F00 to Fki in each of the above embodiments, the number of the respective pixels can be arbitrarily set. Accordingly, the flicker detection pixel blocks F00 to Fki The size can be changed. If the sizes of the flicker detection pixel blocks F00 to Fki are varied, the exposure control unit 21 determines the rate between the display information read from the display pixels and the flicker information according to the size of the flicker detection pixel block. Is variable.

  In addition, the number of blocks in which the flicker detection pixel blocks arranged in the vertical direction are simultaneously averaged on the readout line can be arbitrarily set, and the exposure control unit 21 varies the rate of the readout display information and the flicker information. .

1 is a system block diagram showing a first embodiment of an imaging apparatus such as a digital camera according to the present invention. The figure which shows the equivalent circuit of the pixel of the general CMOS image sensor in the apparatus. The schematic diagram which shows the pixel read-out state at the time of the display to the LCD display part before imaging | photography of the CMOS image sensor in the same apparatus. The figure which shows the relationship between the light source flicker at the time of the exposure of the rolling shutter system by the general XY address scanning reading of the CMOS image sensor in the apparatus, and the in-screen nonuniformity. The figure which shows the system which reads sequentially each reading rate of the image information from the pixel for a display in the CMOS image sensor in the same apparatus, and the image information from the pixel block for a flicker detection at 1: 1. FIG. 4 is a diagram for explaining reading of each accumulated charge from a display pixel and a flicker detection pixel block in the apparatus. The flicker detection flowchart in the same apparatus. In the CMOS image sensor according to the second embodiment of the imaging device such as a digital camera according to the present invention, reading is performed at a higher reading rate between the image information from the display pixels and the image information from the flicker detection pixel block. The figure which shows a system. FIG. 4 is a diagram for explaining readout of each accumulated charge from a display pixel and a flicker detection pixel block in the same device. In the CMOS image sensor according to the third embodiment of the image pickup apparatus such as a digital camera according to the present invention, the image information from the display pixels and the image information from the flicker detection pixel block are read at high speeds. The figure which shows a system. FIG. 4 is a diagram for explaining readout of each accumulated charge from a display pixel and a flicker detection pixel block in the same device. The figure which shows the sampling for the transient flicker detection which performs the light source flicker frequency detection process in the apparatus.

Explanation of symbols

  1: lens unit, 2: camera body, 3: zoom lens, 4: focus lens, 5: aperture, 6: zoom lens driving unit, 7: focus lens driving unit, 8: aperture driving unit, 9: lens control microcomputer 10: Image sensor, 101-1 to 101-mn: Multiple pixels, 102: Row decoder, 103: Column decoder, 20: Timing generator, J00, J01,..., J0n: Horizontal readout line, T00, T01,. , Tm: switching element, K00, K01,..., K0m: vertical readout line, 11: analog front end (AFE), 12: digital signal processor (DSP), 13: LCD display unit, 14: external flash memory, 15: RAM, 12-1: pixel distribution unit, 12-2: display processing unit, 12-3: recording process Section: 12-4: cumulative processing section, 19: system control microcomputer, 20: timing generator (TG), 21: exposure control section, 22: flicker detection section, D00 to Dki: display pixels, F00 to Fki: flicker Detection pixel block, W: output readout line.

Claims (6)

In an imaging device that performs imaging control based on the captured image while displaying the captured image,
A pixel block for flicker detection, which includes pixels for displaying the captured image arranged at predetermined intervals, and a plurality of pixels for detecting a flicker frequency separately from the display pixels. An image sensor;
A readout line that outputs the display information read from the display pixels and the flicker information read from the flicker detection pixel block on the same line;
The exposure control for the display pixel and the exposure control for the flicker detection pixel block are performed independently, and the readout frame rate for the flicker detection pixel block is higher than the readout frame rate for the display pixel. Control means for controlling
An imaging apparatus comprising:   2. The imaging apparatus according to claim 1, wherein the display information read from the display pixels and the flicker information read from the flicker detection pixel block are output through the readout line.   The imaging apparatus according to claim 1, further comprising: a flicker processing unit that performs mixing addition or averaging of the information for each flicker of each pixel read from the pixel block for flicker detection.   The control means sets the exposure time or readout interval for the flicker detection pixel block to be an integral number of the exposure time or readout interval for the display pixel, and the display information read from the display pixel. 3. The imaging apparatus according to claim 2, wherein the flicker information read from the flicker detection pixel block is output in a time division manner.   The image sensor is a global shutter in which the plurality of pixels are arranged vertically and horizontally, and the start and end of exposure for each pixel are the same for each pixel position, or the start of exposure for each pixel The imaging apparatus according to claim 1, wherein the image pickup apparatus is a rolling shutter that sequentially moves.   6. The imaging apparatus according to claim 1, further comprising recording means for generating recording image information from the display pixels and each pixel of the flicker detection pixel block.

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