JP2010088086A - Rf receiving circuit, gps receiver, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of an RF receiving circuit that receives a high frequency signal from a positioning satellite. <P>SOLUTION: The RF receiving circuit 100 includes: an antenna 10; a low noise amplifier circuit 101; a frequency synthesizer circuit 108; a multiplication circuit 102; an automatic gain control circuit 106 cascaded to the output of an n-th filter 104; a gain control circuit 112 cascaded to the output of a primary filter 111; analog-to-digital converter circuits 113, 114; and switch circuits 103, 105, 107 for performing switching between a first connection state where, when the S/N ratio of a high frequency signal received by the antenna 10 is less than a predetermined value, a multiplication signal is input to the n-th filter 104 and the output signal of the automatic gain control circuit 106 is input to the analog-to-digital converter circuit 113, and a second connection state where, when the S/N ratio is equal to or higher than the predetermined value, the multiplication signal is input to the primary filter 111 and the output signal of a gain control circuit 112 is input to the analog-to-digital converter circuit 113. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an RF receiving circuit, a GPS receiver, and an electronic device that receive a high-frequency signal from a positioning satellite.

  The RF (Radio Frequency) receiver circuit for GPS (Global Positioning System) that receives high-frequency signals from positioning satellites has a third-order filter and automatic gain control (AGC) circuit to improve GPS performance. Because it is used, it is generally easy to consume power. Conventionally, in order to reduce power consumption, a method of controlling the current of a low noise amplifier (LNA: Low Noise Amplifier) used in an RF receiver circuit or a VCO (Voltage Controlled Oscillator) constituting a frequency synthesizer circuit has been performed. However, only an effect of about 1 to 2 mA was obtained.

  In order to solve this problem, for example, Patent Document 1 describes a method for reducing the mixer current when the RSSI signal of the received signal strength indicator (RSSI) circuit exceeds a predetermined threshold.

JP-A-10-190570

  However, the conventional method relates to a cellular phone, and there is a problem that this method cannot be used because an RSSI circuit is not used in the GPS receiver.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
An antenna that receives a high-frequency signal from a positioning satellite, a low-noise amplifier circuit that amplifies the high-frequency signal received by the antenna and outputs an amplified signal, a frequency synthesizer circuit that outputs a sine wave signal of a predetermined frequency, and A multiplication circuit that outputs a multiplication signal obtained by multiplying the amplified signal and the sine wave signal, an n-order filter in which RC filters are stacked in n stages (n is an integer of 2 or more), and an output of the n-order filter are cascaded. The S / N ratio of the high-frequency signal received by the antenna is predetermined, the automatic gain control circuit, the primary filter, the gain control circuit cascaded with the output of the primary filter, the analog-digital conversion circuit, Is less than the first value, the multiplication signal is input to the n-th order filter, and the output signal of the automatic gain control circuit is input to the analog-digital conversion circuit. When the connection state and the S / N ratio of the high-frequency signal received by the antenna are greater than or equal to a predetermined value, the multiplication signal is input to the primary filter, and the output signal of the gain control circuit is input to the analog-digital An RF receiving circuit comprising: a switching unit that switches between a second connection state input to the conversion circuit.

  According to this configuration, when the S / N ratio of the high-frequency signal received by the antenna is greater than or equal to a predetermined value, the operation can be switched to the primary filter and the gain control circuit with low power consumption, thereby reducing power consumption. Can be realized.

[Application Example 2]
In the RF receiver circuit described above, the analog-digital converter circuit is composed of m (m is an integer of 2 or more) bits, and the S / N ratio of the high-frequency signal received by the antenna is less than a predetermined value. Processes the output signal of the automatic gain control circuit with m bits, and if the S / N ratio of the high frequency signal received by the antenna is greater than or equal to a predetermined value, the output signal of the gain control circuit is less than m bits. An RF receiving circuit characterized in that the processing is performed.

  According to this configuration, since the nth-order filter and the automatic gain control circuit are connected when the RF receiving circuit is activated, high reception sensitivity can be obtained, and the S / N ratio of the high-frequency signal received by the antenna is a predetermined value. If it becomes above, since it can switch to the primary filter and gain control circuit with little power consumption, and also operate | moves by reducing the bit number of an analog-digital conversion circuit, reduction of power consumption is realizable.

[Application Example 3]
In the RF receiving circuit described above, the frequency synthesizer circuit includes a voltage-controlled oscillator and a phase-locked loop circuit, and when the S / N ratio of the high-frequency signal received by the antenna is less than the predetermined value, A predetermined current flows through the low noise amplifier circuit and the voltage controlled oscillator, and when the S / N ratio of the high frequency signal received by the antenna is equal to or greater than the predetermined value, the low noise amplifier circuit and the voltage An RF receiving circuit, wherein a current less than the predetermined current flows through a controlled oscillator.

  According to this configuration, since the nth-order filter and the automatic gain control circuit are connected when the RF receiving circuit is activated, high reception sensitivity can be obtained, and the S / N ratio of the high-frequency signal received by the antenna is a predetermined value. If it becomes above, it can be switched to a primary filter and a gain control circuit with low power consumption, and further, the current flowing through the low-noise amplifier circuit and the voltage-controlled oscillator can be reduced so that the power consumption can be reduced. .

[Application Example 4]
In the RF receiver circuit described above, the switching unit supplies power to the primary filter and the gain control circuit when the S / N ratio of the high-frequency signal received by the antenna is less than the predetermined value. And when the S / N ratio of the high-frequency signal received by the antenna is equal to or greater than the predetermined value, the power supply to the n-th order filter and the automatic gain control circuit is stopped. Receiver circuit.

  According to this configuration, since the nth-order filter and the automatic gain control circuit are connected when the RF receiving circuit is activated, high reception sensitivity can be obtained, and the S / N ratio of the high-frequency signal received by the antenna is a predetermined value. If it becomes above, it can switch to the primary filter and gain control circuit with little power consumption, and also it can be made to operate by stopping the power supply to the n-th order filter and automatic gain control circuit which is not used. Can be realized.

[Application Example 5]
The RF receiver circuit according to the above, wherein the switching unit of the RF receiver circuit is in the first connection state when activated.

  According to this configuration, since the nth-order filter and the automatic gain control circuit are connected when the RF receiving circuit is activated, high reception sensitivity can be obtained, and the S / N ratio of the high-frequency signal received by the antenna is a predetermined value. If it becomes above, since it can be made to operate | move by switching to a primary filter and a gain control circuit with little power consumption, reduction of power consumption is realizable.

[Application Example 6]
A GPS receiver comprising the RF receiver circuit described above.

  According to this configuration, when the S / N ratio of the high-frequency signal received by the antenna is greater than or equal to a predetermined value, the operation can be switched to the primary filter and the gain control circuit with low power consumption, thereby reducing power consumption. It is possible to supply a GPS receiver that realizes the system.

[Application Example 7]
An electronic apparatus comprising the GPS receiver described above.

  According to this configuration, when the S / N ratio of the high-frequency signal received by the antenna is greater than or equal to a predetermined value, the operation can be switched to the primary filter and the gain control circuit with low power consumption, thereby reducing power consumption. It is possible to supply electronic devices that can be realized.

  Hereinafter, embodiments of a GPS receiver including an RF receiving circuit will be described with reference to the drawings.

(First embodiment)
<Configuration of GPS receiver>
First, the configuration of a GPS receiver including the RF receiving circuit according to the first embodiment will be described with reference to FIG. FIG. 1 is a circuit diagram showing a configuration of a GPS receiver including an RF receiving circuit according to the first embodiment.

  As shown in FIG. 1, the GPS receiver 1 includes an RF receiving circuit 100, a baseband processing circuit 200, an antenna 10 that receives a high-frequency signal from a positioning satellite, and a power source 20.

  The RF receiver circuit 100 includes a low noise amplifier (LNA) 101, a frequency synthesizer circuit 108, a multiplier circuit 102, switch circuits 103, 105, 107, and 115 that constitute a switching unit, and an nth order ( n is an integer of 2 or more) filter 104, automatic gain control (AGC) circuit 106, primary filter 111, gain control (GC) circuit 112, and m = 2-bit analog− It comprises digital conversion circuits (ADC: Analog-to-Digital Converter) 113, 114 and current sources 116, 117.

  The baseband processing circuit 200 includes a correlator 201, an S / N calculation unit 202, and a determination unit 203.

  The LNA 101 amplifies the high frequency signal f1 received by the antenna 10 and outputs an amplified signal f2. The frequency synthesizer circuit 108 includes a VCO 109 and a PLL (Phase-locked loop) 110, and outputs a sine wave signal f4 having a predetermined frequency. The multiplication circuit 102 outputs a multiplication signal f3 obtained by multiplying the amplified signal f2 and the sine wave signal f4.

  In the switch circuit 103, the input terminal i is connected to the output terminal of the multiplication circuit 102, the output terminal a is connected to the input terminal of the n-order filter 104, and the output terminal b is connected to the input terminal of the primary filter 111. . The switch circuit 105 has an input terminal i connected to the power supply line VDD, an output terminal a connected to the power supply terminals of the n-order filter 104 and the AGC circuit 106, and an output terminal b connected to the power supply of the primary filter 111 and the GC circuit 112. Connected to the supply terminal. The switch circuit 107 has an input terminal a connected to the output terminal of the AGC circuit 106, an input terminal b connected to the output terminal of the GC circuit 112, and an output terminal o connected to the ADC 113 and the input terminal of the switch circuit 115. .

  The n-th order filter 104 is configured by overlapping RC filters with n stages (n is an integer of 2 or more), and a filter that filters the multiplication signal f3 when the input terminal i and the output terminal a of the switch circuit 103 are connected. The signal f5 is output. The AGC circuit 106 is cascade-connected to the output terminal of the nth-order filter 104, and outputs a gain signal f6 obtained by automatically adjusting the gain of the filter signal f5.

  The primary filter 111 is composed of a single-stage RC filter, and outputs a filter signal f7 obtained by filtering the multiplication signal f3 when the input terminal i and the output terminal b of the switch circuit 103 are connected. The GC circuit 112 is connected in cascade with the output terminal of the primary filter 111, and outputs a gain signal f8 obtained by adjusting the gain of the filter signal f7.

  The ADC 113 outputs a sign bit signal SIGN obtained by analog-digital conversion of the gain signal f6 when the input terminal a and the output terminal o of the switch circuit 107 are connected. On the other hand, the ADC 113 outputs a sign bit signal SIGN obtained by analog-digital conversion of the gain signal f8 when the input terminal b and the output terminal o of the switch circuit 107 are connected. The ADC 114 outputs an amplitude bit signal MAG obtained by analog-digital conversion of the gain signal f6 when the input terminal a and the output terminal o of the switch circuit 107 are connected and the switch circuit 115 is connected.

  The current source 116 adjusts the amount of current flowing through the LNA 101. The current source 117 adjusts the amount of current flowing through the VCO 109.

  The correlator 201 outputs a correlation signal f9 from the sign bit signal SIGN and the amplitude bit signal MAG. The S / N calculator 202 outputs a signal S / N obtained by calculating the S / N ratio of the high-frequency signal f1 from the correlation signal f9. As shown in FIG. 3, the determination unit 203 sets the switch signal SWC to the H level in the period T1 in which the signal S / N is less than the predetermined value Vth, and the period in which the signal S / N is greater than or equal to the predetermined value Vth. In the case of T2, the switch signal SWC is set to L level.

  In the switch circuits 103 and 105, when the switch signal SWC is at H level, the input terminal i and the output terminal a are connected, and when the switch signal SWC is at L level, the input terminal i and the output terminal b are connected. In the switch circuit 107, the input terminal a and the output terminal o are connected when the switch signal SWC is at the H level, and the input terminal b and the output terminal o are connected when the switch signal SWC is at the L level. In the switch circuit 115, the input terminal and the output terminal are connected when the switch signal SWC is at the H level, and the input terminal and the output terminal are disconnected when the switch signal SWC is at the L level. The current sources 116 and 117 are in a state in which a normal current flows when the switch signal SWC is at an H level, and a state in which a smaller current flows than in a normal state when the switch signal SWC is at an L level.

  FIG. 1 shows the state (first connection state) of the switch circuits 103, 105, 107, and 115 when the switch signal SWC is at the H level, and FIG. 2 shows the switch circuit 103 when the switch signal SWC is at the L level. , 105, 107, and 115 (second connection state).

  As shown in FIG. 1, when the switch signal SWC is at the H level, the switch circuit 105 connects the power supply terminals of the n-order filter 104 and the AGC circuit 106 to the power supply line VDD, and the switch circuit 103 The multiplication signal f3 to be output is input to the nth order filter 104, the filter signal f5 output from the nth order filter 104 is input to the AGC circuit 106, and the gain signal f6 output from the AGC circuit 106 by the switch circuits 107 and 115 is the ADC 113, 114. Further, the switch circuit 105 disconnects the power supply terminals of the primary filter 111 and the GC circuit 112 from the power supply line VDD. Furthermore, the current sources 116 and 117 are in a state where a normal current flows.

  On the other hand, as shown in FIG. 2, when the switch signal SWC is at the L level, the switch circuit 105 connects the power supply terminals of the primary filter 111 and the GC circuit 112 to the power supply line VDD, and the switch circuit 103 multiplies the multiplication circuit. The multiplication signal f3 output from the input filter 102 is input to the primary filter 111, the filter signal f7 output from the primary filter 111 is input to the GC circuit 112, and the gain signal f8 output from the GC circuit 112 by the switch circuits 107 and 115 is obtained. It is input only to the ADC 113. Further, the switch circuit 105 disconnects the power supply terminals of the nth order filter 104 and the AGC circuit 106 from the power supply line VDD. Furthermore, the current sources 116 and 117 are in a state in which less current flows than usual.

  In the period T1 in FIG. 3, the S / N ratio is less than the predetermined value Vth and the S / N ratio of the high-frequency signal f1 is poor. Therefore, it is necessary to increase the reception sensitivity of the high-frequency signal f1 by setting the connection state in FIG. is there. On the other hand, since the S / N ratio is equal to or higher than the predetermined value Vth and the S / N ratio of the high-frequency signal f1 is good in the period T2, the reception sensitivity of the high-frequency signal f1 is lowered by setting the connection state in FIG. Can be lowered.

  According to the present embodiment described above, the following effects can be obtained.

  In the present embodiment, as shown in FIG. 3, the S / N ratio is less than the predetermined value Vth in the period T1, and the S / N ratio of the high-frequency signal f1 is poor. It is necessary to increase the reception sensitivity of the signal f1. On the other hand, since the S / N ratio is equal to or higher than the predetermined value Vth and the S / N ratio of the high-frequency signal f1 is good in the period T2, the reception sensitivity of the high-frequency signal f1 is lowered by setting the connection state in FIG. Can be lowered.

  Although the embodiment of the GPS receiver has been described above, the present invention is not limited to such an embodiment, and can be implemented in various forms without departing from the spirit of the invention. Hereinafter, a modification will be described.

  (Modification 1) An example of an electronic device using a GPS receiver will be described. FIG. 4 is a schematic diagram illustrating a configuration of a mobile phone that is an electronic device using the GPS receiver according to the first modification. In the cellular phone 1200, a main body portion 1210 including operation buttons and a display portion 1220 including a liquid crystal panel are connected to be foldable by a hinge portion 1230. A GPS receiver 1 (not shown) is incorporated in the main body 1210, and current position information of the mobile phone 1200 can be known. In addition, the electronic device using the GPS receiver 1 can be applied to a wristwatch, a PDA, a portable music player, and the like that are small battery driven and require low power consumption.

The circuit diagram which shows the structure of the GPS receiver provided with RF receiving circuit which concerns on 1st Embodiment. The circuit diagram which shows another connection state of the switch circuit of RF receiving circuit. The timing diagram explaining operation | movement of a determination part. Schematic which shows the structure of the mobile telephone which is an electronic device using the GPS receiver which concerns on the modification 1. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... GPS receiver, 10 ... Antenna, 20 ... Power supply, 100 ... RF receiver circuit, 101 ... LNA, 102 ... Multiplier circuit, 103, 105, 107, 115 ... Switch circuit, 104 ... Nth order filter, 106 ... AGC circuit , 108 ... frequency synthesizer circuit, 109 ... VCO, 110 ... PLL, 111 ... primary filter, 112 ... GC circuit, 113, 114 ... ADC, 116, 117 ... current source, 200 ... baseband processing circuit, 201 ... correlator, 202: S / N calculation unit, 203: determination unit, 1200: mobile phone, 1210 ... main body unit, 1220 ... display unit, 1230 ... hinge unit.

Claims (7)

An antenna for receiving high-frequency signals from positioning satellites;
A low-noise amplifier circuit that amplifies the high-frequency signal received by the antenna and outputs an amplified signal;
A frequency synthesizer circuit that outputs a sine wave signal of a predetermined frequency;
A multiplication circuit for outputting a multiplication signal obtained by multiplying the amplified signal and the sine wave signal;
An nth order filter in which RC filters are stacked in n stages (n is an integer of 2 or more);
An automatic gain control circuit cascaded with the output of the nth order filter;
A primary filter;
A gain control circuit cascaded with the output of the primary filter;
An analog-digital conversion circuit;
When the S / N ratio of the high-frequency signal received by the antenna is less than a predetermined value, the multiplication signal is input to the nth-order filter, and the output signal of the automatic gain control circuit is input to the analog-digital conversion circuit. When the input first connection state and the S / N ratio of the high-frequency signal received by the antenna are equal to or greater than a predetermined value, the multiplication signal is input to the primary filter, and the output signal of the gain control circuit A switching section for switching between a second connection state for inputting the signal to the analog-digital conversion circuit;
including,
An RF receiving circuit characterized by the above. The RF receiving circuit according to claim 1,
The analog-digital conversion circuit is composed of m (m is an integer of 2 or more) bits, and when the S / N ratio of the high-frequency signal received by the antenna is less than a predetermined value, the output of the automatic gain control circuit The RF is characterized in that the signal is processed with m bits and the output signal of the gain control circuit is processed with less than m bits when the S / N ratio of the high-frequency signal received by the antenna is a predetermined value or more. Receiver circuit. The RF receiving circuit according to claim 1 or 2,
The frequency synthesizer circuit includes a voltage-controlled oscillator and a phase-locked loop circuit, and when the S / N ratio of the high-frequency signal received by the antenna is less than the predetermined value, the low-noise amplifier circuit and the voltage control circuit When a predetermined current flows through the oscillator and the S / N ratio of the high-frequency signal received by the antenna is equal to or higher than the predetermined value, the low-noise amplifier circuit and the voltage-controlled oscillator are less than the predetermined current. An RF receiving circuit characterized in that a current flows. The RF receiving circuit according to any one of claims 1 to 3,
The switching unit stops power supply to the primary filter and the gain control circuit when the S / N ratio of the high-frequency signal received by the antenna is less than the predetermined value, and the antenna receives the signal. An RF receiving circuit, wherein power supply to the n-th order filter and the automatic gain control circuit is stopped when the S / N ratio of the high-frequency signal is equal to or greater than the predetermined value.   5. The RF receiver circuit according to claim 1, wherein the switching unit of the RF receiver circuit is in the first connection state when activated. 6.   A GPS receiver comprising the RF receiving circuit according to claim 1.   An electronic apparatus comprising the GPS receiver according to claim 6.

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