JP2010087259A - Method of manufacturing nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the method of manufacturing a nonvolatile storage device, which prevents doping profiles of rectifier elements between layers of laminated memory cells from being different. <P>SOLUTION: In the method of manufacturing the nonvolatile storage device, memory cells having a first wiring extending in a first direction, a second wiring extending in a second direction which is not in parallel with the first direction, a recording layer sandwiched between the first wiring and the second wiring, and a rectifier cell 30 for giving orientation to the polarization of voltage applied to the recording layer are laminated on a plurality of layers. The step of forming the rectifier elements includes the steps of forming a p-type semiconductor layer 30a, forming an adjusting layer 31 of an n-type semiconductor on the principal surface of the p-type semiconductor layer, and forming a layer 30b of the n-type semiconductor whose dopant density is lower than the dopant density of the adjusting layer on the principal surface of the adjusting layer. At least one of the dopant density and the thickness dimension of the adjusting layer is made to differ for each laminated memory cell layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile memory device.

  In a NAND-type nonvolatile memory device using a transistor, device operation has become difficult due to the influence of a so-called short channel effect accompanying the miniaturization of the device. The “short channel effect” is a phenomenon that occurs when the distance between the source portion and the drain portion is reduced due to miniaturization of the device, and includes, for example, an increase in leakage current generated between the source and the drain. Therefore, a memory device that replaces the memory device using a transistor is required. As one example, a nonvolatile memory device (resistance-change memory, ReRAM) that uses the characteristic that the resistance of a substance changes when an electric field pulse is applied to a transition metal insulating film or the like has been studied (for example, Patent Document 1). See).

Here, the resistance change type memory is difficult to be multi-valued as compared with the NAND type nonvolatile memory device. Therefore, it is considered to stack memory cells in order to increase the storage capacity.
However, when memory cells are stacked, the thermal history differs between the memory cells formed in the lower layer and the memory cells formed in the upper layer. That is, the lower memory cell formed earlier is repeatedly affected by the thermal process of the memory cell formed in the upper layer. Therefore, for example, the doping profile of the rectifying element of the memory cell formed in the lower layer (for example, a diode for selecting a memory cell) changes, and the doping profile of the rectifying element differs for each stacked layer. There is a risk that. If the doping profile of the rectifying element is different, the characteristics of the rectifying element such as a withstand voltage may vary accordingly.
JP-A-2005-317787

  The present invention provides a method for manufacturing a non-volatile memory device that can prevent the doping profiles of rectifying elements between layers of stacked memory cells from being different.

  According to one aspect of the present invention, a first wiring extending in a first direction, a second wiring extending in a second direction non-parallel to the first direction, and the first wiring Reversible between the first state and the second state by a current sandwiched between the wiring and the second wiring and supplied through the first wiring and the second wiring. And a rectifying element that gives direction to the polarity of a voltage applied to the recording layer, and a method of manufacturing a nonvolatile memory device in which a plurality of layers are stacked. The step of forming the rectifying element includes the step of forming a p-type semiconductor layer, the step of forming an n-type semiconductor adjustment layer on the main surface of the p-type semiconductor layer, and the adjustment on the main surface of the adjustment layer. Forming an n-type semiconductor layer having a dopant concentration lower than the dopant concentration of the layer, Varying at least one of the dopant concentration and thickness for each layer of the stacked memory cell, method of manufacturing the nonvolatile memory device according to claim is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the non-volatile memory device which can suppress that the doping profile of the rectifier element in each layer of the laminated | stacked memory cell becomes different is provided.

  Hereinafter, embodiments of the present invention will be illustrated with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and detailed description is abbreviate | omitted suitably.

1 to 3 are schematic views for illustrating an example of a nonvolatile memory device manufactured by the method of manufacturing a nonvolatile memory device according to this embodiment.
First, an example of a nonvolatile memory device manufactured by the method for manufacturing a nonvolatile memory device according to the present embodiment will be illustrated with reference to FIGS.

FIG. 1 is a schematic diagram of the nonvolatile memory device 2. 1A is a schematic perspective view of the nonvolatile memory device 2, and FIG. 1B is a schematic circuit diagram of the nonvolatile memory device 2.
FIG. 2 is a schematic cross-sectional view of the nonvolatile memory device 2. 2A is a schematic cross-sectional view of the nonvolatile memory device 2 viewed from the first direction (X-axis direction), and FIG. 2B is a cross-sectional view taken along line AA in FIG. It is.
Note that one recording unit 40 provided in a region where one first wiring 20 and one second wiring 50 intersect is one recording unit element, which is referred to as a “memory cell”.
1 and 2 exemplify the memory cell layer formed in the lowermost layer, and the upper-layer memory cell formed so as to be stacked thereon is omitted.
FIG. 3 is a schematic cross-sectional view for illustrating stacked memory cells.
FIG. 3 exemplifies memory cells stacked in two layers as an example. 3A illustrates a case where word lines of stacked memory cells are provided for each layer, and FIG. 3B illustrates a case where word lines of stacked memory cells are shared. Is.

  As shown in FIG. 1A, the nonvolatile memory device 2 includes a substrate 10 and a first wiring 20 (provided on the main surface of the substrate 10) extending in a first direction (X-axis direction). Bit line BL), a second wiring 50 (word line WL) extending in a second direction (Y-axis direction) non-parallel to (intersecting with) the first direction, the first wiring 20 and the first wiring Can be reversibly transitioned between the first state and the second state by the current sandwiched between the two wirings 50 and supplied via the first wiring 20 and the second wiring 50. Recording layer 44. In addition, a rectifying element 30 is provided between the first wiring 20 and the recording layer 44 so as to be sandwiched between them. Here, the “main surface” means a surface (in FIG. 1) perpendicular to the direction in which the first wiring 20, the rectifying element 30, the recording layer 44, etc. are stacked (in FIG. 1, the Z-axis direction; the vertical direction). , XY plane).

In addition, as shown in FIG. 2, electrode layers 42 and 46 that sandwich the recording layer 44 may be provided on both sides of the recording layer 44 in the Z-axis direction. Here, the recording layer 44 and the electrode layers 42 and 46 are collectively referred to as a “recording unit 40”. Further, a barrier layer 32 may be provided between the first wiring 20 and the rectifying element 30.
A conductive material can be used for the wiring L (the first wiring 20 and the second wiring 50). Further, it can be a material having heat resistance. For example, tungsten (W) can be used as a material having conductivity and heat resistance.

  As shown in FIGS. 1 and 2, a stopper layer 52 required in the manufacturing process (planarization process) is provided between the recording layer 44 (recording unit 40) and the second wiring 50. can do. In this case, for example, when a CMP (Chemical Mechanical Polishing) method is used in the planarization step, the stopper layer 52 can be a CMP stopper layer. However, the stopper layer 52 is not necessarily required and may be provided as necessary. For example, if the electrode layer 46 is sufficiently thick and the electrode layer 46 is given the function of a stopper layer, the stopper layer 52 need not be provided.

  Here, if the stopper layer 52 and the second wiring 50 are formed of the same material, the two layers are integrated to serve as the second wiring. The second wiring in such a case is referred to as “second wiring 54”. Therefore, the second wiring 54 has a protruding portion (stopper layer 52) protruding toward the recording layer 44 in each memory cell.

The rectifying element 30 has a rectifying characteristic and is provided to give direction to the polarity of the voltage applied to the recording layer 44. As the rectifying element 30, for example, a PN junction diode, a Zener diode, a Schottky diode, or the like can be used. The configuration of the rectifying element 30 will be described later.
FIG. 1 illustrates the case where the rectifying element 30 is provided between the bit line BL and the electrode layer 42, but the rectifying element 30 is provided between the word line WL and the electrode layer 46. Also good. The rectifying element 30 may be provided in a region other than the region where the bit line BL and the word line WL are opposed to each other.
A barrier layer 32 can be provided between the first wiring 20 and the rectifying element 30 in order to suppress diffusion of elements between them.

Next, the recording unit 40 will be illustrated with reference to FIG.
As illustrated in FIG. 2, the recording unit 40 includes a recording layer 44 and electrode layers 42 and 46 that sandwich the recording layer 44 from the Z-axis direction (vertical direction).
The electrode layers 42 and 46 are provided as necessary so that the recording layer 44 can easily obtain electrical connection. The electrode layers 42 and 46 may also have a function as a barrier layer for suppressing element diffusion between the recording layer 44 and constituent elements in the Z-axis direction (vertical direction), for example. Good.

Further, in order to efficiently heat the recording layer 44 in the erasing (reset) operation, a heater layer (having a resistivity of about 10 ⁻⁵ Ωcm or more) is provided on the cathode side (here, the word line WL side) of the recording layer 44. Material) may be provided. In this case, a barrier layer can be provided between the heater layer and the word line WL.

Next, the recording layer 44 is illustrated.
As will be described later, the nonvolatile memory device 2 can change the voltage applied to each recording unit 40 by a combination of potentials applied to the first wiring 20 and the second wiring 50. Information can be recorded (written) or erased according to the characteristics (for example, resistance value) of the recording unit 40 at that time. Therefore, the characteristics of the recording layer 44 are changed depending on the applied voltage. Examples of the recording layer 44 include a variable resistance layer whose resistance value can be reversibly transitioned and a phase change layer capable of reversibly transitioning between a crystalline state and an amorphous state by an applied voltage. can do.

Moreover, as a material of the recording layer 44, a metal oxide can be illustrated, for example. In this case, for example, chromium (Cr), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), scandium (Sc), Yttrium (Y), Thorium (Tr), Manganese (Mn), Iron (Fe), Ruthenium (Ru), Osmium (Os), Cobalt (Co), Nickel (Ni), Copper (Cu), Zinc (Zn), Cadmium (Cd), aluminum (Al), gallium (Ga), indium (In), silicon (Si), germanium (Ge), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), Alternatively, oxides such as so-called rare earth elements from lanthanum (La) to lutetium (Lu) can be used.
Alternatively, aluminum oxide (Al ₂ O ₃ ), copper oxide (CuO), silicon oxide (SiO ₂ ), or the like can be used.

Moreover, it can also be set as complex oxide. In this case, for example, barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium titanate (CaTiO ₃ ), potassium niobate (KNbO ₃ ), bismuth iron oxide (BiFeO ₃ ), lithium niobate (LiNbO) _3), sodium vanadate _(Na 3 _VO 4), vanadium iron (FeVO _3), titanate vanadium (TiVO _3), chromic acid vanadium (CRVO _3), vanadium, nickel (NiVO _3), magnesium vanadate (MgVO _3), calcium vanadate (Cavo _3), vanadium lanthanum (LaVO _3), molybdate vanadium (VMoO _5), molybdate vanadium _(V 2 _MoO 8), lithium vanadate _{(LiV 2 O} 5), silicates Magne Sium (Mg ₂ SiO ₄ ), magnesium silicate (MgSiO ₃ ), zirconium titanate (ZrTiO ₄ ), strontium titanate (SrTiO ₃ ), lead magnesium acid (PbMgO ₃ ), lead niobate (PbNbO ₃ ), barium borate (BaB ₂ O ₄ ), lanthanum chromate (LaCrO ₃ ), lithium titanate (LiTi ₂ O ₄ ), lanthanum cuprate (LaCuO ₄ ), zinc titanate (ZnTiO ₃ ), calcium tungstate (CaWO ₄ ), etc. can do.

Also, a chalcogenide-based variable resistance material can be used. Chalcogenide is a general term for compounds containing group 16 elements such as Se and Te, and is derived from the fact that group 16 elements are called chalcogens. This chalcogenide-based material is a kind of variable resistance material that can reversibly transition between a crystalline state and an amorphous state by applying a voltage.
Further, an inter-element insulating layer 70 is provided between the memory cells as shown in FIG.

Further, a contact plug (not shown) is provided on the outside in the extending direction of the wiring L (first wiring 20 and second wiring 50; bit line BL and word line WL) with reference to the position of the memory cell. The contact plug is connected to a peripheral circuit (not shown) such as a read / record circuit (write circuit) for recording (writing) and reading data. A current is passed through the recording unit 40 through the contact plug and the wiring L, whereby various operations such as recording (writing) and erasing of the recording unit 40 can be performed.
As described above, the nonvolatile memory device 2 in which the recording unit 40 is provided at the intersection of the bit line BL and the word line WL is called a so-called cross-point nonvolatile memory device (memory).

  In addition, a nonvolatile memory device having a single memory cell layer can be used, but the memory cells can be stacked in the Z-axis direction (vertical direction) in order to increase the storage capacity. In this case, for example, as shown in FIG. 3A, an interlayer insulating film 71 can be provided so that the second wiring 50 (word line WL) is provided for each layer. Further, for example, as shown in FIG. 3B, the second wirings 50 (word lines WL) can be stacked so as to be shared. 3 illustrates the memory cell layer stacked in two layers as an example, but it may be stacked in three or more layers.

  Here, when the layers of the memory cells are stacked, the thermal history is different between the memory cells formed in the lower layer and the memory cells formed in the upper layer. That is, the lower memory cell formed earlier is repeatedly affected by the thermal process of the memory cell formed in the upper layer. In particular, the doping profile may change when the rectifying element 30 is affected by the thermal process of a memory cell formed later.

FIG. 4 is a schematic diagram for illustrating an example of a doping profile of the rectifying element 30. FIG. 4 illustrates a case where a pin diode is used for the rectifying element 30 as an example.
As shown in FIG. 4, the rectifying element 30 is provided with a first layer 30a, a second layer 30b, and a third layer 30c.

  The first layer 30a is a p-type semiconductor layer (p layer) to which a Group III element of the periodic table such as B (boron) is added. The third layer 30c is an n-type semiconductor layer (n layer), and is added with a group V element of the periodic table such as P (phosphorus), As (arsenic), Sb (antimony). The second layer 30b provided so as to be sandwiched between the first layer (p layer) 30a and the third layer (n layer) 30c is also an n-type semiconductor layer. It is a high purity layer (i layer) with a small amount of group element added.

  In the rectifying element 30 having such a configuration, when a bias voltage is applied in the reverse direction, a high breakdown voltage characteristic can be obtained by the high resistance second layer (i layer) 30b. Further, when a bias voltage is applied in the forward direction, variable resistance characteristics can be obtained by the second layer (i layer) 30b.

  However, under the influence of the thermal process of the upper memory cell formed later, for example, thermal diffusion occurs at the junction between the first layer (p layer) 30a and the second layer (i layer) 30b. The doping profile may change. And since the state of the doping profile change is different for each layer of the memory cell, the breakdown voltage characteristic, variable resistance characteristic and the like may be different for each layer.

  Therefore, in the method for manufacturing the nonvolatile memory device according to the present embodiment, an adjustment layer is formed between the first layer (p layer) 30 and the second layer (i layer) 30b, and the thermal history is obtained. Considering this, the dopant concentration, thickness dimension, and the like of the adjustment layer 31 are changed for each memory cell layer to be stacked. And the adjustment layer in which dopant concentration, thickness dimension, etc. differ is formed for every layer, the influence of a thermal process is suppressed and the change of a doping profile is suppressed. Details regarding the formation of the adjustment layer will be described later (see FIG. 6).

As mentioned above, although an example of the non-volatile storage device 2 was illustrated, it is not necessarily limited to the configuration described above, and can be changed as appropriate.
For example, the number, arrangement, and the like of the first wiring 20, the second wiring 50, and the memory cells are not limited to those illustrated in FIG. 1, and can be changed as appropriate.
In the case described above, the first wiring 20 is called a “bit line BL” and the second wiring 50 is called a “word line WL”. Conversely, the first wiring 20 is called a “word line”. WL ”and the second wiring 50 may be called“ bit line BL ”.
Further, the same kind of wiring (for example, two bit lines BL or two word lines WL) may be arranged at both ends in the Z-axis direction (vertical direction) of the nonvolatile memory device 2, and different kinds of wiring (for example, Bit lines BL and word lines WL) may be arranged.

Next, the operation of the nonvolatile memory device 2, that is, the case where the recording (writing) operation, the reading operation, and the erasing operation to the memory cell are executed will be illustrated.
In order to perform a recording (writing) operation, a voltage is applied to a selected memory cell, a potential gradient is generated in the memory cell, and a current pulse is supplied. In this case, for example, the bit line BL may be grounded and a negative potential may be applied to the word line WL so that the potential of the word line WL is relatively lower than the potential of the bit line BL.
Since the selected memory cell has electronic conductivity due to phase change or the like, the recording (writing) operation is completed.
Note that the current pulse for the recording (writing) operation may be generated by creating a state in which the potential of the word line WL is relatively higher than the potential of the bit line BL.

  The read operation is performed by passing a current pulse through the selected memory cell and detecting the resistance value of the memory cell. However, the current pulse needs to have a minute value that does not cause a change in resistance of the material constituting the memory cell.

  In order to perform the erase (reset) operation, the selected memory cell may be Joule-heated with a large current pulse to restore the resistance state of the memory cell.

Next, a method for manufacturing the nonvolatile memory device according to this embodiment is illustrated.
5 and 7 to 9 are schematic process cross-sectional views for illustrating the method for manufacturing the nonvolatile memory device according to this embodiment.
In the present embodiment, as an example, a case where the cross-point type nonvolatile memory device 2 illustrated in FIGS. 1 to 4 is manufactured in a wiring formation process after forming a peripheral circuit will be described.

  First, as shown in FIG. 5A, on the main surface of the substrate 10, the first wiring 20 (bit line), the barrier layer 32, the rectifying element 30, the electrode layer 42, the recording layer 44, the electrode layer 46, The stopper layer 52 and each layer to be the etching mask 60 are formed in this order from the bottom. Examples of the forming method include a sputtering method, a thermal CVD (Chemical Vapor Deposition) method, and a plasma CVD method.

An example of the material of the first wiring 20 is tungsten. Examples of the rectifying element 30 include the pin (p-type semiconductor / insulator / n-type semiconductor) diode described above. The material of the stopper layer 52 is the same material as that of the second wiring 50 (word line) (for example, tungsten). As a material of the etching mask 60, for example, SiO ₂ can be exemplified. The barrier layer 32 and the electrode layers 42 and 46 are provided as necessary. Examples of these materials include titanium and titanium nitride.

Here, the formation of the rectifying element 30 will be further illustrated.
FIG. 6 is a schematic cross-sectional view for illustrating the formation of the rectifying element 30.
In forming the rectifying element 30, the LP (Low Pressure) -CVD method is used to form the rectifying element 30 while simultaneously flowing a material gas such as SiH ₄ gas, H ₂ gas, and N ₂ gas and a doping gas. Each layer to be formed can be formed.

For the formation of the first layer (p layer) 30a, B ₂ H ₆ gas, BCl ₃ gas or the like can be used as a doping gas. And after forming the 1st layer 30a so that it may become a predetermined film thickness, the adjustment layer 31 is formed in the main surface of the 1st layer 30a. After the adjustment layer 31 is formed, the second layer (i layer) 30b and the third layer (n layer) 30c are sequentially formed in this order.

For the formation of the adjustment layer 31, the second layer 30b, and the third layer 30c, which are n-type semiconductor layers, a PH ₃ gas can be used as a doping gas. However, the present invention is not limited to this, and a doping gas that can be used when forming an n-type semiconductor can be used. For example, AsH ₃ gas can be used.

Then, the dopant concentration is controlled by changing the flow rate of the doping gas in accordance with the functions of the adjustment layer 31, the second layer 30b, and the third layer 30c (flow rate ratio between the material gas and the doping gas). To control the dopant concentration). For example, in the formation of the third layer 30c, the dopant concentration is increased (for example, the carrier concentration is 10 ²⁰ / cm ³ or more), and in the second layer 30b, the dopant concentration is decreased (for example, the carrier concentration is 10 ¹⁶ / cm 3). ³ or more).

  As described above, when the memory cell layers are stacked, the thermal history is different between the rectifying element 30 formed in the lower layer and the rectifying element 30 formed in the upper layer. That is, the lower rectifier element 30 formed earlier is repeatedly affected by the thermal process of the memory cell formed in the upper layer. For example, when forming each layer constituting the rectifying element 30 using the LP-CVD method, heat of about 550 ° C. is applied. When this heat is transmitted to the previously formed memory cell, the acceptor is thermally diffused from the first layer (p layer) 30a to the second layer (i layer) 30b, and the doping profile of the rectifying element 30 is May change.

  Therefore, in the present embodiment, the adjustment layer 31 is formed, and the dopant concentration of the adjustment layer 31 is changed for each layer of the memory cells to be stacked in consideration of the thermal history. The adjustment layer 31 is formed so that the dopant concentration is higher than the dopant concentration of the second layer (i layer) 30b. For example, the lower the lower layer, the higher the dopant concentration of the adjustment layer 31. On the contrary, the higher the upper layer, the lower the dopant concentration of the adjustment layer 31. In the uppermost layer, the dopant concentrations of the second layer 30b and the adjustment layer 31 are made substantially the same. The adjustment layer 31 may not be formed in the uppermost layer.

  The case where the dopant concentration of the adjustment layer 31 is controlled by supplying the material gas for forming polysilicon and the doping gas and controlling the flow rate ratio of the material gas and the doping gas is illustrated. The dopant concentration of the adjustment layer 31 may be controlled by controlling the ions implanted after forming the silicon film. However, considering the uniformity of the dopant concentration and the like, it is preferable to control the dopant concentration of the adjustment layer 31 by controlling the flow ratio of the material gas and the doping gas.

In the case described above, the dopant concentration of the adjustment layer 31 is changed. However, the thickness of the adjustment layer 31 can be changed by making the dopant concentration of the adjustment layer 31 substantially constant. For example, the thickness dimension of the adjustment layer 31 can be made thicker as it goes down, and the thickness dimension of the adjustment layer 31 can be made thinner as it goes up. In the uppermost layer, the adjustment layer 31 can be formed very little or not.
In addition, the dopant concentration and thickness dimension of the adjustment layer 31 can be changed as necessary.

In other words, the step of forming the rectifying element 30 includes the step of forming the first layer (p layer) 30a, which is a p-type semiconductor layer, and the n-type semiconductor layer on the main surface of the first layer (p layer) 30a. A step of forming the adjustment layer 31, a step of forming a second layer (i layer) 30b, which is an n-type semiconductor layer having a dopant concentration lower than the dopant concentration of the adjustment layer 31, on the main surface of the adjustment layer 31, A third layer (n layer) 30c, which is an n-type semiconductor layer having a dopant concentration higher than the dopant concentration of the second layer (i layer) 30b, is formed on the main surface of the second layer (i layer) 30b. And a step of performing.
Then, at least one of the dopant concentration and the thickness dimension of the adjustment layer 31 is changed for each layer of the stacked memory cells.
Further, the dopant concentration of the adjustment layer 31 is increased as it is provided in the lower layer.
Moreover, the thickness dimension of the adjustment layer 31 can also be made thicker as what is provided in a lower layer.

  Further, when forming the adjustment layer 31 using the LP-CVD method, by supplying a material gas for forming polysilicon and a doping gas, and controlling a flow rate ratio between the material gas and the doping gas, The dopant concentration of the adjustment layer 31 can be controlled.

  In this process of stacking the memory cell layers, if the adjustment layer 31 is provided in the rectifying element 30 and its dopant concentration, thickness dimension, etc. are appropriate for each layer of the stacked memory cells, the thermal history of The influence can be suppressed. That is, even if the acceptor is thermally diffused from the first layer (p layer) 30a, the acceptor is prevented from diffusing to the second layer (i layer) 30b by being blocked by the adjustment layer 31 having a high dopant concentration. be able to. As a result, since the doping profile can be prevented from changing, the characteristics of the rectifying element 30 (for example, withstand voltage characteristics and variable resistance characteristics) can be stabilized.

It should be noted that when the uppermost memory cell is formed, the dopant concentration of the adjustment layer 31 is such that the doping profile of the rectifying element 30 between the layers of the stacked memory cells becomes substantially the same due to the thermal history so far. It is preferable to use a thickness dimension.
By doing so, the acceptor is thermally diffused from the first layer (p layer) 30a, which is a p-type semiconductor layer, to the adjustment layer 31 by the thermal history until the uppermost memory cell is formed. Thus, the doping profile of the rectifying element 30 between the layers of the stacked memory cells can be made substantially the same.

  In this case, after the uppermost memory cell is formed, there is further provided a step of performing a heat treatment (for example, low-temperature annealing) that makes the doping profile of the rectifying element 30 substantially the same between the layers of the stacked memory cells. May be.

  Next, returning to FIG. 5B, the illustration of the method for manufacturing the nonvolatile memory device 2 is continued. As shown in FIG. 5B, an etching process is performed in the first direction (X-axis direction) of the multilayer body (the one in which the first wiring 20 to the etching mask 60 are laminated) to form an element isolation region 80. Let The etching process is performed up to the interface depth between the substrate 10 and the first wiring 20.

Next, as shown in FIG. 5C, the first insulating layer 70 </ b> A is formed on the surface of the element isolation region 80 using, for example, a plasma CVD (Chemical Vapor Deposition) method. As the raw material gas can be exemplified for example, _SiH 4 / _{O 2.} Thereby, a high-quality insulating layer with few impurities can be formed on the side wall of the memory cell including the side surfaces of the recording unit 40 and the rectifying element 30.
The first insulating layer 70 </ b> A is formed on the surface of the element isolation region 80 and the main surface of the etching mask 60. Therefore, the trench 90 is formed in the element isolation region 80 and its vicinity.

  Then, before the opening 90a of the groove 90 is closed by the first insulating layer 70A, the formation of the first insulating layer 70A by the plasma CVD method is stopped. In this case, the width of the opening 90a (opening width L1) is set to a width (for example, about 5 nm or more) through which the coating agent can pass in the subsequent coating process. In addition, the width | variety through which an coating agent can pass in an application | coating process shall be called "application agent passage width."

  If the formation of the first insulating layer 70A by the plasma CVD method is not stopped at this stage, it is considered that the first insulating layer 70A is deposited relatively in the vicinity of the opening 90a. Therefore, there is a possibility that a gap is formed in the element isolation region 80 after the opening 90a is closed by the first insulating layer 70A. In particular, when the aspect ratio of the element isolation region 80 is high, there is a high possibility that voids are formed. And when a space | gap is formed, there exists a possibility that the insulation of the element isolation region 80 may fall. Therefore, as described above, the formation of the first insulating layer 70A by the plasma CVD method is stopped before the opening 90a of the groove 90 is closed by the first insulating layer 70A.

  Here, in order to make the shape of the groove 90 appropriate, it is preferable to increase the anisotropy of deposition by the plasma CVD method. By doing so, it becomes difficult for the opening 90a to be blocked by the first insulating layer 70A. In order to increase the anisotropy of deposition, for example, the ratio of ions in the plasma atmosphere may be increased by changing process conditions such as bias power and gas pressure.

  In order to secure an appropriate opening width L1, the upper surface of the stacked body (main surface of the stacked body) is flattened by using, for example, a CMP (Chemical Mechanical Polishing) method or the like as necessary. The region 80 may be etched (not shown).

  Next, as shown in FIG. 5D, the second insulating layer 70B is formed on the surface of the first insulating layer 70A by using, for example, a spin coat method. Examples of the coating agent used at this time include polysilazane. When the second insulating layer 70B is formed by filling the groove 90 with the coating agent, the element isolation region 80 is embedded by the first insulating layer 70A and the second insulating layer 70B. Become. In this way, the inter-element insulating layer 70 in the first direction (X-axis direction) can be formed.

Next, as shown in FIG. 7A, the upper surface of the stacked body is planarized using, for example, a CMP method. The planarization is performed until the stopper layer 52 is exposed.
Thereby, processing in the first direction (X-axis direction) is completed.

Next, processing in the second direction (Y-axis direction) is performed.
FIG.7 (b) is the BB sectional drawing of the laminated body shown to Fig.7 (a). That is, FIG. 7B shows the laminate shown in FIG. 7A viewed from the second direction (Y-axis direction) to illustrate processing in the second direction (Y-axis direction). FIG.

  First, as shown in FIG. 7C, a layer of the second wiring 50 is formed on the upper surface of the stacked body. As a method for forming the layer of the second wiring 50, for example, a sputtering method can be exemplified. As described above, the same material can be used for the second wiring 50 (word line) and the stopper layer 52, and these can be integrated to form the second wiring 54.

  Next, as shown in FIG. 8A, a layer of the etching mask 60 is formed on the upper surface of the stacked body by using, for example, a plasma CVD method.

  Next, as illustrated in FIG. 8B, an element isolation region 80 is formed by performing an etching process in the second direction (Y-axis direction) of the stacked body. The etching process is performed up to the interface depth between the first wiring 20 and the barrier layer 32.

Next, as shown in FIG. 8C, a first insulating layer 70A is formed on the surface of the element isolation region 80 using, for example, a plasma CVD method. An example of the source gas is SiH ₄ / O ₂ . Thereby, a high-quality insulating layer with few impurities can be formed on the side wall of the memory cell including the side surfaces of the recording unit 40 and the rectifying element 30.
The first insulating layer 70 </ b> A is formed on the surface of the element isolation region 80 and the main surface of the etching mask 60. Therefore, the trench 90 is formed in the element isolation region 80 and its vicinity.

  Then, similarly to the case illustrated in FIG. 5C, the formation of the first insulating layer 70A by the plasma CVD method is stopped before the opening 90a of the groove 90 is closed by the first insulating layer 70A. Like that. In this case, as described above, the width of the opening 90a (opening width L1) is set to be the coating agent passage width (for example, about 5 nm or more).

Also in the processing in the second direction (Y-axis direction), it is preferable to increase the anisotropy of deposition by the plasma CVD method so that the shape of the groove 90 is appropriate.
In order to secure an appropriate opening width L1, the upper surface of the stacked body (main surface of the stacked body) is flattened by using, for example, a CMP (Chemical Mechanical Polishing) method or the like as necessary. The region 80 may be etched (not shown).

  Next, as shown in FIG. 9A, a second insulating layer 70B is formed on the surface of the first insulating layer 70A by using, for example, a spin coat method. Examples of the coating agent used at this time include polysilazane. When the second insulating layer 70B is formed by filling the groove 90 with the coating agent, the element isolation region 80 is embedded by the first insulating layer 70A and the second insulating layer 70B. Become. In this way, the inter-element insulating layer 70 in the second direction (Y-axis direction) can be formed.

Next, as shown in FIG. 9B, the upper surface of the stacked body is planarized using, for example, a CMP method. The planarization is performed until the second wiring 54 is exposed.
Thereby, processing in the second direction (Y-axis direction) is completed.

If necessary, in order to improve the quality of the second insulating layer 70B formed by a coating method, heat treatment such as low-temperature annealing at 400 ° C. or lower can be performed.
Through the above steps, the memory cell layer located at the lowest layer can be formed. When memory cells are formed in multiple layers, the same procedure may be repeated.
Further, when the memory cells are formed in multiple layers, heat treatment such as low-temperature annealing can be performed so that the doping profile of the rectifying element 30 in each layer of the stacked memory cells is substantially the same.

  Note that the interface between the first insulating layer 70A formed by the plasma CVD method and the second insulating layer 70B formed by the spin coat method is formed on the interface of the second insulating layer 70B by heat treatment such as low-temperature annealing. Nitrogen (N) contained in polysilazane may be precipitated. However, since this nitrogen does not affect the insulation, sufficient insulation can be ensured.

  According to the present embodiment, when forming the layer to be the rectifying element 30, the adjustment layer 31 is formed between the first layer (p layer) 30a and the second layer (i layer) 30b, In consideration of the thermal history, the dopant concentration, thickness dimension, and the like of the adjustment layer 31 are changed for each memory cell layer to be stacked. Therefore, since the influence of the thermal process of the memory cell formed in the upper layer can be suppressed, it is possible to suppress the change in the doping profile of the rectifying element 30 formed in the lower layer.

In addition, by appropriately selecting the dopant concentration and the thickness dimension of the adjustment layer 31, the doping profile of the rectifying element 30 between the layers of the memory cell stacked when the uppermost memory cell is formed can be changed to the heat up to that time. It can be made substantially the same by the history.
Further, after the uppermost memory cell is formed, heat treatment such as low-temperature annealing is performed so that the doping profiles of the rectifying elements 30 in the respective layers of the stacked memory cells can be made substantially the same.

  Therefore, the characteristics of the rectifying element 30 (for example, withstand voltage characteristics and variable resistance characteristics) can be stabilized, and the characteristics and quality of the nonvolatile memory device 2 can be improved.

Heretofore, the present embodiment has been illustrated. However, the present invention is not limited to these descriptions.
As long as the features of the present invention are provided, those skilled in the art appropriately modified the design of the above-described embodiments are also included in the scope of the present invention.
For example, the shape, size, material, arrangement, and the like of each element included in the nonvolatile memory device 2 are not limited to those illustrated, but can be changed as appropriate.
Moreover, each element with which each embodiment mentioned above is combined can be combined as much as possible, and what combined these is also included in the scope of the present invention as long as the characteristics of the present invention are included.

It is a schematic diagram for illustrating an example of a nonvolatile memory device. It is a schematic diagram for illustrating an example of a nonvolatile memory device. It is a schematic diagram for illustrating an example of a nonvolatile memory device. It is a schematic diagram for illustrating an example of the doping profile of a rectifier. It is a schematic process sectional view for illustrating a manufacturing method of the nonvolatile memory device concerning this embodiment. It is a schematic cross section for illustrating about formation of a rectifier. It is a schematic process sectional view for illustrating a manufacturing method of the nonvolatile memory device concerning this embodiment. It is a schematic process sectional view for illustrating a manufacturing method of the nonvolatile memory device concerning this embodiment. It is a schematic process sectional view for illustrating a manufacturing method of the nonvolatile memory device concerning this embodiment.

Explanation of symbols

  2 Nonvolatile memory device, 10 substrate, 20 first wiring, 30 rectifying element, 30a first layer, 30b second layer, 30c third layer, 40 recording unit, 42 electrode layer, 44 recording layer, 46 Electrode layer, 50 second wiring, 52 stopper layer

Claims (7)

A first wiring extending in a first direction;
A second wiring extending in a second direction non-parallel to the first direction;
The first state and the second state are sandwiched between the first wiring and the second wiring, and are supplied via the first wiring and the second wiring. A reversible recording layer,
A rectifying element that gives direction to the polarity of the voltage applied to the recording layer;
A method for manufacturing a nonvolatile memory device in which memory cells having a plurality of layers are stacked,
The step of forming the rectifying element includes a step of forming a p-type semiconductor layer, a step of forming an n-type semiconductor adjustment layer on the main surface of the p-type semiconductor layer, and the main surface of the adjustment layer. Forming an n-type semiconductor layer having a dopant concentration lower than that of the adjustment layer,
A method of manufacturing a nonvolatile memory device, wherein at least one of a dopant concentration and a thickness dimension of the adjustment layer is changed for each layer of the stacked memory cells.   The method of manufacturing a nonvolatile memory device according to claim 1, wherein the dopant concentration of the adjustment layer is increased as the lower layer is provided.   3. The method for manufacturing a nonvolatile memory device according to claim 1, wherein a thickness dimension of the adjustment layer is increased as it is provided in a lower layer. 4. When forming the adjustment layer using the LP-CVD method,
A material gas for forming polysilicon and a doping gas are supplied, and a dopant concentration of the adjustment layer is controlled by controlling a flow rate ratio between the material gas and the doping gas. Item 4. The method for manufacturing a nonvolatile memory device according to any one of Items 1 to 3.   The acceptor thermally diffuses from the p-type semiconductor layer to the adjustment layer due to the thermal history until the uppermost memory cell is formed, so that the rectifying element between the stacked memory cells is The method for manufacturing a nonvolatile memory device according to claim 1, wherein the doping profiles are substantially the same.   2. The method of claim 1, further comprising a step of performing a heat treatment so that a doping profile of the rectifying element is substantially the same between the layers of the stacked memory cells after the uppermost memory cell is formed. The manufacturing method of the non-volatile memory device as described in any one of -5.   Forming an n-type semiconductor layer having a dopant concentration higher than the dopant concentration of the n-type semiconductor layer on a main surface of the n-type semiconductor layer having a dopant concentration lower than the dopant concentration of the adjustment layer. The method for manufacturing a non-volatile memory device according to claim 1, wherein:

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