JP2010062418A - Method of manufacturing nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of stably manufacturing a nonvolatile storage device even when the device has a fine structure. <P>SOLUTION: The method of manufacturing the nonvolatile storage device having first wiring extending in a first direction, second wiring extending in a second direction not parallel with the first direction, and a recording layer sandwiched between the first wiring and second wiring and reversibly changing between a first state and a second state with currents supplied through the first wiring and second wiring, includes the stages of: forming a layer of the first wiring; forming the recording layer on a principal surface of the layer of the first wiring; forming a plurality of laminates extending in the first directions by selectively etching the recording layer and the layer of the first wiring; forming a first insulating layer through vapor growth on a surface of a gap between the plurality of laminates; and forming a second insulating layer through coating on the first insulating layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile memory device, and more particularly to a method for manufacturing a nonvolatile memory device including an inter-element insulating layer that electrically insulates elements.

  In a NAND type nonvolatile memory device using a transistor, device operation has become difficult due to the influence of a so-called short channel effect as the device is miniaturized. The “short channel effect” is a phenomenon that occurs when the distance between the source part and the drain part becomes closer due to miniaturization of the device, and specific examples include an increase in leakage current generated between the source and the drain. . For this reason, a memory device that replaces a memory device using a transistor is required, and as one of them, a nonvolatile memory using a characteristic that the resistance of a substance is changed by applying an electric field pulse to a transition metal insulating film or the like. Devices (resistance-change memory, ReRAM) are being studied.

The resistance change type memory reversibly changes between a high resistance state and a low resistance state by applying an electric field pulse to the resistance change film, so that information can be rewritten using this characteristic, and It is a device that stores information so that information is not lost even when the power is turned off. Since the high resistance state and the low resistance state of the variable resistance film are stable, non-volatility can be realized. Since the resistance change type memory does not use a transistor in the memory portion, it can be integrated with higher density, and there is no problem of the short channel effect described above.
Currently, a cross-point type resistance change memory in which a resistance change element is arranged at a portion where a bit line and a word line cross each other is being studied. According to this, the cell area can be 4F ² (“F” is a design rule (minimum design dimension)) that is theoretically the same as that of the NAND-type nonvolatile memory device. Further, the resistance change type memory has an advantage that the degree of integration can be further increased because a plurality of recording portions can be stacked.

In the creation of a cross-point cell, an inter-element insulating layer is generally formed in order to electrically isolate different elements (cells) after processing the cells in the wiring (bit line / word line) direction. Here, when the memory is miniaturized, the aspect ratio (ratio of the depth to the groove width) of the portion where the inter-element insulating layer is formed increases. When the aspect ratio is large, it is relatively difficult to deposit an inter-element insulating layer, and several resistance change type memory manufacturing methods that take this into account have been proposed (for example, Patent Document 1). .
JP 2007-158112 A

  The present invention provides a method for manufacturing a nonvolatile memory device that can be stably manufactured even with a fine structure.

  According to one aspect of the present invention, a first wiring extending in a first direction, a second wiring extending in a second direction non-parallel to the first direction, and the first wiring Reversible between the first state and the second state by a current sandwiched between the wiring and the second wiring and supplied through the first wiring and the second wiring. A non-volatile memory device having a recording layer capable of transitioning to the first wiring layer, the step of forming the first wiring layer, and the recording layer on the main surface of the first wiring layer. A step of forming a layer, a step of selectively etching the recording layer and the first wiring layer to form a plurality of stacked bodies extending in the first direction, and the plurality of layers A step of forming a first insulating layer on the surface of the gap of the stacked body using a vapor phase growth method; and a second insulating layer on the first insulating layer using a coating method. Method for manufacturing a nonvolatile memory device characterized by comprising a step, of forming is provided.

  According to the present invention, there is provided a method for manufacturing a nonvolatile memory device that can be stably manufactured even with a fine structure.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and detailed description is abbreviate | omitted suitably.

  4 to 7 are process diagrams showing a method for manufacturing the nonvolatile memory device according to the embodiment of the present invention. Before describing the manufacturing method of the present embodiment, first, an example (specific example 1) of a nonvolatile memory device manufactured by the manufacturing method according to the embodiment of the present invention will be described with reference to FIGS. To do.

  FIG. 1 is a schematic diagram of a nonvolatile memory device 2 according to a first specific example. FIG. 1A is a schematic perspective view of the nonvolatile memory device 2, and FIG. 1B is a schematic circuit diagram of the nonvolatile memory device 2. FIG. 2 is a schematic cross-sectional view of the nonvolatile memory device 2. 2A is a schematic cross-sectional view of the nonvolatile memory device 2 viewed from the first direction (X-axis direction), and FIG. 2B is a cross-sectional view taken along line AA in FIG. It is.

  As shown in FIG. 1, the nonvolatile memory device 2 includes a substrate 10 and a first wiring 20 (bit line) provided on the main surface of the substrate 10 and extending in a first direction (X-axis direction). BL), a second wiring 50 (word line WL) extending in a second direction (Y-axis direction) non-parallel (crossing) with the first direction, the first wiring 20 and the second wiring Recording that can be reversibly transitioned between the first state and the second state by a current that is sandwiched between the wiring 50 and supplied via the first wiring 20 and the second wiring 50. A layer 44. Further, a rectifying element 30 sandwiched between the first wiring 20 and the recording layer 44 may be provided. Here, the “main surface” means a surface (in FIG. 1) that is perpendicular to the direction in which the first wiring 20, the rectifying element 30, the recording layer 44, etc. are stacked (in FIG. , XY plane).

  In addition, as illustrated in FIG. 2, electrode layers 42 and 46 that sandwich the recording layer 44 may be provided on both sides of the recording layer 44 in the Z-axis direction. Here, the recording layer 44 and the electrode layers 42 and 46 are collectively referred to as a “recording unit 40”. Further, a barrier layer 32 described later may be provided between the first wiring 20 and the rectifying element 30.

  For the wiring L (the first wiring 20 and the second wiring 50), a conductive material can be used, and a heat-resistant material can be used. Specifically, for example, tungsten (W) having conductivity and heat resistance can be given.

  As shown in FIGS. 1 and 2, a stopper layer 52 used in the planarization process in the manufacturing process is provided between the recording layer 44 (recording unit 40) and the second wiring 50. Also good. For example, when CMP (Chemical Mechanical Polishing) is used as the planarization step, the stopper layer 52 becomes a CMP stopper layer. The stopper layer 52 is provided as necessary. For this reason, for example, if the thickness of the electrode layer 46 described later is sufficiently increased to provide the electrode layer 46 with the function of the stopper layer, it is not necessary to provide the stopper layer 52.

  Here, when the materials of the stopper layer 52 and the second wiring 50 are the same, they are integrated and assume the function of the second wiring. The second wiring in such a case is referred to as “second wiring 54”. That is, the second wiring 54 has a protrusion (protrusion 52) that protrudes toward the recording layer 44 in each cell.

  The rectifying element 30 has a rectifying characteristic and is provided to give directionality to the polarity of the voltage applied to the recording layer 44. As the rectifying element 30, for example, a Zener diode, a PN junction diode, a Schottky diode, or the like can be used. FIG. 1 shows a specific example in which the rectifying element 30 is provided between the bit line BL and the electrode layer 42, but the rectifying element 30 is provided between the word line WL and the electrode layer 46. Also good. Further, the rectifying element 30 may be provided in a region other than the region where the bit line BL and the word line WL are opposed to each other.

A barrier layer 32 may be provided between the first wiring 20 and the rectifying element 30 to prevent element diffusion between the two components.
The recording unit 40 will be described in detail later.
One recording unit 40 provided in a region where one first wiring 20 and one second wiring 50 intersect is one recording unit element, which is called a “cell”.

  The voltage applied to each recording unit 40 varies depending on the combination of potentials applied to the first wiring 20 and the second wiring 50, and information is recorded depending on the characteristics (for example, resistance value) of the recording unit 40 at that time. Can be deleted or deleted. An inter-element insulating layer 70 is provided between the cells as shown in FIG.

  A contact plug (not shown) is attached to the outside in the wiring extending direction of the wiring L (the first wiring 20 and the second wiring 50, the bit line BL and the word line WL) with reference to the cell position. The contact plug is connected to a peripheral circuit such as a read / write circuit for writing and reading data (not shown). A current is passed through the recording unit 40 through the contact plug and the wiring L, whereby various operations such as writing and erasing of the recording unit 40 can be performed.

As described above, the nonvolatile memory device 2 is a so-called cross-point nonvolatile memory device (memory) in which the recording unit 40 is provided at a portion where the bit line BL and the word line WL intersect.
The single-layer nonvolatile memory device 2 may be stacked in the Z-axis direction (so-called “multilayer nonvolatile memory device”), which is also included in the nonvolatile memory device 2 according to the first specific example. It is. Hereinafter, the nonvolatile storage device 2 having one layer may be referred to as “unit device 2A”.
In FIG. 1, four first wirings 20 and two second wirings 50 are provided on the main surface, and 16 cells are provided. However, a different number may be provided. .

In the first specific example, the first wiring 20 is referred to as “bit line BL”, and the second wiring 50 is referred to as “word line WL”. Conversely, the first wiring 20 is referred to as “word line WL”. The second wiring 50 may be referred to as a “bit line BL”.
When the nonvolatile memory device 2 is a multilayer nonvolatile memory device, the constituent elements (the first wiring 20, the rectifying element 30, the recording layer 44, the second wiring 50, etc.) of the unit device 2A adjacent in the vertical direction are arranged. The arrangement relationship may be the same or different in the vertical direction. In particular, it may be symmetrical in the vertical direction.

  Further, when the nonvolatile memory device 2 is a multilayer nonvolatile memory device, the first wiring 20 or the second wiring 50 may be shared or shared between the unit devices 2A adjacent in the vertical direction. It does not have to be. Further, the same kind of wiring (two bit lines BL or two word lines WL) may be arranged at both ends in the vertical direction of the nonvolatile memory device 2, or different kinds of wiring (bit lines BL and word lines WL) may be arranged. May be.

Next, the recording unit 40 will be described with reference to FIG.
FIG. 3 is a schematic cross-sectional view illustrating an example of a cell configuration. As shown in FIG. 3, the recording unit 40 includes a recording layer 44 and electrode layers 42 and 46 that sandwich the recording layer 44 in the vertical direction.

  The electrode layers 42 and 46 are provided to obtain electrical connection to the recording layer 44, and are provided as necessary. Further, the electrode layers 42 and 46 may have a function as a barrier layer for preventing, for example, diffusion of elements between the recording layer 44 and upper and lower components.

In order to efficiently heat the recording layer 44 in the reset (erase) operation, a heater layer (having a resistivity of about 10 ⁻⁵ Ωcm or more) is provided on the cathode side (here, the word line WL side) of the recording layer 44. Material) may be provided. In this case, a barrier layer may be provided between the heater layer and the word line WL.

Next, the recording layer 44 will be described.
As described above, in the nonvolatile memory device 2 according to this example, the voltage applied to each recording unit 40 varies depending on the combination of potentials applied to the first wiring 20 and the second wiring 50, and at that time, Information can be recorded or erased depending on the characteristics (for example, resistance value) of the recording unit 40. For this reason, the recording layer 44 can be made of any material whose characteristics change depending on the applied voltage. For example, a variable resistance layer whose resistance value can be reversibly transitioned and a phase change layer capable of reversibly transition between a crystalline state and an amorphous state by an applied voltage can be used.

Specific examples of such materials include metal oxides. Specifically, for example, chromium (Cr), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), scandium (Sc) ), Yttrium (Y), thorium (Tr), manganese (Mn), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn) ), Cadmium (Cd), aluminum (Al), gallium (Ga), indium (In), silicon (Si), germanium (Ge), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi) Or oxides of so-called rare earth elements from lanthanum (La) to lutetium (Lu). Further, aluminum oxide _{(Al 2 O} 3), copper oxide (CuO), also include silicon oxide (SiO ₂₎ or the like.

Moreover, as complex oxides, for example, barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO ₃ ), calcium titanate (CaTiO ₃ ), potassium niobate (KNbO ₃ ), bismuth iron oxide (BiFeO ₃ ). , lithium niobate (LiNbO _3), sodium vanadate _(Na 3 _VO 4), vanadium iron (FeVO _3), titanate vanadium (TiVO _3), chromic acid vanadium (CRVO _3), vanadium, nickel (NiVO ₃₎ , magnesium vanadate (MgVO _3), calcium vanadate (Cavo _3), vanadium lanthanum (LaVO _3), molybdate vanadium (VMoO _5), molybdate vanadium _(V 2 _MoO 8), lithium vanadate (LiV ₂ O _5), magnesium silicate _(Mg 2 _SiO 4), magnesium silicate (MgSiO _3), zirconium titanate (ZrTiO _4), strontium titanate (SrTiO _3), magnesium lead (PbMgO _3), lead niobate (PbNbO ₃ ), Barium borate (BaB ₂ O ₄ ), lanthanum chromate (LaCrO ₃ ), lithium titanate (LiTi ₂ O ₄ ), lanthanum cuprate (LaCuO ₄ ), zinc titanate (ZnTiO ₃ ), calcium tungstate ( CaWO ₄ ) and the like can be formed into a thin film.

  In addition, chalcogenide-based variable resistance materials are also included. Chalcogenide is a general term for compounds containing group 16 elements such as Se and Te, and is derived from the fact that group 16 elements are called chalcogens. This chalcogenide-based material is a kind of variable resistance material that changes between a crystalline state and an amorphous state by applying a voltage.

Next, the case where the memory cell recording, reproducing, and erasing operations are executed will be described.
Recording (set operation) may be performed by applying a voltage to a selected memory cell, generating a potential gradient in the memory cell, and passing a current pulse. For example, a state in which the potential of the word line WL is relatively lower than the potential of the bit line BL is created. For example, if the bit line BL is set to the ground potential, a negative potential may be applied to the word line WL. Since the selected memory cell has electronic conductivity due to phase change or the like, recording (set operation) is completed.

  The current pulse for recording may be generated by creating a state in which the potential of the word line WL is relatively higher than the potential of the bit line BL.

  Reproduction is performed by passing a current pulse through the selected memory cell and detecting the resistance value of the memory cell. However, the current pulse needs to have a minute value that does not cause a change in resistance of the material constituting the memory cell.

  Regarding the erase (reset) operation, the selected memory cell may be Joule-heated with a large current pulse to restore the resistance state of the memory cell.

(Nonvolatile memory device manufacturing method)
(Production Method Example 1)
Next, an example (manufacturing method example 1) of a method for manufacturing the nonvolatile memory device 2 will be described with reference to FIGS.
The method for manufacturing the nonvolatile memory device 2 according to this embodiment includes a step of forming a layer of the first wiring 20 and a step of forming a layer of the recording layer 44 on the main surface of the layer of the first wiring 20. Etching the processed body to form a plurality of stacked bodies extending in the first direction; forming the inter-element insulating layer 70 in a gap (a space generated by etching) between the plurality of stacked bodies; Is provided.

  Here, the step of forming the inter-element insulating layer 70 includes the step of forming the first insulating layer 70A on the surface forming the space generated by etching using the vapor phase growth method (vapor phase deposition method), Forming a second insulating layer 70B on the surface of the first insulating layer 70A using a coating method. Examples of the vapor phase growth method include plasma CVD (Chemical Vapor Deposition), thermal CVD, ALD (Atomic Layer Deposition), and the like. Moreover, as a coating method, a spin coat method etc. are mentioned, for example. Examples of the coating agent used in the coating method include materials containing silicon, oxygen, and nitrogen, and specific examples include polysilazane and HSQ (hydrogen silsesquioxane).

  Further, between the step of forming the recording layer 44 and the step of etching, a planarized stopper layer 52 made of the same material as the material of the second wiring 50 is formed on the main surface of the processed body. You may further provide a process. In this case, after the step of forming the second insulating layer 70B, the main surface of the processed body is flattened until the stopper layer 52 is exposed. After that, by forming a layer of the second wiring 50 on the main surface of the processed body, the stopper layer 52 and the second wiring 50 are integrated, and the protruding portion 52 protruding to the recording layer 44 side in each cell is formed. A second wiring 54 is formed.

Hereinafter, a specific manufacturing method will be described.
4 to 7 are schematic process cross-sectional views showing Manufacturing Method Example 1. FIG. In this example of the manufacturing method, the cross-point type nonvolatile memory device 2 described above with reference to FIG. 2 is manufactured in the wiring formation step after the peripheral circuit is manufactured. The stopper layer 52 is made of the same material as the second wiring 50 (word line), and the second wiring 54 is formed.

  First, as shown in FIG. 4A, the first wiring 20 (bit line), the barrier layer 32, the rectifying element 30, the electrode layer 42, the recording layer 44, the electrode layer 46, and the stopper are formed on the substrate 10. The layer 52 and the layer of the etching mask 60 are formed in this order from the bottom. Examples of the forming method include sputtering, thermal CVD, and plasma CVD.

An example of the material of the first wiring 20 is tungsten. Examples of the rectifying element 30 include a PIN (p-type semiconductor / insulator / n-type semiconductor) diode and an MIM (metal / insulator / metal) capacitor (capacitor). The material of the stopper layer 52 is the same material as that of the second wiring 50 (word line) (for example, tungsten). The material of the etching mask 60, for example, SiO ₂ and the like. The barrier layer 32 and the electrode layers 42 and 46 are provided as necessary. Examples of these materials include titanium and titanium nitride.

  Next, as shown in FIG. 4B, the processed body is etched in the first direction (X-axis direction). The etching is performed up to the interface depth between the substrate 10 and the first wiring 20. Here, the region generated by the etching is referred to as “element isolation region 80”.

Next, as illustrated in FIG. 4C, the first insulating layer 70 </ b> A is formed on the surface where the element isolation region 80 is formed using, for example, plasma CVD. As the raw material gas include, for example, _SiH 4 / _{O 2.} As a result, a high-quality insulating layer with few impurities is formed on the cell sidewall including the side surfaces of the recording unit 40 and the rectifying element 30.

  The first insulating layer 70 </ b> A is formed on the surface where the element isolation region 80 is formed and the main surface of the etching mask 60. As a result, a trench 90 is formed in the element isolation region 80 and in the vicinity thereof.

  Here, the plasma CVD is stopped before the opening 90a of the groove 90 is closed by the first insulating layer 70A. Specifically, it stops when the width of the opening 90a (opening width L1) is a width (for example, about 5 nm or more) through which the coating agent can pass in the subsequent coating process. Hereinafter, the width through which the coating agent can pass in the coating step is referred to as “coating agent passage width”.

  Note that if plasma CVD is not stopped at this stage, the first insulating layer 70A is considered to be deposited in a relatively large amount in the opening 90a, and the element is formed when the opening 90a is blocked by the first insulating layer 70A. There may be voids in the separation region 80. In particular, when the aspect ratio of the element isolation region 80 is high, it is considered that voids are likely to occur. Thereby, the insulation of the element isolation region 80 may be lowered.

  Here, in order to form the groove 90 in an appropriate shape, the anisotropy of deposition by plasma CVD is increased, that is, a relatively large amount of source gas is deposited on the main surface such as the bottom surface of the element isolation region 80. be able to. As a result, the opening 90a is less likely to be blocked by the first insulating layer 70A. In order to increase the anisotropy, for example, the ratio of ions in the plasma atmosphere can be increased by changing process conditions such as bias power and gas pressure.

  Thereafter, in order to secure an appropriate opening width L1 as necessary, the upper surface of the processed body (main surface of the processed body) may be planarized using CMP, for example, or the element isolation region 80 may be etched. Good (not shown).

  Next, as shown in FIG. 4D, the second insulating layer 70B is formed on the surface of the first insulating layer 70A by using, for example, a spin coat method. Examples of the coating agent include polysilazane. As a result, the groove 90 is filled with the coating agent, and the element isolation region 80 is blocked by the first insulating layer 70A and the second insulating layer 70B. Thereby, the inter-element insulating layer 70 in the X-axis direction is formed.

  Next, as illustrated in FIG. 5A, the upper surface of the processed body is planarized using, for example, CMP. The planarization is performed so that the stopper layer 52 is exposed. Thereby, the processing in the X-axis direction is completed.

Next, processing in the Y-axis direction is performed. FIG.5 (b) is the sectional view on the AA line of the processed body represented to Fig.5 (a).
As shown in FIG. 5C, a layer of the second wiring 50 is formed on the upper surface of the processed body. Examples of the forming method include sputtering. As described above, the same material is used for the second wiring 50 (word line) and the stopper layer 52, and these are integrated to form the second wiring 54. Thereafter, as shown in FIG. 6A, a layer of the etching mask 60 is formed on the upper surface of the processed body by using, for example, plasma CVD.

  Next, as shown in FIG. 6B, the processed body is etched in the second direction (Y-axis direction). Etching is performed up to the interface depth between the first wiring 20 and the barrier layer 32. As a result, the element isolation region 80 in the Y-axis direction is formed.

Next, as illustrated in FIG. 6C, the first insulating layer 70 </ b> A is formed on the surface where the element isolation region 80 is to be formed using, for example, plasma CVD. An example of the source gas is SiH ₄ / O ₂ . As a result, a high-quality insulating layer with few impurities is formed on the cell sidewall including the side surfaces of the recording unit 40 and the rectifying element 30.

  The first insulating layer 70 </ b> A is formed on the surface where the element isolation region 80 is formed and the main surface of the etching mask 60. As a result, a trench 90 is formed in the element isolation region 80 and its vicinity. Here, as described above with reference to FIG. 4C, the plasma CVD is stopped before the opening 90a is closed by the first insulating layer 70A. Specifically, it stops when the opening width L1 is a coating agent passage width (for example, about 5 nm or more).

Here, as described above, since the groove 90 is formed in an appropriate shape, the anisotropy of deposition by plasma CVD can be increased.
Thereafter, if necessary, in order to ensure an appropriate opening width L1, the upper surface of the processed body may be planarized using, for example, CMP, or the element isolation region 80 may be etched (not shown).

  Next, as shown in FIG. 7A, the second insulating layer 70B is formed on the surface of the first insulating layer 70A by using, for example, a spin coat method. Examples of the coating agent include polysilazane. As a result, the groove 90 is filled with the coating agent, and the element isolation region 80 is blocked by the first insulating layer 70A and the second insulating layer 70B. Thereby, the inter-element insulating layer 70 in the Y-axis direction is formed.

Next, as illustrated in FIG. 7B, the upper surface of the processed body is planarized using, for example, CMP. The planarization is performed so that the second wiring 54 is exposed. Thereby, the processing in the Y-axis direction is completed.
Thereafter, in order to improve the quality of the second insulating layer 70B formed by a coating method, heat treatment such as low-temperature annealing at 400 ° C. or lower is performed as necessary.

The nonvolatile memory device 2 is manufactured through the above steps. In the case of manufacturing a multilayer nonvolatile memory device, the above procedure may be repeated.
Note that the polysilazane of the second insulating layer 70B is formed on the interface between the first insulating layer 70A formed by plasma CVD and the second insulating layer 70B formed by spin coating by heat treatment such as low-temperature annealing. Nitrogen (N) contained in may be deposited. However, this nitrogen does not affect the insulation, and insulation is fully ensured.

(Effect of this embodiment)
Next, the effect of this embodiment will be described with reference to FIGS.
FIG. 8 is a schematic process cross-sectional view showing a method for manufacturing the nonvolatile memory device 2 according to the comparative example (Comparative Example 1) to be compared with the present embodiment.

In Comparative Example 1, the inter-element insulating layer is formed using only the vapor phase growth method.
First, the steps described above with reference to FIGS. 4A and 4B are performed (FIG. 8A). Thereby, the element isolation region 80 is formed in the X-axis direction. Next, as illustrated in FIG. 8B, the insulating layer 100 is formed on the surface where the element isolation region 80 is formed using only plasma CVD. Here, as described above with reference to FIG. 4C, the trench 90 is formed in the element isolation region 80 and in the vicinity thereof, but plasma CVD is performed until the opening 90 a of the trench 90 is blocked by the insulating layer 100. . Thereby, an inter-element insulating layer in the X-axis direction is formed.

  Thereafter, although not shown, the steps described above with reference to FIGS. 5A to 6B are performed, and thereafter, only the plasma CVD is used in the element isolation region 80 in the Y-axis direction as in the X-axis direction. An insulating layer 100 is formed. The plasma CVD is performed until the opening 90 a is closed by the insulating layer 100. Thereby, an inter-element insulating layer in the Y-axis direction is formed.

  In this case, as described above, it is considered that a relatively large amount of the insulating layer 100 formed by plasma CVD is deposited in the opening 90a. For this reason, as shown in FIG. 8B, there is a possibility that a void 94 is generated in the element isolation region 80. In particular, when the aspect ratio of the element isolation region 80 is high (for example, when the aspect ratio is about 10 or more), it is considered that the air gap 94 is likely to occur. As a result, it becomes difficult to ensure sufficient insulation of the element isolation region 80.

  On the other hand, according to the present embodiment, the element isolation region 80 is blocked by the first insulating layer 70A and the second insulating layer 70B, and thereby the insulation of the element isolation region 80 is sufficiently ensured. .

Next, it demonstrates, contrasting with another comparative example (comparative example 2).
FIG. 9 is a schematic process cross-sectional view illustrating a method for manufacturing the nonvolatile memory device 2 according to Comparative Example 2.

In Comparative Example 2, etching is performed to solve the problem related to Comparative Example 1, that is, the problem that the gap 94 is generated in the element isolation region 80.
First, as shown in FIG. 9A, as in Comparative Example 1, the insulating layer 100A is formed in the element isolation region 80 in the X-axis direction using only plasma CVD. Plasma CVD is performed until the opening 90a is closed by the insulating layer 100A. As a result, as described above with respect to the comparative example 1, there is a possibility that the gap 94 </ b> A is generated in the element isolation region 80.

  Next, as illustrated in FIG. 9B, the element isolation region 80 is etched. Etching is performed until the gap 94A is opened. Thereby, the groove | channel 90 is formed.

  Next, as shown in FIG. 9C, the insulating layer 100B is formed again on the surface of the insulating layer 100A by using only plasma CVD. Plasma CVD is performed until the opening 90a is blocked by the insulating layer 100B. As a result, the air gap 94B may be generated in the element isolation region 80. However, the size of the gap 94B is smaller than the gap 94A generated in the process described above with reference to FIG. Thereafter, the same procedure is repeated to close the element isolation region 80 with the insulating layer 100 made of the insulating layers 100A, 100B, 100C and the like. Thereby, an inter-element insulating layer in the X-axis direction is formed.

  Thereafter, although not shown, the steps described above with reference to FIGS. 5A to 6B are performed, and then the insulating layer 100A, the element isolation region 80 in the Y-axis direction is formed in the same procedure as in the X-axis direction. 100B, 100C, etc. are formed, and the element isolation region 80 is closed by the insulating layer 100. Thereby, an inter-element insulating layer in the Y-axis direction is formed.

As described above, in Comparative Example 2, plasma CVD and etching are performed a plurality of times in each of the X-axis direction and the Y-axis direction. For this reason, process cost becomes comparatively high.
On the other hand, according to this embodiment, the vapor phase growth method and the coating method need only be performed once in each of the X-axis direction and the Y-axis direction. For this reason, process costs are relatively low.

Next, description will be made while comparing with still another comparative example (Comparative Example 3).
FIG. 10 is a schematic process cross-sectional view illustrating the method for manufacturing the nonvolatile memory device 2 according to Comparative Example 3.

In Comparative Example 3, the inter-element insulating layer is formed using only the coating method.
First, the steps described above with reference to FIGS. 4A and 4B are performed (FIG. 10A). Thereby, the element isolation region 80 is formed in the X-axis direction. Next, as illustrated in FIG. 10B, the insulating layer 104 is formed in the element isolation region 80 using only the spin coat method. Thereby, an inter-element insulating layer in the X-axis direction is formed.

  Thereafter, although not shown in the drawing, the steps described above with reference to FIGS. 5A to 6B are performed, and thereafter, only the spin coat method is used for the element isolation region 80 in the Y-axis direction, as in the X-axis direction. Thus, the insulating layer 104 is formed. Thereby, an inter-element insulating layer in the Y-axis direction is formed.

  Here, unlike an insulating layer formed by plasma CVD, an insulating layer formed by spin coating includes a relatively large amount of impurities such as carbon. Therefore, a coating layer having a relatively large amount of impurities is formed on the cell sidewall including the side surfaces of the recording unit 40 and the rectifying element 30. As a result, impurities may diffuse into the recording unit 40 and the like, leading to deterioration of operating characteristics.

  On the other hand, according to the present embodiment, the high-quality first insulating layer 70A with few impurities formed by plasma CVD is formed on the cell sidewall. For this reason, good operating characteristics are ensured.

  Note that a vapor deposition method such as plasma CVD or ALD or a coating method such as spin coating used in this embodiment can be performed at a relatively low temperature such as room temperature. For this reason, according to the present embodiment, deterioration of the element due to heat is suppressed, and good operating characteristics are ensured.

  As described above, according to the present embodiment, the high-quality inter-element insulating layer 70A can be introduced into the element isolation region 80 having a high aspect ratio (particularly in the vicinity of the sidewall of the memory cell portion). Thereby, deterioration and dispersion | variation in switching characteristics can be suppressed. Further, the forming process of the inter-element insulating layer 70 is relatively easy. Furthermore, since the inter-element insulating layer 70 can be formed at a relatively low temperature, deterioration of the element due to heat can be suppressed.

  That is, according to the present embodiment, a non-volatile memory device having good operating characteristics and easy to process and a method for manufacturing the same are provided.

(Production Method Example 2)
Next, another example (manufacturing method example 2) of the method for manufacturing the nonvolatile memory device 2 will be described with reference to FIGS.
Manufacturing method example 2 is basically the same as manufacturing method example 1, except that the main body of the workpiece is between the step of forming first insulating layer 70A and the step of forming second insulating layer 70B. The method further includes a step of planarizing the surface.

Hereinafter, a specific manufacturing method will be described.
11 and 12 are schematic process cross-sectional views showing Manufacturing Method Example 2. FIG. In the present manufacturing method example, similarly to the manufacturing method example 1, the cross-point type nonvolatile memory device 2 described above with reference to FIG. 2 is manufactured in the wiring forming step after the peripheral circuit is manufactured. The stopper layer 52 is made of the same material as the second wiring 50 (word line), and the second wiring 54 is formed.

  First, as shown in FIG. 11A, the first wiring 20 (bit line), the barrier layer 32, the rectifying element 30, the electrode layer 42, the recording layer 44, the electrode layer 46, and the stopper are formed on the substrate 10. The layer 52 and the layer of the etching mask 60 are formed in this order from the bottom. Examples of the forming method include sputtering, thermal CVD, and plasma CVD. The respective materials and the like are as described above with respect to Production Method Example 1.

  Next, as shown in FIG. 11B, the processed body is etched in the X-axis direction. The etching is performed up to the interface depth between the substrate 10 and the first wiring 20. As a result, an element isolation region 80 is formed.

Next, as illustrated in FIG. 11C, the first insulating layer 70 </ b> A is formed on the surface where the element isolation region 80 is to be formed using, for example, plasma CVD. An example of the source gas is SiO ₂ . As a result, a high-quality insulating layer with few impurities is formed on the cell sidewall including the side surfaces of the recording unit 40 and the rectifying element 30.

  Here, as described above with reference to FIG. 4C, the groove 90 is formed in the element isolation region 80 and the vicinity thereof. In plasma CVD, the opening 90a of the groove 90 is blocked by the first insulating layer 70A. Do this until Thereby, process management becomes easy. That is, in the manufacturing method example 1, in the process described above with reference to FIG. 4C, the plasma CVD is stopped before the opening 90a is closed by the first insulating layer 70A. There is no restriction on the stop time. For this reason, the process stop time can be selected from a relatively wide range.

Thereby, the air gap 94 may be generated in the element isolation region 80 as in the comparative example 1 (FIG. 8B).
Here, in order to form the air gap 94 in an appropriate shape, the anisotropy of deposition by plasma CVD is increased, that is, a relatively large amount of source gas is deposited on the main surface such as the bottom surface of the element isolation region 80. be able to. As a result, the opening 90a is closed by the first insulating layer 70A at a relatively late stage, and the upper end (Z-axis positive side end) of the gap 94 is considered to be positioned relatively upward (Z-axis positive side). In order to increase the anisotropy, for example, the ratio of ions in the plasma atmosphere can be increased by changing process conditions such as bias power and gas pressure.

  The width of the gap 94 (gap width L2) may have a coating agent passage width, or may not be present due to the effect of dishing described later. In the case of having a coating agent passage width, the position on the Z axis where the gap width L2 is the coating agent passage width may exist relatively above (the Z axis positive side) such as the stopper layer 52 and the etching mask 60. Alternatively, it may exist below (Z-axis negative side).

  Next, as illustrated in FIG. 12A, the upper surface of the processed body is planarized using, for example, CMP. The planarization is performed until the gap 94 is opened and the groove 90 is formed. Specifically, the processing is performed up to a position in the stopper layer 52 in the Z-axis direction where the opening width L1 becomes the coating agent passage width (for example, about 5 nm or more).

  Here, in the CMP after the groove 90 is formed, the portion of the opening 90a may be more polished. In this specification, this phenomenon is referred to as “dishing”. For this reason, before the flattened surface (workpiece upper surface) reaches the position on the Z-axis of the portion where the gap width L2 is the coating agent passage width, that is, above this position (Z-axis positive side). It is considered that the opening width L1 can reach the coating agent passage width when it is positioned at the position. Alternatively, even when the gap width L2 does not have the coating agent passage width, it is considered that the groove 90 having the opening width L1 having the coating agent passage width may be formed by dishing.

Note that by performing planarization, the aspect ratio of the groove 90 is reduced, and the second insulating layer 70B can be easily formed in a subsequent coating process.
Thereafter, the chemical solution used in CMP is removed by cleaning.

  Next, as shown in FIG. 12B, the second insulating layer 70B is formed on the surface of the first insulating layer 70A by using, for example, a spin coat method. Examples of the coating agent include polysilazane. As a result, the groove 90 is filled with the coating agent, and the element isolation region 80 is blocked by the first insulating layer 70A and the second insulating layer 70B. Thereby, the inter-element insulating layer 70 in the X-axis direction is formed.

  Next, as illustrated in FIG. 12C, the upper surface of the processed body is planarized using, for example, CMP. The planarization is performed so that the stopper layer 52 is exposed. Thereby, the processing in the X-axis direction is completed.

  Thereafter, although not shown, the steps described above with reference to FIGS. 5A to 6B are performed, and then the processing in the Y-axis direction is performed similarly to the processing in the X-axis direction. Thereafter, in order to improve the quality of the second insulating layer 70B formed by a coating method, heat treatment such as low-temperature annealing at 400 ° C. or lower is performed as necessary.

The nonvolatile memory device 2 is manufactured through the above steps. In the case of manufacturing a multilayer nonvolatile memory device, the above procedure may be repeated.
As in Manufacturing Method Example 1, nitrogen may be deposited at the interface between the first insulating layer 70A and the second insulating layer 70B, but this does not impair the insulating properties.

  Even in this manufacturing method example, the same effects as in manufacturing method example 1 can be obtained. That is, by introducing the high-quality inter-element insulating layer 70A in the element isolation region 80 (particularly in the vicinity of the side wall of the memory cell portion) having a high aspect ratio, deterioration and variation in switching characteristics are suppressed. Further, the forming process of the inter-element insulating layer 70 is relatively easy. Furthermore, since the inter-element insulating layer 70 can be formed at a relatively low temperature, deterioration of the element due to heat can be suppressed. That is, a nonvolatile memory device having good operating characteristics and easy to process and a method for manufacturing the same are provided.

(Production Method Example 3)
Next, another example (manufacturing method example 3) of the method for manufacturing the nonvolatile memory device 2 will be described with reference to FIG.
Manufacturing method example 3 is basically the same as manufacturing method example 1, but between the step of forming first insulating layer 70A and the step of forming second insulating layer 70B, element isolation region 80 is provided. And a step of performing etching. That is, an etching process is introduced instead of the planarization process introduced in the manufacturing method example 2.

Hereinafter, a specific manufacturing method will be described.
FIG. 13 is a schematic process cross-sectional view illustrating Manufacturing Method Example 3.
As illustrated in FIG. 13A, the first insulating layer 70 </ b> A is formed in the manner described above with reference to FIGS. 11A to 11C according to the manufacturing method example 2. As a result, a gap 94 is formed in the element isolation region 80.

  Next, as illustrated in FIG. 13B, the element isolation region 80 is etched. The etching is performed until the gap 94 is opened and the groove 90 is formed. Specifically, the processing is performed up to a position in the stopper layer 52 in the Z-axis direction where the opening width L1 becomes the coating agent passage width (for example, about 5 nm or more).

  For the etching, dry etching such as RIE (Reactive Ion Etching), CDE (Chemical Dry Etching), or wet etching can be used. In the case of dry etching, since there is anisotropy in the etching direction, it is possible to suppress the etching of the cell side wall and etch only the vicinity of the opening 90a. On the other hand, wet etching has the advantage that the process cost is relatively low.

  Next, as illustrated in FIG. 13C, the second insulating layer 70 </ b> B is formed on the surface of the first insulating layer 70 </ b> A by using, for example, a spin coat method. Examples of the coating agent include polysilazane. As a result, the groove 90 is filled with the coating agent, and the element isolation region 80 is blocked by the first insulating layer 70A and the second insulating layer 70B. Thereby, the inter-element insulating layer 70 is formed.

  Thereafter, although not shown, the steps described above with reference to FIGS. 5A to 6B are performed, and then the processing in the Y-axis direction is performed similarly to the processing in the X-axis direction. Thereafter, in order to improve the quality of the second insulating layer 70B formed by a coating method, heat treatment such as low-temperature annealing at 400 ° C. or lower is performed as necessary.

The nonvolatile memory device 2 is manufactured through the above steps. In the case of manufacturing a multilayer nonvolatile memory device, the above procedure may be repeated.
As in Manufacturing Method Example 1, nitrogen may be deposited at the interface between the first insulating layer 70A and the second insulating layer 70B, but this does not impair the insulating properties.

  Even in this manufacturing method example, the same effects as in manufacturing method example 1 can be obtained. That is, by introducing the high-quality inter-element insulating layer 70A in the element isolation region 80 (particularly in the vicinity of the side wall of the memory cell portion) having a high aspect ratio, deterioration and variation in switching characteristics are suppressed. Further, the forming process of the inter-element insulating layer 70 is relatively easy. Furthermore, since the inter-element insulating layer 70 can be formed at a relatively low temperature, deterioration of the element due to heat can be suppressed. That is, a nonvolatile memory device having good operating characteristics and easy to process and a method for manufacturing the same are provided.

  In the above description, the case where the plasma CVD is used as the vapor deposition method and the spin coating method is used as the coating method has been mainly described. However, other vapor deposition methods and coating methods may be used.

(Application examples)
Hereinafter, application examples of the method for manufacturing the nonvolatile memory device according to the present embodiment will be described.
A case where the method for manufacturing a nonvolatile memory device according to the present embodiment is applied to a probe memory and a case where it is applied to a flash memory will be described.

(Probe memory)
First, a case where it is applied to a probe memory will be described.
14 and 15 are schematic views showing the probe memory according to the present embodiment.
On the XY scanner 160, a recording medium provided with the recording unit described above with reference to FIGS. A probe array is arranged to face the recording medium.

The probe array includes a substrate 230 and a plurality of probes (heads) 240 arranged in an array on one surface side of the substrate 230. Each of the plurality of probes 240 is constituted by a cantilever, for example, and is driven by multiplex drivers 250 and 260.
Each of the plurality of probes 240 can be individually operated using a microactuator in the substrate 230. Here, an example will be described in which all of the probes 240 are collectively operated to access the data area of the recording medium. .

First, using the multiplex drivers 250 and 260, all the probes 240 are reciprocated in the X direction at a constant period, and the position information in the Y direction is read from the servo area of the recording medium. The position information in the Y direction is transferred to the driver 150.
The driver 150 drives the XY scanner 160 based on this position information, moves the recording medium in the Y direction, and positions the recording medium and the probe.
When the positioning of both is completed, data reading or writing is performed simultaneously and continuously on all the probes 240 on the data area.

Data reading and writing are continuously performed because the probe 240 reciprocates in the X direction. Data reading and writing are performed line by line in the data area by sequentially changing the position of the recording medium in the Y direction.
Note that the recording medium may be reciprocated in the X direction at a constant period to read position information from the recording medium, and the probe 240 may be moved in the Y direction.

The recording medium includes, for example, a substrate 200, an electrode layer 210 on the substrate 200, and a recording layer 220 on the electrode layer 210.
The recording layer 220 has a plurality of data areas and servo areas arranged at both ends in the X direction of the plurality of data areas. The plurality of data areas occupy the main part of the recording layer 220.

A servo burst signal is recorded in the servo area. The servo burst signal indicates position information in the Y direction within the data area.
In addition to these pieces of information, an address area in which address data is recorded and a preamble area for synchronization are arranged in the recording layer 220.
The data and servo burst signal are recorded on the recording layer 220 as recording bits (electric resistance fluctuation). The “1” and “0” information of the recording bit is read by detecting the electric resistance of the recording layer 220.

In this example, one probe (head) is provided corresponding to one data area, and one probe is provided for one servo area.
The data area is composed of a plurality of tracks. A track in the data area is specified by an address signal read from the address area. The servo burst signal read from the servo area is used to move the probe 240 to the center of the track and eliminate the recording bit reading error.
Here, by making the X direction correspond to the down-track direction and the Y direction correspond to the track direction, it becomes possible to use the head position control technology of the HDD.

Next, the recording / reproducing operation of the probe memory will be described.
FIG. 16 is a conceptual diagram for explaining a state during recording (set operation).
The recording medium includes an electrode layer 210 uniformly provided on a substrate (for example, a semiconductor chip) 200, a plurality of cellular recording layers 220 and electrode layers 130 provided on the electrode layer 210, and a plurality of recording media. An inter-element insulating layer 700 provided between the cells, a contact electrode layer 130C provided on the electrode layer 130 and the inter-element insulating layer 700, and a protective layer 130B provided on the contact electrode layer 130C. It shall consist of The protective layer 130B is made of, for example, a thin insulator.

The recording operation is performed by applying a voltage to the surface of the recording layer 220 and generating a potential gradient in the recording layer 220. Specifically, a current / voltage pulse may be applied to the recording layer 220.
Reproduction is performed by passing a current pulse through the recording layer 220 and detecting the resistance value of the recording layer 220. However, the current pulse has a minute value that does not cause a change in resistance of the material constituting the recording layer 220.

For example, a read current (current pulse) generated by the sense amplifier S / A is passed from the probe 240 to the recording layer 220, and the resistance value of the recording layer 220 is measured by the sense amplifier S / A.
In reproduction, continuous reproduction is possible by scanning the recording medium with the probe 240.

Regarding the erasing (reset) operation, the recording layer 220 may be Joule-heated with a large current pulse to restore the resistance state of the recording layer 220. Alternatively, a pulse that gives a potential difference in the opposite direction to that in the set operation may be applied.
The erasing operation can be performed for each cell, and a plurality of cells can be performed together.

  Here, the inter-element insulating layer 700 is manufactured using the manufacturing method according to the present embodiment. Thereby, the effect mentioned above is acquired. That is, by introducing the high-quality inter-element insulating layer 700A in an element isolation region having a high aspect ratio (particularly in the vicinity of the side wall of the memory cell portion), deterioration and variation in switching characteristics are suppressed. In addition, the formation process of the inter-element insulating layer 700 is relatively easy. Further, since the inter-element insulating layer 700 can be formed at a relatively low temperature, deterioration of the element due to heat can be suppressed. That is, a nonvolatile memory device having good operating characteristics and easy to process and a method for manufacturing the same are provided.

(Flash memory)
In the above description, the cross-point type resistance change type or phase change type nonvolatile memory device has been described. However, the application target of the present embodiment is not limited to such a device. The present embodiment can be applied to any storage device that is required to electrically insulate elements. Hereinafter, a case where the present embodiment is applied to a flash memory will be described.
FIG. 17 is a schematic cross-sectional view showing a memory cell of the flash memory according to the present embodiment.

The memory cell of the flash memory is composed of a MIS (metal-insulator-semiconductor) transistor.
A diffusion layer 420 is formed on the surface region of the semiconductor substrate 410. A gate insulating layer 430 is formed on the channel region between the diffusion layers 420. On the gate insulating layer 430, the recording portion 440 (recording layer (RRAM: Resistive RAM) and upper and lower electrode layers) described above with reference to FIGS. A control gate electrode 450 is formed on the recording unit 440.

  The semiconductor substrate 410 may be a well region, and the semiconductor substrate 410 and the diffusion layer 420 have opposite conductivity types. The control gate electrode 450 becomes a word line and is made of, for example, conductive polysilicon. An inter-element insulating layer (not shown) is provided between the cells.

The basic operation will be described with reference to FIG.
The set (write) operation is performed by applying the potential V1 to the control gate electrode 450 and applying the potential V2 to the semiconductor substrate 410.
The difference between the potentials V1 and V2 needs to be large enough for the recording unit 440 to change phase or change resistance, but the direction is not particularly limited.
That is, either V1> V2 or V1 <V2 may be used.
For example, assuming that the recording unit 440 is an insulator (high resistance) in the initial state (reset state), the gate insulating layer 430 is substantially thickened, and thus the threshold value of the memory cell (MIS transistor). Get higher.

When the recording portion 440 is changed to a conductor (low resistance) by applying the potentials V1 and V2 from this state, the gate insulating layer 430 is substantially thinned. Therefore, the threshold value of the memory cell (MIS transistor) is , Get lower.
Note that the potential V2 is applied to the semiconductor substrate 410, but instead, the potential V2 may be transferred from the diffusion layer 420 to the channel region of the memory cell.

The reset (erase) operation is performed by applying the potential V1 ′ to the control gate electrode 450, applying the potential V3 to one of the diffusion layers 420, and applying the potential V4 (<V3) to the other of the diffusion layers 420.
The potential V1 ′ is set to a value exceeding the threshold value of the memory cell in the set state.
At this time, the memory cell is turned on, electrons flow from the other side of the diffusion layer 420 to one side, and hot electrons are generated. Since the hot electrons are injected into the recording unit 440 through the gate insulating layer 430, the temperature of the recording unit 440 increases.

  As a result, since the recording unit 440 changes from a conductor (low resistance) to an insulator (high resistance), the gate insulating layer 430 is substantially thickened, and the threshold value of the memory cell (MIS transistor) is , Get higher.

(NAND flash memory)
FIG. 18 is a circuit diagram of the NAND cell unit.
FIG. 19 is a schematic diagram showing the structure of the NAND cell unit according to this embodiment.

An N-type well region 410b and a P-type well region 410c are formed in the P-type semiconductor substrate 410a. A NAND cell unit is formed in the P-type well region 410c. An inter-element insulating layer 700 is provided between the cells.
The NAND cell unit is composed of a NAND string composed of a plurality of memory cells MC connected in series, and a total of two select gate transistors ST connected to the both ends one by one.

  The memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 420, a gate insulating layer 430 on a channel region between the N-type diffusion layers 420, and a recording unit 440 (recording layer (RRAM) and upper and lower sides) on the gate insulating layer 430. Electrode layer) and a control gate electrode 450 on the recording portion 440.

The state (insulator / conductor) of the recording unit 440 of the memory cell MC can be changed by the basic operation described above. On the other hand, the recording unit 440 of the select gate transistor ST is fixed in a set state, that is, a conductor (low resistance).
One of the select gate transistors ST is connected to the source line SL, and the other one is connected to the bit line BL.

It is assumed that all memory cells in the NAND cell unit are in a reset state (resistance is large) before the set (write) operation.
The set (write) operation is sequentially performed one by one from the memory cell MC on the source line SL side to the memory cell on the bit line BL side.
V1 (plus potential) is applied to the selected word line (control gate electrode) WL as a write potential, and Vpass is applied to the unselected word line WL as a transfer potential (a potential at which the memory cell MC is turned on).

The select gate transistor ST on the source line SL side is turned off, the select gate transistor ST on the bit line BL side is turned on, and program data is transferred from the bit line BL to the channel region of the selected memory cell MC.
For example, when the program data is “1”, a write inhibit potential (for example, the same potential as V1) is transferred to the channel region of the selected memory cell MC, and the recording section 440 of the selected memory cell MC The resistance value should not change from a high state to a low state.
When the program data is “0”, V2 (<V1) is transferred to the channel region of the selected memory cell MC, and the resistance value of the recording unit 440 of the selected memory cell MC is changed from a high state to a low state. To change.

In the reset (erase) operation, for example, V1 ′ is applied to all the word lines (control gate electrodes) WL, and all the memory cells MC in the NAND cell unit are turned on. Further, the two select gate transistors ST are turned on, V3 is applied to the bit line BL, and V4 (<V3) is applied to the source line SL.
At this time, since hot electrons are injected into the recording units 440 of all the memory cells MC in the NAND cell unit, the reset operation is executed collectively for all the memory cells MC in the NAND cell unit.

In the read operation, a read potential (plus potential) is applied to the selected word line (control gate electrode) WL, and the memory cell MC receives data “0”, “1” on the unselected word line (control gate electrode) WL. A potential to be turned on without fail is given.
Further, the two select gate transistors ST are turned on to supply a read current to the NAND string.
When the read potential is applied, the selected memory cell MC is turned on or off according to the value of the data stored in the selected memory cell MC. For example, data can be read by detecting a change in the read current. it can.

  In the structure shown in FIG. 19, the select gate transistor ST has the same structure as the memory cell MC. For example, as shown in FIG. 20, the select gate transistor ST forms a recording portion. Alternatively, a normal MIS transistor can be used.

FIG. 21 is a schematic diagram showing a modification of the NAND flash memory.
This modification has a structure in which the gate insulating layers of the plurality of memory cells MC constituting the NAND string are replaced with a P-type semiconductor layer 470.
When the integration is advanced and the memory cell MC is miniaturized, the P-type semiconductor layer 470 is filled with a depletion layer in a state where no voltage is applied.

At the time of setting (writing), a positive write potential (for example, 3.5 V) is applied to the control gate electrode 450 of the selected memory cell MC, and a positive transfer potential is applied to the control gate electrode 450 of the non-selected memory cell MC. (For example, 1V).
At this time, the surface of the P-type well region 410c of the plurality of memory cells MC in the NAND string is inverted from P-type to N-type, and a channel is formed.

  Therefore, as described above, the set operation can be performed by turning on the select gate transistor ST on the bit line BL side and transferring the program data “0” from the bit line BL to the channel region of the selected memory cell MC. it can.

  Reset (erase) is performed, for example, by applying a negative erase potential (for example, −3.5 V) to all the control gate electrodes 450 and applying a ground potential (0 V) to the P-type well region 410 c and the P-type semiconductor layer 470. This can be performed collectively for all the memory cells MC constituting the NAND string.

  At the time of reading, a positive read potential (for example, 0.5 V) is applied to the control gate electrode 450 of the selected memory cell MC, and the memory cell MC receives the data “ A transfer potential (for example, 1 V) that always turns on regardless of 0 ”or“ 1 ”is applied.

However, it is assumed that the threshold voltage Vth “1” of the memory cell MC in the “1” state is in the range of 0V <Vth ”1” <0.5V, and the threshold voltage Vth ”of the memory cell MC in the“ 0 ”state. It is assumed that 0 ″ is in the range of 0.5V <Vth ″ 0 ″ <1V.
Further, the two select gate transistors ST are turned on to supply a read current to the NAND string.
In such a state, since the amount of current flowing through the NAND string changes according to the value of the data stored in the selected memory cell MC, data can be read by detecting this change.

In this modification, the hole doping amount of the P-type semiconductor layer 470 is larger than that of the P-type well region 410c, and the Fermi level of the P-type semiconductor layer 470 is 0 than that of the P-type well region 410c. It is desirable that the depth is about 5V.
This is because when a positive potential is applied to the control gate electrode 450, inversion from the P-type to N-type starts from the surface portion of the P-type well region 410c between the N-type diffusion layers 420, and a channel is formed. It is for doing so.

Thus, for example, at the time of writing, the channel of the non-selected memory cell MC is formed only at the interface between the P-type well region 410c and the P-type semiconductor layer 470, and at the time of reading, a plurality of memories in the NAND string is formed. The channel of the cell MC is formed only at the interface between the P-type well region 410 c and the P-type semiconductor layer 470.
That is, even if the recording part 440 of the memory cell MC is a conductor (set state), the diffusion layer 420 and the control gate electrode 450 are not short-circuited.

(NOR flash memory)
FIG. 22 is a circuit diagram of the NOR cell unit.
FIG. 23 is a schematic diagram showing the structure of the NOR cell unit according to this embodiment.

An N-type well region 410b and a P-type well region 410c are formed in the P-type semiconductor substrate 410a. A NOR cell is formed in the P-type well region 410c. An inter-element insulating layer 700 is provided between the cells.
The NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.

  The memory cell MC includes an N-type diffusion layer 420, a gate insulating layer 430 on a channel region between the N-type diffusion layers 420, and a recording unit 440 (recording layer (RRAM) and upper and lower electrode layers) on the gate insulating layer 430. And a control gate electrode 450 on the recording unit 440. The state (insulator / conductor) of the recording unit 440 of the memory cell MC can be changed by the basic operation described above.

(2-transistor flash memory)
FIG. 24 is a circuit diagram of a two-transistor cell unit.
FIG. 25 is a schematic diagram showing the structure of the two tracell unit according to the present embodiment.

The two-transistor cell unit has been recently developed as a new cell structure that combines the characteristics of a NAND cell unit and the characteristics of a NOR cell.
An N-type well region 410b and a P-type well region 410c are formed in the P-type semiconductor substrate 410a. A two-transistor cell unit is formed in the P-type well region 410c. An inter-element insulating layer 700 is provided between the cells.

The two-transistor type cell unit includes one memory cell MC and one select gate transistor ST connected in series.
The memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 420, a gate insulating layer 430 on a channel region between the N-type diffusion layers 420, and a recording portion (recording layer (RRAM) and upper and lower electrodes on the gate insulating layer 430). Layer) and a control gate electrode 450 on the recording portion 440.
The state (insulator / conductor) of the recording unit 440 of the memory cell MC can be changed by the basic operation described above. On the other hand, the recording unit 440 of the select gate transistor ST is fixed in a set state, that is, a conductor (low resistance).

Select gate transistor ST is connected to source line SL, and memory cell MC is connected to bit line BL.
The state (insulator / conductor) of the recording unit 440 of the memory cell MC can be changed by the basic operation described above.
In the structure shown in FIG. 25, the select gate transistor ST has the same structure as the memory cell MC. For example, as shown in FIG. 26, the select gate transistor ST does not form a recording portion. In addition, a normal MIS transistor can be used.

  In these flash memories, the inter-element insulating layer 700 is manufactured using the manufacturing method according to the present embodiment. Thereby, the effect mentioned above is acquired. That is, by introducing the high-quality inter-element insulating layer 700A in an element isolation region having a high aspect ratio (particularly in the vicinity of the side wall of the memory cell portion), deterioration and variation in switching characteristics are suppressed. In addition, the formation process of the inter-element insulating layer 700 is relatively easy. Further, since the inter-element insulating layer 700 can be formed at a relatively low temperature, deterioration of the element due to heat can be suppressed. That is, a nonvolatile memory device having good operating characteristics and easy to process and a method for manufacturing the same are provided.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the present invention as long as they have the characteristics of the present invention. For example, the elements included in each of the specific examples described above and their arrangement, materials, conditions, shapes, sizes, and the like are not limited to those illustrated, but can be changed as appropriate.
Moreover, each element with which each embodiment mentioned above is provided can be combined as long as technically possible, and the combination of these is also included in the scope of the present invention as long as it includes the features of the present invention.

3 is a schematic diagram of a nonvolatile memory device 2 according to Specific Example 1. FIG. 3 is a schematic cross-sectional view of a nonvolatile memory device 2. FIG. It is a schematic cross section showing an example of the composition of a cell. 6 is a schematic process cross-sectional view showing Manufacturing Method Example 1. FIG. 6 is a schematic process cross-sectional view showing Manufacturing Method Example 1. FIG. 6 is a schematic process cross-sectional view showing Manufacturing Method Example 1. FIG. 6 is a schematic process cross-sectional view showing Manufacturing Method Example 1. FIG. It is a typical process sectional view showing a manufacturing method of nonvolatile memory device 2 concerning a comparative example (comparative example 1) contrasted with this embodiment. 12 is a schematic cross-sectional process diagram illustrating a method for manufacturing the nonvolatile memory device 2 according to Comparative Example 2. FIG. 12 is a schematic cross-sectional process diagram illustrating a method for manufacturing a nonvolatile memory device 2 according to Comparative Example 3. FIG. 10 is a schematic process cross-sectional view illustrating Manufacturing Method Example 2. FIG. 10 is a schematic process cross-sectional view illustrating Manufacturing Method Example 2. FIG. 12 is a schematic process cross-sectional view illustrating Manufacturing Method Example 3. FIG. It is a schematic diagram showing the probe memory which concerns on this embodiment. It is a schematic diagram showing the probe memory which concerns on this embodiment. It is a conceptual diagram for demonstrating the state at the time of recording (set operation | movement). 1 is a schematic cross-sectional view showing a memory cell of a flash memory according to an embodiment. It is a circuit diagram of a NAND cell unit. It is a schematic diagram showing the structure of the NAND cell unit which concerns on this embodiment. It is a schematic diagram showing the specific example using a normal MIS transistor. FIG. 10 is a schematic diagram illustrating a modification of a NAND flash memory. It is a circuit diagram of a NOR cell unit. It is a schematic diagram showing the structure of the NOR cell unit which concerns on this embodiment. It is a circuit diagram of a two-transistor type cell unit. It is a schematic diagram showing the structure of the 2 tracell unit which concerns on this embodiment. It is a schematic diagram showing the specific example using a normal MIS transistor.

Explanation of symbols

2 Nonvolatile Memory Device 10 Substrate 20 First Wiring 32 Barrier Layer 30 Rectifier 40 Recording Unit 42 Electrode Layer 44 Recording Layer 46 Electrode Layer 50 Second Wiring 52 Stopper Layer, Projection 54 Second Wiring 60 Etching Mask 70 Inter-element insulating layer 70A First insulating layer 70B Second insulating layer 80 Element isolation region 90 Groove 90a Opening 94 Air gap 94A Air gap 94B Air gap 100 Insulating layer 100A Insulating layer 100B Insulating layer 104 Insulating layer 130 Electrode layer 130B Protective layer 130C Contact electrode layer 150 Driver 160 XY scanner 200 Substrate 210 Electrode layer 220 Recording layer 230 Substrate 240 Probe 250, 260 Multiplex driver 410 Semiconductor substrate 410a P-type semiconductor substrate 410b N-type well region 410c P-type well region 420 Diffusion layer 420d Diffusion layer (drain )
420s diffusion layer (source)
430 Gate insulating layer 440 Recording unit 450 Control gate electrode 460 Select gate 470 P-type semiconductor layer 700 Inter-element insulating layer BL Bit line L1 Opening width L2 Air gap width WL Word line

Claims (7)

A first wiring extending in a first direction;
A second wiring extending in a second direction non-parallel to the first direction;
The first state and the second state are sandwiched between the first wiring and the second wiring, and are supplied via the first wiring and the second wiring. A reversible recording layer,
A method for manufacturing a non-volatile memory device comprising:
Forming a layer of the first wiring;
Forming the recording layer on the main surface of the first wiring layer;
Selectively etching the recording layer and the first wiring layer to form a plurality of stacked bodies extending in the first direction;
Forming a first insulating layer on a surface of a gap between the plurality of stacked bodies using a vapor phase growth method;
Forming a second insulating layer on the first insulating layer using a coating method;
A method for manufacturing a nonvolatile memory device, comprising:   2. The method for manufacturing a nonvolatile memory device according to claim 1, wherein the vapor phase growth method is a plasma chemical vapor deposition method.   The method for manufacturing a nonvolatile memory device according to claim 1, wherein the vapor phase growth method is an atomic layer deposition method.   The method for manufacturing a nonvolatile memory device according to claim 1, wherein the coating method is a spin coating method.   The method for manufacturing a nonvolatile memory device according to claim 1, wherein the coating agent used for the coating method is polysilazane. A step of forming a stopper layer made of the same material as the material of the second wiring on the recording layer between the step of forming the recording layer and the step of forming the stacked body. In addition,
6. The method according to claim 1, further comprising a step of flattening a main surface of the workpiece until the stopper layer is exposed after the step of forming the second insulating layer. The manufacturing method of the non-volatile memory device of description. Between the step of forming the first insulating layer and the step of forming the second insulating layer,
The method for manufacturing a nonvolatile memory device according to claim 1, further comprising a step of flattening a main surface of the workpiece.

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