JP2010068355A - Electronic apparatus and method of controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic apparatus for quickly restoring a normal mode from an energy saving mode, and to provide a method of controlling the same. <P>SOLUTION: Electronic apparatus 100 is configured as electronic apparatus having an energy saving mode, and has: an RAM 109 for storing a register set value managed by an overall control part 106 when a normal mode is shifted to the energy saving mode; and a DMA controller 108 for reading a register set value from the RAM 109 by direct memory access when the normal mode is restored from the energy saving mode. The overall control part 106 is characterized by initialization processing using the read register set value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic device and a control method thereof, and more particularly, to a technique for realizing a quick return from an energy saving mode.

  Patent Documents 1 and 2 are listed as documents describing technologies related to the present invention.

  Patent Document 1 discloses an operation in a normal mode for the purpose of reducing power consumption in the power saving mode and enabling a return from the power saving mode to the normal operation mode in a short time. A configuration is disclosed in which at least a part of data necessary for returning from the energy saving mode is read from the ROM and stored in the main memory.

Further, Patent Document 2 discloses a main in which power supply is stopped in the energy saving mode for the purpose of minimizing power consumption in the energy saving mode and that communication is interrupted when switching between the energy saving mode and the normal mode. A technology is disclosed in which a CPU instructs a sub CPU to shift to an energy saving mode when shifting, and the sub CPU shifts transmission / reception control to its own management without stopping data transfer.
Japanese Patent No. 3798353 JP 2005-303978 A

  In recent years, there has been a great demand for power consumption reduction in image forming apparatuses, and in particular, there has been a demand for reduction of power consumption during standby when there is no operation or print job execution. In view of this, an energy saving mode for stopping power supply to an engine portion with particularly large power consumption is provided, and power consumption is reduced by shifting to the energy saving mode during standby.

  In addition, in order to further reduce power consumption, technology to stop power supply to the CPU, power supply line for control ASIC (Application Specific IC) or SoC (System on Chip) is divided into multiple systems and is not required in energy saving mode A technique for stopping the power supply to various functions is already known.

  However, the conventional technology for stopping power supply to the CPU requires a hardware / software initialization process to return to the normal operation mode in the same manner as when the power is turned on, and the time required for the recovery is long. There was a problem.

  Accordingly, in view of the above circumstances, an object of the present invention is to provide an electronic device and a control method therefor that can quickly return from the energy saving mode to the normal mode.

  In order to achieve the above object, the present invention comprises the following arrangement.

  An electronic apparatus according to the present invention is an electronic apparatus having an energy saving mode, and stores a register setting value managed by a control unit of the entire apparatus at the time of shifting to the energy saving mode, and returns from the energy saving mode. And a DMA control unit that reads the register setting value from the storage unit by direct memory access, and the control unit performs an initialization process using the read register setting value.

  An electronic device control method according to the present invention is a method for controlling an electronic device having an energy saving mode, and stores a register setting managed by a control unit of the entire apparatus when shifting to the energy saving mode; A DMA control step of reading the register setting value stored in the storage step by direct memory access when returning from the energy saving mode; and a step of performing an initialization process by using the read register setting value by the control unit; , Including.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the electronic device and its control method which enable it to return from energy saving mode to normal mode in a short time.

Hereinafter, embodiments of the present invention will be described in detail.
The electronic apparatus according to the present embodiment is not limited, but may be, for example, an electrophotographic image forming apparatus or an inkjet image forming apparatus. Although the image forming apparatus requires a large amount of power consumption during operation, the standby time is long, and the effects of the present invention relating to the control in the energy saving mode can be exhibited particularly advantageously. Hereinafter, the electronic apparatus according to the present embodiment is an inkjet image forming apparatus.

First, the configuration of the present embodiment will be described with reference to FIGS.
FIG. 1 is a block diagram illustrating a schematic configuration of an electronic device 100 according to the present embodiment. As illustrated, the electronic device 100 includes a SoC (System on Chip) 101, a RAM 109, a clock generator 110, and a ROM 111. Hereinafter, each part will be described.

  The SoC 101 includes an overall control unit 106 that controls the entire apparatus, an energy saving control unit 102 that performs control in an energy saving (hereinafter referred to as “energy saving”) state, and a RAM controller 105 that controls the RAM 109.

The clock generator 110 generates a clock necessary for the system.
A RAM 109 is a main memory used for image data and programs.
The RAM controller 105 controls access to the RAM 109, periodic refresh operation control, and a command for shifting to self-refresh when shifting to an energy saving state.
The ROM 111 stores a program, waveform data for print ejection, and the like, and is developed and used in the RAM 109 when the power is turned on. A non-volatile ROM such as FlashROM is used.

  The energy saving control unit 102 has a function of detecting a return factor from the energy saving state, and includes a timer for energy saving return. When the user performs a key operation on an operation / display unit (not shown) of the electronic device 100, the energy saving control unit 102 detects the edge of the input signal and generates a return signal to perform a return operation.

  The overall control unit 106 is a central processing unit (CPU) 107 that performs various calculations and processes necessary for the operation of the electronic device 100, and a DMA that performs control for direct memory access to the RAM 109 and the ROM 111 without using the CPU 107. And a controller 108.

  The electronic device 100 has two reset signals, and both are in a reset state when the power is activated. At the time of energy saving transition, only the RESET_1 signal is reset so that the external terminal is set to Hi-Z and the power supply is prevented from wrapping around.

  At the time of power activation, the CPU 107 activates a program from the ROM 111 after releasing the reset, and initializes each control unit. After the initialization is completed, the CPU 107 copies the program stored in the ROM 111 to the RAM 109 and operates with the program on the RAM 109.

  FIG. 2 is a block diagram illustrating a power supply state when the electronic device 100 is in the energy saving mode. As shown in the figure, the core power supply of the SoC 101 is divided into two systems. The hatched portion in FIG. 2 indicates a block that is not supplied with power in the energy saving state.

  The PWR_CTL signal is a signal for controlling power feeding to the block indicated by the oblique lines in FIG. 2 when shifting to the energy saving state. In the energy saving state, the power source of the overall control unit 106 including the CPU 107 and the ROM 111 connected to the outside is turned off. The RAM 109 is in a self-refresh state by the RAM controller 105, and has a lower power consumption than normal.

Next, the return operation from the energy saving state will be described.
When returning from the energy saving state, power is supplied to the shaded portion in FIG. 2 to cancel the reset signal. The CPU 107 starts activation from the ROM 111 in the same manner as when the power is activated.

  The energy saving control unit 102 has an energy saving return flag 103, which is used for distinguishing between power activation and energy saving return. When shifting to energy saving, this energy saving return flag 103 is set to be effective so that after the CPU 107 starts to start, the flag 103 can be checked to determine whether the power is on or energy saving is returned. It becomes possible. Since the energy saving return flag 103 is in the energy saving control unit 102 in which the power is not turned off during energy saving, it is not cleared even when the energy saving state is entered.

  At the time of energy saving transition, hardware setting values set in the overall control unit 106 are set as a table on the RAM 109. At that time, the start address of the table is recorded in the DMA_SADR register 104. In the present embodiment, DMA_SADR is provided as a register, but an area on the RAM 109 may be used.

  After the activation from the ROM 111, the CPU 107 acquires the value of DMA_SADR and sets it in the DMA controller 108 when it is determined that the energy saving return flag 103 is a return operation from energy saving. When the DMA transfer is started, the register setting value before the energy saving transition is set in each register of the overall control unit 106 by DMA.

FIG. 3 is a diagram illustrating an example of register mapping.
The activation register 202 for instructing the operation start and the operation parameter register 201 for various settings are grouped into different addresses. The DMA transfer size can be reduced by performing the DMA setting so that the setting to the control system is not performed at the time of energy saving return. Also, it is desirable that the arrangement of each register is continuously mapped so as to reduce the DMA transfer size. This makes it possible to perform initial setting at a higher speed.

  FIG. 4 is a diagram for explaining the write protect control of the present embodiment. From the write protect setting register 203, the write_protect signal is connected only to the activation register 202. When the write_protect signal is valid, writing to the activation register 202 is invalid.

  At the time of energy saving return, write protect is set to be effective and register setting is performed by DMA. Thereby, it is possible to suppress an operation that is not desired to be generated in the initialization operation at the time of energy saving return.

  Further, in the example of FIG. 4, compared with the example of FIG. 3, it is not necessary to separate the address of the activation register 202 and the operation parameter, so that register mapping can be packed and register setting can be performed with a smaller DMA transfer size. It becomes.

FIG. 5 is a diagram showing a descriptor format used in DMA.
The DMA controller 108 sets only the first descriptor address.
After starting the energy saving return operation, the DMA operation parameter is obtained by reading the descriptor placed in the memory in the format shown in FIG.
-When the data transfer for the transfer size is completed, it is determined from the end flag whether the transfer is completed.
If not finished, the next descriptor is read from the memory area indicated by the next descriptor address.
Continue until the above processing is completed.

The reason for using the descriptor in this embodiment will be described.
Each register / SRAM that needs to be initialized is dotted on the memory map. However, DMA is effective for continuous addresses, but if it is not continuous, it is necessary to set a transfer destination address each time. Also, even when register setting values are avoided on the RAM 109, memory management becomes difficult if all register setting values are placed in a continuous memory space.

  Therefore, by using the descriptor as shown in FIG. 5, it is possible to transfer the scattered register setting values to the scattered registers through a series of operations. As a result, no CPU intervention is required, and the initialization can be completed at a higher speed.

FIG. 6 is a functional block diagram of the DMA controller 108 equipped with the decompression function.
The activation control unit 301 interprets the descriptor as shown in FIG. 5 and controls the read DMA controller 302 / write DMA controller 303. The decompressor 304 decompresses the compressed data.

  After the DMA activation, the activation control unit 301 activates the read DMA controller 302 for the set first descriptor address. The transfer source / destination address is acquired from the received read data (first descriptor), and the read DMA controller 302 / write DMA controller 303 is activated.

  Data read from the transfer source address is decompressed by the decompressor 304 and transferred to the write DMA controller 303. The write DMA controller 303 transfers the received data to the transfer destination address. Such an operation is performed for the transfer size acquired from the descriptor.

  The decompressor 304 can set whether or not to perform decompression. When the decompression is not performed, the decompressor 304 is passed through. The decompressor 304 also has a function of compressing the register set value when shifting to the energy saving mode.

  By making the configuration of the DMA controller 108 as shown in FIG. 6, by compressing the data, the capacity can be reduced when the register set value is copied to the RAM 109.

  FIG. 7 is a diagram showing still another example of the descriptor format used in the DMA controller of FIG. The difference from FIG. 5 is that the descriptor includes a setting value indicating whether or not expansion is possible. Thus, it is determined whether or not to pass through the expander 304 described above.

FIG. 8 is a flowchart showing a processing flow at the time of energy saving transition of the image forming apparatus.
After any of the last printing operation, copying operation, scanner operation, etc. is completed, the mode shifts to the energy saving mode when a predetermined time has elapsed.
In step S101, it is determined whether or not it is possible to shift to the energy saving mode. If an error such as a status error has occurred, transition is not possible.
If migration is possible, register value avoidance processing is performed in step S102. At this time, each register setting value of the above-described overall control unit 106 is copied onto the RAM 109.
At this time, if each register table becomes large, the table itself is compressed.
Also, here, each descriptor table is prepared on the RAM 109 for DMA processing at the time of return.

In step S 103, the start address of the first descriptor in the descriptor table is set in the DMA_SADR register 104 of the energy saving control unit 102.
In step S104, a transition process to the energy saving mode is performed. The energy saving return flag 103 of the energy saving control unit 102 is set to be effective, and the power to the block that does not require operation when saving energy, such as the CPU 107, is turned off. In step S105, error display or the like is performed.

FIG. 9 is a flowchart illustrating a return operation from energy saving in the present embodiment.
When the reset is released, the CPU 107 starts a boot program. In FIG. 9, a boot operation, particularly a boot operation when returning from energy saving will be described.

  In step S201, it is determined whether the boot operation is a return from energy saving or power-on. By confirming the return flag 103 of the energy saving control unit 102 enabled in step S104 of FIG. 8, it can be seen that the operation is a return operation from the energy saving mode. If it is not a return from the energy saving mode, an initialization process at the time of power activation is performed (step S205).

  In step S202, a DMA transfer start address for initial setting is set. At this time, the start address is acquired from the DMA_SADR register 104 of the energy saving control unit 102 set in step S103 of FIG. 8, and set in the DMA transfer start address setting register.

  By performing the DMA transfer start setting in step S203, the initialization operation is automatically performed. After starting the DMA transfer, in step S204, the completion of the DMA transfer is confirmed.

  Here, all initial settings are performed by DMA, but only some registers may be used. In addition, another operation that does not require an initialization operation may be performed until the DMA transfer is completed, or only a part of the initial settings may be initialized by the CPU 107 and then the external device may be initialized.

An embodiment obtained by modifying the embodiment described above will be described with reference to FIG.
FIG. 10 is a block diagram illustrating a configuration of a portion related to the energy saving mode and the operation at the time of return. In the example shown in FIG. 10, there are two DMA controllers for initialization operation at the time of energy saving return. In FIG. 10, the DMA controller 108 is mainly used for initial setting of registers relating to engine control. The DMA controller 112 is used for purposes other than engine control. The operations of the DMA controller 108 and the DMA controller 112 are the same as those described with reference to FIG.

  When returning from energy saving, initialization operation is performed using the DMA controller 108 and the DMA controller 112. Here, the DMA controller 108 is mainly used for register initialization relating to engine control, but only a part of the registers may be used.

  The DMA controller 108 is intended for an engine that requires an initial operation of the engine by using an initialized control circuit after completion of register initialization. By doing this, it is possible to start an initial operation of the engine which takes time before completing the initial setting of all the registers. Therefore, the system can be restored at a higher speed.

  The preferred embodiment of the present invention has been described above, but the present invention is not limited to this, and various modifications can be made without departing from the scope of the invention.

It is a block diagram which shows schematic structure of the electronic device which concerns on embodiment by this invention. It is a block diagram which shows the electric power feeding state at the time of the energy saving mode of the electronic device which concerns on this embodiment. It is a figure which shows the register mapping example of the register | resistor in this embodiment. It is a figure for demonstrating the write protection control of this embodiment. It is a figure which shows the format of the descriptor used by DMA in this embodiment. It is a functional block diagram which shows the structure of the DMA controller of this embodiment. It is a figure which shows another example of the format of the descriptor used by DMA in this embodiment. It is a flowchart which shows the process sequence at the time of the energy saving transition of this embodiment. It is a flowchart which shows the process sequence at the time of the energy-saving return of this embodiment. It is a block diagram which shows schematic structure of another embodiment by this invention.

Explanation of symbols

100 Electronic Equipment 101 SoC (System on Chip)
102 Energy Saving Control Unit 103 Energy Saving Return Flag 104 DMA_SADR Register 105 RAM Controller 106 Overall Control Unit 107 CPU
108 DMA controller 109 RAM
110 Clock generator 111 ROM
201 Operation Parameter Register 202 Start Register 203 Write Protect Setting Register 301 Start Control Unit 302 Read DMA Controller 303 Write DMA Controller 304 Expander

Claims (5)

An electronic device having an energy saving mode,
Storage means for storing a register setting value managed by the control unit of the entire apparatus at the time of transition to the energy saving mode;
DMA control means for reading the register setting value from the storage means by direct memory access when returning from the energy saving mode,
The electronic device according to claim 1, wherein the control unit performs an initialization process using the read register setting value. The register setting value includes a setting regarding whether or not at least one of the write protection is enabled,
The electronic device according to claim 1, wherein the control unit validates the write protection when returning from the energy saving mode.   The electronic apparatus according to claim 1, wherein the DMA control unit performs direct memory access by a descriptor method.   The DMA control unit includes a compression / expansion unit, and at the time of shifting to the energy saving mode, the register setting value is compressed and stored in the storage unit using the compression / expansion unit, and upon return from the energy saving mode. 4. The electronic apparatus according to claim 1, wherein the register setting value compressed by using the compression / expansion means is expanded and read. A method for controlling an electronic device having an energy saving mode,
A storage step of storing register settings managed by the control unit of the entire apparatus at the time of transition to the energy saving mode;
A DMA control step of reading out the register setting value stored in the storage step by direct memory access when returning from the energy saving mode;
A step of performing an initialization process using the read register setting value by the control unit;
A method for controlling an electronic device, comprising:

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